152 lines
6.0 KiB
Plaintext
152 lines
6.0 KiB
Plaintext
# Reading pref.tcl
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# do run.do
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# --- Using Windows Actel DirectCore AMBA BFM compiler
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# --- Compiling Actel DirectCore AMBA BFM source files ...
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#
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# AMBA BFM Compiler (BETA Version 2.1.107 04Feb09)
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# Reading
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# Processing ./coreapb3_usertb_master.bfm
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# Enumerating
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# Assigning
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# Checking
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# Checking Complete
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# 31 Global localconstants Defined
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# 42 Global localvariables Defined
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# Writing Vectors ./coreapb3_usertb_master.vec
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# Commands Generated 201
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# Vectors Generated 666
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# Vector CheckSum cd447d4c
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#
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# BFM Compiler Completed Okay
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# --- Done Compiling Actel DirectCore AMBA BFM source files.
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# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
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# vmap postlayout ../designer/top/simulation/postlayout
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# Modifying modelsim.ini
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# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
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# vmap PolarFire E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
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# Modifying modelsim.ini
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# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
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# vmap COREAPB3_LIB COREAPB3_LIB
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# Modifying modelsim.ini
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# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
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# vmap COREJTAGDEBUG_LIB COREJTAGDEBUG_LIB
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# Modifying modelsim.ini
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# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
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# vmap CORESPI_LIB CORESPI_LIB
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# Modifying modelsim.ini
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# Model Technology ModelSim Microsemi Pro vlog 2024.3 Compiler 2024.09 Sep 11 2024
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# Start time: 11:58:37 on Apr 16,2026
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# vlog -reportprogress 300 -sv -work postlayout E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
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# -- Compiling module top
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#
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# Top level modules:
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# top
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# End time: 11:58:42 on Apr 16,2026, Elapsed time: 0:00:05
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# Errors: 0, Warnings: 0
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# vsim -L PolarFire -L postlayout -L COREAPB3_LIB -L COREJTAGDEBUG_LIB -L CORESPI_LIB -t 1ps -pli "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll" -sdfmax "/top=E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf" "+transport_path_delays" postlayout.top
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# Start time: 11:58:43 on Apr 16,2026
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# // ModelSim Microsemi Pro 2024.3 Sep 11 2024
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# //
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# // Unpublished work. Copyright 2024 Siemens
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# //
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# // This material contains trade secrets or otherwise confidential information
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# // owned by Siemens Industry Software Inc. or its affiliates (collectively,
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# // "SISW"), or its licensors. Access to and use of this information is strictly
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# // limited as set forth in the Customer's applicable agreements with SISW.
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# //
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# // This material may not be copied, distributed, or otherwise disclosed outside
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# // of the Customer's facilities without the express written permission of SISW,
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# // and may not be used in any way not expressly authorized by SISW.
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# //
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# Loading sv_std.std
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# Loading postlayout.top
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# Loading PolarFire.CFG4
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# Loading PolarFire.SLE
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# Loading PolarFire.SLE_Prim
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# Loading PolarFire.CFG3
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# Loading PolarFire.ARI1_CC
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# Loading PolarFire.CFG4_IP_ABCD
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# Loading PolarFire.BUFF
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# Loading PolarFire.INV_BA
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# Loading PolarFire.RAM64x12_IP
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# Loading PolarFire.OUTPUT_PMOS
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# Loading PolarFire.INPUT_BUF
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# Loading PolarFire.CFG2
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# Loading PolarFire.RAM1K20_IP
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# Loading PolarFire.RAM_DLY
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# Loading PolarFire.ECC_PIPELINE
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# Loading PolarFire.SLE_IP_EN
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# Loading PolarFire.IOTRI_OB_EB
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# Loading PolarFire.CC_CONFIG
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# Loading PolarFire.CFG1
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# Loading PolarFire.CFG4A
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# Loading PolarFire.IOPAD_IN
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# Loading PolarFire.IOPAD_TRI
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# Loading PolarFire.FCEND_BUFF_CC
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# Loading PolarFire.RGB
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# Loading PolarFire.ICB_CLKINT
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# Loading PolarFire.HS_IO_CLK
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# Loading PolarFire.IOPADN_IN
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# Loading PolarFire.IOBI_IB_OB_EB
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# Loading PolarFire.IOIN_IB_E
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# Loading PolarFire.PLL_DELAY
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# Loading PolarFire.PLL_DELAY_IP
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# Loading PolarFire.DLL_DELAY_BLOCK
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# Loading PolarFire.IO_DIFF
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# Loading PolarFire.PLL_IP
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# Loading PolarFire.PLL_DRI_REGISTERS
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# Loading PolarFire.pll_lp_vco
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# Loading PolarFire.CCC_RF_DIV
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# Loading PolarFire.Freq_Divider
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# Loading PolarFire.Even_Divider
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# Loading PolarFire.Odd_Divider
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# Loading PolarFire.CCC_FB_DIV
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# Loading PolarFire.frac_divider
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# Loading PolarFire.freq_multiplier
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# Loading PolarFire.CCC_PLL
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# Loading PolarFire.ABISCB82
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# Loading PolarFire.ABI_PLL_FRONT
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# Loading PolarFire.refstop
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# Loading PolarFire.Divide_2
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# Loading PolarFire.ABI_PHASE
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# Loading PolarFire.PLL_PHASE_SELECT
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_postdiv_pd_sync
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_divsw8
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_tff_st1x_loadb
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_cmosdiv_2to127
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_ffbrx1cstm
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_latchx1cstmb
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# Loading PolarFire.PF_PLLUM28HLPMFFRAC_ffqbibrbx1cstm
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# Loading PolarFire.CCC_POST_DIV
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# Loading PolarFire.CCC_POSTDIVEN_SYNC
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# Loading PolarFire.div2
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# Loading PolarFire.CCC_8X1_MUX
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# Loading PolarFire.CCC_2X1_MUX
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# Loading PolarFire.GB
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# Loading PolarFire.IOPADP_IN
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# Loading PolarFire.ICB_CLKDIV
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# Loading PolarFire.ICB_CLKDIVDELAY
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# Loading PolarFire.clk_div_3p5
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# Loading PolarFire.clk_div_5
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# Loading PolarFire.LANECTRL
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# Loading PolarFire.IOD_IP
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# Loading PolarFire.IOPADN_TRI
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# Loading PolarFire.IOPAD_BI
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# Loading PolarFire.BANKEN
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# Loading PolarFire.IOPADP_TRI
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# Loading PolarFire.CFG0
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# Loading PolarFire.GND
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# Loading PolarFire.VCC
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# SDF 2024.3 Compiler 2024.09 Sep 11 2024
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#
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# Loading instances from E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf
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# Loading PolarFire.UDP_MUX2
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# Loading PolarFire.UDP_DFF
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# Loading PolarFire.UDP_DL
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# Loading PolarFire.UDP_GBLAT_T
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# Loading PolarFire.UDP_GBLAT
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# Loading E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll
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# Loading timing data from E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf
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# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
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# Time: 0 ps Iteration: 0 Instance: /top File: E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
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