head tail filter testing done

This commit is contained in:
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions

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@@ -1 +1 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./PF_TPSRAM_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./PF_TPSRAM_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/SgCore/PF_TPSRAM/1.1.108/PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./PF_TPSRAM_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="SgCore" name="PF_TPSRAM" vendor="Actel" version="1.1.108"/><configuration><configurableElement referenceId="A_DOUT_EN_PN" value="R_DATA_EN"/><configurableElement referenceId="A_DOUT_EN_POLARITY" value="2"/><configurableElement referenceId="A_DOUT_SRST_PN" value="R_DATA_SRST_N"/><configurableElement referenceId="A_DOUT_SRST_POLARITY" value="2"/><configurableElement referenceId="A_WBYTE_EN_PN" value="WBYTE_EN"/><configurableElement referenceId="BUSY_FLAG" value="0"/><configurableElement referenceId="BYTE_ENABLE_WIDTH" value="0"/><configurableElement referenceId="BYTEENABLES" value="0"/><configurableElement referenceId="CASCADE" value="0"/><configurableElement referenceId="CLK_EDGE" value="RISE"/><configurableElement referenceId="CLKS" value="1"/><configurableElement referenceId="CLOCK_PN" value="CLK"/><configurableElement referenceId="DATA_IN_PN" value="W_DATA"/><configurableElement referenceId="DATA_OUT_PN" value="R_DATA"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="IMPORT_FILE" value=""/><configurableElement referenceId="INIT_RAM" value="F"/><configurableElement referenceId="LPM_HINT" value="0"/><configurableElement referenceId="LPMTYPE" value="LPM_RAM"/><configurableElement referenceId="PMODE2" value="0"/><configurableElement referenceId="PTYPE" value="1"/><configurableElement referenceId="RADDRESS_PN" value="R_ADDR"/><configurableElement referenceId="RCLK_EDGE" value="RISE"/><configurableElement referenceId="RCLOCK_PN" value="R_CLK"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_PN" value="R_EN"/><configurableElement referenceId="RE_POLARITY" value="2"/><configurableElement referenceId="RESET_PN" value="R_DATA_ARST_N"/><configurableElement referenceId="RESET_POLARITY" value="2"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SD_EXPORT_HIDDEN_PORTS" value="false"/><configurableElement referenceId="SII_LOCK" value="0"/><configurableElement referenceId="WADDRESS_PN" value="W_ADDR"/><configurableElement referenceId="WCLK_EDGE" value="RISE"/><configurableElement referenceId="WCLOCK_PN" value="W_CLK"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_PN" value="W_EN"/><configurableElement referenceId="WE_POLARITY" value="1"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>W_EN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_DATA</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./PF_TPSRAM_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./PF_TPSRAM_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/SgCore/PF_TPSRAM/1.1.108/PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./PF_TPSRAM_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="SgCore" name="PF_TPSRAM" vendor="Actel" version="1.1.108"/><configuration><configurableElement referenceId="A_DOUT_EN_PN" value="R_DATA_EN"/><configurableElement referenceId="A_DOUT_EN_POLARITY" value="2"/><configurableElement referenceId="A_DOUT_SRST_PN" value="R_DATA_SRST_N"/><configurableElement referenceId="A_DOUT_SRST_POLARITY" value="2"/><configurableElement referenceId="A_WBYTE_EN_PN" value="WBYTE_EN"/><configurableElement referenceId="BUSY_FLAG" value="0"/><configurableElement referenceId="BYTE_ENABLE_WIDTH" value="0"/><configurableElement referenceId="BYTEENABLES" value="0"/><configurableElement referenceId="CASCADE" value="0"/><configurableElement referenceId="CLK_EDGE" value="RISE"/><configurableElement referenceId="CLKS" value="1"/><configurableElement referenceId="CLOCK_PN" value="CLK"/><configurableElement referenceId="DATA_IN_PN" value="W_DATA"/><configurableElement referenceId="DATA_OUT_PN" value="R_DATA"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="IMPORT_FILE" value=""/><configurableElement referenceId="INIT_RAM" value="F"/><configurableElement referenceId="LPM_HINT" value="0"/><configurableElement referenceId="LPMTYPE" value="LPM_RAM"/><configurableElement referenceId="PMODE2" value="0"/><configurableElement referenceId="PTYPE" value="1"/><configurableElement referenceId="RADDRESS_PN" value="R_ADDR"/><configurableElement referenceId="RCLK_EDGE" value="RISE"/><configurableElement referenceId="RCLOCK_PN" value="R_CLK"/><configurableElement referenceId="RDEPTH" value="2048"/><configurableElement referenceId="RE_PN" value="R_EN"/><configurableElement referenceId="RE_POLARITY" value="2"/><configurableElement referenceId="RESET_PN" value="R_DATA_ARST_N"/><configurableElement referenceId="RESET_POLARITY" value="2"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SD_EXPORT_HIDDEN_PORTS" value="false"/><configurableElement referenceId="SII_LOCK" value="0"/><configurableElement referenceId="WADDRESS_PN" value="W_ADDR"/><configurableElement referenceId="WCLK_EDGE" value="RISE"/><configurableElement referenceId="WCLOCK_PN" value="W_CLK"/><configurableElement referenceId="WDEPTH" value="2048"/><configurableElement referenceId="WE_PN" value="W_EN"/><configurableElement referenceId="WE_POLARITY" value="1"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>W_EN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_ADDR</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_ADDR</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_DATA</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:42:58 2026
// Created by SmartDesign Fri Apr 17 05:34:26 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
@@ -38,7 +38,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_TPSRAM:1.1.108} -component
"RADDRESS_PN:R_ADDR" \
"RCLK_EDGE:RISE" \
"RCLOCK_PN:R_CLK" \
"RDEPTH:1024" \
"RDEPTH:2048" \
"RE_PN:R_EN" \
"RE_POLARITY:2" \
"RESET_PN:R_DATA_ARST_N" \
@@ -48,7 +48,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_TPSRAM:1.1.108} -component
"WADDRESS_PN:W_ADDR" \
"WCLK_EDGE:RISE" \
"WCLOCK_PN:W_CLK" \
"WDEPTH:1024" \
"WDEPTH:2048" \
"WE_PN:W_EN" \
"WE_POLARITY:1" \
"WWIDTH:32" }
@@ -71,8 +71,8 @@ module PF_TPSRAM_C0(
// Input
//--------------------------------------------------------------------
input CLK;
input [9:0] R_ADDR;
input [9:0] W_ADDR;
input [10:0] R_ADDR;
input [10:0] W_ADDR;
input [31:0] W_DATA;
input W_EN;
//--------------------------------------------------------------------
@@ -83,9 +83,9 @@ output [31:0] R_DATA;
// Nets
//--------------------------------------------------------------------
wire CLK;
wire [9:0] R_ADDR;
wire [10:0] R_ADDR;
wire [31:0] R_DATA_net_0;
wire [9:0] W_ADDR;
wire [10:0] W_ADDR;
wire [31:0] W_DATA;
wire W_EN;
wire [31:0] R_DATA_net_1;

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@@ -20,9 +20,9 @@ Read Clock Edge : Rising
Write Clock Edge : Rising
A_REN Polarity : None
B_REN Polarity : None
Write Depth : 1024
Write Depth : 2048
Write Width : 32
Read Depth : 1024
Read Depth : 2048
Read Width : 32
Portname DataIn : W_DATA
Portname DataOut : R_DATA
@@ -72,9 +72,9 @@ Lock access : Off
ACCESS_BUSY : Disabled
Cascade Configuration:
Write Port configuration : 1024x20
Read Port configuration : 1024x20
Write Port configuration : 2048x10
Read Port configuration : 2048x10
Number of blocks depth wise: 1
Number of blocks width wise: 2
Number of blocks width wise: 4
Wrote Verilog netlist to E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v.

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@@ -12,71 +12,119 @@ module PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM(
);
input [31:0] W_DATA;
output [31:0] R_DATA;
input [9:0] W_ADDR;
input [9:0] R_ADDR;
input [10:0] W_ADDR;
input [10:0] R_ADDR;
input W_EN;
input CLK;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , \ACCESS_BUSY[0][2] ,
\ACCESS_BUSY[0][3] , VCC, GND, ADLIB_VCC;
wire GND_power_net1;
wire VCC_power_net1;
assign GND = GND_power_net1;
assign VCC = VCC_power_net1;
assign ADLIB_VCC = VCC_power_net1;
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 (.A_DOUT({nc0,
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%2%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 (.A_DOUT({nc0,
nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11,
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc12, nc13,
nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23,
nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][2] ), .A_ADDR({
R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6],
R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1],
R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(
CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC)
, .A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8],
W_ADDR[7], W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3],
W_ADDR[2], W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({
W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, W_DATA[23], W_DATA[22],
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
W_DATA[16]}), .B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 (.A_DOUT({nc24,
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 (.A_DOUT({nc32,
nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40, nc41, nc42,
nc43, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8]}), .B_DOUT({nc44,
nc45, nc46, nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54,
nc55, nc56, nc57, nc58, nc59, nc60, nc61, nc62, nc63}),
.DB_DETECT(), .SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ),
.A_ADDR({R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7],
R_ADDR[6], R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2],
R_ADDR[1], R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC,
VCC}), .A_CLK(CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND}), .A_REN(VCC), .A_WEN({GND, GND}), .A_DOUT_EN(VCC),
.A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10],
W_ADDR[9], W_ADDR[8], W_ADDR[7], W_ADDR[6], W_ADDR[5],
W_ADDR[4], W_ADDR[3], W_ADDR[2], W_ADDR[1], W_ADDR[0], GND,
GND, GND}), .B_BLK_EN({W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
W_DATA[15], W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11],
W_DATA[10], W_DATA[9], W_DATA[8]}), .B_REN(VCC), .B_WEN({GND,
VCC}), .B_DOUT_EN(VCC), .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(
VCC), .ECC_EN(GND), .BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}),
.A_WMODE({GND, GND}), .A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC})
, .B_WMODE({GND, GND}), .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 (.A_DOUT({nc64,
nc65, nc66, nc67, nc68, nc69, nc70, nc71, nc72, nc73, nc74,
nc75, R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc76, nc77, nc78,
nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88,
nc89, nc90, nc91, nc92, nc93, nc94, nc95}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6],
R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1],
R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(
CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC)
, .A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8],
W_ADDR[7], W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3],
W_ADDR[2], W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({
W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, W_DATA[7], W_DATA[6],
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
W_DATA[0]}), .B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%3%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 (.A_DOUT({nc96,
nc97, nc98, nc99, nc100, nc101, nc102, nc103, nc104, nc105,
nc106, nc107, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24]}), .B_DOUT({
nc108, nc109, nc110, nc111, nc112, nc113, nc114, nc115, nc116,
nc117, nc118, nc119, nc120, nc121, nc122, nc123, nc124, nc125,
nc126, nc127}), .DB_DETECT(), .SB_CORRECT(), .ACCESS_BUSY(
\ACCESS_BUSY[0][3] ), .A_ADDR({R_ADDR[10], R_ADDR[9],
R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5], R_ADDR[4],
R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND, GND, GND}),
.A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK), .A_DIN({GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND}), .A_REN(VCC), .A_WEN({GND, GND}),
.A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC),
.B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({W_EN, VCC,
VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, W_DATA[31], W_DATA[30], W_DATA[29],
W_DATA[28], W_DATA[27], W_DATA[26], W_DATA[25], W_DATA[24]}),
.B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
GND GND_power_inst1 (.Y(GND_power_net1));
VCC VCC_power_inst1 (.Y(VCC_power_net1));

View File

@@ -30,7 +30,7 @@ PTYPE:1
RADDRESS_PN:R_ADDR
RCLK_EDGE:RISE
RCLOCK_PN:R_CLK
RDEPTH:1024
RDEPTH:2048
RESET_PN:R_DATA_ARST_N
RESET_POLARITY:2
RE_PN:R_EN
@@ -41,7 +41,7 @@ SII_LOCK:0
WADDRESS_PN:W_ADDR
WCLK_EDGE:RISE
WCLOCK_PN:W_CLK
WDEPTH:1024
WDEPTH:2048
WE_PN:W_EN
WE_POLARITY:1
WWIDTH:32

View File

@@ -1,6 +1,6 @@
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 22:42:59 2026
Date : Fri Apr 17 05:34:27 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : PF_TPSRAM_C0
Family : PolarFire

Binary file not shown.

View File

@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:44:24 2026
// Created by SmartDesign Fri Apr 17 08:26:46 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
@@ -107,10 +107,9 @@ wire [31:0] CORETSE_0_MRXDAT;
wire CORETSE_0_MRXEOF;
wire CORETSE_0_MRXRDY;
wire CORETSE_0_MRXSOF;
wire CORETSE_0_MTXACPT;
wire [9:0] CORETSE_0_TCG;
wire fifo_to_tpsram_bridge_0_fifo_rd_en;
wire [9:0] fifo_to_tpsram_bridge_0_ram_w_addr_1;
wire [10:0] fifo_to_tpsram_bridge_0_ram_w_addr_4;
wire [31:0] fifo_to_tpsram_bridge_0_ram_w_data;
wire fifo_to_tpsram_bridge_0_ram_w_en;
wire INBUF_DIFF_0_Y;
@@ -204,7 +203,8 @@ wire [9:0] ANX_STATE_net_0;
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
wire [9:0] R_ADDR_const_net_0;
wire [31:0] MTXDAT_const_net_0;
wire [10:0] R_ADDR_const_net_0;
//--------------------------------------------------------------------
// Inverted Nets
//--------------------------------------------------------------------
@@ -230,7 +230,8 @@ wire [7:0] CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0;
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign R_ADDR_const_net_0 = 10'h000;
assign MTXDAT_const_net_0 = 32'h00000000;
assign R_ADDR_const_net_0 = 11'h000;
//--------------------------------------------------------------------
// Inversions
//--------------------------------------------------------------------
@@ -433,11 +434,11 @@ CORESPI_0 CORESPI_0_0(
CORETSE_0 CORETSE_0_inst_0(
// Inputs
.MTXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MTXRDY ( CORETSE_0_MRXRDY ),
.MTXRDY ( GND_net ),
.MTXSOF ( CORETSE_0_MRXSOF ),
.MTXEOF ( CORETSE_0_MRXEOF ),
.MRXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MRXACPT ( CORETSE_0_MTXACPT ),
.MRXACPT ( VCC_net ),
.TXCLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
.RXCLK ( PF_IOD_CDR_C0_0_RX_CLK_R ),
.TBI_TX_CLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
@@ -449,13 +450,13 @@ CORETSE_0 CORETSE_0_inst_0(
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
.PSEL ( CoreAPB3_0_0_APBmslave0_PSELx ),
.MTXDAT ( CORETSE_0_MRXDAT ),
.MTXDAT ( MTXDAT_const_net_0 ),
.MTXBYTEVALID ( CORETSE_0_MRXBYTEVALID ),
.RCG ( PF_IOD_CDR_C0_0_RX_DATA ),
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR ),
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA ),
// Outputs
.MTXACPT ( CORETSE_0_MTXACPT ),
.MTXACPT ( ),
.MTXHWM ( ),
.MRXRDY ( CORETSE_0_MRXRDY ),
.MRXSOF ( CORETSE_0_MRXSOF ),
@@ -511,7 +512,7 @@ fifo_to_tpsram_bridge fifo_to_tpsram_bridge_0(
.transfer_enable ( VCC_net ),
// Outputs
.fifo_rd_en ( fifo_to_tpsram_bridge_0_fifo_rd_en ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.ram_w_data ( fifo_to_tpsram_bridge_0_ram_w_data ),
.ram_w_en ( fifo_to_tpsram_bridge_0_ram_w_en ),
.buffer_full ( )
@@ -633,7 +634,7 @@ PF_TPSRAM_C0 PF_TPSRAM_C0_0(
.W_EN ( fifo_to_tpsram_bridge_0_ram_w_en ),
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.W_DATA ( fifo_to_tpsram_bridge_0_ram_w_data ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.R_ADDR ( R_ADDR_const_net_0 ),
// Outputs
.R_DATA ( R_DATA_net_0 )

View File

@@ -1,6 +1,6 @@
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 22:44:25 2026
Date : Fri Apr 17 08:26:46 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : top
Family : PolarFire

Binary file not shown.

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View File

@@ -34,7 +34,7 @@
<p>Family: PolarFire</p>
<p>Die: MPF300TS</p>
<p>Package: FCG1152</p>
<p>Date: Wed Apr 15 23:10:40 2026
<p>Date: Fri Apr 17 08:54:46 2026
</p>
<p>Report path: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\Design_Initialization_Data_Report.xml</p>
<h2>

View File

@@ -3,7 +3,7 @@ Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 20
Family: PolarFire
Die: MPF300TS
Package: FCG1152
Date: Wed Apr 15 23:10:41 2026
Date: Fri Apr 17 08:54:47 2026
Report path: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\Design_Initialization_Data_Report.txt

View File

@@ -6,7 +6,7 @@
<text>Family: PolarFire</text>
<text>Die: MPF300TS</text>
<text>Package: FCG1152</text>
<text>Date: Wed Apr 15 23:10:40 2026
<text>Date: Fri Apr 17 08:54:46 2026
</text>
<text>Report path: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\Design_Initialization_Data_Report.xml</text>
<section>

View File

@@ -7,7 +7,7 @@ CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pu
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
@@ -18,14 +18,14 @@ CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sy
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oool1_inst_1,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111_inst_2,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111,0
@@ -38,4 +38,4 @@ CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEC
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo,1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo[0],0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0],1
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0],0
1 Synchronizer SLE From Synchronizer SLE To Manhattan Cluster Distance
7 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 0
8 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo[0] 0
9 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0] 0
10 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0] 0 1
11 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0] 0
12 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 0
13 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 0
18 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 0
19 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 0
20 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 0
21 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 0 1
22 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 0
23 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 0 1
24 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oool1_inst_1 0
25 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1 0
26 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo[0] 0
27 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0] 0
28 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo[0] 1 0
29 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0] 1
30 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111_inst_2 0
31 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111 0
38 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo 1
39 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo 0
40 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo[0] 0
41 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0] CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0] 1 0

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Design name: top
Checksum: 2AAE
Design version: 0
Fabric component bitstream digest: 2023b563fb974c64df85596c3345981f1b545e9900b6d2622fdff17d252bca98
sNVM component bitstream digest: 989b5cdf4f58a2535714ed80d54028dcd50e0d45912036b430907a693bf31fe8
Entire bitstream digest: d180ada8e741bd0eb6975b1d330b1f9ee7a7ea08fc1f248920a9fb4b5e20c6fa

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@@ -1,5 +1,5 @@
;--------------------------------------------------------------------------------
; Date: Wed Apr 15 23:06:44 2026
; Date: Fri Apr 17 08:50:49 2026
; version: 2025.1 2025.1.0.14
; Design: top
; Family: PolarFire

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@@ -1,7 +1,7 @@
Jitter Estimation Report
========================
Date : Wed Apr 15 22:52:38 2026
Date : Fri Apr 17 08:36:42 2026
Libero version : 2025.1.0.14
Design : top
Family : PolarFire

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@@ -1,5 +1,5 @@
# Microchip Technology Inc.
# Date: 2026-Apr-15 22:52:43
# Date: 2026-Apr-17 08:36:48
# This file was generated based on the following SDC source files:
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc
@@ -50,31 +50,31 @@ set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pl
set_clock_uncertainty 0.000992228 [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -rise_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -fall_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PHY_MDC_CLOCK } ] -rise_to [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PHY_MDC_CLOCK } ] -fall_to [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty 0.00483062 [ get_clocks { REFCLK_P } ]
set_clock_uncertainty 0.00478087 [ get_clocks { REFCLK_P } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REFCLK_P } ] -rise_to [ get_clocks { REFCLK_P } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REFCLK_P } ] -fall_to [ get_clocks { REFCLK_P } ]
set_clock_uncertainty 0.00483062 [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REF_CLK_0 } ] -rise_to [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REF_CLK_0 } ] -fall_to [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { TCK } ]
set_clock_uncertainty 0.00478087 [ get_clocks { TCK } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { TCK } ] -rise_to [ get_clocks { TCK } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { TCK } ] -fall_to [ get_clocks { TCK } ]
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]

21
designer/top/run_g4ba.tcl Normal file
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@@ -0,0 +1,21 @@
set_device \
-family PolarFire \
-die PA5M300TS \
-package fcg1152 \
-speed -1 \
-tempr {IND} \
-voltr {IND}
set_def {VOLTAGE} {1.05}
set_def {VCCI_1.2_VOLTR} {IND}
set_def {VCCI_1.5_VOLTR} {IND}
set_def {VCCI_1.8_VOLTR} {IND}
set_def {VCCI_2.5_VOLTR} {IND}
set_def {VCCI_3.3_VOLTR} {IND}
set_operating_conditions -name {slow_lv_lt}
set_operating_conditions -name {slow_lv_ht}
set_operating_conditions -name {fast_hv_lt}
set_name top
set_workdir {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top}
set_filename {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_ba}
set_design_state post_layout
set_language verilog

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@@ -0,0 +1,37 @@
m255
K4
z2
!s11f vlog 2024.3 2024.09, Sep 11 2024
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dE:/AbhishekV/rising/ethernet_tpsram_test/simulation
vtop
2E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
DXx6 sv_std 3 std 0 22 VYECXdT12H8WgbUP_5Y6:3
!s110 1776320922
!i10b 1
!s100 MmMgBAbi>EfF;FM[XVW^i0
I?_;eYkem78a>gmf4c^afP2
S1
R0
w1776320821
8E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
FE:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
!i122 0
L0 6 352821
VDg1SIo80bB@j0V0VzS_@n1
OW;L;2024.3;79
r1
!s85 0
31
!s108 1776320917.000000
!s107 E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v|
!s90 -reportprogress|300|-sv|-work|postlayout|E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v|
!s101 -O0
!i113 1
o-sv -work postlayout -O0
tCvgOpt 0

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@@ -0,0 +1,4 @@
m255
K4
z0
cModel Technology

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@@ -1,5 +1,5 @@
# Microchip Technology Inc.
# Date: 2026-Apr-15 22:44:52
# Date: 2026-Apr-17 08:27:15
# This file was generated based on the following SDC source files:
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc

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@@ -1 +1 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><dca xmlns="http://actel.com/sweng/afi"><format name="Design Configuration and Access" version="01.00"/><creator name="Libero" version="2025.1.0.14"/><date>Wednesday April 15 23:10:53 2026</date><project_name>top</project_name><family>PolarFire</family><device>MPF300TS</device><package>FCG1152</package><fabric_configuration><avionics_mode>0</avionics_mode><enable_uathena>1</enable_uathena><ff_clock_gate_delay>000</ff_clock_gate_delay></fabric_configuration><uic><uic_addr>000000ca</uic_addr><uic_type>3</uic_type><uic_script_timeout>fe</uic_script_timeout><uic_spiclk_div>1</uic_spiclk_div></uic></dca>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><dca xmlns="http://actel.com/sweng/afi"><format name="Design Configuration and Access" version="01.00"/><creator name="Libero" version="2025.1.0.14"/><date>Friday April 17 08:54:59 2026</date><project_name>top</project_name><family>PolarFire</family><device>MPF300TS</device><package>FCG1152</package><fabric_configuration><avionics_mode>0</avionics_mode><enable_uathena>1</enable_uathena><ff_clock_gate_delay>000</ff_clock_gate_delay></fabric_configuration><uic><uic_addr>000000ca</uic_addr><uic_type>3</uic_type><uic_script_timeout>fe</uic_script_timeout><uic_spiclk_div>1</uic_spiclk_div></uic></dca>

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@@ -8,7 +8,7 @@
# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1
# Date generated: Wed Apr 15 22:52:34 2026
# Date generated: Fri Apr 17 08:36:36 2026
#

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@@ -7,4 +7,4 @@ logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_T
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-2 Port_A_Width-6 Port_B_Depth-2 Port_B_Width-6 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-PF_TPSRAM_C0_0/PF_TPSRAM_C0_0 Physical_names-[PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-32 Port_B_Depth-1024 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
logical_instance_name-PF_TPSRAM_C0_0/PF_TPSRAM_C0_0 Physical_names-[PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-2048 Port_A_Width-32 Port_B_Depth-2048 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0

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@@ -1,5 +1,5 @@
********************************************************************
I/O Bank Report - Date: Wed Apr 15 23:06:21 2026
I/O Bank Report - Date: Fri Apr 17 08:50:27 2026
Product: Designer
Release: 2025.1
Version: 2025.1.0.14

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@@ -1,6 +1,6 @@
I/O Register Combining Report
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date: Wed Apr 15 22:52:30 2026
Date: Fri Apr 17 08:36:31 2026
I/O Register Combining Summary
+

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@@ -3,7 +3,7 @@
<doc>
<title>I/O Register Combining Report</title>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 22:52:30 2026
<text>Date: Fri Apr 17 08:36:31 2026
</text>
<section><name>I/O Register Combining Summary</name></section>
<table>

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@@ -13,8 +13,8 @@ Info: Global design data:
Info: Global design data:
Total globals: 4
Globals that cannot be demoted: 3
Globals that cannot be demoted: 3
Globals considered for demotion: 1

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@@ -1,14 +1,14 @@
Detailed Resource Usage
Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,Differential I/O Pairs,uSRAM (64x12),LSRAM (20K),Chip Globals,Row Global,PLL,DLL
COREFIFO_C0_0/COREFIFO_C0_0/Primitives,35,35,0,0,0,0,0,0,0,0,0,0
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/Primitives,76,45,0,0,0,0,0,0,0,0,0,0
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/Primitives,74,45,0,0,0,0,0,0,0,0,0,0
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/Primitives,38,68,0,0,0,0,0,0,0,0,0,0
COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/Primitives,0,0,72,72,0,0,0,2,0,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/Primitives,40,0,0,0,0,0,0,0,2,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/Primitives,114,17,0,0,0,0,0,0,0,0,0,0
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/Primitives,115,17,0,0,0,0,0,0,0,0,0,0
CORESPI_0_0/CORESPI_0_0/USPI/UCC/Primitives,203,168,0,0,0,0,0,0,0,0,0,0
CORESPI_0_0/CORESPI_0_0/USPI/UCC/UCLKMUX1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
CORESPI_0_0/CORESPI_0_0/USPI/UCON/Primitives,14,0,0,0,0,0,0,0,0,0,0,0
@@ -21,22 +21,22 @@ CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/Primitives,0,0,12,12
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/Primitives,0,14,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Primitives,0,20,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Primitives,195,208,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Primitives,190,208,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Primitives,22,18,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Primitives,2,60,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Primitives,262,171,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/Primitives,164,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Primitives,264,121,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/Primitives,152,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Primitives,307,103,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Primitives,181,124,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Primitives,259,171,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/Primitives,169,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Primitives,257,121,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/Primitives,145,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Primitives,306,103,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Primitives,177,124,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/Primitives,1,5,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/Primitives,116,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/Primitives,133,97,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/Primitives,110,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/Primitives,134,97,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/Primitives,1,2,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Primitives,108,108,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Primitives,109,108,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/Primitives,20,24,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/Primitives,12,6,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/Primitives,13,6,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
@@ -54,9 +54,9 @@ CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pul
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/Primitives,0,0,288,288,0,0,0,8,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/Primitives,0,0,144,144,0,0,0,4,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Primitives,115,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Primitives,422,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/Primitives,121,65,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Primitives,589,51,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Primitives,414,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/Primitives,124,65,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Primitives,587,51,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/Primitives,53,25,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/Primitives,52,25,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
@@ -106,54 +106,54 @@ CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sy
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/Primitives,0,10,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Primitives,68,266,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Primitives,209,238,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Primitives,251,303,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Primitives,147,152,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Primitives,211,198,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Primitives,63,266,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Primitives,161,197,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Primitives,253,303,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Primitives,55,98,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Primitives,199,183,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Primitives,116,90,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Primitives,171,230,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Primitives,170,230,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Primitives,82,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Primitives,79,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/Primitives,93,52,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Primitives,5,13,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Primitives,71,222,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Primitives,64,222,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Primitives,195,104,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/Primitives,78,32,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Primitives,416,191,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Primitives,418,191,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Primitives,200,117,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/Primitives,163,32,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Primitives,527,292,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Primitives,528,292,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/Primitives,150,36,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/Primitives,16,0,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
CORETSE_0_inst_0/CORETSE_0_0/i.OI/Primitives,125,104,0,0,0,0,0,0,0,0,0,0
CoreAPB3_0_0/CoreAPB3_0_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/Primitives,11,0,0,0,0,0,0,0,0,0,0,0
CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/Primitives,12,0,0,0,0,0,0,0,0,0,0,0
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/Primitives,27,24,0,0,0,0,0,0,0,0,0,0
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/Primitives,6,9,0,0,0,0,0,0,0,0,0,0
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/Primitives,24,19,0,0,0,0,0,0,0,0,0,0
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/Primitives,67,41,0,0,0,0,0,0,0,0,0,0
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/Primitives,28,21,0,0,0,0,0,0,0,0,0,0
Core_reset_pf_0/Core_reset_pf_0/Primitives,2,16,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/Primitives,35,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/Primitives,154,111,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/Primitives,17,4,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Primitives,416,176,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/Primitives,206,109,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/Primitives,33,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/Primitives,152,111,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/Primitives,18,4,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Primitives,417,176,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/Primitives,200,109,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/Primitives,53,96,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/Primitives,45,80,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/Primitives,46,80,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/Primitives,68,213,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/Primitives,710,166,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/Primitives,712,166,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/Primitives,0,55,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/Primitives,1402,0,648,648,0,0,0,18,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/Primitives,66,3,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/Primitives,61,3,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/Primitives,81,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/Primitives,98,283,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/Primitives,36,20,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/Primitives,100,283,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/Primitives,35,20,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
@@ -161,20 +161,20 @@ MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/g
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/Primitives,139,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/Primitives,73,8,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/Primitives,145,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/Primitives,72,8,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/Primitives,5,3,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/Primitives,373,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/Primitives,392,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/Primitives,66,32,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[0].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[1].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/Primitives,1,30,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/Primitives,3,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/Primitives,34,32,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/Primitives,0,31,0,0,0,0,0,0,0,0,0,0
@@ -188,19 +188,19 @@ MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_cs
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/Primitives,33,32,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/Primitives,66,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/Primitives,11,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/Primitives,3,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/Primitives,9,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/Primitives,2023,202,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/Primitives,1043,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/Primitives,64,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/Primitives,9,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/Primitives,15,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/Primitives,7,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/Primitives,2012,202,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/Primitives,1071,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/Primitives,38,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/Primitives,270,5,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/Primitives,213,215,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/Primitives,202,22,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/Primitives,313,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/Primitives,267,5,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/Primitives,219,215,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/Primitives,193,22,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/Primitives,301,0,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/Primitives,19,29,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/Primitives,13,17,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/Primitives,11,17,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/Primitives,12,1,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/Primitives,13,5,0,0,0,0,0,0,0,0,0,0
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
@@ -209,13 +209,13 @@ MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_s
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
PF_CCC_0_0/PF_CCC_0_0/Primitives,0,0,0,0,0,0,0,0,1,0,1,0
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/Primitives,226,59,0,0,0,0,0,0,0,0,0,0
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/Primitives,0,0,0,0,0,1,0,0,0,0,0,0
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/Primitives,0,0,0,0,0,1,0,0,0,0,0,0
PF_IOD_CDR_C0_0/PF_LANECTRL_0/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
PF_IOD_CDR_C0_0/Primitives,0,0,0,0,0,1,0,0,0,1,0,0
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/Primitives,0,0,0,0,0,0,0,0,0,0,1,1
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/Primitives,30,31,0,0,0,0,0,0,0,0,0,0
PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/Primitives,0,0,72,72,0,0,0,2,0,0,0,0
Primitives/Primitives,3,0,0,0,47,1,0,0,0,0,0,0
PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/Primitives,0,0,144,144,0,0,0,4,0,0,0,0
Primitives/Primitives,4,0,0,0,47,1,0,0,0,0,0,0
SSDetect_0/Primitives,6,2,0,0,0,0,0,0,0,0,0,0
fifo_to_tpsram_bridge_0/Primitives,16,12,0,0,0,0,0,0,0,0,0,0
fifo_to_tpsram_bridge_0/Primitives,46,14,0,0,0,0,0,0,0,0,0,0
1 Detailed Resource Usage
2 Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,Differential I/O Pairs,uSRAM (64x12),LSRAM (20K),Chip Globals,Row Global,PLL,DLL
3 COREFIFO_C0_0/COREFIFO_C0_0/Primitives,35,35,0,0,0,0,0,0,0,0,0,0
4 COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/Primitives,76,45,0,0,0,0,0,0,0,0,0,0 COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/Primitives,74,45,0,0,0,0,0,0,0,0,0,0
5 COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/Primitives,38,68,0,0,0,0,0,0,0,0,0,0
6 COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/Primitives,0,0,72,72,0,0,0,2,0,0,0,0
7 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/Primitives,40,0,0,0,0,0,0,0,2,0,0,0
8 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
9 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
10 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
11 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/Primitives,114,17,0,0,0,0,0,0,0,0,0,0 COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/Primitives,115,17,0,0,0,0,0,0,0,0,0,0
12 CORESPI_0_0/CORESPI_0_0/USPI/UCC/Primitives,203,168,0,0,0,0,0,0,0,0,0,0
13 CORESPI_0_0/CORESPI_0_0/USPI/UCC/UCLKMUX1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
14 CORESPI_0_0/CORESPI_0_0/USPI/UCON/Primitives,14,0,0,0,0,0,0,0,0,0,0,0
21 CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
22 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/Primitives,0,14,0,0,0,0,0,0,0,0,0,0
23 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Primitives,0,20,0,0,0,0,0,0,0,0,0,0
24 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Primitives,195,208,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Primitives,190,208,0,0,0,0,0,0,0,0,0,0
25 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Primitives,22,18,0,0,0,0,0,0,0,0,0,0
26 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Primitives,2,60,0,0,0,0,0,0,0,0,0,0
27 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Primitives,262,171,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Primitives,259,171,0,0,0,0,0,0,0,0,0,0
28 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/Primitives,164,0,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/Primitives,169,0,0,0,0,0,0,0,0,0,0,0
29 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Primitives,264,121,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Primitives,257,121,0,0,0,0,0,0,0,0,0,0
30 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/Primitives,152,0,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/Primitives,145,0,0,0,0,0,0,0,0,0,0,0
31 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Primitives,307,103,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Primitives,306,103,0,0,0,0,0,0,0,0,0,0
32 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Primitives,181,124,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Primitives,177,124,0,0,0,0,0,0,0,0,0,0
33 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/Primitives,1,5,0,0,0,0,0,0,0,0,0,0
34 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/Primitives,116,0,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/Primitives,110,0,0,0,0,0,0,0,0,0,0,0
35 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/Primitives,133,97,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/Primitives,134,97,0,0,0,0,0,0,0,0,0,0
36 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/Primitives,1,2,0,0,0,0,0,0,0,0,0,0
37 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Primitives,108,108,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Primitives,109,108,0,0,0,0,0,0,0,0,0,0
38 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/Primitives,20,24,0,0,0,0,0,0,0,0,0,0
39 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/Primitives,12,6,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/Primitives,13,6,0,0,0,0,0,0,0,0,0,0
40 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
41 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
42 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
54 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/Primitives,0,0,288,288,0,0,0,8,0,0,0,0
55 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/Primitives,0,0,144,144,0,0,0,4,0,0,0,0
56 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Primitives,115,3,0,0,0,0,0,0,0,0,0,0
57 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Primitives,422,0,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Primitives,414,0,0,0,0,0,0,0,0,0,0,0
58 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/Primitives,121,65,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/Primitives,124,65,0,0,0,0,0,0,0,0,0,0
59 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Primitives,589,51,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Primitives,587,51,0,0,0,0,0,0,0,0,0,0
60 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/Primitives,53,25,0,0,0,0,0,0,0,0,0,0
61 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/Primitives,52,25,0,0,0,0,0,0,0,0,0,0
62 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
106 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
107 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
108 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/Primitives,0,10,0,0,0,0,0,0,0,0,0,0
109 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Primitives,68,266,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Primitives,63,266,0,0,0,0,0,0,0,0,0,0
110 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Primitives,209,238,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Primitives,161,197,0,0,0,0,0,0,0,0,0,0
111 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Primitives,251,303,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Primitives,253,303,0,0,0,0,0,0,0,0,0,0
112 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Primitives,147,152,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Primitives,55,98,0,0,0,0,0,0,0,0,0,0
113 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Primitives,211,198,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Primitives,199,183,0,0,0,0,0,0,0,0,0,0
114 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Primitives,116,90,0,0,0,0,0,0,0,0,0,0
115 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
116 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
117 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Primitives,171,230,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Primitives,170,230,0,0,0,0,0,0,0,0,0,0
118 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
119 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Primitives,82,0,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Primitives,79,0,0,0,0,0,0,0,0,0,0,0
120 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/Primitives,93,52,0,0,0,0,0,0,0,0,0,0
121 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Primitives,5,13,0,0,0,0,0,0,0,0,0,0
122 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Primitives,71,222,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Primitives,64,222,0,0,0,0,0,0,0,0,0,0
123 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Primitives,195,104,0,0,0,0,0,0,0,0,0,0
124 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/Primitives,78,32,0,0,0,0,0,0,0,0,0,0
125 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Primitives,416,191,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Primitives,418,191,0,0,0,0,0,0,0,0,0,0
126 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Primitives,200,117,0,0,0,0,0,0,0,0,0,0
127 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/Primitives,163,32,0,0,0,0,0,0,0,0,0,0
128 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Primitives,527,292,0,0,0,0,0,0,0,0,0,0 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Primitives,528,292,0,0,0,0,0,0,0,0,0,0
129 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/Primitives,150,36,0,0,0,0,0,0,0,0,0,0
130 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
131 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/Primitives,16,0,0,0,0,0,0,0,0,0,0,0
132 CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
133 CORETSE_0_inst_0/CORETSE_0_0/i.OI/Primitives,125,104,0,0,0,0,0,0,0,0,0,0
134 CoreAPB3_0_0/CoreAPB3_0_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
135 CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/Primitives,11,0,0,0,0,0,0,0,0,0,0,0 CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/Primitives,12,0,0,0,0,0,0,0,0,0,0,0
136 CoreUARTapb_0_inst_0/CoreUARTapb_0_0/Primitives,27,24,0,0,0,0,0,0,0,0,0,0
137 CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/Primitives,6,9,0,0,0,0,0,0,0,0,0,0
138 CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/Primitives,24,19,0,0,0,0,0,0,0,0,0,0
139 CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/Primitives,67,41,0,0,0,0,0,0,0,0,0,0
140 CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/Primitives,28,21,0,0,0,0,0,0,0,0,0,0
141 Core_reset_pf_0/Core_reset_pf_0/Primitives,2,16,0,0,0,0,0,0,0,0,0,0
142 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/Primitives,35,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/Primitives,33,0,0,0,0,0,0,0,0,0,0,0
143 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/Primitives,154,111,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/Primitives,152,111,0,0,0,0,0,0,0,0,0,0
144 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/Primitives,17,4,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/Primitives,18,4,0,0,0,0,0,0,0,0,0,0
145 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Primitives,416,176,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Primitives,417,176,0,0,0,0,0,0,0,0,0,0
146 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/Primitives,206,109,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/Primitives,200,109,0,0,0,0,0,0,0,0,0,0
147 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/Primitives,53,96,0,0,0,0,0,0,0,0,0,0
148 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/Primitives,45,80,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/Primitives,46,80,0,0,0,0,0,0,0,0,0,0
149 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/Primitives,68,213,0,0,0,0,0,0,0,0,0,0
150 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/Primitives,710,166,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/Primitives,712,166,0,0,0,0,0,0,0,0,0,0
151 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/Primitives,0,55,0,0,0,0,0,0,0,0,0,0
152 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/Primitives,1402,0,648,648,0,0,0,18,0,0,0,0
153 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/Primitives,66,3,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/Primitives,61,3,0,0,0,0,0,0,0,0,0,0
154 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/Primitives,81,0,0,0,0,0,0,0,0,0,0,0
155 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/Primitives,98,283,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/Primitives,100,283,0,0,0,0,0,0,0,0,0,0
156 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/Primitives,36,20,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/Primitives,35,20,0,0,0,0,0,0,0,0,0,0
157 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
158 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
159 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
161 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
162 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
163 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
164 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/Primitives,139,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/Primitives,145,0,0,0,0,0,0,0,0,0,0,0
165 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/Primitives,73,8,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/Primitives,72,8,0,0,0,0,0,0,0,0,0,0
166 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/Primitives,5,3,0,0,0,0,0,0,0,0,0,0
167 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/Primitives,1,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
168 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/Primitives,373,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/Primitives,392,1,0,0,0,0,0,0,0,0,0,0
169 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
170 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/Primitives,0,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
171 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/Primitives,0,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
172 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/Primitives,66,32,0,0,0,0,0,0,0,0,0,0
173 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[0].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
174 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[1].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
175 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/Primitives,1,30,0,0,0,0,0,0,0,0,0,0
176 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
177 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/Primitives,3,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
178 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/Primitives,34,32,0,0,0,0,0,0,0,0,0,0
179 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
180 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/Primitives,0,31,0,0,0,0,0,0,0,0,0,0
188 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/Primitives,33,32,0,0,0,0,0,0,0,0,0,0
189 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
190 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
191 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/Primitives,66,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/Primitives,64,0,0,0,0,0,0,0,0,0,0,0
192 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/Primitives,11,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/Primitives,9,0,0,0,0,0,0,0,0,0,0,0
193 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/Primitives,3,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/Primitives,15,1,0,0,0,0,0,0,0,0,0,0
194 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/Primitives,9,1,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/Primitives,7,1,0,0,0,0,0,0,0,0,0,0
195 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/Primitives,2023,202,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/Primitives,2012,202,0,0,0,0,0,0,0,0,0,0
196 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/Primitives,1043,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/Primitives,1071,0,0,0,0,0,0,0,0,0,0,0
197 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/Primitives,38,0,0,0,0,0,0,0,0,0,0,0
198 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/Primitives,270,5,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/Primitives,267,5,0,0,0,0,0,0,0,0,0,0
199 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/Primitives,213,215,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/Primitives,219,215,0,0,0,0,0,0,0,0,0,0
200 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/Primitives,202,22,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/Primitives,193,22,0,0,0,0,0,0,0,0,0,0
201 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/Primitives,313,0,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/Primitives,301,0,0,0,0,0,0,0,0,0,0,0
202 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/Primitives,19,29,0,0,0,0,0,0,0,0,0,0
203 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/Primitives,13,17,0,0,0,0,0,0,0,0,0,0 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/Primitives,11,17,0,0,0,0,0,0,0,0,0,0
204 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/Primitives,12,1,0,0,0,0,0,0,0,0,0,0
205 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/Primitives,13,5,0,0,0,0,0,0,0,0,0,0
206 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
209 MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
210 PF_CCC_0_0/PF_CCC_0_0/Primitives,0,0,0,0,0,0,0,0,1,0,1,0
211 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/Primitives,226,59,0,0,0,0,0,0,0,0,0,0
212 PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/Primitives,0,0,0,0,0,1,0,0,0,0,0,0 PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/Primitives,0,0,0,0,0,1,0,0,0,0,0,0
213 PF_IOD_CDR_C0_0/PF_LANECTRL_0/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
214 PF_IOD_CDR_C0_0/Primitives,0,0,0,0,0,1,0,0,0,1,0,0
215 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/Primitives,0,0,0,0,0,0,0,0,0,0,1,1
216 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0
217 PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/Primitives,30,31,0,0,0,0,0,0,0,0,0,0
218 PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/Primitives,0,0,72,72,0,0,0,2,0,0,0,0 PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/Primitives,0,0,144,144,0,0,0,4,0,0,0,0
219 Primitives/Primitives,3,0,0,0,47,1,0,0,0,0,0,0 Primitives/Primitives,4,0,0,0,47,1,0,0,0,0,0,0
220 SSDetect_0/Primitives,6,2,0,0,0,0,0,0,0,0,0,0
221 fifo_to_tpsram_bridge_0/Primitives,16,12,0,0,0,0,0,0,0,0,0,0 fifo_to_tpsram_bridge_0/Primitives,46,14,0,0,0,0,0,0,0,0,0,0

View File

@@ -1,6 +1,6 @@
Compile Report
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date: Wed Apr 15 22:52:30 2026
Date: Fri Apr 17 08:36:31 2026
Device Selection
+------------------------+-------------+
@@ -29,8 +29,8 @@ Resource Usage
+-----------------------------+-------+--------+------------+
| Type | Used | Total | Percentage |
+-----------------------------+-------+--------+------------+
| 4LUT | 18889 | 299544 | 6.31 |
| DFF | 8665 | 299544 | 2.89 |
| 4LUT | 18818 | 299544 | 6.28 |
| DFF | 8629 | 299544 | 2.88 |
| User I/O | 53 | 512 | 10.35 |
| -- Single-ended I/O | 47 | 512 | 9.18 |
| -- Differential I/O Pairs | 3 | 256 | 1.17 |
@@ -40,7 +40,7 @@ Resource Usage
| -- Output I/O Flip-Flops | 0 | 512 | 0.00 |
| -- Enable I/O Flip-Flops | 0 | 512 | 0.00 |
| uSRAM | 11 | 2772 | 0.40 |
| LSRAM | 34 | 952 | 3.57 |
| LSRAM | 36 | 952 | 3.78 |
| Math | 0 | 924 | 0.00 |
| H-Chip Global | 4 | 48 | 8.33 |
| Local Global | 1 | 1008 | 0.10 |
@@ -59,24 +59,24 @@ Detailed Logic Resource Usage
+-----------------------+-------+------+
| Type | 4LUT | DFF |
+-----------------------+-------+------+
| Fabric Logic | 17533 | 7309 |
| Fabric Logic | 17390 | 7201 |
| uSRAM Interface Logic | 132 | 132 |
| LSRAM Interface Logic | 1224 | 1224 |
| LSRAM Interface Logic | 1296 | 1296 |
| Math Interface Logic | 0 | 0 |
| Total Used | 18889 | 8665 |
| Total Used | 18818 | 8629 |
+-----------------------+-------+------+
Detailed Carry Chains Resource Usage
+--------+------+
| Length | Used |
| 6 | 3 |
| 7 | 6 |
| 7 | 5 |
| 8 | 11 |
| 9 | 9 |
| 10 | 3 |
| 11 | 3 |
| 12 | 9 |
| 13 | 32 |
| 11 | 2 |
| 12 | 7 |
| 13 | 30 |
| 14 | 8 |
| 15 | 3 |
| 16 | 7 |
@@ -93,16 +93,16 @@ Detailed Carry Chains Resource Usage
| 33 | 4 |
| 64 | 2 |
| 65 | 1 |
| Total | 135 |
| Total | 129 |
+--------+------+
Detailed 4LUT Groups Resource Usage
+--------+------+
| Length | Used |
| 2 | 93 |
| 5 | 5 |
| 2 | 97 |
| 5 | 2 |
| 22 | 1 |
| Total | 99 |
| Total | 100 |
+--------+------+
I/O Function
@@ -120,10 +120,10 @@ Nets assigned to chip global resources
+--------+---------+--------------------------------------------------------------------------------------+
| Fanout | Type | Name |
+--------+---------+--------------------------------------------------------------------------------------+
| 4694 | INT_NET | Net : PF_CCC_0_0_OUT0_FABCLK_0 |
| 4605 | INT_NET | Net : PF_CCC_0_0_OUT0_FABCLK_0 |
| | | Driver: PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1 |
| | | Source: NETLIST |
| 1288 | INT_NET | Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G |
| 1273 | INT_NET | Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G |
| | | Driver: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1 |
| | | Source: NETLIST |
| 205 | INT_NET | Net : COREJTAGDEBUG_C0_0_TGT_TCK_0_i |
@@ -149,7 +149,7 @@ High fanout nets
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
| 1649 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 |
| 939 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
| 943 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
| | | Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0] |
| 492 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1 |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 |
@@ -165,7 +165,7 @@ High fanout nets
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo |
| 283 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1 |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 |
| 244 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
| 247 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 |
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
@@ -175,7 +175,7 @@ High fanout nets (through buffer trees)
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
| 1649 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 |
| 939 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
| 943 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
| | | Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0] |
| 492 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1 |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 |
@@ -191,7 +191,7 @@ High fanout nets (through buffer trees)
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo |
| 283 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1 |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 |
| 244 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
| 247 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 |
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+

View File

@@ -3,7 +3,7 @@
<doc>
<title>Compile Report</title>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 22:52:29 2026
<text>Date: Fri Apr 17 08:36:31 2026
</text>
<section><name>Device Selection</name></section>
<table>
@@ -74,15 +74,15 @@
</header>
<row>
<cell>4LUT</cell>
<cell>18889</cell>
<cell>18818</cell>
<cell>299544</cell>
<cell>6.31</cell>
<cell>6.28</cell>
</row>
<row>
<cell>DFF</cell>
<cell>8665</cell>
<cell>8629</cell>
<cell>299544</cell>
<cell>2.89</cell>
<cell>2.88</cell>
</row>
<row>
<cell>User I/O</cell>
@@ -140,9 +140,9 @@
</row>
<row>
<cell>LSRAM</cell>
<cell>34</cell>
<cell>36</cell>
<cell>952</cell>
<cell>3.57</cell>
<cell>3.78</cell>
</row>
<row>
<cell>Math</cell>
@@ -226,8 +226,8 @@
</header>
<row>
<cell>Fabric Logic</cell>
<cell>17533</cell>
<cell>7309</cell>
<cell>17390</cell>
<cell>7201</cell>
</row>
<row>
<cell>uSRAM Interface Logic</cell>
@@ -236,8 +236,8 @@
</row>
<row>
<cell>LSRAM Interface Logic</cell>
<cell>1224</cell>
<cell>1224</cell>
<cell>1296</cell>
<cell>1296</cell>
</row>
<row>
<cell>Math Interface Logic</cell>
@@ -246,8 +246,8 @@
</row>
<row>
<cell>Total Used</cell>
<cell>18889</cell>
<cell>8665</cell>
<cell>18818</cell>
<cell>8629</cell>
</row>
</table>
<section><name>Detailed Carry Chains Resource Usage</name></section>
@@ -264,7 +264,7 @@
</row>
<row>
<cell>7</cell>
<cell>6</cell>
<cell>5</cell>
</row>
<row>
<cell>8</cell>
@@ -280,15 +280,15 @@
</row>
<row>
<cell>11</cell>
<cell>3</cell>
<cell>2</cell>
</row>
<row>
<cell>12</cell>
<cell>9</cell>
<cell>7</cell>
</row>
<row>
<cell>13</cell>
<cell>32</cell>
<cell>30</cell>
</row>
<row>
<cell>14</cell>
@@ -356,7 +356,7 @@
</row>
<row>
<cell>Total</cell>
<cell>135</cell>
<cell>129</cell>
</row>
</table>
<section><name>Detailed 4LUT Groups Resource Usage</name></section>
@@ -369,11 +369,11 @@
</row>
<row>
<cell>2</cell>
<cell>93</cell>
<cell>97</cell>
</row>
<row>
<cell>5</cell>
<cell>5</cell>
<cell>2</cell>
</row>
<row>
<cell>22</cell>
@@ -381,7 +381,7 @@
</row>
<row>
<cell>Total</cell>
<cell>99</cell>
<cell>100</cell>
</row>
</table>
<section><name>I/O Function</name></section>
@@ -431,7 +431,7 @@
<cell>Name</cell>
</header>
<row>
<cell>4694</cell>
<cell>4605</cell>
<cell>INT_NET</cell>
<cell>Net : PF_CCC_0_0_OUT0_FABCLK_0</cell>
</row>
@@ -446,7 +446,7 @@
<cell>Source: NETLIST</cell>
</row>
<row>
<cell>1288</cell>
<cell>1273</cell>
<cell>INT_NET</cell>
<cell>Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G</cell>
</row>
@@ -532,7 +532,7 @@
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</cell>
</row>
<row>
<cell>939</cell>
<cell>943</cell>
<cell>INT_NET</cell>
<cell>Net : Core_reset_pf_0_Core_reset_pf_0_dff</cell>
</row>
@@ -612,7 +612,7 @@
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</cell>
</row>
<row>
<cell>244</cell>
<cell>247</cell>
<cell>INT_NET</cell>
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</cell>
</row>
@@ -640,7 +640,7 @@
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</cell>
</row>
<row>
<cell>939</cell>
<cell>943</cell>
<cell>INT_NET</cell>
<cell>Net : Core_reset_pf_0_Core_reset_pf_0_dff</cell>
</row>
@@ -720,7 +720,7 @@
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</cell>
</row>
<row>
<cell>244</cell>
<cell>247</cell>
<cell>INT_NET</cell>
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</cell>
</row>

View File

@@ -1,5 +1,5 @@
********************************************************************
Delay Instance Report - Date: Wed Apr 15 23:06:11 2026
Delay Instance Report - Date: Fri Apr 17 08:50:17 2026
Product: Designer
Release: 2025.1
Version: 2025.1.0.14

Binary file not shown.

View File

@@ -6,7 +6,7 @@ The 'open_project' command succeeded.
Info: Programming is already enabled for device 'MPF300TS'.
The 'enable_device' command succeeded.
PPD file 'E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top.ppd' has been loaded successfully.
DESIGN : top; CHECKSUM : 332E; PDB_VERSION : 1.0
DESIGN : top; CHECKSUM : BF33; PDB_VERSION : 1.0
The 'set_programming_file' command succeeded.
The 'set_programming_action' command succeeded.
programmer 'E2008FOFN9' : Scan Chain...
@@ -22,13 +22,13 @@ programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CRCERR[1] = 0
programmer 'E2008FOFN9' : device 'MPF300TS' : Programming Mode: JTAG
programmer 'E2008FOFN9' : device 'MPF300TS' : Programming FPGA Array and sNVM...
programmer 'E2008FOFN9' : device 'MPF300TS' : Calculating component bitstream digests using programming file...
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Fabric component bitstream digest[256] = 3536c84cd7ebd4e18d3b8d737acb9bfbf214a36a0468b786bee6e80299ff4529
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT sNVM component bitstream digest[256] = b3e37a02195dfac353265b684794c7104a80cdf5c7be9a90e72c2dd2b1333ec6
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Entire bitstream digest[256] = 11f02c1686e51e570863d2f5a10232076078baa292ec867fc6e23c051fcd1c22
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Fabric component bitstream digest[256] = 58912ec112d5b4bdbb61b5419f5b71aafcd5e4ee0c3bfc7d75ce24747ed78e83
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT sNVM component bitstream digest[256] = 40d7b621c6846c960a29a4c738a22ba14028e40f2b128c9ffffb0fdb551aadf8
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Entire bitstream digest[256] = cb427091a6fc8a2c9b7c20f8ac0a6c8e9d8ade51581d1aa5d20e1a41706f5f13
programmer 'E2008FOFN9' : device 'MPF300TS' : Reading digests for all the segments from the device...
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CHECK FABRIC digest[256] = 525bdeb65dfa527647dd8e87641760aa9eb22b3b433b56be9ee5a7d6f65bb379
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CC digest[256] = b0a959be4f9a973a07f1c4c8c417d2aaddbfa5318750755490932b913ce9a300
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT SNVM digest[256] = 7c8817fbb43c33e3b14f758e14bc23828035d0a9c8652bb2c0dd9db573b8ed58
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CHECK FABRIC digest[256] = da7db3b8ae2d09853ba0eec551541688fe6ec0b5fe2308819a4c609a6195d1ad
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CC digest[256] = b2d1994cef3583aa2182b161ff57596e5a00131b1700f2210832cd04a3cd949d
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT SNVM digest[256] = 62d58412f997e823348170f6c55841b729f7af62b0a991636763f942e79af2a4
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UL digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST0 digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST1 digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
@@ -43,10 +43,10 @@ programmer 'E2008FOFN9' : device 'MPF300TS' : Please refer to System Services Us
programmer 'E2008FOFN9' : device 'MPF300TS' : ===================================================================================
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT DSN[128] = b6b0660d60864c5c632795558d6e2c8f
programmer 'E2008FOFN9' : device 'MPF300TS' : ===================================================================================
programmer 'E2008FOFN9' : Finished: Wed Apr 15 23:23:12 2026 (Elapsed time 00:01:40)
programmer 'E2008FOFN9' : Finished: Fri Apr 17 16:59:24 2026 (Elapsed time 00:01:42)
programmer 'E2008FOFN9' : device 'MPF300TS' : Executing action PROGRAM PASSED.
programmer 'E2008FOFN9' : Chain programming PASSED.
Chain Programming Finished: Wed Apr 15 23:23:12 2026 (Elapsed time 00:01:40)
Chain Programming Finished: Fri Apr 17 16:59:24 2026 (Elapsed time 00:01:42)
o - o - o - o - o - o

View File

@@ -1,15 +1,15 @@
Software Version: 2025.1.0.14
Opened 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.pro'
PDB file 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.pdb' has been loaded successfully.
DESIGN : top; CHECKSUM : 332E; PDB_VERSION : 1.9
DESIGN : top; CHECKSUM : BF33; PDB_VERSION : 1.9
Info: Programming Interface selected is JTAG.
Info: Design version: 0
File/Folder 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.ppd' will be overwritten.
Successfully exported PPD file for currently secured device: 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.ppd'; file programs Fabric and sNVM.
Fabric component bitstream digest: 3536c84cd7ebd4e18d3b8d737acb9bfbf214a36a0468b786bee6e80299ff4529
sNVM component bitstream digest: b3e37a02195dfac353265b684794c7104a80cdf5c7be9a90e72c2dd2b1333ec6
Entire bitstream digest: 11f02c1686e51e570863d2f5a10232076078baa292ec867fc6e23c051fcd1c22
Finished: Wed Apr 15 23:12:26 2026 (Elapsed time 00:01:25)
Fabric component bitstream digest: 58912ec112d5b4bdbb61b5419f5b71aafcd5e4ee0c3bfc7d75ce24747ed78e83
sNVM component bitstream digest: 40d7b621c6846c960a29a4c738a22ba14028e40f2b128c9ffffb0fdb551aadf8
Entire bitstream digest: cb427091a6fc8a2c9b7c20f8ac0a6c8e9d8ade51581d1aa5d20e1a41706f5f13
Finished: Fri Apr 17 08:56:37 2026 (Elapsed time 00:01:28)
Project saved.
Project closed.

View File

@@ -31,7 +31,7 @@
<body>
<h1 align="center">Global Net Report</h1>
<p>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</p>
<p>Date: Wed Apr 15 23:03:20 2026
<p>Date: Fri Apr 17 08:47:07 2026
</p>
<h2>Global Nets Information</h2>
<table cellpadding="4">
@@ -47,14 +47,14 @@
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</td>
<td>(1154, 162)</td>
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</td>
<td>4694</td>
<td>4605</td>
</tr>
<tr>
<td>2</td>
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</td>
<td>(1153, 162)</td>
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</td>
<td>1288</td>
<td>1273</td>
</tr>
<tr>
<td>3</td>
@@ -88,7 +88,7 @@
<tr>
<td>1</td>
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK:Y</td>
<td>(561, 114)</td>
<td>(634, 117)</td>
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</td>
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/un1_DUT_TCK</td>
<td>ROUTED</td>
@@ -199,7 +199,7 @@
<td>HARDWIRED</td>
<td>1252</td>
<td>(580, 178)</td>
<td>466</td>
<td>603</td>
</tr>
<tr>
<td/>
@@ -209,7 +209,7 @@
<td/>
<td/>
<td>(580, 205)</td>
<td>780</td>
<td>646</td>
</tr>
<tr>
<td/>
@@ -219,7 +219,7 @@
<td/>
<td/>
<td>(580, 232)</td>
<td>6</td>
<td>3</td>
</tr>
</table>
<p/>
@@ -240,10 +240,10 @@
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</td>
<td>(1154, 162)</td>
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</td>
<td>4694</td>
<td>4605</td>
<td>1</td>
<td>(577, 149)</td>
<td>711</td>
<td>27</td>
</tr>
<tr>
<td/>
@@ -253,7 +253,7 @@
<td/>
<td>2</td>
<td>(577, 179)</td>
<td>1015</td>
<td>861</td>
</tr>
<tr>
<td/>
@@ -263,7 +263,7 @@
<td/>
<td>3</td>
<td>(577, 206)</td>
<td>989</td>
<td>1043</td>
</tr>
<tr>
<td/>
@@ -273,7 +273,7 @@
<td/>
<td>4</td>
<td>(577, 233)</td>
<td>169</td>
<td>449</td>
</tr>
<tr>
<td/>
@@ -283,7 +283,7 @@
<td/>
<td>5</td>
<td>(577, 260)</td>
<td>14</td>
<td>113</td>
</tr>
<tr>
<td/>
@@ -292,8 +292,8 @@
<td/>
<td/>
<td>6</td>
<td>(583, 14)</td>
<td>4</td>
<td>(583, 68)</td>
<td>16</td>
</tr>
<tr>
<td/>
@@ -302,8 +302,8 @@
<td/>
<td/>
<td>7</td>
<td>(583, 41)</td>
<td>12</td>
<td>(583, 122)</td>
<td>307</td>
</tr>
<tr>
<td/>
@@ -312,8 +312,8 @@
<td/>
<td/>
<td>8</td>
<td>(583, 95)</td>
<td>8</td>
<td>(583, 149)</td>
<td>681</td>
</tr>
<tr>
<td/>
@@ -322,8 +322,8 @@
<td/>
<td/>
<td>9</td>
<td>(583, 122)</td>
<td>517</td>
<td>(583, 179)</td>
<td>725</td>
</tr>
<tr>
<td/>
@@ -332,8 +332,8 @@
<td/>
<td/>
<td>10</td>
<td>(583, 149)</td>
<td>713</td>
<td>(583, 206)</td>
<td>377</td>
</tr>
<tr>
<td/>
@@ -342,8 +342,8 @@
<td/>
<td/>
<td>11</td>
<td>(583, 179)</td>
<td>498</td>
<td>(583, 233)</td>
<td>4</td>
</tr>
<tr>
<td/>
@@ -352,18 +352,18 @@
<td/>
<td/>
<td>12</td>
<td>(583, 206)</td>
<td>44</td>
<td>(583, 260)</td>
<td>2</td>
</tr>
<tr>
<td>2</td>
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</td>
<td>(1153, 162)</td>
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</td>
<td>1288</td>
<td>1273</td>
<td>1</td>
<td>(579, 147)</td>
<td>302</td>
<td>(579, 177)</td>
<td>802</td>
</tr>
<tr>
<td/>
@@ -372,8 +372,8 @@
<td/>
<td/>
<td>2</td>
<td>(579, 177)</td>
<td>287</td>
<td>(579, 204)</td>
<td>388</td>
</tr>
<tr>
<td/>
@@ -382,18 +382,8 @@
<td/>
<td/>
<td>3</td>
<td>(579, 204)</td>
<td>538</td>
</tr>
<tr>
<td/>
<td/>
<td/>
<td/>
<td/>
<td>4</td>
<td>(579, 231)</td>
<td>161</td>
<td>83</td>
</tr>
<tr>
<td>3</td>
@@ -401,19 +391,9 @@
<td>(1155, 162)</td>
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</td>
<td>205</td>
<td>1</td>
<td>(580, 122)</td>
<td>29</td>
</tr>
<tr>
<td/>
<td/>
<td/>
<td/>
<td/>
<td>2</td>
<td>(586, 122)</td>
<td>176</td>
<td>205</td>
</tr>
<tr>
<td>4</td>
@@ -422,8 +402,8 @@
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</td>
<td>18</td>
<td>1</td>
<td>(576, 93)</td>
<td>15</td>
<td>(576, 120)</td>
<td>1</td>
</tr>
<tr>
<td/>
@@ -432,8 +412,8 @@
<td/>
<td/>
<td>2</td>
<td>(576, 120)</td>
<td>3</td>
<td>(582, 120)</td>
<td>17</td>
</tr>
</table>
<p/>
@@ -446,15 +426,15 @@
</tr>
<tr>
<td>The number of clock signals through Row Global resources</td>
<td>23</td>
<td>21</td>
</tr>
<tr>
<td>The number of clock signals through Sector Global resources</td>
<td>94</td>
<td>86</td>
</tr>
<tr>
<td>The number of clock signals through Cluster Global resources</td>
<td>1075</td>
<td>1080</td>
</tr>
</table>
<p/>

View File

@@ -3,7 +3,7 @@
<doc>
<title>Global Net Report</title>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 23:03:20 2026
<text>Date: Fri Apr 17 08:47:07 2026
</text>
<section>
<name>Global Nets Information</name>
@@ -20,14 +20,14 @@
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</cell>
<cell>(1154, 162)</cell>
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</cell>
<cell>4694</cell>
<cell>4605</cell>
</row>
<row>
<cell>2</cell>
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</cell>
<cell>(1153, 162)</cell>
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</cell>
<cell>1288</cell>
<cell>1273</cell>
</row>
<row>
<cell>3</cell>
@@ -65,7 +65,7 @@
<row>
<cell>1</cell>
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK:Y</cell>
<cell>(561, 114)</cell>
<cell>(634, 117)</cell>
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</cell>
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/un1_DUT_TCK</cell>
<cell>ROUTED</cell>
@@ -182,7 +182,7 @@
<cell>HARDWIRED</cell>
<cell>1252</cell>
<cell>(580, 178)</cell>
<cell>466</cell>
<cell>603</cell>
</row>
<row>
<cell> </cell>
@@ -192,7 +192,7 @@
<cell> </cell>
<cell> </cell>
<cell>(580, 205)</cell>
<cell>780</cell>
<cell>646</cell>
</row>
<row>
<cell> </cell>
@@ -202,7 +202,7 @@
<cell> </cell>
<cell> </cell>
<cell>(580, 232)</cell>
<cell>6</cell>
<cell>3</cell>
</row>
</table>
<text></text>
@@ -225,10 +225,10 @@
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</cell>
<cell>(1154, 162)</cell>
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</cell>
<cell>4694</cell>
<cell>4605</cell>
<cell>1</cell>
<cell>(577, 149)</cell>
<cell>711</cell>
<cell>27</cell>
</row>
<row>
<cell> </cell>
@@ -238,7 +238,7 @@
<cell></cell>
<cell>2</cell>
<cell>(577, 179)</cell>
<cell>1015</cell>
<cell>861</cell>
</row>
<row>
<cell> </cell>
@@ -248,7 +248,7 @@
<cell></cell>
<cell>3</cell>
<cell>(577, 206)</cell>
<cell>989</cell>
<cell>1043</cell>
</row>
<row>
<cell> </cell>
@@ -258,7 +258,7 @@
<cell></cell>
<cell>4</cell>
<cell>(577, 233)</cell>
<cell>169</cell>
<cell>449</cell>
</row>
<row>
<cell> </cell>
@@ -268,7 +268,7 @@
<cell></cell>
<cell>5</cell>
<cell>(577, 260)</cell>
<cell>14</cell>
<cell>113</cell>
</row>
<row>
<cell> </cell>
@@ -277,8 +277,8 @@
<cell></cell>
<cell></cell>
<cell>6</cell>
<cell>(583, 14)</cell>
<cell>4</cell>
<cell>(583, 68)</cell>
<cell>16</cell>
</row>
<row>
<cell> </cell>
@@ -287,8 +287,8 @@
<cell></cell>
<cell></cell>
<cell>7</cell>
<cell>(583, 41)</cell>
<cell>12</cell>
<cell>(583, 122)</cell>
<cell>307</cell>
</row>
<row>
<cell> </cell>
@@ -297,8 +297,8 @@
<cell></cell>
<cell></cell>
<cell>8</cell>
<cell>(583, 95)</cell>
<cell>8</cell>
<cell>(583, 149)</cell>
<cell>681</cell>
</row>
<row>
<cell> </cell>
@@ -307,8 +307,8 @@
<cell></cell>
<cell></cell>
<cell>9</cell>
<cell>(583, 122)</cell>
<cell>517</cell>
<cell>(583, 179)</cell>
<cell>725</cell>
</row>
<row>
<cell> </cell>
@@ -317,8 +317,8 @@
<cell></cell>
<cell></cell>
<cell>10</cell>
<cell>(583, 149)</cell>
<cell>713</cell>
<cell>(583, 206)</cell>
<cell>377</cell>
</row>
<row>
<cell> </cell>
@@ -327,8 +327,8 @@
<cell></cell>
<cell></cell>
<cell>11</cell>
<cell>(583, 179)</cell>
<cell>498</cell>
<cell>(583, 233)</cell>
<cell>4</cell>
</row>
<row>
<cell> </cell>
@@ -337,18 +337,18 @@
<cell></cell>
<cell></cell>
<cell>12</cell>
<cell>(583, 206)</cell>
<cell>44</cell>
<cell>(583, 260)</cell>
<cell>2</cell>
</row>
<row>
<cell>2</cell>
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</cell>
<cell>(1153, 162)</cell>
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</cell>
<cell>1288</cell>
<cell>1273</cell>
<cell>1</cell>
<cell>(579, 147)</cell>
<cell>302</cell>
<cell>(579, 177)</cell>
<cell>802</cell>
</row>
<row>
<cell> </cell>
@@ -357,8 +357,8 @@
<cell></cell>
<cell></cell>
<cell>2</cell>
<cell>(579, 177)</cell>
<cell>287</cell>
<cell>(579, 204)</cell>
<cell>388</cell>
</row>
<row>
<cell> </cell>
@@ -367,18 +367,8 @@
<cell></cell>
<cell></cell>
<cell>3</cell>
<cell>(579, 204)</cell>
<cell>538</cell>
</row>
<row>
<cell> </cell>
<cell></cell>
<cell></cell>
<cell></cell>
<cell></cell>
<cell>4</cell>
<cell>(579, 231)</cell>
<cell>161</cell>
<cell>83</cell>
</row>
<row>
<cell>3</cell>
@@ -386,19 +376,9 @@
<cell>(1155, 162)</cell>
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</cell>
<cell>205</cell>
<cell>1</cell>
<cell>(580, 122)</cell>
<cell>29</cell>
</row>
<row>
<cell> </cell>
<cell></cell>
<cell></cell>
<cell></cell>
<cell></cell>
<cell>2</cell>
<cell>(586, 122)</cell>
<cell>176</cell>
<cell>205</cell>
</row>
<row>
<cell>4</cell>
@@ -407,8 +387,8 @@
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</cell>
<cell>18</cell>
<cell>1</cell>
<cell>(576, 93)</cell>
<cell>15</cell>
<cell>(576, 120)</cell>
<cell>1</cell>
</row>
<row>
<cell> </cell>
@@ -417,8 +397,8 @@
<cell></cell>
<cell></cell>
<cell>2</cell>
<cell>(576, 120)</cell>
<cell>3</cell>
<cell>(582, 120)</cell>
<cell>17</cell>
</row>
</table>
<text></text>
@@ -434,15 +414,15 @@
</row>
<row>
<cell>The number of clock signals through Row Global resources</cell>
<cell>23</cell>
<cell>21</cell>
</row>
<row>
<cell>The number of clock signals through Sector Global resources</cell>
<cell>94</cell>
<cell>86</cell>
</row>
<row>
<cell>The number of clock signals through Cluster Global resources</cell>
<cell>1075</cell>
<cell>1080</cell>
</row>
</table>
<text></text>

View File

@@ -1090,7 +1090,7 @@
00000000000001110000000000000000
10110000000000000000001000000010
00000011000000001010000101001100
00010011100101100000000000000000
00010011000101000000000000000000
00100000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
@@ -2116,9 +2116,9 @@
00000000000000111111010011000100
00000000000000100000000001100011
00000000000000000010000000000111
00110011100101100000000000000000
01000011100101100000000000000000
00010011000100000000000000000000
00110011000101000000000000000000
01000011000101000000000000000000
00010011100101000100000000000000
00100000000000000000000000000000
00000000000000000000000001101111
00000000000000000000010000010000
@@ -3144,9 +3144,9 @@
00000000000000000010000000000001
00000000000000000000000001110011
00000000000000001100000000100000
00110011000100000000000000000000
01000011000100000000000000000000
00010011100100000000000000000000
00110011100101000100000000000000
01000011100101000100000000000000
00010011000100100100000000000000
00100000000000000000000000000000
00000000000000100001110010010011
00000000000000000000100001000111
@@ -4172,9 +4172,9 @@
00000000000000000001010001000111
00000000000000000001110000110111
00000000000000000001100010000001
00110011100100000000000000000000
01000011100100000000000000000000
00010011000100000100000000000000
00110011000100100100000000000000
01000011000100100100000000000000
00010011000101100000000000000000
00100000000000000000000000000000
00000000000000000001110000010011
00000000000000111111110011110111
@@ -5200,9 +5200,9 @@
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00110011000100000100000000000000
01000011000100000100000000000000
00010011000110000000000000000000
00110011000101100000000000000000
01000011000101100000000000000000
00010011100101000000000000000000
00100000000000000000000000000000
00000000000000001001110010000011
00000000000000111111010010000100
@@ -6228,8 +6228,8 @@
00000000000000000000000011100111
00000000000000000001110010110111
00000000000000011000000000000000
00110011000110000000000000000000
01000011000110000000000000000000
00110011100101000000000000000000
01000011100101000000000000000000
11000000000001100000000000000000
00000000000000000000000100000001
10110000000000100000001000000000

View File

@@ -1139,7 +1139,7 @@ STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00111001011000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001010000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -2168,14 +2168,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x20063
WORD-0x02007
INIT_LSRAM ID-00111001011000 ID_MASK-00000000000000
INIT_LSRAM ID-00110001010000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001011000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001010000 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001000000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00111001010001 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -3204,14 +3204,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x00073
WORD-0x0C020
INIT_LSRAM ID-00110001000000 ID_MASK-00000000000000
INIT_LSRAM ID-00111001010001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001000000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001010001 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00111001000000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001001001 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -4240,14 +4240,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x01C37
WORD-0x01881
INIT_LSRAM ID-00111001000000 ID_MASK-00000000000000
INIT_LSRAM ID-00110001001001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001000000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001001001 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001000001 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001011000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -5276,14 +5276,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x00000
WORD-0x00000
INIT_LSRAM ID-00110001000001 ID_MASK-00000000000000
INIT_LSRAM ID-00110001011000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001000001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001011000 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001100000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00111001010000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -6312,9 +6312,9 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x01CB7
WORD-0x18000
INIT_LSRAM ID-00110001100000 ID_MASK-00000000000000
INIT_LSRAM ID-00111001010000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001100000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001010000 ID_MASK-00000000000000
// SRAM_INIT_FROM_SNVM_DONE.
BITWISE_LOAD DEST_ACC_ID-0x0

View File

@@ -1,6 +1,6 @@
;----------------------------------------------------------------------------------
; Register Lock Bits Configuration File for peripheral blocks
; Date: Wed Apr 15 23:06:44 2026
; Date: Fri Apr 17 08:50:49 2026
; Version: 2025.1 2025.1.0.14
; Design: top
; Family: PolarFire

View File

@@ -1,7 +1,7 @@
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00111001011000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001010000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -1030,14 +1030,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x20063
WORD-0x02007
INIT_LSRAM ID-00111001011000 ID_MASK-00000000000000
INIT_LSRAM ID-00110001010000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001011000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001010000 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001000000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00111001010001 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -2066,14 +2066,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x00073
WORD-0x0C020
INIT_LSRAM ID-00110001000000 ID_MASK-00000000000000
INIT_LSRAM ID-00111001010001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001000000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001010001 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00111001000000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001001001 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -3102,14 +3102,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x01C37
WORD-0x01881
INIT_LSRAM ID-00111001000000 ID_MASK-00000000000000
INIT_LSRAM ID-00110001001001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001000000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001001001 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001000001 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00110001011000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -4138,14 +4138,14 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x00000
WORD-0x00000
INIT_LSRAM ID-00110001000001 ID_MASK-00000000000000
INIT_LSRAM ID-00110001011000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001000001 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001011000 ID_MASK-00000000000000
// LSRAM memory file initialization for instance MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP
TAKEOVER_LSRAM ID-00110001100000 ID_MASK-00000000000000
TAKEOVER_LSRAM ID-00111001010000 ID_MASK-00000000000000
// Filling contents of mem file to sram buffer
FILL_SRAM_BUFFER SRAM_TYPE-0
@@ -5174,9 +5174,9 @@ FILL_SRAM_BUFFER SRAM_TYPE-0
WORD-0x01CB7
WORD-0x18000
INIT_LSRAM ID-00110001100000 ID_MASK-00000000000000
INIT_LSRAM ID-00111001010000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00110001100000 ID_MASK-00000000000000
HANDOVER_LSRAM ID-00111001010000 ID_MASK-00000000000000
// SRAM_INIT_FROM_SNVM_DONE.
BITWISE_LOAD DEST_ACC_ID-0x0

View File

@@ -1,4 +1,4 @@
00010011100101100000000000000000
00010011000101000000000000000000
00100000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
@@ -1024,9 +1024,9 @@
00000000000000111111010011000100
00000000000000100000000001100011
00000000000000000010000000000111
00110011100101100000000000000000
01000011100101100000000000000000
00010011000100000000000000000000
00110011000101000000000000000000
01000011000101000000000000000000
00010011100101000100000000000000
00100000000000000000000000000000
00000000000000000000000001101111
00000000000000000000010000010000
@@ -2052,9 +2052,9 @@
00000000000000000010000000000001
00000000000000000000000001110011
00000000000000001100000000100000
00110011000100000000000000000000
01000011000100000000000000000000
00010011100100000000000000000000
00110011100101000100000000000000
01000011100101000100000000000000
00010011000100100100000000000000
00100000000000000000000000000000
00000000000000100001110010010011
00000000000000000000100001000111
@@ -3080,9 +3080,9 @@
00000000000000000001010001000111
00000000000000000001110000110111
00000000000000000001100010000001
00110011100100000000000000000000
01000011100100000000000000000000
00010011000100000100000000000000
00110011000100100100000000000000
01000011000100100100000000000000
00010011000101100000000000000000
00100000000000000000000000000000
00000000000000000001110000010011
00000000000000111111110011110111
@@ -4108,9 +4108,9 @@
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00110011000100000100000000000000
01000011000100000100000000000000
00010011000110000000000000000000
00110011000101100000000000000000
01000011000101100000000000000000
00010011100101000000000000000000
00100000000000000000000000000000
00000000000000001001110010000011
00000000000000111111010010000100
@@ -5136,8 +5136,8 @@
00000000000000000000000011100111
00000000000000000001110010110111
00000000000000011000000000000000
00110011000110000000000000000000
01000011000110000000000000000000
00110011100101000000000000000000
01000011100101000000000000000000
11000000000001100000000000000000
00000000000000000000000100000001
10110000000000100000001000000000

Binary file not shown.

View File

@@ -1,58 +1,58 @@
# Version: 1.0
# pin_name pad_name function_name pin_type port_name macro_cell
n18adp0b423 AJ1 HSIO164PB0 REG R_DATA[6] ADLIB:OUTBUF
n52adp0b389 AJ5 HSIO147PB0/DQS REG R_DATA[6] ADLIB:OUTBUF
s150adp6b134 E25 HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 REG REF_CLK_0 ADLIB:INBUF
s164adp6b148 D25 HSIO70PB6/CCC_SE_PLL1_OUT1 REG LINK_OK ADLIB:OUTBUF
s96adp6b80 J20 HSIO36PB6 REG SPISS ADLIB:OUTBUF
w78amp4b503 Y12 GPIO204PB4 REG PHY_MDC ADLIB:OUTBUF
n34adp0b407 AE8 HSIO156PB0 REG R_DATA[19] ADLIB:OUTBUF
n44adp0b397 AD13 HSIO151PB0 REG R_DATA[19] ADLIB:OUTBUF
s134adp6b118 K22 HSIO55PB6 REG RESET_N ADLIB:INBUF
s105adn6b88 L20 HSIO40NB6 REG SPISDI ADLIB:INBUF
s99adn6b82 G17 HSIO37NB6 REG TX ADLIB:OUTBUF
n32adp0b409 AE7 HSIO157PB0 REG R_DATA[23] ADLIB:OUTBUF
n47adn0b395 AD11 HSIO150NB0 REG R_DATA[23] ADLIB:OUTBUF
s153adn6b136 F22 HSIO64NB6 REG RD_BC_ERROR ADLIB:OUTBUF
s98adp6b82 H18 HSIO37PB6 REG RX ADLIB:INBUF
s104adp6b88 K20 HSIO40PB6 REG SPISDO ADLIB:OUTBUF
w75amn4b507 U11 GPIO206NB4 REG PHY_RST ADLIB:OUTBUF
n28adp0b413 AG7 HSIO159PB0/DQS REG R_DATA[11] ADLIB:OUTBUF
n20adp0b421 AH4 HSIO163PB0 REG R_DATA[7] ADLIB:OUTBUF
n46adp0b395 AE11 HSIO150PB0 REG R_DATA[24] ADLIB:OUTBUF
n31adn0b411 AG9 HSIO158NB0 REG R_DATA[12] ADLIB:OUTBUF
n15adn0b427 AH2 HSIO166NB0 REG R_DATA[10] ADLIB:OUTBUF
n23adn0b419 AL2 HSIO162NB0 REG R_DATA[2] ADLIB:OUTBUF
n38adp0b403 AG10 HSIO154PB0 REG R_DATA[11] ADLIB:OUTBUF
n48adp0b393 AH6 HSIO149PB0 REG R_DATA[7] ADLIB:OUTBUF
n37adn0b405 AF12 HSIO155NB0 REG R_DATA[24] ADLIB:OUTBUF
n40adp0b401 AE13 HSIO153PB0/DQS REG R_DATA[12] ADLIB:OUTBUF
n39adn0b403 AF10 HSIO154NB0 REG R_DATA[10] ADLIB:OUTBUF
n59adn0b383 AK8 HSIO144NB0 REG R_DATA[2] ADLIB:OUTBUF
w74amp4b507 U12 GPIO206PB4 REG coma_mode ADLIB:OUTBUF
w108amp4b473 AA10 GPIO189PB4 REG REF_CLK_SEL ADLIB:OUTBUF
w62amp4b519 U2 GPIO212PB4 REG RX_P ADLIB:INBUF_DIFF
w63amn4b519 U1 GPIO212NB4 REG RX_N ADLIB:INBUF_DIFF
n40adp0b401 AE13 HSIO153PB0/DQS REG R_DATA[29] ADLIB:OUTBUF
n26adp0b415 AD6 HSIO160PB0 REG R_DATA[4] ADLIB:OUTBUF
n21adn0b421 AJ4 HSIO163NB0 REG R_DATA[15] ADLIB:OUTBUF
n30adp0b411 AF9 HSIO158PB0 REG R_DATA[0] ADLIB:OUTBUF
n38adp0b403 AG10 HSIO154PB0 REG R_DATA[18] ADLIB:OUTBUF
n24adp0b417 AD9 HSIO161PB0 REG R_DATA[9] ADLIB:OUTBUF
w67amn4b515 V2 GPIO210NB4 REG TX_N ADLIB:OUTBUF_DIFF
n32adp0b409 AE7 HSIO157PB0 REG R_DATA[29] ADLIB:OUTBUF
n58adp0b383 AK7 HSIO144PB0/CLKIN_N_5 REG R_DATA[4] ADLIB:OUTBUF
n43adn0b399 AE10 HSIO152NB0 REG R_DATA[15] ADLIB:OUTBUF
n55adn0b387 AH9 HSIO146NB0 REG R_DATA[0] ADLIB:OUTBUF
n45adn0b397 AD14 HSIO151NB0 REG R_DATA[18] ADLIB:OUTBUF
n41adn0b401 AF13 HSIO153NB0/DQS REG R_DATA[9] ADLIB:OUTBUF
w66amp4b515 V1 GPIO210PB4 REG TX_P ADLIB:OUTBUF_DIFF
n33adn0b409 AF7 HSIO157NB0 REG R_DATA[16] ADLIB:OUTBUF
n47adn0b395 AD11 HSIO150NB0 REG R_DATA[21] ADLIB:OUTBUF
n44adp0b397 AD13 HSIO151PB0 REG R_DATA[17] ADLIB:OUTBUF
w57amn4b525 U5 GPIO215NB4 REG REFCLK_N ADLIB:INBUF_DIFF
w67amn4b515 V2 GPIO210NB4 REG TX_N ADLIB:OUTBUF_DIFF
n51adn0b391 AJ8 HSIO148NB0 REG R_DATA[16] ADLIB:OUTBUF
n42adp0b399 AD10 HSIO152PB0 REG R_DATA[21] ADLIB:OUTBUF
n46adp0b395 AE11 HSIO150PB0 REG R_DATA[17] ADLIB:OUTBUF
w56amp4b525 U4 GPIO215PB4/CLKIN_W_5/CCC_NW_CLKIN_W_5 REG REFCLK_P ADLIB:INBUF_DIFF
w57amn4b525 U5 GPIO215NB4 REG REFCLK_N ADLIB:INBUF_DIFF
w79amn4b503 Y13 GPIO204NB4 REG PHY_MDIO ADLIB:BIBUF
n41adn0b401 AF13 HSIO153NB0/DQS REG R_DATA[22] ADLIB:OUTBUF
n43adn0b399 AE10 HSIO152NB0 REG R_DATA[20] ADLIB:OUTBUF
n16adp0b425 AK3 HSIO165PB0/DQS REG R_DATA[8] ADLIB:OUTBUF
n25adn0b417 AD8 HSIO161NB0 REG R_DATA[5] ADLIB:OUTBUF
n19adn0b423 AK1 HSIO164NB0 REG R_DATA[3] ADLIB:OUTBUF
n49adn0b393 AH7 HSIO149NB0 REG R_DATA[22] ADLIB:OUTBUF
n53adn0b389 AJ6 HSIO147NB0/DQS REG R_DATA[20] ADLIB:OUTBUF
n31adn0b411 AG9 HSIO158NB0 REG R_DATA[8] ADLIB:OUTBUF
n54adp0b387 AH8 HSIO146PB0/CLKIN_N_4 REG R_DATA[5] ADLIB:OUTBUF
n56adp0b385 AK5 HSIO145PB0 REG R_DATA[3] ADLIB:OUTBUF
s101adn6b84 K21 HSIO38NB6/DQS REG SPISCLKO ADLIB:OUTBUF
n29adn0b413 AG6 HSIO159NB0/DQS REG R_DATA[13] ADLIB:OUTBUF
n39adn0b403 AF10 HSIO154NB0 REG R_DATA[25] ADLIB:OUTBUF
n35adn0b407 AF8 HSIO156NB0 REG R_DATA[28] ADLIB:OUTBUF
n45adn0b397 AD14 HSIO151NB0 REG R_DATA[31] ADLIB:OUTBUF
n27adn0b415 AE6 HSIO160NB0 REG R_DATA[1] ADLIB:OUTBUF
n22adp0b419 AK2 HSIO162PB0 REG R_DATA[14] ADLIB:OUTBUF
n37adn0b405 AF12 HSIO155NB0 REG R_DATA[26] ADLIB:OUTBUF
n42adp0b399 AD10 HSIO152PB0 REG R_DATA[27] ADLIB:OUTBUF
n36adp0b405 AE12 HSIO155PB0 REG R_DATA[30] ADLIB:OUTBUF
n35adn0b407 AF8 HSIO156NB0 REG R_DATA[13] ADLIB:OUTBUF
n36adp0b405 AE12 HSIO155PB0 REG R_DATA[25] ADLIB:OUTBUF
n28adp0b413 AG7 HSIO159PB0/DQS REG R_DATA[28] ADLIB:OUTBUF
n33adn0b409 AF7 HSIO157NB0 REG R_DATA[31] ADLIB:OUTBUF
n50adp0b391 AJ9 HSIO148PB0 REG R_DATA[1] ADLIB:OUTBUF
n30adp0b411 AF9 HSIO158PB0 REG R_DATA[14] ADLIB:OUTBUF
n34adp0b407 AE8 HSIO156PB0 REG R_DATA[26] ADLIB:OUTBUF
n29adn0b413 AG6 HSIO159NB0/DQS REG R_DATA[27] ADLIB:OUTBUF
n26adp0b415 AD6 HSIO160PB0 REG R_DATA[30] ADLIB:OUTBUF
jtag_tck J10 TCK RES TCK NULL
jtag_trstb N14 TRSTB RES TRSTB NULL
jtag_tdi K11 TDI RES TDI NULL
@@ -367,19 +367,19 @@ n63adn0b379 AN2 HSIO142NB0
n62adp0b379 AN1 HSIO142PB0 REG NULL NULL
n61adn0b381 AM2 HSIO143NB0 REG NULL NULL
n60adp0b381 AM1 HSIO143PB0 REG NULL NULL
n59adn0b383 AK8 HSIO144NB0 REG NULL NULL
n58adp0b383 AK7 HSIO144PB0/CLKIN_N_5 REG NULL NULL
n57adn0b385 AK6 HSIO145NB0 REG NULL NULL
n56adp0b385 AK5 HSIO145PB0 REG NULL NULL
n55adn0b387 AH9 HSIO146NB0 REG NULL NULL
n54adp0b387 AH8 HSIO146PB0/CLKIN_N_4 REG NULL NULL
n53adn0b389 AJ6 HSIO147NB0/DQS REG NULL NULL
n52adp0b389 AJ5 HSIO147PB0/DQS REG NULL NULL
n51adn0b391 AJ8 HSIO148NB0 REG NULL NULL
n50adp0b391 AJ9 HSIO148PB0 REG NULL NULL
n49adn0b393 AH7 HSIO149NB0 REG NULL NULL
n48adp0b393 AH6 HSIO149PB0 REG NULL NULL
n27adn0b415 AE6 HSIO160NB0 REG NULL NULL
n25adn0b417 AD8 HSIO161NB0 REG NULL NULL
n24adp0b417 AD9 HSIO161PB0 REG NULL NULL
n23adn0b419 AL2 HSIO162NB0 REG NULL NULL
n22adp0b419 AK2 HSIO162PB0 REG NULL NULL
n21adn0b421 AJ4 HSIO163NB0 REG NULL NULL
n20adp0b421 AH4 HSIO163PB0 REG NULL NULL
n19adn0b423 AK1 HSIO164NB0 REG NULL NULL
n18adp0b423 AJ1 HSIO164PB0 REG NULL NULL
n17adn0b425 AL3 HSIO165NB0/DQS REG NULL NULL
n16adp0b425 AK3 HSIO165PB0/DQS REG NULL NULL
n15adn0b427 AH2 HSIO166NB0 REG NULL NULL
n14adp0b427 AH1 HSIO166PB0 REG NULL NULL
n13adn0b429 AJ3 HSIO167NB0 REG NULL NULL
n12adp0b429 AH3 HSIO167PB0 REG NULL NULL

View File

@@ -4,7 +4,7 @@
<title>Combinational Loop Report</title>
<text>SmartTime Version 2025.1.0.14</text>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 22:53:22 2026
<text>Date: Fri Apr 17 08:37:31 2026
</text>
<table>
<header>

View File

@@ -1,6 +1,6 @@
I/O Register Combining Report
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date: Wed Apr 15 23:06:21 2026
Date: Fri Apr 17 08:50:27 2026
I/O Register Combining Summary
+

View File

@@ -3,7 +3,7 @@
<doc>
<title>I/O Register Combining Report</title>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 23:06:21 2026
<text>Date: Fri Apr 17 08:50:27 2026
</text>
<section><name>I/O Register Combining Summary</name></section>
<table>

View File

@@ -28,10 +28,10 @@ Info: I/O Bank and Globals Assigner identified bank 'Bank4' as being fixed at V
INFO: Reading User PDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\io\io_constraints.pdc. 0 error(s) and 0 warning(s)
Running Timing based Global Demotion.
Demoted 0 global pins.
@@ -46,29 +46,29 @@ CDC Report:
Info: I/O Bank and Globals Assigner identified bank 'Bank4' as being fixed at VCCI:2.50V VCCR:n/a
Info: I/O Bank and Globals Assigner detected (1) out of (7) I/O Bank(s) with locked I/O technologies.
Info: I/O Bank and Globals Assigner detected (1) out of (7) I/O Bank(s) with locked I/O technologies.
I/O Bank and Globals Assigner completed successfully.
Total time spent in I/O Bank and Globals Assigner: 9 seconds
Placer V5.0 - 2025.1.0
Design: top Started: Wed Apr 15 22:53:55 2026
Design: top Started: Fri Apr 17 08:38:08 2026
Initializing High-Effort Timing-Driven Placement ...
Initializing High-Effort Timing-Driven Placement ...
Clustering ...
@@ -79,9 +79,9 @@ Resource Usage
CDC Report:
CDC Report:
Total number of CDC synchronizer driver/sink pairs : 40

View File

@@ -1,6 +1,6 @@
Device Selection
Report Version,Date,Product,Release,Version,Design Name,Family,Die,Package
0.1,Wed Apr 15 23:06:21 2026,Designer,2025.1,2025.1.0.14,top,PolarFire,MPF300TS,FCG1152
0.1,Fri Apr 17 08:50:27 2026,Designer,2025.1,2025.1.0.14,top,PolarFire,MPF300TS,FCG1152
Pin Report
Pin,Port,Function,Bank,State,I/O Std,Direction,Used I/O Reg,User I/O Lock Down,Clamp Diode,Resistor Pull,Use I/O Calibration from the lane,Schmitt Trigger,Vcm Input Range,On Die Termination,Odt Value (Ohm),Input Delay,Slew,Output Drive (mA),Impedance (ohm),Output Load (pF),Source Termination (Ohm),Output Delay,Board Layout
A2,---,GPIO251PB2,Bank2,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI2 through resistor (10K ohm) is allowed. CLAMP=OFF"
@@ -142,15 +142,15 @@ AD2,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---
AD3,---,GPIO174NB4,Bank4,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF"
AD4,---,GPIO180PB4/CLKIN_W_6/CCC_NW_CLKIN_W_6/CCC_NW_PLL0_OUT1,Bank4,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF"
AD5,---,GPIO180NB4,Bank4,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF"
AD6,R_DATA[4],HSIO160PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[4]
AD6,R_DATA[30],HSIO160PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[30]
AD7,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AD8,R_DATA[5],HSIO161NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[5]
AD9,R_DATA[9],HSIO161PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[9]
AD10,R_DATA[27],HSIO152PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[27]
AD11,R_DATA[21],HSIO150NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[21]
AD8,---,HSIO161NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AD9,---,HSIO161PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AD10,R_DATA[21],HSIO152PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[21]
AD11,R_DATA[23],HSIO150NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[23]
AD12,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AD13,R_DATA[17],HSIO151PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[17]
AD14,R_DATA[31],HSIO151NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[31]
AD13,R_DATA[19],HSIO151PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[19]
AD14,R_DATA[18],HSIO151NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[18]
AD15,---,HSIO131PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AD16,---,HSIO129NB7/DQS,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AD17,---,HSIO127PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
@@ -176,14 +176,14 @@ AE2,---,HSIO171PB0/DQS/CCC_NW_PLL1_OUT0,Bank0,Unassigned,---,---,---,---,---,---
AE3,---,HSIO172PB0/CCC_NW_CLKIN_N_1,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AE4,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AE5,---,HSIO173PB0/CCC_NW_CLKIN_N_0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AE6,R_DATA[1],HSIO160NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[1]
AE7,R_DATA[23],HSIO157PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[23]
AE8,R_DATA[19],HSIO156PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[19]
AE6,---,HSIO160NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AE7,R_DATA[29],HSIO157PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[29]
AE8,R_DATA[26],HSIO156PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[26]
AE9,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AE10,R_DATA[20],HSIO152NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[20]
AE11,R_DATA[24],HSIO150PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[24]
AE12,R_DATA[30],HSIO155PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[30]
AE13,R_DATA[29],HSIO153PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[29]
AE10,R_DATA[15],HSIO152NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[15]
AE11,R_DATA[17],HSIO150PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[17]
AE12,R_DATA[25],HSIO155PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[25]
AE13,R_DATA[12],HSIO153PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[12]
AE14,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AE15,---,HSIO131NB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AE16,---,HSIO129PB7/DQS,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
@@ -211,13 +211,13 @@ AF3,---,HSIO169NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,
AF4,---,HSIO172NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AF5,---,HSIO173NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AF6,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AF7,R_DATA[16],HSIO157NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[16]
AF8,R_DATA[28],HSIO156NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[28]
AF9,R_DATA[0],HSIO158PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[0]
AF10,R_DATA[25],HSIO154NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[25]
AF7,R_DATA[31],HSIO157NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[31]
AF8,R_DATA[13],HSIO156NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[13]
AF9,R_DATA[14],HSIO158PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[14]
AF10,R_DATA[10],HSIO154NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[10]
AF11,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AF12,R_DATA[26],HSIO155NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[26]
AF13,R_DATA[22],HSIO153NB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[22]
AF12,R_DATA[24],HSIO155NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[24]
AF13,R_DATA[9],HSIO153NB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[9]
AF14,---,HSIO130PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AF15,---,HSIO128PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AF16,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
@@ -244,11 +244,11 @@ AG2,---,HSIO168NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,
AG3,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AG4,---,HSIO170PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2/CCC_NW_PLL1_OUT0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AG5,---,HSIO170NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AG6,R_DATA[13],HSIO159NB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[13]
AG7,R_DATA[11],HSIO159PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[11]
AG6,R_DATA[27],HSIO159NB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[27]
AG7,R_DATA[28],HSIO159PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[28]
AG8,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AG9,R_DATA[12],HSIO158NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[12]
AG10,R_DATA[18],HSIO154PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[18]
AG9,R_DATA[8],HSIO158NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[8]
AG10,R_DATA[11],HSIO154PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[11]
AG11,---,HSIO137PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AG12,---,HSIO136PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AG13,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
@@ -274,14 +274,14 @@ AG32,---,XCVR_2_RX2_N,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,-
AG33,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AG34,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AH1,---,HSIO166PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH2,R_DATA[10],HSIO166NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[10]
AH2,---,HSIO166NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH3,---,HSIO167PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH4,R_DATA[7],HSIO163PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[7]
AH4,---,HSIO163PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH5,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AH6,---,HSIO149PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH7,---,HSIO149NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH8,---,HSIO146PB0/CLKIN_N_4,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH9,---,HSIO146NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH6,R_DATA[7],HSIO149PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[7]
AH7,R_DATA[22],HSIO149NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[22]
AH8,R_DATA[5],HSIO146PB0/CLKIN_N_4,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[5]
AH9,R_DATA[0],HSIO146NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[0]
AH10,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AH11,---,HSIO137NB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AH12,---,HSIO136NB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
@@ -307,15 +307,15 @@ AH31,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,--
AH32,---,VDDA,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Must connect VDDA directly to 1.0v/1.05v, or to VSS through resistor (10K ohm). For PolarFire CORE devices: Must connect VDDA to VSS through resistor (10K ohm)"
AH33,---,XCVR_2_TX3_P,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined"
AH34,---,XCVR_2_TX3_N,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined"
AJ1,R_DATA[6],HSIO164PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[6]
AJ1,---,HSIO164PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ2,---,VDDI0,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,1.8v
AJ3,---,HSIO167NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ4,R_DATA[15],HSIO163NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[15]
AJ5,---,HSIO147PB0/DQS,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ6,---,HSIO147NB0/DQS,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ4,---,HSIO163NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ5,R_DATA[6],HSIO147PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[6]
AJ6,R_DATA[20],HSIO147NB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[20]
AJ7,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AJ8,---,HSIO148NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ9,---,HSIO148PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ8,R_DATA[16],HSIO148NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[16]
AJ9,R_DATA[1],HSIO148PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[1]
AJ10,---,HSIO134PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ11,---,HSIO134NB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AJ12,---,VDDI7,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Must connect VDDI7 directly to 1.2v/1.5v/1.8v, or to VSS through resistor (10K ohm)"
@@ -341,14 +341,14 @@ AJ31,---,NC,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---
AJ32,---,NC,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (100K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined"
AJ33,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AJ34,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AK1,R_DATA[3],HSIO164NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[3]
AK2,R_DATA[14],HSIO162PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[14]
AK3,R_DATA[8],HSIO165PB0/DQS,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[8]
AK1,---,HSIO164NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK2,---,HSIO162PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK3,---,HSIO165PB0/DQS,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK4,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AK5,---,HSIO145PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK5,R_DATA[3],HSIO145PB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[3]
AK6,---,HSIO145NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK7,---,HSIO144PB0/CLKIN_N_5,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK8,---,HSIO144NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK7,R_DATA[4],HSIO144PB0/CLKIN_N_5,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[4]
AK8,R_DATA[2],HSIO144NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[2]
AK9,---,VDDI7,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Must connect VDDI7 directly to 1.2v/1.5v/1.8v, or to VSS through resistor (10K ohm)"
AK10,---,HSIO125PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AK11,---,HSIO122PB7,Bank7,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
@@ -376,7 +376,7 @@ AK32,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,--
AK33,---,NC,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined"
AK34,---,NC,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined"
AL1,---,VSS,---,Reserved,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,VSS
AL2,R_DATA[2],HSIO162NB0,Bank0,Assigned,LVCMOS18,Output,None,No,ON,None,No,---,---,---,120,---,OFF,8,---,5,---,OFF,R_DATA[2]
AL2,---,HSIO162NB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AL3,---,HSIO165NB0/DQS,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AL4,---,HSIO141PB0/DQS,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
AL5,---,HSIO139PB0,Bank0,Unassigned,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,---,"DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON"
1 Device Selection
2 Report Version
3 0.1
4 Pin Report
5 Pin
6 A2
142 AD3
143 AD4
144 AD5
145 AD6
146 AD7
147 AD8
148 AD9
149 AD10
150 AD11
151 AD12
152 AD13
153 AD14
154 AD15
155 AD16
156 AD17
176 AE3
177 AE4
178 AE5
179 AE6
180 AE7
181 AE8
182 AE9
183 AE10
184 AE11
185 AE12
186 AE13
187 AE14
188 AE15
189 AE16
211 AF4
212 AF5
213 AF6
214 AF7
215 AF8
216 AF9
217 AF10
218 AF11
219 AF12
220 AF13
221 AF14
222 AF15
223 AF16
244 AG3
245 AG4
246 AG5
247 AG6
248 AG7
249 AG8
250 AG9
251 AG10
252 AG11
253 AG12
254 AG13
274 AG33
275 AG34
276 AH1
277 AH2
278 AH3
279 AH4
280 AH5
281 AH6
282 AH7
283 AH8
284 AH9
285 AH10
286 AH11
287 AH12
307 AH32
308 AH33
309 AH34
310 AJ1
311 AJ2
312 AJ3
313 AJ4
314 AJ5
315 AJ6
316 AJ7
317 AJ8
318 AJ9
319 AJ10
320 AJ11
321 AJ12
341 AJ32
342 AJ33
343 AJ34
344 AK1
345 AK2
346 AK3
347 AK4
348 AK5
349 AK6
350 AK7
351 AK8
352 AK9
353 AK10
354 AK11
376 AK33
377 AK34
378 AL1
379 AL2
380 AL3
381 AL4
382 AL5

View File

@@ -1,6 +1,6 @@
----------------------------------------------------------------
-Report version: 0.1
-Pin Report - Date: Wed Apr 15 23:06:21 2026 Pinchecksum: NOT-AVAILABLE
-Pin Report - Date: Fri Apr 17 08:50:27 2026 Pinchecksum: NOT-AVAILABLE
-Product: Designer
-Release: 2025.1
-Version: 2025.1.0.14
@@ -151,15 +151,15 @@ AD2 --- VSS ---
AD3 --- GPIO174NB4 Bank4 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF
AD4 --- GPIO180PB4/CLKIN_W_6/CCC_NW_CLKIN_W_6/CCC_NW_PLL0_OUT1 Bank4 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF
AD5 --- GPIO180NB4 Bank4 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDDI4 through resistor (10K ohm) is allowed. CLAMP=OFF
AD6 R_DATA[4] HSIO160PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[4]
AD6 R_DATA[30] HSIO160PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[30]
AD7 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AD8 R_DATA[5] HSIO161NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[5]
AD9 R_DATA[9] HSIO161PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[9]
AD10 R_DATA[27] HSIO152PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[27]
AD11 R_DATA[21] HSIO150NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[21]
AD8 --- HSIO161NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AD9 --- HSIO161PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AD10 R_DATA[21] HSIO152PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[21]
AD11 R_DATA[23] HSIO150NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[23]
AD12 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AD13 R_DATA[17] HSIO151PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[17]
AD14 R_DATA[31] HSIO151NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[31]
AD13 R_DATA[19] HSIO151PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[19]
AD14 R_DATA[18] HSIO151NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[18]
AD15 --- HSIO131PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AD16 --- HSIO129NB7/DQS Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AD17 --- HSIO127PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
@@ -185,14 +185,14 @@ AE2 --- HSIO171PB0/DQS/CCC_NW_PLL1_OUT0 Bank
AE3 --- HSIO172PB0/CCC_NW_CLKIN_N_1 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AE4 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AE5 --- HSIO173PB0/CCC_NW_CLKIN_N_0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AE6 R_DATA[1] HSIO160NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[1]
AE7 R_DATA[23] HSIO157PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[23]
AE8 R_DATA[19] HSIO156PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[19]
AE6 --- HSIO160NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AE7 R_DATA[29] HSIO157PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[29]
AE8 R_DATA[26] HSIO156PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[26]
AE9 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AE10 R_DATA[20] HSIO152NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[20]
AE11 R_DATA[24] HSIO150PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[24]
AE12 R_DATA[30] HSIO155PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[30]
AE13 R_DATA[29] HSIO153PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[29]
AE10 R_DATA[15] HSIO152NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[15]
AE11 R_DATA[17] HSIO150PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[17]
AE12 R_DATA[25] HSIO155PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[25]
AE13 R_DATA[12] HSIO153PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[12]
AE14 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AE15 --- HSIO131NB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AE16 --- HSIO129PB7/DQS Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
@@ -220,13 +220,13 @@ AF3 --- HSIO169NB0 Bank
AF4 --- HSIO172NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AF5 --- HSIO173NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AF6 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AF7 R_DATA[16] HSIO157NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[16]
AF8 R_DATA[28] HSIO156NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[28]
AF9 R_DATA[0] HSIO158PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[0]
AF10 R_DATA[25] HSIO154NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[25]
AF7 R_DATA[31] HSIO157NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[31]
AF8 R_DATA[13] HSIO156NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[13]
AF9 R_DATA[14] HSIO158PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[14]
AF10 R_DATA[10] HSIO154NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[10]
AF11 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AF12 R_DATA[26] HSIO155NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[26]
AF13 R_DATA[22] HSIO153NB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[22]
AF12 R_DATA[24] HSIO155NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[24]
AF13 R_DATA[9] HSIO153NB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[9]
AF14 --- HSIO130PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AF15 --- HSIO128PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AF16 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
@@ -253,11 +253,11 @@ AG2 --- HSIO168NB0 Bank
AG3 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AG4 --- HSIO170PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2/CCC_NW_PLL1_OUT0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AG5 --- HSIO170NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AG6 R_DATA[13] HSIO159NB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[13]
AG7 R_DATA[11] HSIO159PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[11]
AG6 R_DATA[27] HSIO159NB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[27]
AG7 R_DATA[28] HSIO159PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[28]
AG8 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AG9 R_DATA[12] HSIO158NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[12]
AG10 R_DATA[18] HSIO154PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[18]
AG9 R_DATA[8] HSIO158NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[8]
AG10 R_DATA[11] HSIO154PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[11]
AG11 --- HSIO137PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AG12 --- HSIO136PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AG13 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
@@ -283,14 +283,14 @@ AG32 --- XCVR_2_RX2_N ---
AG33 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AG34 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AH1 --- HSIO166PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH2 R_DATA[10] HSIO166NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[10]
AH2 --- HSIO166NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH3 --- HSIO167PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH4 R_DATA[7] HSIO163PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[7]
AH4 --- HSIO163PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH5 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AH6 --- HSIO149PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH7 --- HSIO149NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH8 --- HSIO146PB0/CLKIN_N_4 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH9 --- HSIO146NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH6 R_DATA[7] HSIO149PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[7]
AH7 R_DATA[22] HSIO149NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[22]
AH8 R_DATA[5] HSIO146PB0/CLKIN_N_4 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[5]
AH9 R_DATA[0] HSIO146NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[0]
AH10 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AH11 --- HSIO137NB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AH12 --- HSIO136NB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
@@ -316,15 +316,15 @@ AH31 --- VSS ---
AH32 --- VDDA --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Must connect VDDA directly to 1.0v/1.05v, or to VSS through resistor (10K ohm). For PolarFire CORE devices: Must connect VDDA to VSS through resistor (10K ohm)
AH33 --- XCVR_2_TX3_P --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined
AH34 --- XCVR_2_TX3_N --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined
AJ1 R_DATA[6] HSIO164PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[6]
AJ1 --- HSIO164PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ2 --- VDDI0 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 1.8v
AJ3 --- HSIO167NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ4 R_DATA[15] HSIO163NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[15]
AJ5 --- HSIO147PB0/DQS Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ6 --- HSIO147NB0/DQS Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ4 --- HSIO163NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ5 R_DATA[6] HSIO147PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[6]
AJ6 R_DATA[20] HSIO147NB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[20]
AJ7 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AJ8 --- HSIO148NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ9 --- HSIO148PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ8 R_DATA[16] HSIO148NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[16]
AJ9 R_DATA[1] HSIO148PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[1]
AJ10 --- HSIO134PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ11 --- HSIO134NB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AJ12 --- VDDI7 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Must connect VDDI7 directly to 1.2v/1.5v/1.8v, or to VSS through resistor (10K ohm)
@@ -350,14 +350,14 @@ AJ31 --- NC ---
AJ32 --- NC --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (100K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined
AJ33 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AJ34 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AK1 R_DATA[3] HSIO164NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[3]
AK2 R_DATA[14] HSIO162PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[14]
AK3 R_DATA[8] HSIO165PB0/DQS Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[8]
AK1 --- HSIO164NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK2 --- HSIO162PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK3 --- HSIO165PB0/DQS Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK4 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AK5 --- HSIO145PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK5 R_DATA[3] HSIO145PB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[3]
AK6 --- HSIO145NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK7 --- HSIO144PB0/CLKIN_N_5 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK8 --- HSIO144NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK7 R_DATA[4] HSIO144PB0/CLKIN_N_5 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[4]
AK8 R_DATA[2] HSIO144NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[2]
AK9 --- VDDI7 --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Must connect VDDI7 directly to 1.2v/1.5v/1.8v, or to VSS through resistor (10K ohm)
AK10 --- HSIO125PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AK11 --- HSIO122PB7 Bank7 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
@@ -385,7 +385,7 @@ AK32 --- VSS ---
AK33 --- NC --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined
AK34 --- NC --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Safety Critical Applications: DNC, LiberoSOC Defined. Connect to VSS through resistor (10K ohm) for higher noise immunity is allowed. All other applications:DNC, LiberoSOC Defined
AL1 --- VSS --- Reserved --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- VSS
AL2 R_DATA[2] HSIO162NB0 Bank0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF R_DATA[2]
AL2 --- HSIO162NB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AL3 --- HSIO165NB0/DQS Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AL4 --- HSIO141PB0/DQS Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON
AL5 --- HSIO139PB0 Bank0 Unassigned --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- DNC, LiberoSOC Defined High-Z with weak pull up ON. Connection to VDD18 through resistor (10K ohm) is allowed. CLAMP=ON

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@@ -1,5 +1,5 @@
----------------------------------------------------------------
-Pin Report - Date: Wed Apr 15 23:06:21 2026 Pinchecksum: NOT-AVAILABLE
-Pin Report - Date: Fri Apr 17 08:50:27 2026 Pinchecksum: NOT-AVAILABLE
-Product: Designer
-Release: 2025.1
-Version: 2025.1.0.14
@@ -16,38 +16,38 @@ LINK_OK D25 Yes HSIO70PB6/CCC_SE_PLL1_OUT1
PHY_MDC Y12 Yes GPIO204PB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
PHY_MDIO Y13 Yes GPIO204NB4 Bank4 LVCMOS25 Inout None No ON Up No OFF --- OFF 120 OFF OFF 8 --- 5 --- OFF
PHY_RST U11 Yes GPIO206NB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[0] AF9 No HSIO158PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[1] AE6 No HSIO160NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[2] AL2 No HSIO162NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[3] AK1 No HSIO164NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[4] AD6 No HSIO160PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[5] AD8 No HSIO161NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[6] AJ1 No HSIO164PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[7] AH4 No HSIO163PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[8] AK3 No HSIO165PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[9] AD9 No HSIO161PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[10] AH2 No HSIO166NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[11] AG7 No HSIO159PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[12] AG9 No HSIO158NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[13] AG6 No HSIO159NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[14] AK2 No HSIO162PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[15] AJ4 No HSIO163NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[16] AF7 No HSIO157NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[17] AD13 No HSIO151PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[18] AG10 No HSIO154PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[19] AE8 No HSIO156PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[20] AE10 No HSIO152NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[21] AD11 No HSIO150NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[22] AF13 No HSIO153NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[23] AE7 No HSIO157PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[24] AE11 No HSIO150PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[25] AF10 No HSIO154NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[26] AF12 No HSIO155NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[27] AD10 No HSIO152PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[28] AF8 No HSIO156NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[29] AE13 No HSIO153PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[30] AE12 No HSIO155PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[31] AD14 No HSIO151NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[0] AH9 No HSIO146NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[1] AJ9 No HSIO148PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[2] AK8 No HSIO144NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[3] AK5 No HSIO145PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[4] AK7 No HSIO144PB0/CLKIN_N_5 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[5] AH8 No HSIO146PB0/CLKIN_N_4 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[6] AJ5 No HSIO147PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[7] AH6 No HSIO149PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[8] AG9 No HSIO158NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[9] AF13 No HSIO153NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[10] AF10 No HSIO154NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[11] AG10 No HSIO154PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[12] AE13 No HSIO153PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[13] AF8 No HSIO156NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[14] AF9 No HSIO158PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[15] AE10 No HSIO152NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[16] AJ8 No HSIO148NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[17] AE11 No HSIO150PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[18] AD14 No HSIO151NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[19] AD13 No HSIO151PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[20] AJ6 No HSIO147NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[21] AD10 No HSIO152PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[22] AH7 No HSIO149NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[23] AD11 No HSIO150NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[24] AF12 No HSIO155NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[25] AE12 No HSIO155PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[26] AE8 No HSIO156PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[27] AG6 No HSIO159NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[28] AG7 No HSIO159PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[29] AE7 No HSIO157PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[30] AD6 No HSIO160PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[31] AF7 No HSIO157NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
RD_BC_ERROR F22 Yes HSIO64NB6 Bank6 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
REF_CLK_0 E25 Yes HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 Bank6 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- ---
REF_CLK_SEL AA10 Yes GPIO189PB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF

View File

@@ -1,5 +1,5 @@
----------------------------------------------------------------
-Pin Report - Date: Wed Apr 15 23:06:21 2026 Pinchecksum: NOT-AVAILABLE
-Pin Report - Date: Fri Apr 17 08:50:27 2026 Pinchecksum: NOT-AVAILABLE
-Product: Designer
-Release: 2025.1
-Version: 2025.1.0.14
@@ -16,38 +16,38 @@ LINK_OK D25 Yes HSIO70PB6/CCC_SE_PLL1_OUT1
PHY_MDC Y12 Yes GPIO204PB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
PHY_MDIO Y13 Yes GPIO204NB4 Bank4 LVCMOS25 Inout None No ON Up No OFF --- OFF 120 OFF OFF 8 --- 5 --- OFF
PHY_RST U11 Yes GPIO206NB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[0] AF9 No HSIO158PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[1] AE6 No HSIO160NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[2] AL2 No HSIO162NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[3] AK1 No HSIO164NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[4] AD6 No HSIO160PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[5] AD8 No HSIO161NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[6] AJ1 No HSIO164PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[7] AH4 No HSIO163PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[8] AK3 No HSIO165PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[9] AD9 No HSIO161PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[10] AH2 No HSIO166NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[11] AG7 No HSIO159PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[12] AG9 No HSIO158NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[13] AG6 No HSIO159NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[14] AK2 No HSIO162PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[15] AJ4 No HSIO163NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[16] AF7 No HSIO157NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[17] AD13 No HSIO151PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[18] AG10 No HSIO154PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[19] AE8 No HSIO156PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[20] AE10 No HSIO152NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[21] AD11 No HSIO150NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[22] AF13 No HSIO153NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[23] AE7 No HSIO157PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[24] AE11 No HSIO150PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[25] AF10 No HSIO154NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[26] AF12 No HSIO155NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[27] AD10 No HSIO152PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[28] AF8 No HSIO156NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[29] AE13 No HSIO153PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[30] AE12 No HSIO155PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[31] AD14 No HSIO151NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[0] AH9 No HSIO146NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[1] AJ9 No HSIO148PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[2] AK8 No HSIO144NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[3] AK5 No HSIO145PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[4] AK7 No HSIO144PB0/CLKIN_N_5 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[5] AH8 No HSIO146PB0/CLKIN_N_4 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[6] AJ5 No HSIO147PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[7] AH6 No HSIO149PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[8] AG9 No HSIO158NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[9] AF13 No HSIO153NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[10] AF10 No HSIO154NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[11] AG10 No HSIO154PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[12] AE13 No HSIO153PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[13] AF8 No HSIO156NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[14] AF9 No HSIO158PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[15] AE10 No HSIO152NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[16] AJ8 No HSIO148NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[17] AE11 No HSIO150PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[18] AD14 No HSIO151NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[19] AD13 No HSIO151PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[20] AJ6 No HSIO147NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[21] AD10 No HSIO152PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[22] AH7 No HSIO149NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[23] AD11 No HSIO150NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[24] AF12 No HSIO155NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[25] AE12 No HSIO155PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[26] AE8 No HSIO156PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[27] AG6 No HSIO159NB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[28] AG7 No HSIO159PB0/DQS Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[29] AE7 No HSIO157PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[30] AD6 No HSIO160PB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
R_DATA[31] AF7 No HSIO157NB0 Bank0 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
RD_BC_ERROR F22 Yes HSIO64NB6 Bank6 LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
REF_CLK_0 E25 Yes HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 Bank6 LVCMOS18 Input None No ON Up No OFF --- OFF 120 OFF --- --- --- --- --- ---
REF_CLK_SEL AA10 Yes GPIO189PB4 Bank4 LVCMOS25 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF

View File

@@ -1,5 +1,5 @@
----------------------------------------------------------------
-Pin Report - Date: Wed Apr 15 23:06:21 2026 Pinchecksum: NOT-AVAILABLE
-Pin Report - Date: Fri Apr 17 08:50:27 2026 Pinchecksum: NOT-AVAILABLE
-Product: Designer
-Release: 2025.1
-Version: 2025.1.0.14
@@ -150,15 +150,15 @@ AD2 VSS Re
AD3 GPIO174NB4 Unassigned
AD4 GPIO180PB4/CLKIN_W_6/CCC_NW_CLKIN_W_6/CCC_NW_PLL0_OUT1 Unassigned
AD5 GPIO180NB4 Unassigned
AD6 R_DATA[4] HSIO160PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD6 R_DATA[30] HSIO160PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD7 VDDI0 Reserved
AD8 R_DATA[5] HSIO161NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD9 R_DATA[9] HSIO161PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD10 R_DATA[27] HSIO152PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD11 R_DATA[21] HSIO150NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD8 HSIO161NB0 Unassigned
AD9 HSIO161PB0 Unassigned
AD10 R_DATA[21] HSIO152PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD11 R_DATA[23] HSIO150NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD12 VSS Reserved
AD13 R_DATA[17] HSIO151PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD14 R_DATA[31] HSIO151NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD13 R_DATA[19] HSIO151PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD14 R_DATA[18] HSIO151NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AD15 HSIO131PB7 Unassigned
AD16 HSIO129NB7/DQS Unassigned
AD17 HSIO127PB7 Unassigned
@@ -184,14 +184,14 @@ AE2 HSIO171PB0/DQS/CCC_NW_PLL1_OUT0 Un
AE3 HSIO172PB0/CCC_NW_CLKIN_N_1 Unassigned
AE4 VDDI0 Reserved
AE5 HSIO173PB0/CCC_NW_CLKIN_N_0 Unassigned
AE6 R_DATA[1] HSIO160NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE7 R_DATA[23] HSIO157PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE8 R_DATA[19] HSIO156PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE6 HSIO160NB0 Unassigned
AE7 R_DATA[29] HSIO157PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE8 R_DATA[26] HSIO156PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE9 VSS Reserved
AE10 R_DATA[20] HSIO152NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE11 R_DATA[24] HSIO150PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE12 R_DATA[30] HSIO155PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE13 R_DATA[29] HSIO153PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE10 R_DATA[15] HSIO152NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE11 R_DATA[17] HSIO150PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE12 R_DATA[25] HSIO155PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE13 R_DATA[12] HSIO153PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AE14 VDDI0 Reserved
AE15 HSIO131NB7 Unassigned
AE16 HSIO129PB7/DQS Unassigned
@@ -219,13 +219,13 @@ AF3 HSIO169NB0 Un
AF4 HSIO172NB0 Unassigned
AF5 HSIO173NB0 Unassigned
AF6 VSS Reserved
AF7 R_DATA[16] HSIO157NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF8 R_DATA[28] HSIO156NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF9 R_DATA[0] HSIO158PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF10 R_DATA[25] HSIO154NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF7 R_DATA[31] HSIO157NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF8 R_DATA[13] HSIO156NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF9 R_DATA[14] HSIO158PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF10 R_DATA[10] HSIO154NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF11 VDDI0 Reserved
AF12 R_DATA[26] HSIO155NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF13 R_DATA[22] HSIO153NB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF12 R_DATA[24] HSIO155NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF13 R_DATA[9] HSIO153NB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AF14 HSIO130PB7 Unassigned
AF15 HSIO128PB7 Unassigned
AF16 VSS Reserved
@@ -252,11 +252,11 @@ AG2 HSIO168NB0 Un
AG3 VSS Reserved
AG4 HSIO170PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2/CCC_NW_PLL1_OUT0 Unassigned
AG5 HSIO170NB0 Unassigned
AG6 R_DATA[13] HSIO159NB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG7 R_DATA[11] HSIO159PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG6 R_DATA[27] HSIO159NB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG7 R_DATA[28] HSIO159PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG8 VDDI0 Reserved
AG9 R_DATA[12] HSIO158NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG10 R_DATA[18] HSIO154PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG9 R_DATA[8] HSIO158NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG10 R_DATA[11] HSIO154PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AG11 HSIO137PB7 Unassigned
AG12 HSIO136PB7 Unassigned
AG13 VSS Reserved
@@ -282,14 +282,14 @@ AG32 XCVR_2_RX2_N Re
AG33 VSS Reserved
AG34 VSS Reserved
AH1 HSIO166PB0 Unassigned
AH2 R_DATA[10] HSIO166NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH2 HSIO166NB0 Unassigned
AH3 HSIO167PB0 Unassigned
AH4 R_DATA[7] HSIO163PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH4 HSIO163PB0 Unassigned
AH5 VDDI0 Reserved
AH6 HSIO149PB0 Unassigned
AH7 HSIO149NB0 Unassigned
AH8 HSIO146PB0/CLKIN_N_4 Unassigned
AH9 HSIO146NB0 Unassigned
AH6 R_DATA[7] HSIO149PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH7 R_DATA[22] HSIO149NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH8 R_DATA[5] HSIO146PB0/CLKIN_N_4 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH9 R_DATA[0] HSIO146NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AH10 VSS Reserved
AH11 HSIO137NB7 Unassigned
AH12 HSIO136NB7 Unassigned
@@ -315,15 +315,15 @@ AH31 VSS Re
AH32 VDDA Reserved
AH33 XCVR_2_TX3_P Reserved
AH34 XCVR_2_TX3_N Reserved
AJ1 R_DATA[6] HSIO164PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ1 HSIO164PB0 Unassigned
AJ2 VDDI0 Reserved
AJ3 HSIO167NB0 Unassigned
AJ4 R_DATA[15] HSIO163NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ5 HSIO147PB0/DQS Unassigned
AJ6 HSIO147NB0/DQS Unassigned
AJ4 HSIO163NB0 Unassigned
AJ5 R_DATA[6] HSIO147PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ6 R_DATA[20] HSIO147NB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ7 VSS Reserved
AJ8 HSIO148NB0 Unassigned
AJ9 HSIO148PB0 Unassigned
AJ8 R_DATA[16] HSIO148NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ9 R_DATA[1] HSIO148PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AJ10 HSIO134PB7 Unassigned
AJ11 HSIO134NB7 Unassigned
AJ12 VDDI7 Reserved
@@ -349,14 +349,14 @@ AJ31 NC Re
AJ32 NC Reserved
AJ33 VSS Reserved
AJ34 VSS Reserved
AK1 R_DATA[3] HSIO164NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK2 R_DATA[14] HSIO162PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK3 R_DATA[8] HSIO165PB0/DQS Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK1 HSIO164NB0 Unassigned
AK2 HSIO162PB0 Unassigned
AK3 HSIO165PB0/DQS Unassigned
AK4 VSS Reserved
AK5 HSIO145PB0 Unassigned
AK5 R_DATA[3] HSIO145PB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK6 HSIO145NB0 Unassigned
AK7 HSIO144PB0/CLKIN_N_5 Unassigned
AK8 HSIO144NB0 Unassigned
AK7 R_DATA[4] HSIO144PB0/CLKIN_N_5 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK8 R_DATA[2] HSIO144NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AK9 VDDI7 Reserved
AK10 HSIO125PB7 Unassigned
AK11 HSIO122PB7 Unassigned
@@ -384,7 +384,7 @@ AK32 VSS Re
AK33 NC Reserved
AK34 NC Reserved
AL1 VSS Reserved
AL2 R_DATA[2] HSIO162NB0 Assigned LVCMOS18 Output None No ON None No --- --- --- 120 --- OFF 8 --- 5 --- OFF
AL2 HSIO162NB0 Unassigned
AL3 HSIO165NB0/DQS Unassigned
AL4 HSIO141PB0/DQS Unassigned
AL5 HSIO139PB0 Unassigned

Binary file not shown.

View File

@@ -3,7 +3,7 @@
<doc>
<text>SmartTime Version 2025.1.0.14</text>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date: Wed Apr 15 22:53:24 2026 </text>
Date: Fri Apr 17 08:37:34 2026 </text>
<table>
<header>
</header>
@@ -50,15 +50,15 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</header>
<row>
<cell>Setup</cell>
<cell> 22875</cell>
<cell> 22705</cell>
<cell> 23</cell>
<cell> 22898</cell>
<cell> 22728</cell>
</row>
<row>
<cell>Recovery</cell>
<cell> 10961</cell>
<cell> 10854</cell>
<cell> 0</cell>
<cell> 10961</cell>
<cell> 10854</cell>
</row>
<row>
<cell>Output Setup</cell>
@@ -68,22 +68,22 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Setup</cell>
<cell> 33838</cell>
<cell> 33561</cell>
<cell> 73</cell>
<cell> 33911</cell>
<cell> 33634</cell>
</row>
<separator/>
<row>
<cell>Hold</cell>
<cell> 22875</cell>
<cell> 22705</cell>
<cell> 23</cell>
<cell> 22898</cell>
<cell> 22728</cell>
</row>
<row>
<cell>Removal</cell>
<cell> 10961</cell>
<cell> 10854</cell>
<cell> 0</cell>
<cell> 10961</cell>
<cell> 10854</cell>
</row>
<row>
<cell>Output Hold</cell>
@@ -93,9 +93,9 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Hold</cell>
<cell> 33838</cell>
<cell> 33561</cell>
<cell> 73</cell>
<cell> 33911</cell>
<cell> 33634</cell>
</row>
</table>
<section>
@@ -111,15 +111,15 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</header>
<row>
<cell>Setup</cell>
<cell> 10503</cell>
<cell> 10361</cell>
<cell> 2</cell>
<cell> 10505</cell>
<cell> 10363</cell>
</row>
<row>
<cell>Recovery</cell>
<cell> 3365</cell>
<cell> 3273</cell>
<cell> 0</cell>
<cell> 3365</cell>
<cell> 3273</cell>
</row>
<row>
<cell>Output Setup</cell>
@@ -129,22 +129,22 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Setup</cell>
<cell> 13869</cell>
<cell> 13635</cell>
<cell> 41</cell>
<cell> 13910</cell>
<cell> 13676</cell>
</row>
<separator/>
<row>
<cell>Hold</cell>
<cell> 10503</cell>
<cell> 10361</cell>
<cell> 2</cell>
<cell> 10505</cell>
<cell> 10363</cell>
</row>
<row>
<cell>Removal</cell>
<cell> 3365</cell>
<cell> 3273</cell>
<cell> 0</cell>
<cell> 3365</cell>
<cell> 3273</cell>
</row>
<row>
<cell>Output Hold</cell>
@@ -154,9 +154,9 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Hold</cell>
<cell> 13869</cell>
<cell> 13635</cell>
<cell> 41</cell>
<cell> 13910</cell>
<cell> 13676</cell>
</row>
</table>
<section>
@@ -834,15 +834,15 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</header>
<row>
<cell>Setup</cell>
<cell> 1843</cell>
<cell> 1815</cell>
<cell> 0</cell>
<cell> 1843</cell>
<cell> 1815</cell>
</row>
<row>
<cell>Recovery</cell>
<cell> 1251</cell>
<cell> 1236</cell>
<cell> 0</cell>
<cell> 1251</cell>
<cell> 1236</cell>
</row>
<row>
<cell>Output Setup</cell>
@@ -852,22 +852,22 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Setup</cell>
<cell> 3095</cell>
<cell> 3052</cell>
<cell> 2</cell>
<cell> 3097</cell>
<cell> 3054</cell>
</row>
<separator/>
<row>
<cell>Hold</cell>
<cell> 1843</cell>
<cell> 1815</cell>
<cell> 0</cell>
<cell> 1843</cell>
<cell> 1815</cell>
</row>
<row>
<cell>Removal</cell>
<cell> 1251</cell>
<cell> 1236</cell>
<cell> 0</cell>
<cell> 1251</cell>
<cell> 1236</cell>
</row>
<row>
<cell>Output Hold</cell>
@@ -877,9 +877,9 @@ Date: Wed Apr 15 22:53:24 2026 </text>
</row>
<row>
<cell>Total Hold</cell>
<cell> 3095</cell>
<cell> 3052</cell>
<cell> 2</cell>
<cell> 3097</cell>
<cell> 3054</cell>
</row>
</table>
<section>

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@@ -22,7 +22,7 @@
<write_protect/>
<fabric_accessible/>
<mss_accessible/>
000096130000002000000000000000000000000000000000000000000000
000014130000002000000000000000000000000000000000000000000000
000000000000000000007340010000c000007340010040c0000097c00300
fffc03009300020080f80100f388000010c0000093c80300120000006358
020002080000f388000050c0000093c8030032000000130c000010000000
@@ -158,8 +158,8 @@
03002308020007000000130000000000000083800000c108000003900000
8108000013040000010c000067000200000000001304000001f403002398
000011080000239000008108000013100000010c000023b80000a4f00300
23b00000b4f00300839c0000c4f403006300020007200000000096330000
964300001013000000206f000000100400006f000000c01c000000000000
23b00000b4f00300839c0000c4f403006300020007200000000014330000
144300409413000000206f000000100400006f000000c01c000000000000
0000000000000000000000006f000000c040000000000000000000000000
00000000000000000000000000006f000000406000000000000000000000
000000000000000000000000000000006f000000c07c0000000000000000
@@ -295,8 +295,8 @@
8110000003a80000c110000083a800000114000003ac00004114000083ac
00008114000003b00000c114000083b000000118000003b4000041180000
83b400008118000003b80000c118000083b80000011c000003bc0000411c
000083bc0000811c000013040000012000007300000020c0000000001033
000010430000901300000020931c020047080000131c0000100000002380
000083bc0000811c000013040000012000007300000020c0000000409433
004094430040121300000020931c020047080000131c0000100000002380
0200e70000001300000000000000b71c000000800100931c0200470c0000
839c020007000000e368020007f80300b71c000000800100931c0200070c
0000839c02000700000023980000f4f80300b71c000000800100931c0200
@@ -432,8 +432,8 @@
000001000000131c000007c0030023800200e7000000b71c000000800100
931c0200c7100000371c0000ff3c000023800200e7000000b71c00000080
0100931c020007140000371c000000100000131c00000760000023800200
e7000000b71c000000800100931c020047140000371c0000811800000000
9033000090430040101300000020131c0000f7fc030023800200e7000000
e7000000b71c000000800100931c020047140000371c0000811800000040
1233004012430000161300000020131c0000f7fc030023800200e7000000
b71c000000800100931c0200871400002380020007000000b71c00000080
0100931c0200c7140000371c000008000000131c0000f7fc030023800200
e7000000b71c000000800100931c020007700000131c0000f00000002380
@@ -570,7 +570,7 @@
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000
00401033004010430000181300000020839c000084f40300633002000718
00001633000016430000941300000020839c000084f40300633002000718
00002398000004f803006f000000c0140000839c0000c4f40300839c0200
07000000931c0200070400001314020007000000efc003009f980300931c
00000500000093dc030017000000a3140000f4f80300831c0100b4f80300
@@ -707,11 +707,11 @@
e70000001300000000000000b71c000000800100931c0200470c0000839c
020007000000e368020007f80300b71c000000800100931c020087080000
379c000000000000131c00001700030023800200e7000000b71c00000080
01000000183300001843000006c001010000000202b000000000000203b0
01000000943300009443000006c001010000000202b000000000000203b0
03000000000006c021010000000202b000000000000203b0010000000200
00d0000000f0
<crc>
2c1a
e502
</crc>
</region>
<region name="INIT_STAGE_1_SNVM_CLIENT" address="0x0000ca" retrieveAddressFromFile="false" size="4384" format="HEX" type="PlainText NonAuthenticated" wordSize="8" numberWords="4384" memFile="designer\top\top_init_stage_1_snvm.mem" memType="Microsemi Binary 32-bit" memFileTimeStamp="" clientType="public" program="true">

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@@ -193,6 +193,68 @@ SIZE="5136"
PARENT="<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\COREDELAYCODE_TIP.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf,actgen_cxf"
STATE="utd"
TIME="1776257512"
SIZE="1298"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="697"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="13955"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="22096"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="3801"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="2194"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="2287"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
STATE="utd"
TIME="1776225025"
SIZE="1981"
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf,actgen_cxf"
STATE="utd"
TIME="1776096661"
@@ -478,6 +540,12 @@ SIZE="364"
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
ENDFILE
VALUE "<project>\component\Actel\SgCore\PF_TPSRAM\1.1.108\PF_TPSRAM.cxf,actgen_cxf"
STATE="utd"
TIME="1776384266"
SIZE="246"
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
ENDFILE
VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v,hdl"
STATE="utd"
TIME="1776075084"
@@ -545,6 +613,126 @@ SIZE="13295"
PARENT="<project>\component\work\CoreAPB3_0\CoreAPB3_0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1776257514"
SIZE="4447"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="5479"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf,actgen_cxf"
STATE="utd"
TIME="1776257512"
SIZE="3861"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
STATE="utd"
TIME="1776257512"
SIZE="997"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
STATE="utd"
TIME="1776257512"
SIZE="23"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
STATE="utd"
TIME="1776257512"
SIZE="3286"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="71458"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="55032"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="4400"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v,hdl"
STATE="utd"
TIME="1776257511"
SIZE="2224"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="13313"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="2549"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="2332"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="33348"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v,hdl"
STATE="utd"
TIME="1776257512"
SIZE="23539"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
STATE="utd"
TIME="1776257512"
SIZE="19026"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
MODULE_UNDER_TEST="testbench"
SIMULATION_TIME=" -all"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
STATE="utd"
TIME="1776257512"
SIZE="401"
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
VALUE "<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1776096662"
@@ -993,15 +1181,40 @@ SIZE="3712"
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf,actgen_cxf"
STATE="utd"
TIME="1776384267"
SIZE="4881"
ENDFILE
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v,hdl"
STATE="utd"
TIME="1776384266"
SIZE="3681"
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf,actgen_cxf"
STATE="utd"
TIME="1776384266"
SIZE="772"
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
ENDFILE
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v,hdl"
STATE="utd"
TIME="1776384266"
SIZE="7800"
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf"
IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\work\top\top.cxf,actgen_cxf"
STATE="utd"
TIME="1776096796"
SIZE="6732"
TIME="1776394606"
SIZE="7212"
ENDFILE
VALUE "<project>\component\work\top\top.v,hdl"
STATE="utd"
TIME="1776096796"
SIZE="23777"
TIME="1776394606"
SIZE="26020"
PARENT="<project>\component\work\top\top.cxf"
IS_READONLY="TRUE"
ENDFILE
@@ -1020,11 +1233,21 @@ STATE="utd"
TIME="1776096825"
SIZE="4809"
ENDFILE
VALUE "<project>\hdl\fifo_to_tpsram_bridge.v,hdl"
STATE="utd"
TIME="1776394591"
SIZE="3691"
ENDFILE
VALUE "<project>\hdl\SSDetect.v,hdl"
STATE="utd"
TIME="1776096660"
SIZE="1303"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.log,log"
STATE="utd"
TIME="1776320914"
SIZE="407"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1776075074"
@@ -1049,36 +1272,157 @@ TIME="1776096673"
SIZE="13597"
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
ENDFILE
VALUE "<project>\simulation\run.do,do"
STATE="utd"
TIME="1776320890"
SIZE="1760"
ENDFILE
VALUE "<project>\simulation\user_tb.bfm,sim"
STATE="utd"
TIME="1776075075"
SIZE="7303"
PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
ENDFILE
VALUE "<project>\synthesis\synwork\layer0.so,so"
STATE="utd"
TIME="1776384138"
SIZE="159"
ENDFILE
VALUE "<project>\synthesis\top.so,so"
STATE="utd"
TIME="1776097335"
SIZE="244"
TIME="1776395162"
SIZE="221"
ENDFILE
VALUE "<project>\synthesis\top.vm,syn_vm"
STATE="utd"
TIME="1776097331"
SIZE="6195567"
TIME="1776395157"
SIZE="6235009"
ENDFILE
VALUE "<project>\synthesis\top_syn.prj,prj"
STATE="utd"
TIME="1776097336"
SIZE="11812"
TIME="1776395163"
SIZE="12159"
ENDFILE
VALUE "<project>\synthesis\top_vm.sdc,syn_sdc"
STATE="utd"
TIME="1776097332"
TIME="1776395158"
SIZE="6962"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
FILE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work"
FILE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
ENDLIST
ENDLIST
LIST "CORETSE::work"
FILE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v,hdl"
LIST Other_Association
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
FILE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "top::work"
FILE "<project>\component\work\top\top.v,hdl"
LIST SynthesisConstraints
@@ -1094,11 +1438,229 @@ VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
VALUE "<project>\constraint\io\io_constraints.pdc,io_pdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB"
FILE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
FILE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v,hdl"
LIST Other_Association
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST "CORESPI::CORESPI_LIB"
FILE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\user_tb.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST ProjectState5.1
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST COREJTAGDEBUG
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
ENDLIST
LIST CORESPI
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST CORETSE
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
ENDLIST
LIST CoreAPB3
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST COREFIFO_C0_COREFIFO_C0_0_COREFIFO
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
ENDLIST
LIST COREJTAGDEBUG
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
ENDLIST
LIST CORESPI
VALUE "<project>\simulation\user_tb.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
ENDLIST
LIST CORETSE
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
ENDLIST
LIST CoreAPB3
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
ENDLIST
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
@@ -1196,6 +1758,90 @@ IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CORETSE::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "top::work"
LIST Impl1
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST "CORESPI::CORESPI_LIB"
LIST Impl1
ideSTIMULUS=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
@@ -1225,6 +1871,29 @@ LIST "CORECDR4_CNTL_TIP::work","component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0
ENDLIST
LIST "COREDELAYCODE_TIP::work","component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
ENDLIST
LIST "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
SUBBLOCK "COREJTAGDEBUG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v","FALSE","FALSE"
ENDLIST
@@ -1256,6 +1925,13 @@ LIST "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_Tx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_COREUART::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v","FALSE","FALSE"
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v","FALSE","FALSE"
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v","FALSE","FALSE"
@@ -1388,6 +2064,8 @@ LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.20
ENDLIST
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
ENDLIST
LIST "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
ENDLIST
LIST "miv_rv32_axi_egress_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
ENDLIST
LIST "miv_rv32_axi_egress_slip_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
@@ -1461,8 +2139,8 @@ LIST "miv_rv32_bistdualdata_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.2
SUBBLOCK "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
ENDLIST
LIST "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
SUBBLOCK "pmc_logic_mux_behav::work","","FALSE","FALSE"
SUBBLOCK "miv_rv32_logic_mux_behav_v2::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
SUBBLOCK "pmc_logic_mux_behav::work","","FALSE","FALSE"
ENDLIST
LIST "miv_rv32_bootrom::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
ENDLIST
@@ -1754,6 +2432,11 @@ SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::wo
ENDLIST
LIST "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
ENDLIST
LIST "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
SUBBLOCK "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
ENDLIST
LIST "pmc_logic_mux_behav::work","","FALSE","FALSE"
ENDLIST
LIST "pmc_sync_flop_behav_v3::work","","FALSE","FALSE"
@@ -1763,6 +2446,7 @@ ENDLIST
LIST "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
ENDLIST
LIST "top::work","component\work\top\top.v","TRUE","FALSE"
SUBBLOCK "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
SUBBLOCK "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
SUBBLOCK "CORESPI_0::work","component\work\CORESPI_0\CORESPI_0.v","TRUE","FALSE"
SUBBLOCK "CORETSE_0::work","component\work\CORETSE_0\CORETSE_0.v","TRUE","FALSE"
@@ -1773,9 +2457,15 @@ SUBBLOCK "MIV_RV32_C0::work","component\work\MIV_RV32_C0\MIV_RV32_C0.v","TRUE","
SUBBLOCK "PF_CCC_0::work","component\work\PF_CCC_0\PF_CCC_0.v","TRUE","FALSE"
SUBBLOCK "PF_IOD_CDR_C0::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v","TRUE","FALSE"
SUBBLOCK "PF_IOD_CDR_CCC_C0::work","component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v","TRUE","FALSE"
SUBBLOCK "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
SUBBLOCK "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
SUBBLOCK "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
SUBBLOCK "pf_init_monitor_0::work","component\work\pf_init_monitor_0\pf_init_monitor_0.v","TRUE","FALSE"
ENDLIST
LIST "clock_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v","FALSE","TRUE"
ENDLIST
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
ENDLIST
LIST "corereset_pf_tb::work","component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v","FALSE","TRUE"
SUBBLOCK "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work","component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v","FALSE","FALSE"
ENDLIST
@@ -1816,12 +2506,27 @@ LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
ENDLIST
LIST "fifo_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v","FALSE","TRUE"
ENDLIST
LIST "fifo_monitor::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v","FALSE","TRUE"
ENDLIST
LIST "g4_dp_ext_mem::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v","FALSE","TRUE"
SUBBLOCK "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
SUBBLOCK "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
SUBBLOCK "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
ENDLIST
LIST "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
ENDLIST
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
ENDLIST
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
ENDLIST
LIST "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
ENDLIST
LIST "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
ENDLIST
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
ENDLIST
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
@@ -1831,6 +2536,13 @@ SUBBLOCK "CORETSE::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\co
SUBBLOCK "CoreTSE_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
SUBBLOCK "CoreTSE_AXI4S_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
ENDLIST
LIST "testbench::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
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517
filter_tpsram.txt Normal file
View File

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Memory Block Name: PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP
Data Bit Mode: 8192 X 2
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View File

@@ -1,79 +1,128 @@
module fifo_to_tpsram_bridge #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10 // 1024 depth
parameter ADDR_WIDTH = 11
)(
input wire clk,
input wire reset_n,
// CoreFIFO Interface (FWFT Mode)
// FIFO Interface (FWFT)
input wire [DATA_WIDTH-1:0] fifo_data_out,
input wire fifo_empty,
output reg fifo_rd_en,
// TPSRAM Port A Interface (Write Port)
// TPSRAM Interface
output reg [ADDR_WIDTH-1:0] ram_w_addr,
output reg [DATA_WIDTH-1:0] ram_w_data,
output reg ram_w_en,
// Control/Status
input wire transfer_enable,
output reg buffer_full
);
// State Encoding
localparam IDLE = 2'b00,
WRITE = 2'b01,
FULL = 2'b10;
// ==============================
// MARKERS (AFTER BYTE FLIP)
// ==============================
localparam START_MARKER = 32'h00112233;
localparam END_MARKER = 32'hAABBCCDD;
// ==============================
// STATES
// ==============================
localparam IDLE = 2'b00,
IGNORE = 2'b01,
WRITE = 2'b10;
reg [1:0] state, next_state;
// Address Counter Logic
// ==============================
// BYTE FLIP (ENDIAN SWAP)
// ==============================
wire [31:0] flipped_data;
assign flipped_data = {fifo_data_out[7:0],
fifo_data_out[15:8],
fifo_data_out[23:16],
fifo_data_out[31:24]};
// ==============================
// ADDRESS COUNTER
// ==============================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ram_w_addr <= 0;
ram_w_addr <= 0;
buffer_full <= 0;
end else if (ram_w_en) begin
if (ram_w_addr == {ADDR_WIDTH{1'b1}}) begin
buffer_full <= 1; // Memory is topped off
buffer_full <= 1;
end else begin
ram_w_addr <= ram_w_addr + 1;
end
end
end
// FSM State Transitions
// ==============================
// FSM STATE REGISTER
// ==============================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) state <= IDLE;
else state <= next_state;
if (!reset_n)
state <= IDLE;
else
state <= next_state;
end
// Next State Logic
// ==============================
// NEXT STATE LOGIC
// ==============================
always @(*) begin
next_state = state;
case (state)
IDLE: begin
// Start writing if FIFO has data and RAM isn't full
if (!fifo_empty && transfer_enable && !buffer_full)
if (transfer_enable && !buffer_full)
next_state = IGNORE;
end
IGNORE: begin
if (!fifo_empty && flipped_data == START_MARKER)
next_state = WRITE;
end
WRITE: begin
if (fifo_empty || buffer_full)
if (!fifo_empty && flipped_data == END_MARKER)
next_state = IGNORE;
else if (buffer_full)
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end
// Output Logic
// ==============================
// OUTPUT LOGIC
// ==============================
always @(*) begin
fifo_rd_en = 0;
ram_w_en = 0;
ram_w_data = fifo_data_out;
ram_w_data = flipped_data;
if (state == WRITE && !fifo_empty && !buffer_full) begin
fifo_rd_en = 1;
ram_w_en = 1;
end
case (state)
IGNORE: begin
// Keep flushing FIFO
if (!fifo_empty)
fifo_rd_en = 1;
end
WRITE: begin
if (!fifo_empty && !buffer_full) begin
fifo_rd_en = 1;
// Do NOT write END marker
if (flipped_data != END_MARKER) begin
ram_w_en = 1;
end
end
end
endcase
end
endmodule
endmodule

View File

@@ -1,5 +1,5 @@
# Microsemi Corp.
# Date: 2026-Apr-15 18:03:35
# Date: 2026-Apr-17 17:02:32
Libero Release : 2025.1
Libero Version : 2025.1.0.14
Operating System Name : Windows 8
@@ -68,7 +68,7 @@ Environment Variables :
VXIPNPPATH=C:\Program Files (x86)\IVI Foundation\VISA\
VXIPNPPATH64=C:\Program Files\IVI Foundation\VISA\
windir=C:\Windows
ACTEL_SW_DIR=E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer
AMHOME=E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/am
HOME=C:\Users\S-SPACE
TCL_LIBRARY=E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/lib/tcl8.5
ACTEL_SW_DIR=E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer

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