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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v"
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v"

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#-- Synopsys, Inc.
#-- Version V-2023.09M-5
#-- Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\run_options.txt
#-- Written on Wed Apr 15 22:44:56 2026
#project files
add_file -verilog "../component/syn_comps.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_graytobinconv.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_fwft.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_bufd.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_uj_jtag.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_ujtag_wrapper.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_chanctrl.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_fifo.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_rf.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORESPI_0/CORESPI_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORETSE_0/CORETSE_0.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreAPB3_0/CoreAPB3_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Clock_gen.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Rx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Tx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/fifo_256x8_g5.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUART.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUARTapb.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf_0/core/corereset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_hart_cfg_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/hart_merged/miv_rv32_hart_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_subsys_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/subsys_merged/miv_rv32_subsys_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp_ecc.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0_0/rtl/miv_rv32.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/rtl/vlog/core/CoreDelayCode_TIP.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CCC_0/PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CLK_DIV_0/PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_IOD_CDR_CCC_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/SSDetect.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/fifo_to_tpsram_bridge.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0_0/pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/top/top.v"
add_file -fpga_constraint "E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/synthesis.fdc"
#implementation: "synthesis"
impl -add synthesis -type fpga
#
#implementation attributes
set_option -vlog_std sysv
#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"
# hdl_compiler_options
set_option -hdl_strict_syntax 0
# mapper_without_write_options
set_option -frequency 100.000
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0
# actel_options
set_option -rw_check_on_ram 0
# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -infer_seqShift 1
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -async_clkint_removal 1
# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -report_preserve_cdc 1
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0
set_option -pack_uram_addr_reg 1
set_option -act_wide_mul_size 35
# NFilter
set_option -no_sequential_opt 0
# common_options
set_option -add_dut_hierarchy 0
set_option -prepare_readback 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"

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synthesis/scratchproject.prs Normal file
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#-- Synopsys, Inc.
#-- Version V-2023.09M-5
#-- Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs
#project files
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/syn_comps.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_graytobinconv.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_fwft.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_bufd.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_uj_jtag.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_ujtag_wrapper.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_chanctrl.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_fifo.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_rf.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORESPI_0/CORESPI_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORETSE_0/CORETSE_0.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreAPB3_0/CoreAPB3_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Clock_gen.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Rx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Tx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/fifo_256x8_g5.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUART.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUARTapb.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf_0/core/corereset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_hart_cfg_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/hart_merged/miv_rv32_hart_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_subsys_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/subsys_merged/miv_rv32_subsys_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp_ecc.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0_0/rtl/miv_rv32.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/rtl/vlog/core/CoreDelayCode_TIP.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CCC_0/PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CLK_DIV_0/PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_IOD_CDR_CCC_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/SSDetect.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/fifo_to_tpsram_bridge.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0_0/pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/top/top.v"
add_file -fpga_constraint "E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/synthesis.fdc"
#implementation: "synthesis"
impl -add E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -type fpga
#
#implementation attributes
set_option -vlog_std sysv
#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"
# hdl_compiler_options
set_option -hdl_strict_syntax 0
# mapper_without_write_options
set_option -frequency 100.000
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0
# actel_options
set_option -rw_check_on_ram 0
# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -infer_seqShift 1
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -async_clkint_removal 1
# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -report_preserve_cdc 1
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0
set_option -pack_uram_addr_reg 1
set_option -act_wide_mul_size 35
# NFilter
set_option -no_sequential_opt 0
# common_options
set_option -add_dut_hierarchy 0
set_option -prepare_readback 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis/top.vm"
impl -active "synthesis"

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synthesis/synlog.tcl Normal file
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run_tcl -fg top_syn.tcl

1
synthesis/synlog/hierarea.rpt.rptmap Normal file
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rpt_top.areasrr,hierarea.rpt,Hierarchical Area Report

1
synthesis/synlog/incr_compile.rpt.rptmap Normal file
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./synwork/incr_compile.rpt,incr_compile.rpt,Incremental Compile Report

1
synthesis/synlog/layer0.tlg.rptmap Normal file
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./synwork/layer0.tlg,layer0.tlg,An incremental, partial HDL compilation log file that may allow early access to errors or other messages.

0
synthesis/synlog/report/highrel.rpt Normal file
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BIN
synthesis/synlog/report/metrics.db Normal file
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Binary file not shown.

237
synthesis/synlog/report/top_compiler_notes.txt Normal file
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@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 : | Running Verilog Compiler in System Verilog mode
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":437:13:437:25|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":449:13:449:24|Read directive translate_on.
@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":160:38:160:50|Read a parallel_case directive.
@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":223:34:223:46|Read a parallel_case directive.
@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v":69:31:69:43|Read a parallel_case directive.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":796:18:796:30|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":798:18:798:29|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":1536:18:1536:30|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":1550:18:1550:29|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21267:12:21267:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21316:12:21316:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21861:20:21861:32|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21877:20:21877:31|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":22391:12:22391:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":22459:12:22459:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25452:12:25452:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25460:12:25460:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25769:12:25769:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25777:12:25777:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27214:20:27214:32|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27217:20:27217:31|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27227:20:27227:32|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27237:20:27237:31|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27242:12:27242:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27300:12:27300:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28378:20:28378:32|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28381:20:28381:31|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28391:20:28391:32|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28401:20:28401:31|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28406:12:28406:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28464:12:28464:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":40250:14:40250:26|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":40254:14:40254:25|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41809:12:41809:24|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41814:12:41814:23|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41866:18:41866:30|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41880:18:41880:29|Read directive translate_on.
@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42004:14:42004:26|Read directive translate_off.
@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42037:14:42037:25|Read directive translate_on.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v":70:8:70:28|Synthesizing module miv_rv32_hart_cfg_pkg in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":73:8:73:19|Synthesizing module miv_rv32_pkg in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v":69:8:69:26|Synthesizing module miv_rv32_subsys_pkg in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":314:0:314:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":77:0:77:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit in library work.
@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB
@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":121:7:121:10|Synthesizing module AND2 in library work.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":333:7:333:11|Synthesizing module BIBUF in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":21:7:21:48|Synthesizing module Core_reset_pf_Core_reset_pf_0_CORERESET_PF in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v":21:7:21:19|Synthesizing module Core_reset_pf in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v":57:7:57:16|Synthesizing module CoreAPB3_0 in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":19:7:19:40|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_COREFIFO in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":20:7:20:51|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":20:7:20:45|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft in library work.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":254:38:254:55|Removing redundant assignment.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":578:7:578:13|Synthesizing module RAM1K20 in library work.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":500:7:500:9|Synthesizing module GND in library work.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":504:7:504:9|Synthesizing module VCC in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v":5:7:5:41|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":4:7:4:43|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v":49:7:49:17|Synthesizing module COREFIFO_C0 in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Synthesizing module COREJTAGDEBUG in library COREJTAGDEBUG_LIB.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":1442:7:1442:11|Synthesizing module UJTAG in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v":20:7:20:24|Synthesizing module corejtagdebug_bufd in library COREJTAGDEBUG_LIB.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":229:7:229:10|Synthesizing module BUFD in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v":47:7:47:27|Synthesizing module COREJTAGDEBUG_UJ_JTAG in library COREJTAGDEBUG_LIB.
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v":56:7:56:22|Synthesizing module COREJTAGDEBUG_C0 in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":31:7:31:12|Synthesizing module spi_rf in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v":24:7:24:17|Synthesizing module spi_control in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":25:7:25:14|Synthesizing module spi_fifo in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v":24:7:24:18|Synthesizing module spi_clockmux in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":29:7:29:18|Synthesizing module spi_chanctrl in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":29:7:29:9|Synthesizing module spi in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Synthesizing module CORESPI in library CORESPI_LIB.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v":32:7:32:15|Synthesizing module CORESPI_0 in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":31:7:31:15|Synthesizing module CORETSE_0 in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":356:21:356:29|Removing redundant assignment.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":30:7:30:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async in library work.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":254:23:254:35|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":280:18:280:25|Removing redundant assignment.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_COREUART in library work.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":390:22:390:33|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":254:31:254:41|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":275:31:275:41|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6111:72:6111:89|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6112:72:6112:89|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6113:72:6113:89|Removing redundant assignment.
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
@N: CL189 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Register bit gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5] is always 0.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16165:67:16165:73|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16173:67:16173:73|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16193:48:16193:54|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16194:48:16194:54|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16195:48:16195:54|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16196:48:16196:55|Removing redundant assignment.
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16380:45:16380:49|Removing redundant assignment.
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=41
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=34
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6281:36:6281:48|Removing redundant assignment.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v":59:0:59:5|Trying to extract state machine for register state.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":70:13:70:20|Input DLL_LOCK is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":77:13:77:20|Input PLL_LOCK is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":31:7:31:13|Input FAB_CLK is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|Trying to extract state machine for register tune_st.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13005:27:13005:40|Input mtime_count_in is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Trying to extract state machine for register cpu_d_wr_rd_state.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10821:49:10821:64|Input subsys_parity_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10830:49:10830:68|Input cpu_i_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10832:49:10832:64|Input cpu_i_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10834:49:10834:64|Input cpu_i_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10840:49:10840:68|Input cpu_d_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10842:49:10842:62|Input cpu_d_req_read is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10843:49:10843:63|Input cpu_d_req_write is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10845:49:10845:64|Input cpu_d_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10847:49:10847:67|Input cpu_d_req_wr_data_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10849:49:10849:64|Input cpu_d_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10855:49:10855:62|Input udma_req_valid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10857:49:10857:67|Input udma_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10858:49:10858:67|Input udma_req_wr_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10859:49:10859:61|Input udma_req_read is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10860:49:10860:62|Input udma_req_write is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10861:49:10861:61|Input udma_req_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10862:49:10862:63|Input udma_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10863:49:10863:60|Input udma_req_len is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10864:49:10864:64|Input udma_req_wr_data is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10865:49:10865:66|Input udma_req_wr_data_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10867:49:10867:63|Input udma_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10874:49:10874:70|Input tcm_dma_access_disable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10875:49:10875:70|Input tcm_tas_access_disable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10876:49:10876:65|Input tcm_tas_req_valid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10878:49:10878:70|Input tcm_tas_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10879:49:10879:70|Input tcm_tas_req_wr_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10880:49:10880:64|Input tcm_tas_req_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10881:49:10881:66|Input tcm_tas_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10882:49:10882:67|Input tcm_tas_req_wr_data is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10883:49:10883:69|Input tcm_tas_req_wr_data_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10885:49:10885:66|Input tcm_tas_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10890:49:10890:61|Input tcm_ram_sb_in is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10891:49:10891:71|Input tcm_ecc_error_injection is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Trying to extract state machine for register gen_apb_byte_shim.apb_st.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6063:49:6063:64|Input subsys_parity_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6070:49:6070:68|Input cpu_i_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6072:49:6072:64|Input cpu_i_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6074:49:6074:64|Input cpu_i_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6080:49:6080:68|Input cpu_d_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6083:49:6083:64|Input cpu_d_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6087:49:6087:64|Input cpu_d_resp_ready is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14736:0:14736:8|Trying to extract state machine for register debug_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Trying to extract state machine for register command_reg_state.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13800:39:13800:52|Input dmi_resp_ready is unused.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|Trying to extract state machine for register sba_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15942:48:15942:60|Input dtm_req_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":191:50:191:60|Input m_timer_irq is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":227:50:227:72|Input tcm1_cpu_access_disable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":228:50:228:72|Input tcm1_dma_access_disable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":229:50:229:72|Input tcm1_tas_access_disable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":230:50:230:62|Input tcm_tas_paddr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":231:50:231:64|Input tcm_tas_paddr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":232:50:232:62|Input tcm_tas_pprot is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":233:50:233:61|Input tcm_tas_psel is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":234:50:234:64|Input tcm_tas_penable is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":235:50:235:63|Input tcm_tas_pwrite is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":236:50:236:63|Input tcm_tas_pwdata is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":237:50:237:65|Input tcm_tas_pwdata_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":248:50:248:63|Input tcm1_ram_sb_in is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":252:50:252:60|Input axi_aclk_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":261:50:261:60|Input axi_arready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":264:50:264:58|Input axi_rresp is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":265:50:265:58|Input axi_rdata is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":266:50:266:58|Input axi_rlast is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":267:50:267:56|Input axi_rid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":269:50:269:59|Input axi_rvalid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":270:50:270:61|Input axi_r_data_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":280:50:280:60|Input axi_awready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":286:50:286:59|Input axi_wready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":289:50:289:58|Input axi_bresp is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":290:50:290:56|Input axi_bid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":292:50:292:59|Input axi_bvalid is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":305:50:305:59|Input ahb_hrdata is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":306:50:306:61|Input ahb_hrdata_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":307:50:307:59|Input ahb_hready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":308:50:308:58|Input ahb_hresp is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2492:49:2492:66|Input cfg_axi_start_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2493:49:2493:64|Input cfg_axi_end_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2496:49:2496:66|Input cfg_ahb_start_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2497:49:2497:64|Input cfg_ahb_end_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2498:49:2498:72|Input cfg_udma_ctrl_start_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2499:49:2499:70|Input cfg_udma_ctrl_end_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2504:49:2504:67|Input cfg_tcm1_start_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2505:49:2505:65|Input cfg_tcm1_end_addr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2575:49:2575:63|Input apb_trx_os_d_rd is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2576:49:2576:63|Input apb_trx_os_d_wr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2604:49:2604:64|Input tcm0_trx_os_d_rd is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2605:49:2605:64|Input tcm0_trx_os_d_wr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2611:49:2611:64|Input tcm1_i_req_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2621:49:2621:64|Input tcm1_d_req_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2635:49:2635:64|Input tcm1_trx_os_d_rd is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2636:49:2636:64|Input tcm1_trx_os_d_wr is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2642:49:2642:63|Input axi_i_req_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2647:49:2647:63|Input axi_i_resp_last is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2653:49:2653:63|Input axi_d_req_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2668:49:2668:63|Input axi_trx_os_d_rd is unused.
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=7
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=11
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=6
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":286:0:286:5|Trying to extract state machine for register rx_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Trying to extract state machine for register xmit_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state.
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=1
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=16
@N: CL135 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1.
@N|Running in 64-bit mode

41
synthesis/synlog/report/top_compiler_runstatus.xml Normal file
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@@ -0,0 +1,41 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the job information from compiler to be displayed as part of the summary report.
*******************************************************************************************-->
<job_run_status name="compiler">
<report_link name="Detailed report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr</data>
<title>Synopsys HDL Compiler</title>
</report_link>
<job_status>
<data>Completed </data>
</job_status>
<job_info>
<info name="Notes">
<data>236</data>
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>403</data>
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
<data>0</data>
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_errors.txt</data></report_link>
</info>
<info name="CPU Time">
<data>-</data>
</info>
<info name="Real Time">
<data>00h:02m:53s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1776273469</data>
</info>
</job_info>
</job_run_status>

404
synthesis/synlog/report/top_compiler_warnings.txt Normal file
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@@ -0,0 +1,404 @@
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":21:13:21:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":61:13:61:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":88:13:88:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":118:13:118:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":168:13:168:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":213:13:213:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":232:13:232:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":281:13:281:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":335:13:335:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":657:13:657:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":761:13:761:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":795:13:795:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1059:13:1059:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1369:13:1369:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1396:13:1396:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1441:13:1441:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1474:13:1474:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1492:13:1492:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1518:13:1518:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1559:13:1559:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1581:13:1581:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1599:13:1599:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1616:13:1616:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1635:13:1635:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1652:13:1652:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1681:13:1681:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1712:13:1712:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1802:13:1802:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2026:13:2026:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2187:13:2187:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2203:13:2203:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2219:13:2219:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2235:13:2235:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2267:13:2267:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2648:13:2648:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3661:13:3661:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3732:13:3732:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3861:13:3861:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3879:13:3879:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3896:13:3896:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3911:13:3911:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3926:13:3926:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3953:13:3953:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4067:13:4067:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4098:13:4098:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4144:13:4144:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4255:13:4255:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4439:13:4439:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4480:13:4480:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4506:13:4506:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4523:13:4523:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4600:13:4600:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":5364:13:5364:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6174:13:6174:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6283:13:6283:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6321:13:6321:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6394:13:6394:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":7283:13:7283:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":8340:13:8340:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":9299:13:9299:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10035:13:10035:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10750:13:10750:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10784:13:10784:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10820:13:10820:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10867:13:10867:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10901:13:10901:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":11767:13:11767:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12810:13:12810:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12822:15:12822:27|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12831:13:12831:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12843:13:12843:25|User defined pragma syn_black_box detected
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12856:13:12856:25|User defined pragma syn_black_box detected
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":805:7:805:17|Net resetn_rx_s is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":430844:0:430844:4|Net ooOI1 is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":430859:0:430859:4|Net ioOI1 is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":476678:0:476678:4|Net oI0i0 is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":476693:0:476693:4|Net Ol0i0 is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548082:0:548082:4|Net l0iIo is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548102:0:548102:4|Net o0iIo is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548122:0:548122:4|Net i0iIo is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548142:0:548142:4|Net O1iIo is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548162:0:548162:4|Net I1iIo is not declared.
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548182:0:548182:4|Net l1iIo is not declared.
@W: CS138 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":26989:0:26931:8|Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine.
@W: CS138 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":26990:0:26931:8|Macro definition for RAM_BIST_VIEW not found. Cannot undefine.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":29121:14:29121:28|Unrecognized synthesis directive dc_script_begin. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":29124:14:29124:26|Unrecognized synthesis directive dc_script_end. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":33910:104:33910:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":34706:104:34706:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35086:104:35086:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35316:104:35316:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35536:104:35536:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35932:104:35932:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36264:104:36264:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36476:104:36476:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36692:104:36692:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37011:104:37011:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37227:104:37227:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37457:104:37457:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37837:104:37837:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38116:104:38116:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38316:104:38316:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38581:104:38581:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CG104 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":39241:39:39241:39|Unsized number in concatenation is 32 bits
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":39806:106:39806:105|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42208:104:42208:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42549:104:42549:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":173:29:173:37|Removing wire neg_reset, as there is no assignment to it.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register full_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":371:4:371:9|Pruning unused register sc_w[10:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":331:6:331:11|Pruning unused register we_f_i. Make sure that there are no unused intermediate registers.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.wack_r assign 0, register removed by optimization.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.overflow_r assign 0, register removed by optimization.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to underflow_r assign 0, register removed by optimization.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to dvld_r assign 0, register removed by optimization.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":275:3:275:8|All reachable assignments to rdcnt[10:0] assign 0, register removed by optimization.
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":248:3:248:8|All reachable assignments to wrcnt[10:0] assign 0, register removed by optimization.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":119:27:119:32|Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":125:27:125:33|Removing wire aresetn, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":132:27:132:32|Removing wire empty1, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":140:8:140:17|Removing wire reset_wclk, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":141:8:141:17|Removing wire reset_rclk, as there is no assignment to it.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":358:3:358:8|Pruning unused register we_p_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":244:3:244:8|Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":233:4:233:9|Pruning unused register re_p_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":46:26:46:37|*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":47:26:47:37|*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":48:26:48:36|*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":49:26:49:36|*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":211:36:211:46|Removing wire pf_MEMRADDR, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":217:36:217:39|Removing wire pf_Q, as there is no assignment to it.
@W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":236:36:236:45|Removing wire DVLD_async, as it has the load but no drivers.
@W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":238:36:238:44|Removing wire DVLD_sync, as it has the load but no drivers.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":241:36:241:42|Removing wire pf_dvld, as there is no assignment to it.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":250:36:250:44|Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":264:36:264:41|Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":283:8:283:17|Removing wire reset_rclk, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":284:8:284:17|Removing wire reset_wclk, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":285:8:285:19|Removing wire reset_sync_r, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":286:8:286:19|Removing wire reset_sync_w, as there is no assignment to it.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1175:3:1175:8|Pruning unused register RDATA_ext_r1[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1165:3:1165:8|Pruning unused register RDATA_ext_r[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1088:3:1088:8|Pruning unused register RDATA_r2[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1078:3:1078:8|Pruning unused register RDATA_r1[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1068:3:1068:8|Pruning unused register RDATA_r_pre[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1058:3:1058:8|Pruning unused register fwft_Q_r[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|Removing wire UTRSTB, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|Removing wire UTMS, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":169:8:169:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":176:8:176:52|Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":183:8:183:52|Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":190:8:190:52|Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":241:28:241:37|Removing wire iURSTB_inv, as there is no assignment to it.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL208 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":134:0:134:5|All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization.
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":195:12:195:22|Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":196:12:196:22|Removing wire resetn_rx_p, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":200:12:200:22|Removing wire resetn_rx_r, as there is no assignment to it.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":222:12:222:36|Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":1130:0:1130:5|Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":719:0:719:5|Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers.
@W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":343:0:343:5|Sharing sequential element cfg_enable_P1 and merging msrx_async_reset_ok. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":270:0:270:10|Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
@W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":501:0:501:5|Sharing sequential element clear_framing_error_en and merging clear_parity_en. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":136:8:136:17|Object data_ready is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":376:0:376:5|Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":326:0:326:5|Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":293:0:293:5|Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":159:0:159:5|Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":158:20:158:30|Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19009:38:19009:51|Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19017:38:19017:57|Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19020:38:19020:53|Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19021:38:19021:58|Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19022:38:19022:62|Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19023:38:19023:67|Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19024:38:19024:49|Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19025:38:19025:49|Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19026:38:19026:56|Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19027:38:19027:52|Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration.
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10766:32:10766:40|Object fpu_frm_i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10767:32:10767:35|Object op_i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":843:10:843:11|Object status_o.NV is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":844:10:844:11|Object status_o.DZ is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":845:10:845:11|Object status_o.OF is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":846:10:846:11|Object status_o.UF is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4310:6:4310:26|Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10390:2:10390:7|Pruning unused register sreset. Make sure that there are no unused intermediate registers.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Pruning register bit 5 of gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25538:12:25538:44|Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25498:12:25498:43|Removing instance miv_rv32_ram_singleport_lp_R20C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25465:27:25465:41|Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25376:12:25376:43|Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25295:12:25295:43|Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25265:27:25265:41|Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25182:12:25182:43|Removing instance miv_rv32_ram_singleport_lp_R24C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25159:27:25159:41|Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25104:27:25104:40|Removing instance \CFG2_BLKY2[6] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25049:12:25049:43|Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24993:12:24993:43|Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24990:27:24990:33|Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24953:12:24953:43|Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24901:12:24901:44|Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24863:12:24863:43|Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24853:27:24853:41|Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24804:12:24804:43|Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24764:12:24764:43|Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24686:12:24686:44|Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24667:27:24667:41|Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24622:12:24622:44|Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24548:12:24548:43|Removing instance miv_rv32_ram_singleport_lp_R31C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24502:27:24502:41|Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24492:27:24492:41|Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24490:28:24490:34|Removing instance CFG3_22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24451:12:24451:43|Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24412:12:24412:43|Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24308:12:24308:43|Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24268:12:24268:43|Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24254:28:24254:34|Removing instance CFG3_11 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24231:27:24231:32|Removing instance CFG3_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24202:28:24202:34|Removing instance CFG3_21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24148:12:24148:43|Removing instance miv_rv32_ram_singleport_lp_R25C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24142:27:24142:41|Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24105:12:24105:43|Removing instance miv_rv32_ram_singleport_lp_R28C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24033:12:24033:43|Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24029:27:24029:40|Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23903:12:23903:44|Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23864:12:23864:44|Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23805:12:23805:43|Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23799:27:23799:40|Removing instance \CFG2_BLKY2[7] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23753:12:23753:44|Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23685:12:23685:43|Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23662:27:23662:40|Removing instance \CFG2_BLKY2[5] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23601:12:23601:44|Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23540:27:23540:41|Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23490:12:23490:43|Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23440:12:23440:43|Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23401:12:23401:44|Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23338:12:23338:43|Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23292:27:23292:41|Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23222:12:23222:43|Removing instance miv_rv32_ram_singleport_lp_R26C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23130:12:23130:43|Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23092:12:23092:43|Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23071:27:23071:41|Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23012:12:23012:43|Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22972:12:22972:44|Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22882:27:22882:41|Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22821:12:22821:43|Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22779:12:22779:43|Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22733:12:22733:43|Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22687:12:22687:43|Removing instance miv_rv32_ram_singleport_lp_R27C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22671:27:22671:41|Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22665:27:22665:41|Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22600:12:22600:43|Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22556:12:22556:44|Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22510:12:22510:43|Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22433:27:22433:41|Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22330:12:22330:43|Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22260:12:22260:43|Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22193:12:22193:43|Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22147:12:22147:43|Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22094:12:22094:43|Removing instance miv_rv32_ram_singleport_lp_R29C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21997:12:21997:44|Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21988:27:21988:41|Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21943:12:21943:43|Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21894:12:21894:43|Removing instance miv_rv32_ram_singleport_lp_R30C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21848:12:21848:43|Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21845:27:21845:40|Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21838:28:21838:33|Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21814:27:21814:41|Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21791:27:21791:41|Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21713:12:21713:44|Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21667:12:21667:43|Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21589:12:21589:43|Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21586:27:21586:41|Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21578:27:21578:41|Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21562:27:21562:41|Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21440:12:21440:43|Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21385:12:21385:43|Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21341:27:21341:41|Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21304:12:21304:43|Removing instance miv_rv32_ram_singleport_lp_R18C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21236:12:21236:44|Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21193:12:21193:43|Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21098:28:21098:33|Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_tas_access_disable_reg. Make sure that there are no unused intermediate registers.
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11237:2:11237:7|Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1481:45:1481:63|Port-width mismatch for port cpu_i_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1494:45:1494:63|Port-width mismatch for port cpu_d_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1509:45:1509:66|Port-width mismatch for port udma_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1526:44:1526:64|Port-width mismatch for port tcm_tas_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v":343:13:343:33|Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it.
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v":305:34:305:52|Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:45:70:45|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:54:70:54|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":64:23:64:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":67:13:67:13|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:34:49:34|Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:46:49:46|Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:59:49:59|Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:17:50:17|Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:26:50:26|Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:41:50:41|Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:55:50:55|Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:69:50:69|Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:21:51:21|Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:35:51:35|Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:49:51:49|Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:65:51:65|Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:19:52:19|Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:34:52:34|Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:59:52:59|Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:20:54:20|Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:36:54:36|Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":59:21:59:21|Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:23:94:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:32:94:32|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
@W: CG168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":47:27:47:36|Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v":24:12:24:18|Input port bits 9 to 7 of rx_data[9:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10831:49:10831:62|Input port bits 1 to 0 of cpu_i_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10844:49:10844:62|Input port bits 1 to 0 of cpu_d_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2494:49:2494:66|Input port bits 11 to 0 of cfg_apb_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2495:49:2495:64|Input port bits 11 to 0 of cfg_apb_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2500:49:2500:73|Input port bits 11 to 0 of cfg_subsys_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2501:49:2501:71|Input port bits 11 to 0 of cfg_subsys_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2502:49:2502:67|Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2503:49:2503:65|Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4490:49:4490:71|Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4495:49:4495:68|Input port bits 31 to 3 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6360:31:6360:36|Input port bit 5 of waddr0[5:0] is unused
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":1854:60:1854:72|Input port bit 1 of excpt_trigger[1:0] is unused
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6896:43:6896:57|Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":104:20:104:24|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.

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synthesis/synlog/report/top_fpga_mapper_area_report.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the area information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<report_table display_priority="1" name="Area Summary">
<report_link name="Detailed report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_resourceusage.rpt</data>
<title>Resource Usage</title>
</report_link>
<report_link name="Hierarchical Area report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_hier_area_report.xml</data>
<title>Hierarchical Area Report</title>
</report_link>
<parameter tooltip="Total Carry Cells used" name="Carry Cells">
<data>2335</data>
</parameter>
<parameter tooltip="Total Sequential Cells used" name="Sequential Cells">
<data>7316</data>
</parameter>
<parameter tcl_name="dsp_used" tooltip="Total DSP Blocks used" name="DSP Blocks">
<data>0</data>
</parameter>
<parameter tooltip="Total I/O Cells used" name="I/O Cells">
<data>50</data>
</parameter>
<parameter tooltip="Total Global Clock Buffers used" name="Global Clock Buffers">
<data>7</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total RAM1K20 used" name="RAM1K20">
<data>34</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total RAM64x12 used" name="RAM64x12">
<data>11</data>
</parameter>
<parameter tcl_name="total_luts" tooltip="Total LUTs used" name="LUTs">
<data>15992</data>
</parameter>
</report_table>

0
synthesis/synlog/report/top_fpga_mapper_errors.txt Normal file
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238
synthesis/synlog/report/top_fpga_mapper_hier_area.csv Normal file
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. Module name, SLE, CFG, ARI1, BUFFER, MACC_PA, RAM1K20, RAM64X12, GLOBAL, IO
. top, 7316, 13657, 2335, 102, 0, 34, 11, 7, 50
. . COREFIFO_C0, 148, 90, 58, 0, 0, 2, 0, 0, 0
. . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2, 148, 90, 58, 0, 0, 2, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4, 68, 38, 0, 0, 0, 0, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3, 45, 17, 58, 0, 0, 0, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . . . . COREFIFO_C0_COREFIFO_C0_0_LSRAM_top, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . COREJTAGDEBUG_C0, 17, 117, 0, 102, 0, 0, 0, 2, 0
. . . COREJTAGDEBUG_Z5, 17, 117, 0, 102, 0, 0, 0, 2, 0
. . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0, 17, 114, 0, 68, 0, 0, 0, 0, 0
. . . . . corejtagdebug_bufd_34s, 0, 0, 0, 34, 0, 0, 0, 0, 0
. . . . . corejtagdebug_bufd_34s_0, 0, 0, 0, 34, 0, 0, 0, 0, 0
. . . . corejtagdebug_bufd_34s_2, 0, 0, 0, 34, 0, 0, 0, 0, 0
. . CORESPI_0, 247, 345, 30, 0, 0, 0, 4, 0, 0
. . . CORESPI_Z7, 247, 345, 30, 0, 0, 0, 4, 0, 0
. . . . spi_32s_16s_32s_16s_0_0_1_0s, 247, 345, 30, 0, 0, 0, 4, 0, 0
. . . . . spi_chanctrl_Z6, 168, 187, 18, 0, 0, 0, 0, 0, 0
. . . . . . spi_clockmux, 0, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . spi_control_16s, 0, 14, 0, 0, 0, 0, 0, 0, 0
. . . . . spi_fifo_16s_32s_5_0, 18, 29, 6, 0, 0, 0, 2, 0, 0
. . . . . spi_fifo_16s_32s_5_1, 18, 31, 6, 0, 0, 0, 2, 0, 0
. . . . . spi_rf_32s_16s_0, 43, 84, 0, 0, 0, 0, 0, 0, 0
. . CORETSE_0, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
. . . CORETSE_Z11, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
. . . . CTSE_CORETSE_TOP_Z10, 4497, 6431, 1302, 0, 0, 12, 0, 0, 0
. . . . . CTSE_CLKRST_26s_1s, 14, 7, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_ECC_0s_26s_16s, 44, 20, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_3, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_3, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_4, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_5, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s, 1041, 1814, 113, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVRXI_26s, 208, 188, 7, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVRXO_26s, 18, 22, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVTXI_26s, 108, 108, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVTXO_26s, 24, 12, 8, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s, 681, 1483, 98, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s, 231, 194, 67, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEANX_SYNC_1s_26s, 60, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PCS_0s_26s_1s, 121, 553, 27, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_0, 0, 131, 21, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_1, 0, 158, 6, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4, 103, 307, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETBM_26s_0s_1s, 124, 181, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETCR_26s_1s, 5, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETEX_TOP_26s_0s_1s, 97, 245, 4, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_T8B10B, 0, 112, 4, 0, 0, 0, 0, 0, 0
. . . . . CTSE_RX4096X36_12s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 8, 0, 0, 0
. . . . . CTSE_TSMAC_TOP_Z9, 3378, 4590, 1189, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s, 231, 257, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_DECODER, 0, 82, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_TSM_SYSREG_26s_1s_0s, 230, 171, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MMCXWOL_1s_26s, 52, 93, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PEMSTAT_26s, 764, 1447, 606, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s, 65, 121, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s, 51, 589, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_STORE_26s, 648, 737, 606, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s, 25, 28, 24, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s_0, 25, 27, 24, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_0, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_1, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_10, 19, 21, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_11, 19, 21, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_2, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_3, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_4, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_5, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_6, 19, 21, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_7, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_8, 19, 22, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_9, 19, 21, 18, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SADD_1s_26s, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_0, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_1, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_2, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_3, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_4, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_0, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_1, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_2, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_3, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_4, 13, 14, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_0, 13, 16, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_1, 13, 16, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_10, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_11, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_12, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_2, 13, 16, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_3, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_4, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_5, 13, 16, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_6, 13, 16, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_7, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_8, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_9, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s, 1046, 1569, 266, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PECAR_26s_1s, 13, 9, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEHST_1s_26s, 222, 71, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMGT_1s_26s, 111, 209, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s, 700, 1264, 266, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s, 223, 362, 128, 0, 0, 0, 0, 0, 0
. . . . . . . . . CTSE_PECRC_1s_26s_1, 32, 78, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PERMC_TOP_1s_26s, 117, 177, 23, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s, 324, 610, 79, 0, 0, 0, 0, 0, 0
. . . . . . . . . CTSE_PECRC_1s_26s_0, 32, 163, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PETMC_TOP_1s_26s, 36, 114, 36, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SI_SAL_26s, 3, 115, 0, 0, 0, 0, 0, 0, 0
. . . . . . OiOI1_26s_11s_12s_32s_2s_0s, 1263, 683, 317, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXFIF_CLKRST_26s_1s, 10, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXFIF_HST_Z8, 266, 68, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s, 238, 176, 33, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s, 303, 188, 62, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s, 152, 86, 60, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s, 198, 121, 88, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0, 90, 39, 74, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_TX2048X40_11s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 4, 0, 0, 0
. . . . CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12, 104, 57, 68, 0, 0, 0, 0, 0, 0
. . CoreAPB3_0, 0, 15, 0, 0, 0, 0, 0, 0, 0
. . . CoreAPB3_Z1, 0, 15, 0, 0, 0, 0, 0, 0, 0
. . . . COREAPB3_MUXPTOB3, 0, 11, 0, 0, 0, 0, 0, 0, 0
. . CoreUARTapb_0, 114, 134, 19, 0, 0, 0, 0, 0, 0
. . . CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13, 114, 134, 19, 0, 0, 0, 0, 0, 0
. . . . CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s, 90, 107, 19, 0, 0, 0, 0, 0, 0
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s, 19, 10, 14, 0, 0, 0, 0, 0, 0
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s, 41, 68, 0, 0, 0, 0, 0, 0, 0
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s, 21, 23, 5, 0, 0, 0, 0, 0, 0
. . Core_reset_pf, 16, 2, 0, 0, 0, 0, 0, 0, 0
. . . Core_reset_pf_Core_reset_pf_0_CORERESET_PF, 16, 2, 0, 0, 0, 0, 0, 0, 0
. . MIV_RV32_C0, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . . miv_rv32_ipcore_Z19, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . . . miv_rv32_hart_Z17, 1001, 4216, 580, 0, 0, 0, 6, 0, 0
. . . . . . miv_rv32_expipe_Z16, 759, 3565, 546, 0, 0, 0, 6, 0, 0
. . . . . . . miv_rv32_bcu, 0, 47, 92, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_decode_1s_1s_0s, 0, 38, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_privarch_Z15, 254, 697, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_decode_0s_1s_0s, 0, 66, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_2, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_3, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_5, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12, 1, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_5, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4, 1, 339, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_30s_1s_536870913, 30, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_31s_0s_0s, 31, 32, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_0, 32, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_1, 32, 33, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_0, 32, 34, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_1, 31, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968, 32, 66, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_3s_1s_0s_0, 3, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_5s_1s_0, 5, 8, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_priv_irq_2s_0_0, 2, 23, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s, 1, 9, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1, 202, 1599, 422, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s, 20, 42, 0, 0, 0, 0, 6, 0, 0
. . . . . . . . miv_rv32_gpr_ram_array_32s_6s_32s, 0, 6, 0, 0, 0, 0, 6, 0, 0
. . . . . . . miv_rv32_idecode_1_1s_1s_0s, 0, 1044, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14, 220, 453, 30, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s, 215, 213, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s, 22, 198, 4, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5, 115, 172, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_2s_1s_1s, 4, 18, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_debug_1s, 664, 1043, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_dtm_jtag_1s, 109, 207, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_du, 379, 738, 40, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_debug_sba, 166, 670, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_fifo_34s_1s_1s, 80, 45, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_fifo_41s_1s_1s, 96, 53, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_interconnect_Z18, 55, 373, 0, 0, 0, 0, 1, 0, 0
. . . . . . miv_rv32_buffer_11s_2s_1s_1s, 29, 19, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_buffer_6s_2s_1s_1s, 17, 13, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s, 9, 28, 0, 0, 0, 0, 1, 0, 0
. . . . . . . miv_rv32_buffer_7s_2s_1s_1s, 5, 13, 0, 0, 0, 0, 1, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_1, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820, 176, 270, 145, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_tcm_Z20, 58, 169, 0, 0, 0, 18, 0, 0, 0
. . . . . . miv_rv32_ram_singleport_lp_Z21, 0, 22, 0, 0, 0, 18, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_3s_1s_1s, 3, 147, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_fixed_arb_3s_2, 0, 81, 0, 0, 0, 0, 0, 0, 0
. . PF_CCC_0, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_CCC_0_PF_CCC_0_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . PF_IOD_CDR_C0, 59, 153, 74, 0, 0, 0, 0, 2, 2
. . . CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1, 59, 151, 74, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL, 0, 1, 0, 0, 0, 0, 0, 1, 0
. . PF_IOD_CDR_CCC_C0, 31, 22, 8, 0, 0, 0, 0, 2, 0
. . . COREDELAYCODE_TIP, 31, 22, 8, 0, 0, 0, 0, 0, 0
. . . PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . PF_TPSRAM_C0, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . SSDetect, 2, 7, 0, 0, 0, 0, 0, 0, 0
. . fifo_to_tpsram_bridge, 12, 5, 11, 0, 0, 0, 0, 0, 0
. . pf_init_monitor_0, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR, 0, 0, 0, 0, 0, 0, 0, 0, 0
1 . Module name SLE CFG ARI1 BUFFER MACC_PA RAM1K20 RAM64X12 GLOBAL IO
2 . top 7316 13657 2335 102 0 34 11 7 50
3 . . COREFIFO_C0 148 90 58 0 0 2 0 0 0
4 . . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 148 90 58 0 0 2 0 0 0
5 . . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 68 38 0 0 0 0 0 0 0
6 . . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 45 17 58 0 0 0 0 0 0
7 . . . . COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s 0 0 0 0 0 2 0 0 0
8 . . . . . COREFIFO_C0_COREFIFO_C0_0_LSRAM_top 0 0 0 0 0 2 0 0 0
9 . . COREJTAGDEBUG_C0 17 117 0 102 0 0 0 2 0
10 . . . COREJTAGDEBUG_Z5 17 117 0 102 0 0 0 2 0
11 . . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 17 114 0 68 0 0 0 0 0
12 . . . . . corejtagdebug_bufd_34s 0 0 0 34 0 0 0 0 0
13 . . . . . corejtagdebug_bufd_34s_0 0 0 0 34 0 0 0 0 0
14 . . . . corejtagdebug_bufd_34s_2 0 0 0 34 0 0 0 0 0
15 . . CORESPI_0 247 345 30 0 0 0 4 0 0
16 . . . CORESPI_Z7 247 345 30 0 0 0 4 0 0
17 . . . . spi_32s_16s_32s_16s_0_0_1_0s 247 345 30 0 0 0 4 0 0
18 . . . . . spi_chanctrl_Z6 168 187 18 0 0 0 0 0 0
19 . . . . . . spi_clockmux 0 1 0 0 0 0 0 0 0
20 . . . . . spi_control_16s 0 14 0 0 0 0 0 0 0
21 . . . . . spi_fifo_16s_32s_5_0 18 29 6 0 0 0 2 0 0
22 . . . . . spi_fifo_16s_32s_5_1 18 31 6 0 0 0 2 0 0
23 . . . . . spi_rf_32s_16s_0 43 84 0 0 0 0 0 0 0
24 . . CORETSE_0 4601 6488 1370 0 0 12 0 0 0
25 . . . CORETSE_Z11 4601 6488 1370 0 0 12 0 0 0
26 . . . . CTSE_CORETSE_TOP_Z10 4497 6431 1302 0 0 12 0 0 0
27 . . . . . CTSE_CLKRST_26s_1s 14 7 0 0 0 0 0 0 0
28 . . . . . CTSE_ECC_0s_26s_16s 44 20 0 0 0 0 0 0 0
29 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_0 3 0 0 0 0 0 0 0 0
30 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_1 3 0 0 0 0 0 0 0 0
31 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s 8 2 0 0 0 0 0 0 0
32 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_1 3 0 0 0 0 0 0 0 0
33 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_2 3 0 0 0 0 0 0 0 0
34 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16_0 8 2 0 0 0 0 0 0 0
35 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_2 3 0 0 0 0 0 0 0 0
36 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_3 3 0 0 0 0 0 0 0 0
37 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17 8 2 0 0 0 0 0 0 0
38 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_2 3 0 0 0 0 0 0 0 0
39 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_3 3 0 0 0 0 0 0 0 0
40 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17_0 8 2 0 0 0 0 0 0 0
41 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_4 3 0 0 0 0 0 0 0 0
42 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_5 3 0 0 0 0 0 0 0 0
43 . . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s 1041 1814 113 0 0 0 0 0 0
44 . . . . . . CTSE_MSGMII_CNVRXI_26s 208 188 7 0 0 0 0 0 0
45 . . . . . . CTSE_MSGMII_CNVRXO_26s 18 22 0 0 0 0 0 0 0
46 . . . . . . CTSE_MSGMII_CNVTXI_26s 108 108 0 0 0 0 0 0 0
47 . . . . . . CTSE_MSGMII_CNVTXO_26s 24 12 8 0 0 0 0 0 0
48 . . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s 681 1483 98 0 0 0 0 0 0
49 . . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s 231 194 67 0 0 0 0 0 0
50 . . . . . . . . CTSE_PEANX_SYNC_1s_26s 60 2 0 0 0 0 0 0 0
51 . . . . . . . CTSE_PEREX_PCS_0s_26s_1s 121 553 27 0 0 0 0 0 0
52 . . . . . . . . CTSE_R10B8B_0 0 131 21 0 0 0 0 0 0
53 . . . . . . . . CTSE_R10B8B_1 0 158 6 0 0 0 0 0 0
54 . . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 103 307 0 0 0 0 0 0 0
55 . . . . . . . CTSE_PETBM_26s_0s_1s 124 181 0 0 0 0 0 0 0
56 . . . . . . . CTSE_PETCR_26s_1s 5 3 0 0 0 0 0 0 0
57 . . . . . . . CTSE_PETEX_TOP_26s_0s_1s 97 245 4 0 0 0 0 0 0
58 . . . . . . . . CTSE_T8B10B 0 112 4 0 0 0 0 0 0
59 . . . . . CTSE_RX4096X36_12s_26s_1s_1s_4s 0 0 0 0 0 8 0 0 0
60 . . . . . CTSE_TSMAC_TOP_Z9 3378 4590 1189 0 0 0 0 0 0
61 . . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s 231 257 0 0 0 0 0 0 0
62 . . . . . . . CTSE_DECODER 0 82 0 0 0 0 0 0 0
63 . . . . . . . CTSE_TSM_SYSREG_26s_1s_0s 230 171 0 0 0 0 0 0 0
64 . . . . . . CTSE_MMCXWOL_1s_26s 52 93 0 0 0 0 0 0 0
65 . . . . . . CTSE_PEMSTAT_26s 764 1447 606 0 0 0 0 0 0
66 . . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s 65 121 0 0 0 0 0 0 0
67 . . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s 51 589 0 0 0 0 0 0 0
68 . . . . . . . CTSE_PEMSTAT_STORE_26s 648 737 606 0 0 0 0 0 0
69 . . . . . . . . CTSE_PEMSTAT_LADD_1s_26s 25 28 24 0 0 0 0 0 0
70 . . . . . . . . CTSE_PEMSTAT_LADD_1s_26s_0 25 27 24 0 0 0 0 0 0
71 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s 19 22 18 0 0 0 0 0 0
72 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_0 19 22 18 0 0 0 0 0 0
73 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_1 19 22 18 0 0 0 0 0 0
74 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_10 19 21 18 0 0 0 0 0 0
75 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_11 19 21 18 0 0 0 0 0 0
76 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_2 19 22 18 0 0 0 0 0 0
77 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_3 19 22 18 0 0 0 0 0 0
78 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_4 19 22 18 0 0 0 0 0 0
79 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_5 19 22 18 0 0 0 0 0 0
80 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_6 19 21 18 0 0 0 0 0 0
81 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_7 19 22 18 0 0 0 0 0 0
82 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_8 19 22 18 0 0 0 0 0 0
83 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_9 19 21 18 0 0 0 0 0 0
84 . . . . . . . . CTSE_PEMSTAT_SADD_1s_26s 13 14 12 0 0 0 0 0 0
85 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s 13 15 12 0 0 0 0 0 0
86 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_0 13 15 12 0 0 0 0 0 0
87 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_1 13 15 12 0 0 0 0 0 0
88 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_2 13 14 12 0 0 0 0 0 0
89 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_3 13 14 12 0 0 0 0 0 0
90 . . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_4 13 14 12 0 0 0 0 0 0
91 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s 13 14 12 0 0 0 0 0 0
92 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_0 13 14 12 0 0 0 0 0 0
93 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_1 13 14 12 0 0 0 0 0 0
94 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_2 13 14 12 0 0 0 0 0 0
95 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_3 13 14 12 0 0 0 0 0 0
96 . . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_4 13 14 12 0 0 0 0 0 0
97 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s 13 15 12 0 0 0 0 0 0
98 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_0 13 16 12 0 0 0 0 0 0
99 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_1 13 16 12 0 0 0 0 0 0
100 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_10 13 15 12 0 0 0 0 0 0
101 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_11 13 15 12 0 0 0 0 0 0
102 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_12 13 15 12 0 0 0 0 0 0
103 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_2 13 16 12 0 0 0 0 0 0
104 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_3 13 15 12 0 0 0 0 0 0
105 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_4 13 15 12 0 0 0 0 0 0
106 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_5 13 16 12 0 0 0 0 0 0
107 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_6 13 16 12 0 0 0 0 0 0
108 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_7 13 15 12 0 0 0 0 0 0
109 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_8 13 15 12 0 0 0 0 0 0
110 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_9 13 15 12 0 0 0 0 0 0
111 . . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s 1046 1569 266 0 0 0 0 0 0
112 . . . . . . . CTSE_PECAR_26s_1s 13 9 0 0 0 0 0 0 0
113 . . . . . . . CTSE_PEHST_1s_26s 222 71 0 0 0 0 0 0 0
114 . . . . . . . CTSE_PEMGT_1s_26s 111 209 0 0 0 0 0 0 0
115 . . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s 700 1264 266 0 0 0 0 0 0
116 . . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s 223 362 128 0 0 0 0 0 0
117 . . . . . . . . . CTSE_PECRC_1s_26s_1 32 78 0 0 0 0 0 0 0
118 . . . . . . . . CTSE_PERMC_TOP_1s_26s 117 177 23 0 0 0 0 0 0
119 . . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s 324 610 79 0 0 0 0 0 0
120 . . . . . . . . . CTSE_PECRC_1s_26s_0 32 163 0 0 0 0 0 0 0
121 . . . . . . . . CTSE_PETMC_TOP_1s_26s 36 114 36 0 0 0 0 0 0
122 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_1 3 0 0 0 0 0 0 0 0
123 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_0 8 2 0 0 0 0 0 0 0
124 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_0 3 0 0 0 0 0 0 0 0
125 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_1 3 0 0 0 0 0 0 0 0
126 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16 8 2 0 0 0 0 0 0 0
127 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s 3 0 0 0 0 0 0 0 0
128 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_0 3 0 0 0 0 0 0 0 0
129 . . . . . . CTSE_SI_SAL_26s 3 115 0 0 0 0 0 0 0
130 . . . . . . OiOI1_26s_11s_12s_32s_2s_0s 1263 683 317 0 0 0 0 0 0
131 . . . . . . . CTSE_AMCXFIF_CLKRST_26s_1s 10 5 0 0 0 0 0 0 0
132 . . . . . . . CTSE_AMCXFIF_HST_Z8 266 68 0 0 0 0 0 0 0
133 . . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s 238 176 33 0 0 0 0 0 0
134 . . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s 303 188 62 0 0 0 0 0 0
135 . . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s 152 86 60 0 0 0 0 0 0
136 . . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s 198 121 88 0 0 0 0 0 0
137 . . . . . . . CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 90 39 74 0 0 0 0 0 0
138 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8 3 0 0 0 0 0 0 0 0
139 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_0 3 0 0 0 0 0 0 0 0
140 . . . . . CTSE_TX2048X40_11s_26s_1s_1s_4s 0 0 0 0 0 4 0 0 0
141 . . . . CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 104 57 68 0 0 0 0 0 0
142 . . CoreAPB3_0 0 15 0 0 0 0 0 0 0
143 . . . CoreAPB3_Z1 0 15 0 0 0 0 0 0 0
144 . . . . COREAPB3_MUXPTOB3 0 11 0 0 0 0 0 0 0
145 . . CoreUARTapb_0 114 134 19 0 0 0 0 0 0
146 . . . CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 114 134 19 0 0 0 0 0 0
147 . . . . CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s 90 107 19 0 0 0 0 0 0
148 . . . . . CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s 19 10 14 0 0 0 0 0 0
149 . . . . . CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s 41 68 0 0 0 0 0 0 0
150 . . . . . CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s 21 23 5 0 0 0 0 0 0
151 . . Core_reset_pf 16 2 0 0 0 0 0 0 0
152 . . . Core_reset_pf_Core_reset_pf_0_CORERESET_PF 16 2 0 0 0 0 0 0 0
153 . . MIV_RV32_C0 2069 6278 765 0 0 18 7 0 0
154 . . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 2069 6278 765 0 0 18 7 0 0
155 . . . . miv_rv32_ipcore_Z19 2069 6278 765 0 0 18 7 0 0
156 . . . . . miv_rv32_hart_Z17 1001 4216 580 0 0 0 6 0 0
157 . . . . . . miv_rv32_expipe_Z16 759 3565 546 0 0 0 6 0 0
158 . . . . . . . miv_rv32_bcu 0 47 92 0 0 0 0 0 0
159 . . . . . . . miv_rv32_csr_decode_1s_1s_0s 0 38 0 0 0 0 0 0 0
160 . . . . . . . miv_rv32_csr_privarch_Z15 254 697 32 0 0 0 0 0 0
161 . . . . . . . . miv_rv32_csr_decode_0s_1s_0s 0 66 0 0 0 0 0 0 0
162 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s 1 0 0 0 0 0 0 0 0
163 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_0 1 0 0 0 0 0 0 0 0
164 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_1 1 0 0 0 0 0 0 0 0
165 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_2 1 0 0 0 0 0 0 0 0
166 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_3 1 0 0 0 0 0 0 0 0
167 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_5 1 2 0 0 0 0 0 0 0
168 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12 1 5 0 0 0 0 0 0 0
169 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12_0 1 3 0 0 0 0 0 0 0
170 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_5 1 0 0 0 0 0 0 0 0
171 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7 1 3 0 0 0 0 0 0 0
172 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9 1 2 0 0 0 0 0 0 0
173 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0 1 1 0 0 0 0 0 0 0
174 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1 1 0 0 0 0 0 0 0 0
175 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2 1 0 0 0 0 0 0 0 0
176 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3 1 0 0 0 0 0 0 0 0
177 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4 1 339 32 0 0 0 0 0 0
178 . . . . . . . . miv_rv32_csr_gpr_state_reg_30s_1s_536870913 30 1 0 0 0 0 0 0 0
179 . . . . . . . . miv_rv32_csr_gpr_state_reg_31s_0s_0s 31 32 0 0 0 0 0 0 0
180 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_0 32 0 0 0 0 0 0 0 0
181 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_1 32 33 0 0 0 0 0 0 0
182 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_0 32 34 0 0 0 0 0 0 0
183 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_1 31 0 0 0 0 0 0 0 0
184 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 32 66 0 0 0 0 0 0 0
185 . . . . . . . . miv_rv32_csr_gpr_state_reg_3s_1s_0s_0 3 5 0 0 0 0 0 0 0
186 . . . . . . . . miv_rv32_csr_gpr_state_reg_5s_1s_0 5 8 0 0 0 0 0 0 0
187 . . . . . . . . miv_rv32_priv_irq_2s_0_0 2 23 0 0 0 0 0 0 0
188 . . . . . . . . . miv_rv32_irq_reg_0s 1 9 0 0 0 0 0 0 0
189 . . . . . . . . . miv_rv32_irq_reg_0s_0 1 3 0 0 0 0 0 0 0
190 . . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 202 1599 422 0 0 0 0 0 0
191 . . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s 20 42 0 0 0 0 6 0 0
192 . . . . . . . . miv_rv32_gpr_ram_array_32s_6s_32s 0 6 0 0 0 0 6 0 0
193 . . . . . . . miv_rv32_idecode_1_1s_1s_0s 0 1044 0 0 0 0 0 0 0
194 . . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 220 453 30 0 0 0 0 0 0
195 . . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s 215 213 0 0 0 0 0 0 0
196 . . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s 22 198 4 0 0 0 0 0 0
197 . . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 115 172 0 0 0 0 0 0 0
198 . . . . . . miv_rv32_rr_pri_arb_2s_1s_1s 4 18 0 0 0 0 0 0 0
199 . . . . . miv_rv32_subsys_debug_1s 664 1043 40 0 0 0 0 0 0
200 . . . . . . miv_rv32_debug_dtm_jtag_1s 109 207 0 0 0 0 0 0 0
201 . . . . . . miv_rv32_debug_du 379 738 40 0 0 0 0 0 0
202 . . . . . . . miv_rv32_debug_sba 166 670 40 0 0 0 0 0 0
203 . . . . . . miv_rv32_debug_fifo_34s_1s_1s 80 45 0 0 0 0 0 0 0
204 . . . . . . miv_rv32_debug_fifo_41s_1s_1s 96 53 0 0 0 0 0 0 0
205 . . . . . miv_rv32_subsys_interconnect_Z18 55 373 0 0 0 0 1 0 0
206 . . . . . . miv_rv32_buffer_11s_2s_1s_1s 29 19 0 0 0 0 0 0 0
207 . . . . . . miv_rv32_buffer_6s_2s_1s_1s 17 13 0 0 0 0 0 0 0
208 . . . . . . miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s 9 28 0 0 0 0 1 0 0
209 . . . . . . . miv_rv32_buffer_7s_2s_1s_1s 5 13 0 0 0 0 1 0 0
210 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s 1 2 0 0 0 0 0 0 0
211 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_0 1 0 0 0 0 0 0 0 0
212 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_1 1 1 0 0 0 0 0 0 0
213 . . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 176 270 145 0 0 0 0 0 0
214 . . . . . miv_rv32_subsys_tcm_Z20 58 169 0 0 0 18 0 0 0
215 . . . . . . miv_rv32_ram_singleport_lp_Z21 0 22 0 0 0 18 0 0 0
216 . . . . . . miv_rv32_rr_pri_arb_3s_1s_1s 3 147 0 0 0 0 0 0 0
217 . . . . . . . miv_rv32_fixed_arb_3s_2 0 81 0 0 0 0 0 0 0
218 . . PF_CCC_0 0 0 0 0 0 0 0 1 0
219 . . . PF_CCC_0_PF_CCC_0_0_PF_CCC 0 0 0 0 0 0 0 1 0
220 . . PF_IOD_CDR_C0 59 153 74 0 0 0 0 2 2
221 . . . CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 59 151 74 0 0 0 0 0 0
222 . . . PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD 0 0 0 0 0 0 0 0 0
223 . . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD 0 0 0 0 0 0 0 0 0
224 . . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD 0 0 0 0 0 0 0 0 0
225 . . . PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD 0 0 0 0 0 0 0 0 0
226 . . . PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL 0 1 0 0 0 0 0 1 0
227 . . PF_IOD_CDR_CCC_C0 31 22 8 0 0 0 0 2 0
228 . . . COREDELAYCODE_TIP 31 22 8 0 0 0 0 0 0
229 . . . PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC 0 0 0 0 0 0 0 1 0
230 . . . PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV 0 0 0 0 0 0 0 1 0
231 . . . PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL 0 0 0 0 0 0 0 0 0
232 . . PF_TPSRAM_C0 0 0 0 0 0 2 0 0 0
233 . . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM 0 0 0 0 0 2 0 0 0
234 . . SSDetect 2 7 0 0 0 0 0 0 0
235 . . fifo_to_tpsram_bridge 12 5 11 0 0 0 0 0 0
236 . . pf_init_monitor_0 0 0 0 0 0 0 0 0 0
237 . . . pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR 0 0 0 0 0 0 0 0 0

2851
synthesis/synlog/report/top_fpga_mapper_hier_area_report.xml Normal file
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103
synthesis/synlog/report/top_fpga_mapper_notes.txt Normal file
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@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.reg_valid_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.empty_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) mapped in logic.
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|Found ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) with 10 words by 2 bits.
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic.
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|Found ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 3 bits.
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|Found ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) with 3 words by 3 bits.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":636:3:636:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memraddr_r[9:0]
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":620:3:620:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memwaddr_r[9:0]
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance stxs_bitcnt[4:0]
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance spi_clk_count[7:0]
@N: MF179 :|Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog))
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\clock_gen.v":283:6:283:11|Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0]
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":31:4:31:9|Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[9:0]
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)).
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0]
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits.
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[6:0] is 2 words by 7 bits.
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[3].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[4].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[5].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[6].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[3].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[4].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[5].
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[6].
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] is 2 words by 34 bits.
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] is 2 words by 41 bits.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[0] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[16] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] is 4 words by 1 bits.
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[0] is 4 words by 1 bits.
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] is 4 words by 32 bits.
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] is 4 words by 16 bits.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9798:4:9798:9|Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Found counter in view:work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog) instance mul_div_cnt[5:0]
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11165:64:11165:92|Found 32 by 32 bit equality operator ('==') un152_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog))
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] with specified coding style. Inferring block RAM.
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] with specified coding style. Inferring block RAM.
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15548:0:15548:8|Found counter in view:work.miv_rv32_debug_sba(verilog) instance counter[7:0]
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13076:6:13076:14|Found counter in view:work.miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820(verilog) instance mtime_count_out[63:0]
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0]
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":8721:2:8721:7|Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9395:2:9395:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4035
@N: FP130 |Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4036
@N: FP130 |Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4037
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4038
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
@N: MT615 |Found clock REF_CLK_0 with period 20.00ns
@N: MT615 |Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns
@N: MT615 |Found clock REFCLK_P with period 8.00ns
@N: MT615 |Found clock TCK with period 100.00ns
@N: MT615 |Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns
@N: MT615 |Found clock PHY_MDC_CLOCK with period 350.00ns
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

6
synthesis/synlog/report/top_fpga_mapper_opt_report.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the optimization information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<report_table display_priority="3" name="Optimizations Summary"></report_table>

59
synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt Normal file
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Resource Usage Report for top
Mapping to part: mpf300tfcg1152-1
Cell usage:
AND2 1 use
BANKEN 1 use
BUFD 102 uses
CLKINT 6 uses
DLL 1 use
HS_IO_CLK 4 uses
ICB_CLKDIV 1 use
INIT 1 use
INV 4 uses
IOD 5 uses
LANECTRL 2 uses
OR2 32 uses
OR4 1344 uses
PLL 2 uses
RCLKINT 1 use
UJTAG 1 use
CFG1 110 uses
CFG2 1957 uses
CFG3 3420 uses
CFG4 8170 uses
Carry cells:
ARI1 2102 uses - used for arithmetic functions
ARI1 233 uses - used for Wide-Mux implementation
Total ARI1 2335 uses
Sequential Cells:
SLE 7316 uses
DSP Blocks: 0 of 924 (0%)
I/O ports: 58
I/O primitives: 50
BIBUF 1 use
INBUF 4 uses
INBUF_DIFF 2 uses
OUTBUF 42 uses
OUTBUF_DIFF 1 use
Global Clock Buffers: 7
Total LUTs: 15992
Extra resources required for RAM and MACC_PA interface logic during P&R:
RAM64X12 Interface Logic : SLEs = 132; LUTs = 132;
RAM1K20 Interface Logic : SLEs = 1224; LUTs = 1224;
MACC_PA Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0;
Total number of SLEs after P&R: 7316 + 132 + 1224 + 0 = 8672;
Total number of LUTs after P&R: 15992 + 132 + 1224 + 0 = 17348;

46
synthesis/synlog/report/top_fpga_mapper_runstatus.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the job information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<job_run_status name="Mapper">
<report_link name="Detailed report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr</data>
<title></title>
</report_link>
<job_status>
<data>Completed</data>
</job_status>
<job_info>
<info name="Notes">
<data>103</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_notes.txt</data>
</report_link>
</info>
<info name="Warnings">
<data>120</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_warnings.txt</data>
</report_link>
</info>
<info name="Errors">
<data>0</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_errors.txt</data>
</report_link>
</info>
<info name="CPU Time">
<data>0h:03m:51s</data>
</info>
<info name="Real Time">
<data>0h:03m:54s</data>
</info>
<info name="Peak Memory">
<data>521MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1776273723</data>
</info>
</job_info>
</job_run_status>

101
synthesis/synlog/report/top_fpga_mapper_timing_report.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
*******************************************************************************************-->
<report_table display_priority="2" name="Timing Summary">
<report_link name="Detailed report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr</data>
<title>START OF TIMING REPORT</title>
</report_link>
<row>
<data tcl_name="clock_name">Clock Name</data>
<data tcl_name="req_freq">Req Freq</data>
<data tcl_name="est_freq">Est Freq</data>
<data tcl_name="slack">Slack</data>
</row>
<row>
<data>COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</data>
<data>100.0 MHz</data>
<data>13.4 MHz</data>
<data>-32.246</data>
</row>
<row>
<data>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</data>
<data>80.0 MHz</data>
<data>55.0 MHz</data>
<data>-5.671</data>
</row>
<row>
<data>PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</data>
<data>125.0 MHz</data>
<data>116.7 MHz</data>
<data>-0.228</data>
</row>
<row>
<data>PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</data>
<data>100.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</data>
<data>625.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</data>
<data>625.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</data>
<data>625.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</data>
<data>625.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</data>
<data>125.0 MHz</data>
<data>230.3 MHz</data>
<data>3.659</data>
</row>
<row>
<data>PHY_MDC_CLOCK</data>
<data>2.9 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>REFCLK_P</data>
<data>125.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>REF_CLK_0</data>
<data>50.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>TCK</data>
<data>10.0 MHz</data>
<data>NA</data>
<data>NA</data>
</row>
<row>
<data>System</data>
<data>100.0 MHz</data>
<data>26.5 MHz</data>
<data>-27.793</data>
</row>
</report_table>

120
synthesis/synlog/report/top_fpga_mapper_warnings.txt Normal file
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@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":261:0:261:5|Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[25] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9414:2:9414:7|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":47:0:47:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":48:0:48:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":49:0:49:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":50:0:50:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":51:0:51:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":52:0:52:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":53:0:53:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":54:0:54:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW150 :|Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":40:53:40:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK.
@W: MT420 |Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK_0.
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design

0
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@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11493:2:11493:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11473:2:11473:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":169:8:169:52|Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":176:8:176:52|Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":183:8:183:52|Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":190:8:190:52|Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7016:2:7016:23|Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2565:4:2565:35|Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4653:2:4653:23|Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4904:4:4904:42|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4923:4:4923:44|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_lanectrl_0\pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v":107:12:107:32|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_ccc_c0\pf_lanectrl_core_reader_0\pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v":93:46:93:66|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2594:4:2594:30|Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10461:2:10461:7|Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6376:4:6376:9|Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6361:2:6361:7|Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":438:3:438:8|Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16308:7:16308:15|Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":630:0:630:5|Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.

6
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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the optimization information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<report_table display_priority="3" name="Optimizations Summary"></report_table>

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<?xml version="1.0" encoding="UTF-8" ?>
<!-- *************************************************************************************
FILE DESCRIPTION
The file contains the job information from mapper to be displayed as part of the summary report.
*******************************************************************************************-->
<job_run_status name="Mapper">
<report_link name="Detailed report">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr</data>
<title></title>
</report_link>
<job_status>
<data>Completed</data>
</job_status>
<job_info>
<info name="Notes">
<data>65</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_notes.txt</data>
</report_link>
</info>
<info name="Warnings">
<data>15</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_warnings.txt</data>
</report_link>
</info>
<info name="Errors">
<data>0</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_errors.txt</data>
</report_link>
</info>
<info name="CPU Time">
<data>0h:00m:13s</data>
</info>
<info name="Real Time">
<data>0h:00m:13s</data>
</info>
<info name="Peak Memory">
<data>365MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1776273488</data>
</info>
</job_info>
</job_run_status>

15
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@W: FX1183 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\core_reset_pf\core_reset_pf_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_iod_cdr_rx_n_0\pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v":48:53:48:59|Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance.
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug_uj_jtag.v":215:0:215:5|Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance.
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .

1
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./top_scck.rpt,syntax_constraint_check.rpt,Syntax Constraint Check Report

1
synthesis/synlog/top_comp.rt.csv.rptmap Normal file
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./synwork/top_comp.rt.csv,top_comp.rt.csv,Module Runtime Summary

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./synlog/top_compiler.srr,top_compiler.srr,Compile Log

3159
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###########################################################[
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @
@N|Running in 64-bit mode
File E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 157MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
Process completed successfully.
# Wed Apr 15 22:47:53 2026
###########################################################]

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# Wed Apr 15 22:47:54 2026
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
Synopsys Microchip Technology Pre-mapping, Version map202309act, Build 395R, Built Apr 29 2025 06:36:49, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
Reading constraint file: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc
@L: E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt
See clock summary report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt"
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 261MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 265MB peak: 265MB)
Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 266MB peak: 267MB)
Vector Gate Optimization Enabled: Optimizing Partial Hanging Logic.
NConnInternalConnection caching is on
@W: FX1183 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\core_reset_pf\core_reset_pf_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11493:2:11493:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11473:2:11473:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture.
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
Starting HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 338MB)
Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 339MB)
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":169:8:169:52|Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":176:8:176:52|Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":183:8:183:52|Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":190:8:190:52|Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
Started DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 340MB)
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7016:2:7016:23|Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2565:4:2565:35|Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4653:2:4653:23|Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4904:4:4904:42|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4923:4:4923:44|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_lanectrl_0\pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v":107:12:107:32|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_ccc_c0\pf_lanectrl_core_reader_0\pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v":93:46:93:66|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2594:4:2594:30|Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10461:2:10461:7|Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6376:4:6376:9|Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6361:2:6361:7|Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":438:3:438:8|Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16308:7:16308:15|Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":630:0:630:5|Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
Finished netlist restructuring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 348MB peak: 348MB)
Some data will not be shown as it is part of encrypted module
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT0_GRP 3
2 .. PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 8.000 generated (from REFCLK_P) Y_DIV_GRP 1410
1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT1_GRP 1
1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT2_GRP 1
1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT3_GRP 1
0 - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 8.000 declared SGMII_CDR_0_0_CLK_OUT_GRP 1323
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - TCK 10.0 MHz 100.000 declared JTAG_Async_2 0
0 - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0_3 184
0 - PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz 10.000 inferred Inferred_clkgroup_0_1 2
====================================================================================================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PHY_MDC_CLOCK 0 - - - -
REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 3 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0(PLL) PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3.A(HS_IO_CLK)
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 1410 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV(ICB_CLKDIV) PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1:0].C - -
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7.A(HS_IO_CLK)
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.REF_CLK(DLL)
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15.A(HS_IO_CLK)
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 1323 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R(LANECTRL) SSDetect_0.rx_start[1:0].C - PF_IOD_CDR_C0_0.RCLKINT_0.A(RCLKINT)
System 0 - - - -
TCK 0 TCK(port) - - -
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 184 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst.UDRCK(UJTAG) MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.genblk1\.rst_synch_reg[1:0].C - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.un1_jtag_tck.I[0](inv)
PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK(LANECTRL) PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.CDR_CLK - -
===========================================================================================================================================================================================================================================================================================================================================================================================================================
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_iod_cdr_rx_n_0\pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v":48:53:48:59|Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance.
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug_uj_jtag.v":215:0:215:5|Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
Starting constraint checker (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 333MB peak: 349MB)
Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog))
original code -> new code
0000 -> 000001
0001 -> 000010
0010 -> 000100
0111 -> 001000
1000 -> 010000
1001 -> 100000
Encoding state machine genblk1\.O0Il1[4:0] (in view: work.CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog))
original code -> new code
0000 -> 00001
1000 -> 00010
1100 -> 00100
1110 -> 01000
1111 -> 10000
Encoding state machine l0i11[31:0] (in view: work.CTSE_PEMGT_1s_26s(verilog))
original code -> new code
00000 -> 00000000000000000000000000000001
00001 -> 00000000000000000000000000000010
00010 -> 00000000000000000000000000000100
00011 -> 00000000000000000000000000001000
00100 -> 00000000000000000000000000010000
00101 -> 00000000000000000000000000100000
00110 -> 00000000000000000000000001000000
00111 -> 00000000000000000000000010000000
01000 -> 00000000000000000000000100000000
01001 -> 00000000000000000000001000000000
01010 -> 00000000000000000000010000000000
01011 -> 00000000000000000000100000000000
01100 -> 00000000000000000001000000000000
01101 -> 00000000000000000010000000000000
01110 -> 00000000000000000100000000000000
01111 -> 00000000000000001000000000000000
10000 -> 00000000000000010000000000000000
10001 -> 00000000000000100000000000000000
10010 -> 00000000000001000000000000000000
10011 -> 00000000000010000000000000000000
10100 -> 00000000000100000000000000000000
10101 -> 00000000001000000000000000000000
10110 -> 00000000010000000000000000000000
10111 -> 00000000100000000000000000000000
11000 -> 00000001000000000000000000000000
11001 -> 00000010000000000000000000000000
11010 -> 00000100000000000000000000000000
11011 -> 00001000000000000000000000000000
11100 -> 00010000000000000000000000000000
11101 -> 00100000000000000000000000000000
11110 -> 01000000000000000000000000000000
11111 -> 10000000000000000000000000000000
Encoding state machine lI101_1[3:0] (in view: work.CTSE_PEREX_PCS_0s_26s_1s(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
Encoding state machine xmit_state[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
original code -> new code
00000000000000000000000000000000 -> 000001
00000000000000000000000000000001 -> 000010
00000000000000000000000000000010 -> 000100
00000000000000000000000000000011 -> 001000
00000000000000000000000000000100 -> 010000
00000000000000000000000000000101 -> 100000
Encoding state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog))
original code -> new code
00 -> 0
01 -> 1
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
original code -> new code
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
Encoding state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
Encoding state machine debug_state[5:0] (in view: work.miv_rv32_debug_du(verilog))
original code -> new code
000001 -> 000001
000010 -> 000010
000100 -> 000100
001000 -> 001000
010000 -> 010000
100000 -> 100000
Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog))
original code -> new code
01 -> 00
10 -> 01
11 -> 10
Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog))
original code -> new code
000 -> 000001
001 -> 000010
010 -> 000100
011 -> 001000
100 -> 010000
101 -> 100000
Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog))
original code -> new code
001 -> 0000001
010 -> 0000010
011 -> 0000100
100 -> 0001000
101 -> 0010000
110 -> 0100000
111 -> 1000000
Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_subsys_tcm_Z20(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog))
original code -> new code
00 -> 00
01 -> 01
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 341MB peak: 349MB)
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .
Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 351MB peak: 365MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 249MB peak: 365MB)
Process took 0h:00m:13s realtime, 0h:00m:13s cputime
# Wed Apr 15 22:48:08 2026
###########################################################]

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synthesis/synlog/top_premap.szr Normal file
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Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 22:44:55 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 22:47:50 2026
Return Code: 0
Run Time:00h:02m:53s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 22:47:50 2026
multi_srs_gen completed
# Wed Apr 15 22:47:53 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 22:47:53 2026
premap completed with warnings
# Wed Apr 15 22:48:08 2026
Return Code: 1
Run Time:00h:00m:15s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 22:48:08 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 22:48:08 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 22:52:04 2026
Return Code: 1
Run Time:00h:03m:55s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

102
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@@ -0,0 +1,102 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 21:56:01 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 21:59:08 2026
Return Code: 0
Run Time:00h:03m:05s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 21:59:08 2026
multi_srs_gen completed
# Wed Apr 15 21:59:11 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 21:59:11 2026
premap completed with warnings
# Wed Apr 15 21:59:27 2026
Return Code: 1
Run Time:00h:00m:15s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 21:59:27 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 21:59:27 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 22:03:19 2026
Return Code: 1
Run Time:00h:03m:52s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

102
synthesis/synplify.log.bak.1 Normal file
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@@ -0,0 +1,102 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 20:20:12 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 20:23:56 2026
Return Code: 0
Run Time:00h:03m:42s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 20:23:56 2026
multi_srs_gen completed
# Wed Apr 15 20:23:59 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 20:23:59 2026
premap completed with warnings
# Wed Apr 15 20:24:13 2026
Return Code: 1
Run Time:00h:00m:14s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 20:28:51 2026
Return Code: 1
Run Time:00h:04m:38s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

102
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@@ -0,0 +1,102 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 19:30:13 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 19:33:17 2026
Return Code: 0
Run Time:00h:03m:02s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 19:33:17 2026
multi_srs_gen completed
# Wed Apr 15 19:33:21 2026
Return Code: 0
Run Time:00h:00m:04s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 19:33:21 2026
premap completed with warnings
# Wed Apr 15 19:33:37 2026
Return Code: 1
Run Time:00h:00m:15s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 19:33:37 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 19:33:37 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 19:37:27 2026
Return Code: 1
Run Time:00h:03m:50s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

102
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@@ -0,0 +1,102 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 18:31:21 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 18:34:18 2026
Return Code: 0
Run Time:00h:02m:55s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 18:34:18 2026
multi_srs_gen completed
# Wed Apr 15 18:34:22 2026
Return Code: 0
Run Time:00h:00m:04s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 18:34:22 2026
premap completed with warnings
# Wed Apr 15 18:34:37 2026
Return Code: 1
Run Time:00h:00m:15s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 18:34:37 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 18:34:37 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 18:38:40 2026
Return Code: 1
Run Time:00h:04m:03s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

101
synthesis/synplify.log.bak.4 Normal file
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@@ -0,0 +1,101 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Mon Apr 13 21:43:58 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
Implementation not found: synthesis
log file: "E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
compiler completed
# Mon Apr 13 21:47:56 2026
Return Code: 0
Run Time:00h:03m:56s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Mon Apr 13 21:47:56 2026
multi_srs_gen completed
# Mon Apr 13 21:47:59 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Mon Apr 13 21:47:59 2026
premap completed with warnings
# Mon Apr 13 21:48:16 2026
Return Code: 1
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srm
fpga_mapper completed with warnings
# Mon Apr 13 21:52:16 2026
Return Code: 1
Run Time:00h:04m:00s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\backup\top.srr
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
License checkin: synplifypro_actel

85
synthesis/synplify_job.log Normal file
View File

@@ -0,0 +1,85 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "22:52:04 15-Apr-2026",
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85
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{
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85
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{
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}
}
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}
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85
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{
"Synplify Pro (R) Job Log" : {
"Date" : "19:37:27 15-Apr-2026",
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},
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},
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"fpga_mapper" : {
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"Up-to-date (run skipped)" : "no"
}
}
}
}
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{
"Synplify Pro (R) Job Log" : {
"Date" : "18:38:40 15-Apr-2026",
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}
}
}
}
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{
"Synplify Pro (R) Job Log" : {
"Date" : "21:52:16 13-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -sap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -otap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.tap -omap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -multisrs -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -sap ..\top.sap -otap ..\top.tap -omap ..\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile ..\scratchproject.prs -multisrs -ovm ..\top.vm -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_prem.srd -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\top.srm -prjdir ..\ -prjname top_syn -log ..\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
rc:1 success:1 runtime:236
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\top.map|io:o|time:1776273723|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776273719|size:6264001|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_prem.srd|io:i|time:1776273483|size:1522539|exec:0|csum:DB252AC6E8654F85B7F9005EEC2CBE52
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273723|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776273714|size:28753|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776273723|size:628611|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_multi_srs_gen.srr
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs ..\synwork\top_comp.srs -osyn ..\synwork\top_mult.srs -log ..\synlog\top_multi_srs_gen.srr
rc:0 success:1 runtime:3
file:..\synwork\top_comp.srs|io:i|time:1776273468|size:2498683|exec:0|csum:D55B0D932EA25F21DF76D09F4D077B94
file:..\synwork\top_mult.srs|io:o|time:1776273473|size:16492|exec:0|csum:
file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776273473|size:1172|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\syn_nfilter.exe|io:i|time:1745943928|size:10549248|exec:1|csum:0E24E2994826988AAC59CDBFBC24908C

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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -flow prepass -gcc_prepass -osrd E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -qsap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -conchk_prepass E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile ..\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -flow prepass -gcc_prepass -osrd ..\synwork\top_prem.srd -qsap ..\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm ..\top.vm -conchk_prepass ..\top_cck.rpt -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_mult.srs -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\synwork\top_prem.srd -prjdir ..\ -prjname top_syn -log ..\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
rc:1 success:1 runtime:15
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.vm|io:o|time:1776270794|size:6521569|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776273487|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_mult.srs|io:i|time:1776273473|size:16492|exec:0|csum:8A8FBA27CAD8D4F9ABE7B311078B4CA3
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273475|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776273488|size:50209|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

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<?xml version="1.0" encoding="utf-8"?>
<!--
Synopsys, Inc.
Version V-2023.09M-5
Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\run_option.xml
Written on Wed Apr 15 22:44:56 2026
-->
<project_attribute_list name="Project Settings">
<option name="project_name" display_name="Project Name">top_syn</option>
<option name="device_name" display_name="Device Name">synthesis: Microchip PolarFire : MPF300T</option>
<option name="impl_name" display_name="Implementation Name">synthesis</option>
<option name="top_module" display_name="Top Module">top</option>
<option name="retiming" display_name="Retiming">0</option>
<option name="resource_sharing" display_name="Resource Sharing">1</option>
<option name="maxfan" display_name="Fanout Guide">10000</option>
<option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
<option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
<option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
</project_attribute_list>

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<html>
<head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
<title>Project Status Summary Page</title>
<link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
<script type = "text/javascript" src="projectstatuspage.js"></script>
</head>
<body style="background-color:#f0f0ff;">
<table style="border:none;" width="100%" ><tr> <td class="outline">
<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> top_syn</td> <td class="optionTitle" align="left"> Device Name</td> <td> synthesis: Microchip PolarFire : MPF300T</td> </tr>
<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> synthesis</td> <td class="optionTitle" align="left"> Top Module</td> <td> top</td> </tr>
</thead>
<tbody> <tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 10000</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
<tr> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
</tbody>
</table><br> <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
<thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
<tbody>
<tr>
<th align="left" width="17%">Job Name</th>
<th align="left">Status</th>
<td class="lnote" align="center" title="Notes"></td>
<td class="lwarn" align="center" title="Warnings"></td>
<td class="lerror" align="center" title="Errors"></td>
<th align="left">CPU Time</th>
<th align="left">Real Time</th>
<th align="left">Memory</th>
<th align="left">Date/Time</th>
</tr>
<tr>
<td class="optionTitle"> (compiler)</td><td>Complete</td>
<td>236</td>
<td>403</td>
<td>0</td>
<td>-</td>
<td>02m:53s</td>
<td>-</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td>
</tr>
<tr>
<td class="optionTitle"> (premap)</td><td>Complete</td>
<td>65</td>
<td>15</td>
<td>0</td>
<td>0m:13s</td>
<td>0m:13s</td>
<td>365MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:48 PM</font></td>
</tr>
<tr>
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
<td>103</td>
<td>120</td>
<td>0</td>
<td>03m:51s</td>
<td>03m:54s</td>
<td>521MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:52 PM</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
<thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
<tfoot> <tr> <td class="optionTitle" colspan="2"></td><td class="optionTitle" colspan="2"></td></tr>
</tfoot>
<tbody> <tr>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2335</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7316</td>
</tr>
<tr>
<td title ="Total DSP Blocks used" class="optionTitle" align="left">DSP Blocks
(dsp_used)</td> <td>0</td>
<td title ="Total I/O Cells used" class="optionTitle" align="left">I/O Cells</td> <td>50</td>
</tr>
<tr>
<td title ="Total Global Clock Buffers used" class="optionTitle" align="left">Global Clock Buffers</td> <td>7</td>
<td title ="Total RAM1K20 used" class="optionTitle" align="left">RAM1K20
(v_ram)</td> <td>34</td>
</tr>
<tr>
<td title ="Total RAM64x12 used" class="optionTitle" align="left">RAM64x12
(v_ram)</td> <td>11</td>
<td title ="Total LUTs used" class="optionTitle" align="left">LUTs
(total_luts)</td> <td>15992</td>
</tr>
</tbody>
</table><br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
<thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
</tfoot>
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</td><td align="left">100.0 MHz</td><td align="left">13.4 MHz</td><td align="left">-32.246</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.0 MHz</td><td align="left">-5.671</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</td><td align="left">125.0 MHz</td><td align="left">116.7 MHz</td><td align="left">-0.228</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">230.3 MHz</td><td align="left">3.659</td></tr>
<tr> <td align="left">PHY_MDC_CLOCK</td><td align="left">2.9 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REFCLK_P</td><td align="left">125.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REF_CLK_0</td><td align="left">50.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">TCK</td><td align="left">10.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">26.5 MHz</td><td align="left">-27.793</td></tr>
</tbody>
</table>
<br>
<br>
</td></tr></table></body>
</html>

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@P: Worst Slack : -32.246
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Frequency : 13.4 MHz
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Frequency : 100.0 MHz
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Period : 74.491
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Period : 10.000
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Slack : -32.246
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Frequency : 80.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.171
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Period : 12.500
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.671
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Frequency : 116.7 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Period : 8.569
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Period : 8.000
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Slack : -0.228
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Estimated Frequency : NA
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Requested Frequency : 100.0 MHz
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Estimated Period : NA
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Requested Period : 10.000
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Estimated Frequency : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Requested Frequency : 625.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Estimated Frequency : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Requested Frequency : 625.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Estimated Frequency : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Requested Frequency : 625.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Frequency : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Frequency : 625.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 230.3 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.341
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Period : 8.000
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.659
@P: PHY_MDC_CLOCK - Estimated Frequency : NA
@P: PHY_MDC_CLOCK - Requested Frequency : 2.9 MHz
@P: PHY_MDC_CLOCK - Estimated Period : NA
@P: PHY_MDC_CLOCK - Requested Period : 350.000
@P: PHY_MDC_CLOCK - Slack : NA
@P: REFCLK_P - Estimated Frequency : NA
@P: REFCLK_P - Requested Frequency : 125.0 MHz
@P: REFCLK_P - Estimated Period : NA
@P: REFCLK_P - Requested Period : 8.000
@P: REFCLK_P - Slack : NA
@P: REF_CLK_0 - Estimated Frequency : NA
@P: REF_CLK_0 - Requested Frequency : 50.0 MHz
@P: REF_CLK_0 - Estimated Period : NA
@P: REF_CLK_0 - Requested Period : 20.000
@P: REF_CLK_0 - Slack : NA
@P: TCK - Estimated Frequency : NA
@P: TCK - Requested Frequency : 10.0 MHz
@P: TCK - Estimated Period : NA
@P: TCK - Requested Period : 100.000
@P: TCK - Slack : NA
@P: System - Estimated Frequency : 26.5 MHz
@P: System - Requested Frequency : 100.0 MHz
@P: System - Estimated Period : 37.793
@P: System - Requested Period : 10.000
@P: System - Slack : -27.793
@P: top Part : mpf300tfcg1152-1
@P: top Register bits : 7316
@P: top DSP Blocks : 0
@P: top I/O primitives : 50
@P: top RAM1K20 : 34
@P: top RAM64x12 : 11
@P: CPU Time : 0h:03m:50s

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<html><body><samp><pre>
<!@TC:1776273296>
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
# Written on Wed Apr 15 22:48:07 2026
##### DESIGN INFO #######################################################
Top View: "top"
Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc"
##### SUMMARY ############################################################
Found 15 issues in 15 out of 47 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | No paths | 10.000 | No paths
REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 | 8.000 | 3.200 | 4.800
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | No paths | No paths
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp | No paths | No paths | No paths
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp | No paths | Diff grp | No paths
PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | Diff grp | No paths
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 | No paths | No paths | No paths
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 | No paths | No paths | No paths
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | Diff grp
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | 10.000 | 5.000 | 5.000
=========================================================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
<a name=UnconstrainedStartEndPointsCCK60></a>Unconstrained Start/End Points</a>
******************************
p:LINK_OK
p:PHY_RST
p:RD_BC_ERROR
p:REFCLK_N
p:REF_CLK_SEL
p:RX
p:RX_N
p:RX_P
p:R_DATA[0]
p:R_DATA[1]
p:R_DATA[2]
p:R_DATA[3]
p:R_DATA[4]
p:R_DATA[5]
p:R_DATA[6]
p:R_DATA[7]
p:R_DATA[8]
p:R_DATA[9]
p:R_DATA[10]
p:R_DATA[11]
p:R_DATA[12]
p:R_DATA[13]
p:R_DATA[14]
p:R_DATA[15]
p:R_DATA[16]
p:R_DATA[17]
p:R_DATA[18]
p:R_DATA[19]
p:R_DATA[20]
p:R_DATA[21]
p:R_DATA[22]
p:R_DATA[23]
p:R_DATA[24]
p:R_DATA[25]
p:R_DATA[26]
p:R_DATA[27]
p:R_DATA[28]
p:R_DATA[29]
p:R_DATA[30]
p:R_DATA[31]
p:SPISCLKO
p:SPISDI
p:SPISDO
p:SPISS
p:TDI
p:TDO
p:TMS
p:TRSTB
p:TX
p:TX_N
p:TX_P
p:coma_mode
<a name=InapplicableconstraintsCCK61></a>Inapplicable constraints</a>
************************
(none)
<a name=ApplicableConstraintsWithIssuesCCK62></a>Applicable constraints with issues</a>
**********************************
set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
set_false_path -to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
<a name=ConstraintsWithMatchingWildcardExpressionsCCK63></a>Constraints with matching wildcard expressions</a>
**********************************************
set_false_path -from [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":46:0:46:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]" applies to objects:
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane6_0_i4
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane_4
set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|expression "[get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }]" applies to objects:
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[0]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[4]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[5]
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":28:0:28:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]" applies to objects:
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[0]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[1]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[2]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[3]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[4]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[5]
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6]
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":30:0:30:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]" applies to objects:
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1]
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":31:0:31:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]" applies to objects:
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1]
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":29:0:29:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]" applies to objects:
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1]
set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":44:0:44:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]" applies to objects:
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1]
set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":43:0:43:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]" applies to objects:
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1]
<a name=LibraryReportCCK64></a>Library Report</a>
**************
# End of Constraint Checker Report
</pre></samp></body></html>

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synthesis/syntmp/top_cck_rpt.tgl Normal file
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Unconstrained Start/End Points, UnconstrainedStartEndPointsCCK60
Inapplicable constraints, InapplicableconstraintsCCK61
Applicable constraints with issues, ApplicableConstraintsWithIssuesCCK62
Constraints with matching wildcard expressions, ConstraintsWithMatchingWildcardExpressionsCCK63
Library Report, LibraryReportCCK64

13
synthesis/syntmp/top_dsp_rpt_txt.htm Normal file
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<html><body><samp><pre>
<!@TC:1776273296>
##### START OF DSP REPORT #####
SNo Instantiated Instance_Name User_Attribute MACC_Structure MACC_Name Primitive_Type DOTP P_REG(EN/ARST/SRST) A_REG(EN/ARST/SRST) B_REG(EN/ARST/SRST) C_REG(EN/ARST/SRST) D_REG(EN/ARST/SRST) SUB_REG(EN/ARST/SRST) B2_REG(EN/ARST/SRST) PortName Retiming_level RTL_reference
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
===================================================================================================================================================================================================================================================================================================================================================
##### END OF DSP REPORT #####
</pre></samp></body></html>

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synthesis/syntmp/top_fanout_rpt_txt.htm Normal file
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<html><body><samp><pre>
<!@TC:1776273296>
######## REPORT FOR HIGH FANOUT NETS ########
CLOCK GLOBAL THRESHOLD - 2
ASYNC GLOBAL THRESHOLD - 800
GLOBAL THRESHOLD - 5000
NET NAME CLOCK LOADS ASYNC RST LOADS SYNC RST LOADS ENABLE LOADS DATA LOADS TOTAL FANOUT GLOBAL BUFFER PRESENT
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PF_CCC_0_0_OUT0_FABCLK_0 4701 0 0 0 0 4701 YES
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1288 0 0 0 0 1288 YES
PF_IOD_CDR_C0_0_RX_CLK_R 1252 0 0 0 0 1252 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0_TGT_TCK_0_i 205 0 0 0 0 205 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK 17 0 0 0 1 18 YES
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 2 0 0 0 0 2 YES
PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK 2 0 0 0 0 2 YES
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.CLKRST_U.hstrst 0 1649 0 0 0 1649 NO
======================================================================================================================================================================================================
</pre></samp></body></html>

226
synthesis/syntmp/top_ram_rpt_txt.htm Normal file
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<html><body><samp><pre>
<!@TC:1776273296>
##### START OF RAM REPORT #####
##### LSRAM REPORT #####
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH(A/B) LOW-POWER_MODE ECC A_DOUT_PIPE_REG(EN/ARST/SRST) B_DOUT_PIPE_REG(EN/ARST/SRST) WRITE_MODE(A/B) COMMENTS
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io[35:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_0 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_1 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_2 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_3 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_4 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_5 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_6 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io[39:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_0 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_1 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_2 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_3 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
=====================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### URAM REPORT #####
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH LOW-POWER_MODE ECC R_ADDR_REG(EN/ARST/SRST) R_DATA_PIPE_REG(EN/ARST/SRST) COMMENTS
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
NO CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
NO CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[6:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data_gen_buff_loop\[0\]\.buff_data_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
===================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### REG/LOGIC REPORT #####
RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE COMMENTS
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Core_reset_pf_0.Core_reset_pf_0.dff NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_FAB_1.lI1I1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lo0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lI0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Ii0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.o10l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Il0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.oO0l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.iOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.olIIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.O0IO1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.ilIO1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.OOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.IiiOo[7:0] NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lo1Oo[3:0] NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.Ol1Oo NA NA Mapping instance using registers.
CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_out_2 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i1oIo[5:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.IooIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.lO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.IO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[5:0] RAM DEFAULT RAM instance meets the required threshold for mapping using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[10:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_lsu_0.lsu_emi_req_fence_1 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
============================================================================================================================================================================================================================================================================
##### END OF RAM REPORT #####
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<html>
<head>
<script type="text/javascript" src="file:///E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\report\reportlog_tree.js"></script>
<link rel="stylesheet" type="text/css" href="file:///E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\report\reportlog_tree.css" />
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<script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
<ul id="synthesis-menu" class="treeview" style="padding-left:12;">
<li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">top_syn (synthesis)</b>
<ul rel="open" style="font-size:small;">
<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
<ul rel="open">
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport9" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport20" target="srrFrame" title="">Pre-mapping Report</a>
<ul rel="open" >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport21" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport32" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#timingReport33" target="srrFrame" title="">Timing Report</a>
<ul rel="open" >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#performanceSummary34" target="srrFrame" title="">Performance Summary</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockRelationships35" target="srrFrame" title="">Clock Relationships</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#interfaceInfo36" target="srrFrame" title="">Interface Information</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#inputPorts37" target="srrFrame" title="">Input Ports</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#outputPorts38" target="srrFrame" title="">Output Ports</a> </li></ul></li>
<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport39" target="srrFrame" title="">Clock: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#startingSlack56" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#endingSlack57" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#worstPaths58" target="srrFrame" title="">Worst Path Information</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport43" target="srrFrame" title="">Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport47" target="srrFrame" title="">Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport51" target="srrFrame" title="">Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport55" target="srrFrame" title="">Clock: System</a> </li></ul></li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (22:49 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#resourceUsage59" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (22:48 15-Apr)</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#UnconstrainedStartEndPointsCCK60" target="srrFrame" title="">Unconstrained Start/End Points</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#InapplicableconstraintsCCK61" target="srrFrame" title="">Inapplicable constraints</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ApplicableConstraintsWithIssuesCCK62" target="srrFrame" title="">Applicable constraints with issues</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ConstraintsWithMatchingWildcardExpressionsCCK63" target="srrFrame" title="">Constraints with matching wildcard expressions</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#LibraryReportCCK64" target="srrFrame" title="">Library Report</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (22:52 15-Apr)</a> </li></ul></li> </ul>
</li>
</ul>
<script type="text/javascript"> reportLogObj.generateLog("synthesis-menu")</script>
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@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a42256":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a42256":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a42256":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a42256":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a42256":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Running optimization stage 1 on MUXCY_L .......
Finished optimization stage 1 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Post processing for work.eq_element.eqn
Running optimization stage 1 on eq_element .......
Finished optimization stage 1 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Post processing for work.cmp_eq.cell_level
Running optimization stage 1 on CMP_EQ .......
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Post processing for work.top.gen
Running optimization stage 1 on top .......
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Running optimization stage 2 on MUXCY_L .......
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Running optimization stage 2 on eq_element .......
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Running optimization stage 2 on CMP_EQ .......
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Running optimization stage 2 on top .......
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)

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