3160 lines
611 KiB
Plaintext
3160 lines
611 KiB
Plaintext
# Wed Apr 15 22:48:09 2026
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Copyright (C) 1994-2023 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: V-2023.09M-5
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Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
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OS: Windows 10 or later
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Hostname: SOFTWARE-PC
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Implementation : synthesis
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Synopsys Microchip Technology Mapper, Version map202309act, Build 395R, Built Apr 29 2025 06:36:49, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 199MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 199MB)
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Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 199MB)
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Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 199MB)
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Vector Gate Optimization Enabled: Optimizing Partial Hanging Logic.
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 296MB peak: 296MB)
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.reg_valid_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.empty_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) mapped in logic.
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@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|Found ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) with 10 words by 2 bits.
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@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic.
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@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|Found ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 3 bits.
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@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
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@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
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@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|Found ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) with 3 words by 3 bits.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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Finished RTL optimizations (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 310MB peak: 320MB)
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":636:3:636:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memraddr_r[9:0]
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":620:3:620:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memwaddr_r[9:0]
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@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
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@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
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Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog))
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original code -> new code
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0000 -> 000001
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0001 -> 000010
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0010 -> 000100
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0111 -> 001000
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1000 -> 010000
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1001 -> 100000
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance stxs_bitcnt[4:0]
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance spi_clk_count[7:0]
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Encoding state machine genblk1\.O0Il1[4:0] (in view: work.CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog))
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original code -> new code
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0000 -> 00001
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1000 -> 00010
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1100 -> 00100
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1110 -> 01000
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1111 -> 10000
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@N: MF179 :|Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog))
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Encoding state machine l0i11[31:0] (in view: work.CTSE_PEMGT_1s_26s(verilog))
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original code -> new code
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00000 -> 00000000000000000000000000000001
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00001 -> 00000000000000000000000000000010
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00010 -> 00000000000000000000000000000100
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00011 -> 00000000000000000000000000001000
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00100 -> 00000000000000000000000000010000
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00101 -> 00000000000000000000000000100000
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00110 -> 00000000000000000000000001000000
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00111 -> 00000000000000000000000010000000
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01000 -> 00000000000000000000000100000000
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01001 -> 00000000000000000000001000000000
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01010 -> 00000000000000000000010000000000
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01011 -> 00000000000000000000100000000000
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01100 -> 00000000000000000001000000000000
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01101 -> 00000000000000000010000000000000
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01110 -> 00000000000000000100000000000000
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01111 -> 00000000000000001000000000000000
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10000 -> 00000000000000010000000000000000
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10001 -> 00000000000000100000000000000000
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10010 -> 00000000000001000000000000000000
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10011 -> 00000000000010000000000000000000
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10100 -> 00000000000100000000000000000000
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10101 -> 00000000001000000000000000000000
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10110 -> 00000000010000000000000000000000
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10111 -> 00000000100000000000000000000000
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11000 -> 00000001000000000000000000000000
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11001 -> 00000010000000000000000000000000
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11010 -> 00000100000000000000000000000000
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11011 -> 00001000000000000000000000000000
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11100 -> 00010000000000000000000000000000
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11101 -> 00100000000000000000000000000000
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11110 -> 01000000000000000000000000000000
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11111 -> 10000000000000000000000000000000
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Encoding state machine lI101_1[3:0] (in view: work.CTSE_PEREX_PCS_0s_26s_1s(verilog))
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original code -> new code
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00 -> 00
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01 -> 01
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10 -> 10
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11 -> 11
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\clock_gen.v":283:6:283:11|Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0]
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Encoding state machine xmit_state[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
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original code -> new code
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00000000000000000000000000000000 -> 000001
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00000000000000000000000000000001 -> 000010
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00000000000000000000000000000010 -> 000100
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00000000000000000000000000000011 -> 001000
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00000000000000000000000000000100 -> 010000
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00000000000000000000000000000101 -> 100000
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Encoding state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog))
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original code -> new code
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00 -> 00
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01 -> 01
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10 -> 10
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11 -> 11
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@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":261:0:261:5|Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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Encoding state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog))
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original code -> new code
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00 -> 0
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01 -> 1
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@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":31:4:31:9|Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[9:0]
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[25] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
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@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)).
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@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0]
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits.
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[6:0] is 2 words by 7 bits.
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[3].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[4].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[5].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[6].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[3].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[4].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[5].
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@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[6].
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] is 2 words by 34 bits.
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] is 2 words by 41 bits.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[0] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[16] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] is 4 words by 1 bits.
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[0] is 4 words by 1 bits.
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] is 4 words by 32 bits.
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@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] is 4 words by 16 bits.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
|
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
|
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9798:4:9798:9|Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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|
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9414:2:9414:7|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
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|
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Found counter in view:work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog) instance mul_div_cnt[5:0]
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|
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11165:64:11165:92|Found 32 by 32 bit equality operator ('==') un152_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog))
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|
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] with specified coding style. Inferring block RAM.
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|
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
|
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] with specified coding style. Inferring block RAM.
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|
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
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|
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
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@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
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Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
|
|
original code -> new code
|
|
0000 -> 0000000000000001
|
|
0001 -> 0000000000000010
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|
0010 -> 0000000000000100
|
|
0011 -> 0000000000001000
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|
0100 -> 0000000000010000
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|
0101 -> 0000000000100000
|
|
0110 -> 0000000001000000
|
|
0111 -> 0000000010000000
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|
1000 -> 0000000100000000
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|
1001 -> 0000001000000000
|
|
1010 -> 0000010000000000
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|
1011 -> 0000100000000000
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|
1100 -> 0001000000000000
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1101 -> 0010000000000000
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|
1110 -> 0100000000000000
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1111 -> 1000000000000000
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Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
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|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
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Encoding state machine debug_state[5:0] (in view: work.miv_rv32_debug_du(verilog))
|
|
original code -> new code
|
|
000001 -> 000001
|
|
000010 -> 000010
|
|
000100 -> 000100
|
|
001000 -> 001000
|
|
010000 -> 010000
|
|
100000 -> 100000
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|
Encoding state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15548:0:15548:8|Found counter in view:work.miv_rv32_debug_sba(verilog) instance counter[7:0]
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Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog))
|
|
original code -> new code
|
|
000 -> 000001
|
|
001 -> 000010
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|
010 -> 000100
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|
011 -> 001000
|
|
100 -> 010000
|
|
101 -> 100000
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|
Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog))
|
|
original code -> new code
|
|
01 -> 00
|
|
10 -> 01
|
|
11 -> 10
|
|
Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_subsys_tcm_Z20(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog))
|
|
original code -> new code
|
|
001 -> 0000001
|
|
010 -> 0000010
|
|
011 -> 0000100
|
|
100 -> 0001000
|
|
101 -> 0010000
|
|
110 -> 0100000
|
|
111 -> 1000000
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|
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13076:6:13076:14|Found counter in view:work.miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820(verilog) instance mtime_count_out[63:0]
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|
Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
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|
Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
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@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0]
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|
Starting factoring (Real Time elapsed 0h:00m:45s; CPU Time elapsed 0h:00m:42s; Memory used current: 344MB peak: 344MB)
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|
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":8721:2:8721:7|Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances.
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Finished factoring (Real Time elapsed 0h:01m:07s; CPU Time elapsed 0h:01m:04s; Memory used current: 440MB peak: 448MB)
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|
|
|
Available hyper_sources - for debug and ip models
|
|
None Found
|
|
|
|
NConnInternalConnection caching is on
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9395:2:9395:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances.
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances.
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.
|
|
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:01m:18s; CPU Time elapsed 0h:01m:15s; Memory used current: 413MB peak: 473MB)
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|
|
|
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
|
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:01m:24s; CPU Time elapsed 0h:01m:21s; Memory used current: 420MB peak: 473MB)
|
|
|
|
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:02m:49s; CPU Time elapsed 0h:02m:46s; Memory used current: 408MB peak: 473MB)
|
|
|
|
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:02m:50s; CPU Time elapsed 0h:02m:47s; Memory used current: 409MB peak: 473MB)
|
|
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances.
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.
|
|
|
|
Finished preparing to map (Real Time elapsed 0h:02m:59s; CPU Time elapsed 0h:02m:56s; Memory used current: 410MB peak: 473MB)
|
|
|
|
|
|
Finished technology mapping (Real Time elapsed 0h:03m:10s; CPU Time elapsed 0h:03m:07s; Memory used current: 502MB peak: 502MB)
|
|
|
|
Pass CPU time Worst Slack Luts / Registers
|
|
------------------------------------------------------------
|
|
1 0h:03m:09s -32.17ns 16366 / 7316
|
|
2 0h:03m:10s -32.17ns 16059 / 7316
|
|
3 0h:03m:11s -32.17ns 16058 / 7316
|
|
4 0h:03m:12s -32.17ns 16058 / 7316
|
|
|
|
5 0h:03m:19s -32.17ns 16067 / 7316
|
|
6 0h:03m:20s -32.17ns 16072 / 7316
|
|
7 0h:03m:21s -32.17ns 16072 / 7316
|
|
8 0h:03m:22s -32.17ns 16074 / 7316
|
|
9 0h:03m:23s -32.17ns 16075 / 7316
|
|
|
|
|
|
10 0h:03m:26s -32.17ns 16082 / 7316
|
|
11 0h:03m:27s -32.17ns 16086 / 7316
|
|
12 0h:03m:27s -32.17ns 16088 / 7316
|
|
13 0h:03m:28s -32.17ns 16090 / 7316
|
|
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4035
|
|
@N: FP130 |Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4036
|
|
@N: FP130 |Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4037
|
|
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4038
|
|
|
|
Added 0 Buffers
|
|
Added 0 Cells via replication
|
|
Added 0 Sequential Cells via replication
|
|
Added 0 Combinational Cells via replication
|
|
|
|
Added 0 Buffers
|
|
Added 0 Cells via replication
|
|
Added 0 Sequential Cells via replication
|
|
Added 0 Combinational Cells via replication
|
|
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:03m:38s; CPU Time elapsed 0h:03m:35s; Memory used current: 515MB peak: 515MB)
|
|
|
|
|
|
Finished restoring hierarchy (Real Time elapsed 0h:03m:39s; CPU Time elapsed 0h:03m:36s; Memory used current: 518MB peak: 521MB)
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|
|
|
|
|
Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:03m:40s; CPU Time elapsed 0h:03m:37s; Memory used current: 520MB peak: 521MB)
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|
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|
|
|
Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:03m:40s; CPU Time elapsed 0h:03m:37s; Memory used current: 520MB peak: 521MB)
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|
|
|
|
|
Start Writing Netlists (Real Time elapsed 0h:03m:41s; CPU Time elapsed 0h:03m:38s; Memory used current: 352MB peak: 521MB)
|
|
|
|
Writing Analyst data base E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm
|
|
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:03m:45s; CPU Time elapsed 0h:03m:42s; Memory used current: 450MB peak: 521MB)
|
|
|
|
Writing Verilog Simulation files
|
|
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
|
|
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":47:0:47:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":48:0:48:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":49:0:49:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":50:0:50:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":51:0:51:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":52:0:52:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":53:0:53:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":54:0:54:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
@W: BW150 :|Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated
|
|
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
|
|
|
Finished Writing Verilog Simulation files (Real Time elapsed 0h:03m:51s; CPU Time elapsed 0h:03m:48s; Memory used current: 440MB peak: 521MB)
|
|
|
|
|
|
Finished Writing Netlists (Real Time elapsed 0h:03m:51s; CPU Time elapsed 0h:03m:48s; Memory used current: 440MB peak: 521MB)
|
|
|
|
|
|
Start final timing analysis (Real Time elapsed 0h:03m:52s; CPU Time elapsed 0h:03m:49s; Memory used current: 426MB peak: 521MB)
|
|
|
|
@W: MT246 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":40:53:40:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
|
@N: MT615 |Found clock REF_CLK_0 with period 20.00ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns
|
|
@N: MT615 |Found clock REFCLK_P with period 8.00ns
|
|
@N: MT615 |Found clock TCK with period 100.00ns
|
|
@N: MT615 |Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns
|
|
@N: MT615 |Found clock PHY_MDC_CLOCK with period 350.00ns
|
|
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns
|
|
@W: MT420 |Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK.
|
|
@W: MT420 |Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK_0.
|
|
|
|
|
|
##### START OF TIMING REPORT #####[
|
|
# Timing report written on Wed Apr 15 22:52:02 2026
|
|
#
|
|
|
|
|
|
Top view: top
|
|
Requested Frequency: 2.9 MHz
|
|
Wire load mode: top
|
|
Paths requested: 5
|
|
Constraint File(s): E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc
|
|
|
|
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
|
|
|
|
|
Performance Summary
|
|
*******************
|
|
|
|
|
|
Worst slack in design: -32.246
|
|
|
|
Requested Estimated Requested Estimated Clock Clock
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 13.4 MHz 10.000 74.491 -32.246 inferred Inferred_clkgroup_0_3
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 55.0 MHz 12.500 18.171 -5.671 generated (from REF_CLK_0) (multiple)
|
|
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 116.7 MHz 8.000 8.569 -0.228 declared SGMII_CDR_0_0_CLK_OUT_GRP
|
|
PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0_1
|
|
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT0_GRP
|
|
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT1_GRP
|
|
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT2_GRP
|
|
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT3_GRP
|
|
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 230.3 MHz 8.000 4.341 3.659 generated (from REFCLK_P) Y_DIV_GRP
|
|
PHY_MDC_CLOCK 2.9 MHz NA 350.000 NA NA generated (from REF_CLK_0) default_clkgroup
|
|
REFCLK_P 125.0 MHz NA 8.000 NA NA declared default_clkgroup
|
|
REF_CLK_0 50.0 MHz NA 20.000 NA NA declared default_clkgroup
|
|
TCK 10.0 MHz NA 100.000 NA NA declared JTAG_Async_2
|
|
System 100.0 MHz 26.5 MHz 10.000 37.793 -27.793 system system_clkgroup
|
|
========================================================================================================================================================================================
|
|
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
|
|
|
|
|
|
|
|
|
|
|
Clock Relationships
|
|
*******************
|
|
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
|
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 11.225 | No paths - | No paths - | No paths -
|
|
System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 -27.793 | No paths - | 10.000 -26.963 | No paths -
|
|
REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 1.875 | 8.000 3.354 | 3.200 -0.228 | 4.800 3.427
|
|
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 -5.671 | No paths - | No paths - | No paths -
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths -
|
|
PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | Diff grp - | No paths -
|
|
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths -
|
|
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 3.659 | No paths - | No paths - | No paths -
|
|
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 8.633 | No paths - | No paths - | No paths -
|
|
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | Diff grp -
|
|
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 5.767 | 10.000 6.499 | 5.000 1.978 | 5.000 -32.246
|
|
====================================================================================================================================================================================================
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
|
|
|
|
|
|
|
Interface Information
|
|
*********************
|
|
|
|
|
|
|
|
Input Ports:
|
|
|
|
Port Starting User Arrival Required
|
|
Name Reference Constraint Time Time Slack
|
|
Clock
|
|
-------------------------------------------------------------------------------------
|
|
PHY_MDIO PHY_MDC_CLOCK (rising) 20.000 NA NA NA
|
|
RESET_N REF_CLK_0 (rising) 20.000 NA NA NA
|
|
=====================================================================================
|
|
|
|
|
|
Output Ports:
|
|
|
|
Port Starting User Arrival Required
|
|
Name Reference Constraint Time Time Slack
|
|
Clock
|
|
-------------------------------------------------------------------------------------------------------------------------------
|
|
PHY_MDIO PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 (rising) 10.000(PHY_MDC_CLOCK rising) 4.556 NA NA
|
|
===============================================================================================================================
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q tmsenb 0.218 -32.246
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.endofshift COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q endofshift 0.218 -32.148
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[2] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[2] 0.218 1.581
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[1] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[1] 0.218 1.622
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[0] 0.201 1.866
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[3] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[3] 0.218 1.906
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[4] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[4] 0.201 1.964
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[0] 0.218 1.978
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[4] 0.218 2.048
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[1] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[1] 0.218 2.054
|
|
============================================================================================================================================================================================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_99_i 5.000 -32.246
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_110_i 5.000 -32.246
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_102_i 5.000 -32.201
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_113_i 5.000 -32.201
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_92_i 5.000 -32.181
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_97_i 5.000 -32.181
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[7] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[7] 5.000 -32.181
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[9] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[9] 5.000 -32.181
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D N_108_i 5.000 -32.181
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[14] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[14] 5.000 -32.181
|
|
====================================================================================================================================================================================================================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 5.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 5.000
|
|
|
|
- Propagation time: 37.246
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : -32.246
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] / D
|
|
The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r -
|
|
tmsenb Net - - 0.118 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 D In - 36.916 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 Y Out 0.212 37.128 f -
|
|
N_99_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] SLE D In - 37.246 f -
|
|
==========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.246 is 4.070(10.9%) logic and 33.176(89.1%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 5.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 5.000
|
|
|
|
- Propagation time: 37.246
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : -32.246
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] / D
|
|
The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r -
|
|
tmsenb Net - - 0.118 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 D In - 36.916 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 Y Out 0.212 37.128 f -
|
|
N_110_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] SLE D In - 37.246 f -
|
|
===========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.246 is 4.070(10.9%) logic and 33.176(89.1%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 5.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 5.000
|
|
|
|
- Propagation time: 37.201
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -32.201
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] / D
|
|
The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r -
|
|
tmsenb Net - - 0.118 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 D In - 36.916 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 Y Out 0.168 37.083 r -
|
|
N_102_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] SLE D In - 37.201 r -
|
|
==========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.201 is 4.026(10.8%) logic and 33.176(89.2%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 5.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 5.000
|
|
|
|
- Propagation time: 37.201
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -32.201
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] / D
|
|
The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r -
|
|
tmsenb Net - - 0.118 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 D In - 36.916 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 Y Out 0.168 37.083 r -
|
|
N_113_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] SLE D In - 37.201 r -
|
|
===========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.201 is 4.026(10.8%) logic and 33.176(89.2%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 5.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 5.000
|
|
|
|
- Propagation time: 37.181
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -32.181
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D
|
|
The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r -
|
|
tmsenb Net - - 0.118 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 C In - 36.916 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.148 37.063 r -
|
|
N_92_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.181 r -
|
|
==========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.181 is 4.006(10.8%) logic and 33.176(89.2%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q trace_priv_i 0.218 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_lsu_0.buff_rd_ptr[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q buff_rd_ptr[0] 0.218 -5.518
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.buff_rd_ptr[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q buff_rd_ptr[0] 0.218 -5.433
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.stage_state_retr PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q stage_state_retr 0.218 -5.336
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.buff_rd_ptr[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q buff_rd_ptr[0] 0.218 -5.313
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_valid[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q d_trx_resp_valid_pkd[0] 0.201 -5.312
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_valid[1] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q d_trx_resp_valid_pkd[1] 0.201 -5.244
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[0] 2.241 -5.226
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[1] 2.241 -5.206
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R11C0_B_DOUT[0] 2.241 -5.195
|
|
=================================================================================================================================================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[1] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[4] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[5] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[6] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[7] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[8] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[9] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNIQ13595 12.373 -5.671
|
|
=================================================================================================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 12.500
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 12.373
|
|
|
|
- Propagation time: 18.044
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -5.671
|
|
|
|
Number of logic level(s): 25
|
|
Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] / EN
|
|
The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r -
|
|
trace_priv_i Net - - 1.255 - 242
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f -
|
|
per_trigger_debug[0] Net - - 0.547 - 3
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f -
|
|
trigger_debug_enter_taken Net - - 0.674 - 12
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 C In - 2.904 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 Y Out 0.130 3.034 r -
|
|
debug_enter_retr_i Net - - 0.563 - 4
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 D In - 3.598 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 Y Out 0.212 3.810 f -
|
|
interrupt_m1_0_a2_0_5 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 D In - 3.928 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 Y Out 0.192 4.120 f -
|
|
interrupt_taken_timer Net - - 0.579 - 5
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 C In - 4.699 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 Y Out 0.145 4.844 f -
|
|
machine_implicit_wr_mtval_tval_wr_en Net - - 1.012 - 85
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 A In - 5.857 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 Y Out 0.048 5.904 f -
|
|
d_N_6_mux Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 D In - 6.554 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 Y Out 0.232 6.786 r -
|
|
start_slow_mul_1_0 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 B In - 6.904 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 Y Out 0.088 6.991 f -
|
|
start_slow_mul Net - - 0.883 - 40
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 A In - 7.874 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 Y Out 0.048 7.922 f -
|
|
un1_alu_op_sel_int Net - - 0.747 - 19
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 C In - 8.669 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 Y Out 0.145 8.814 f -
|
|
un1_N_7_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 C In - 8.932 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 Y Out 0.145 9.078 f -
|
|
un1_N_7_i Net - - 0.623 - 8
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 D In - 9.701 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 Y Out 0.232 9.933 r -
|
|
un5_fetch_ptr_sel_0_a2_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 D In - 10.051 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 Y Out 0.168 10.218 r -
|
|
un5_fetch_ptr_sel_i Net - - 0.896 - 43
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 D In - 11.115 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 Y Out 0.232 11.346 f -
|
|
apb_i_req_addr_net[14] Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 C In - 11.996 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 Y Out 0.145 12.142 f -
|
|
un8_cpu_i_req_is_tcm0lt3 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 D In - 12.259 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 Y Out 0.232 12.491 r -
|
|
d_m5_0_1 Net - - 0.594 - 6
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 B In - 13.086 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 Y Out 0.083 13.169 r -
|
|
cpu_i_req_is_tcm0 Net - - 0.609 - 7
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 D In - 13.778 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 Y Out 0.212 13.990 f -
|
|
d_m6_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 C In - 14.108 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 Y Out 0.148 14.256 r -
|
|
cpu_i_req_is_apb_RNIGPOAJ9 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 C In - 14.380 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 Y Out 0.148 14.527 r -
|
|
bcu_op_completing_ex Net - - 0.686 - 13
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 D In - 15.213 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 Y Out 0.212 15.425 f -
|
|
instr_m3_1_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 D In - 15.543 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 Y Out 0.232 15.775 r -
|
|
instr_accepted_ex Net - - 1.125 - 150
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 A In - 16.900 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 Y Out 0.051 16.951 r -
|
|
instr_accepted_ex_2_1_RNIT40LK2 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 A In - 17.075 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 Y Out 0.051 17.125 r -
|
|
instr_accepted_ex_2_1_RNIQ13595 Net - - 0.918 - 34
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] SLE EN In - 18.044 r -
|
|
==========================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 18.171 is 4.084(22.5%) logic and 14.087(77.5%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 12.500
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 12.373
|
|
|
|
- Propagation time: 18.044
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -5.671
|
|
|
|
Number of logic level(s): 25
|
|
Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_mem_error_ex / EN
|
|
The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r -
|
|
trace_priv_i Net - - 1.255 - 242
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f -
|
|
per_trigger_debug[0] Net - - 0.547 - 3
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f -
|
|
trigger_debug_enter_taken Net - - 0.674 - 12
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 C In - 2.904 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 Y Out 0.130 3.034 r -
|
|
debug_enter_retr_i Net - - 0.563 - 4
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 D In - 3.598 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 Y Out 0.212 3.810 f -
|
|
interrupt_m1_0_a2_0_5 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 D In - 3.928 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 Y Out 0.192 4.120 f -
|
|
interrupt_taken_timer Net - - 0.579 - 5
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 C In - 4.699 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 Y Out 0.145 4.844 f -
|
|
machine_implicit_wr_mtval_tval_wr_en Net - - 1.012 - 85
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 A In - 5.857 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 Y Out 0.048 5.904 f -
|
|
d_N_6_mux Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 D In - 6.554 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 Y Out 0.232 6.786 r -
|
|
start_slow_mul_1_0 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 B In - 6.904 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 Y Out 0.088 6.991 f -
|
|
start_slow_mul Net - - 0.883 - 40
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 A In - 7.874 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 Y Out 0.048 7.922 f -
|
|
un1_alu_op_sel_int Net - - 0.747 - 19
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 C In - 8.669 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 Y Out 0.145 8.814 f -
|
|
un1_N_7_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 C In - 8.932 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 Y Out 0.145 9.078 f -
|
|
un1_N_7_i Net - - 0.623 - 8
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 D In - 9.701 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 Y Out 0.232 9.933 r -
|
|
un5_fetch_ptr_sel_0_a2_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 D In - 10.051 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 Y Out 0.168 10.218 r -
|
|
un5_fetch_ptr_sel_i Net - - 0.896 - 43
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 D In - 11.115 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 Y Out 0.232 11.346 f -
|
|
apb_i_req_addr_net[14] Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 C In - 11.996 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 Y Out 0.145 12.142 f -
|
|
un8_cpu_i_req_is_tcm0lt3 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 D In - 12.259 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 Y Out 0.232 12.491 r -
|
|
d_m5_0_1 Net - - 0.594 - 6
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 B In - 13.086 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 Y Out 0.083 13.169 r -
|
|
cpu_i_req_is_tcm0 Net - - 0.609 - 7
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 D In - 13.778 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 Y Out 0.212 13.990 f -
|
|
d_m6_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 C In - 14.108 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 Y Out 0.148 14.256 r -
|
|
cpu_i_req_is_apb_RNIGPOAJ9 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 C In - 14.380 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 Y Out 0.148 14.527 r -
|
|
bcu_op_completing_ex Net - - 0.686 - 13
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 D In - 15.213 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 Y Out 0.212 15.425 f -
|
|
instr_m3_1_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 D In - 15.543 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 Y Out 0.232 15.775 r -
|
|
instr_accepted_ex Net - - 1.125 - 150
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 A In - 16.900 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 Y Out 0.051 16.951 r -
|
|
instr_accepted_ex_2_1_RNIT40LK2 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 A In - 17.075 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 Y Out 0.051 17.125 r -
|
|
instr_accepted_ex_2_1_RNIQ13595 Net - - 0.918 - 34
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_mem_error_ex SLE EN In - 18.044 r -
|
|
==========================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 18.171 is 4.084(22.5%) logic and 14.087(77.5%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 12.500
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 12.373
|
|
|
|
- Propagation time: 18.044
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -5.671
|
|
|
|
Number of logic level(s): 25
|
|
Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_misalign_error_ex / EN
|
|
The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r -
|
|
trace_priv_i Net - - 1.255 - 242
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f -
|
|
per_trigger_debug[0] Net - - 0.547 - 3
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f -
|
|
trigger_debug_enter_taken Net - - 0.674 - 12
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 C In - 2.904 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 Y Out 0.130 3.034 r -
|
|
debug_enter_retr_i Net - - 0.563 - 4
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 D In - 3.598 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 Y Out 0.212 3.810 f -
|
|
interrupt_m1_0_a2_0_5 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 D In - 3.928 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 Y Out 0.192 4.120 f -
|
|
interrupt_taken_timer Net - - 0.579 - 5
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 C In - 4.699 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 Y Out 0.145 4.844 f -
|
|
machine_implicit_wr_mtval_tval_wr_en Net - - 1.012 - 85
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 A In - 5.857 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 Y Out 0.048 5.904 f -
|
|
d_N_6_mux Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 D In - 6.554 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 Y Out 0.232 6.786 r -
|
|
start_slow_mul_1_0 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 B In - 6.904 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 Y Out 0.088 6.991 f -
|
|
start_slow_mul Net - - 0.883 - 40
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 A In - 7.874 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 Y Out 0.048 7.922 f -
|
|
un1_alu_op_sel_int Net - - 0.747 - 19
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 C In - 8.669 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 Y Out 0.145 8.814 f -
|
|
un1_N_7_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 C In - 8.932 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 Y Out 0.145 9.078 f -
|
|
un1_N_7_i Net - - 0.623 - 8
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 D In - 9.701 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 Y Out 0.232 9.933 r -
|
|
un5_fetch_ptr_sel_0_a2_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 D In - 10.051 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 Y Out 0.168 10.218 r -
|
|
un5_fetch_ptr_sel_i Net - - 0.896 - 43
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 D In - 11.115 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 Y Out 0.232 11.346 f -
|
|
apb_i_req_addr_net[14] Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 C In - 11.996 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 Y Out 0.145 12.142 f -
|
|
un8_cpu_i_req_is_tcm0lt3 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 D In - 12.259 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 Y Out 0.232 12.491 r -
|
|
d_m5_0_1 Net - - 0.594 - 6
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 B In - 13.086 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 Y Out 0.083 13.169 r -
|
|
cpu_i_req_is_tcm0 Net - - 0.609 - 7
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 D In - 13.778 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 Y Out 0.212 13.990 f -
|
|
d_m6_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 C In - 14.108 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 Y Out 0.148 14.256 r -
|
|
cpu_i_req_is_apb_RNIGPOAJ9 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 C In - 14.380 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 Y Out 0.148 14.527 r -
|
|
bcu_op_completing_ex Net - - 0.686 - 13
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 D In - 15.213 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 Y Out 0.212 15.425 f -
|
|
instr_m3_1_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 D In - 15.543 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 Y Out 0.232 15.775 r -
|
|
instr_accepted_ex Net - - 1.125 - 150
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 A In - 16.900 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 Y Out 0.051 16.951 r -
|
|
instr_accepted_ex_2_1_RNIT40LK2 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 A In - 17.075 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 Y Out 0.051 17.125 r -
|
|
instr_accepted_ex_2_1_RNIQ13595 Net - - 0.918 - 34
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_misalign_error_ex SLE EN In - 18.044 r -
|
|
==========================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 18.171 is 4.084(22.5%) logic and 14.087(77.5%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 12.500
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 12.373
|
|
|
|
- Propagation time: 18.044
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -5.671
|
|
|
|
Number of logic level(s): 25
|
|
Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] / EN
|
|
The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r -
|
|
trace_priv_i Net - - 1.255 - 242
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f -
|
|
per_trigger_debug[0] Net - - 0.547 - 3
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f -
|
|
trigger_debug_enter_taken Net - - 0.674 - 12
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 C In - 2.904 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 Y Out 0.130 3.034 r -
|
|
debug_enter_retr_i Net - - 0.563 - 4
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 D In - 3.598 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 Y Out 0.212 3.810 f -
|
|
interrupt_m1_0_a2_0_5 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 D In - 3.928 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 Y Out 0.192 4.120 f -
|
|
interrupt_taken_timer Net - - 0.579 - 5
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 C In - 4.699 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 Y Out 0.145 4.844 f -
|
|
machine_implicit_wr_mtval_tval_wr_en Net - - 1.012 - 85
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 A In - 5.857 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 Y Out 0.048 5.904 f -
|
|
d_N_6_mux Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 D In - 6.554 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 Y Out 0.232 6.786 r -
|
|
start_slow_mul_1_0 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 B In - 6.904 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 Y Out 0.088 6.991 f -
|
|
start_slow_mul Net - - 0.883 - 40
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 A In - 7.874 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 Y Out 0.048 7.922 f -
|
|
un1_alu_op_sel_int Net - - 0.747 - 19
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 C In - 8.669 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 Y Out 0.145 8.814 f -
|
|
un1_N_7_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 C In - 8.932 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 Y Out 0.145 9.078 f -
|
|
un1_N_7_i Net - - 0.623 - 8
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 D In - 9.701 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 Y Out 0.232 9.933 r -
|
|
un5_fetch_ptr_sel_0_a2_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 D In - 10.051 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 Y Out 0.168 10.218 r -
|
|
un5_fetch_ptr_sel_i Net - - 0.896 - 43
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 D In - 11.115 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 Y Out 0.232 11.346 f -
|
|
apb_i_req_addr_net[14] Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 C In - 11.996 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 Y Out 0.145 12.142 f -
|
|
un8_cpu_i_req_is_tcm0lt3 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 D In - 12.259 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 Y Out 0.232 12.491 r -
|
|
d_m5_0_1 Net - - 0.594 - 6
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 B In - 13.086 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 Y Out 0.083 13.169 r -
|
|
cpu_i_req_is_tcm0 Net - - 0.609 - 7
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 D In - 13.778 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 Y Out 0.212 13.990 f -
|
|
d_m6_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 C In - 14.108 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 Y Out 0.148 14.256 r -
|
|
cpu_i_req_is_apb_RNIGPOAJ9 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 C In - 14.380 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 Y Out 0.148 14.527 r -
|
|
bcu_op_completing_ex Net - - 0.686 - 13
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 D In - 15.213 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 Y Out 0.212 15.425 f -
|
|
instr_m3_1_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 D In - 15.543 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 Y Out 0.232 15.775 r -
|
|
instr_accepted_ex Net - - 1.125 - 150
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 A In - 16.900 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 Y Out 0.051 16.951 r -
|
|
instr_accepted_ex_2_1_RNIT40LK2 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 A In - 17.075 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 Y Out 0.051 17.125 r -
|
|
instr_accepted_ex_2_1_RNIQ13595 Net - - 0.918 - 34
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] SLE EN In - 18.044 r -
|
|
==========================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 18.171 is 4.084(22.5%) logic and 14.087(77.5%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 12.500
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 12.373
|
|
|
|
- Propagation time: 18.044
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -5.671
|
|
|
|
Number of logic level(s): 25
|
|
Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] / EN
|
|
The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r -
|
|
trace_priv_i Net - - 1.255 - 242
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f -
|
|
per_trigger_debug[0] Net - - 0.547 - 3
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f -
|
|
trigger_debug_enter_taken Net - - 0.674 - 12
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 C In - 2.904 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.ebreak_debug_enter_taken_RNIRN07L CFG4 Y Out 0.130 3.034 r -
|
|
debug_enter_retr_i Net - - 0.563 - 4
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 D In - 3.598 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_m1_0_a2_0_5 CFG4 Y Out 0.212 3.810 f -
|
|
interrupt_m1_0_a2_0_5 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 D In - 3.928 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_timer.interrupt_capture_reg_RNI7T9PR6 CFG4 Y Out 0.192 4.120 f -
|
|
interrupt_taken_timer Net - - 0.579 - 5
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 C In - 4.699 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG3 Y Out 0.145 4.844 f -
|
|
machine_implicit_wr_mtval_tval_wr_en Net - - 1.012 - 85
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 A In - 5.857 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.un2_exception_taken_RNIDRB35 CFG2 Y Out 0.048 5.904 f -
|
|
d_N_6_mux Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 D In - 6.554 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_1_0 CFG4 Y Out 0.232 6.786 r -
|
|
start_slow_mul_1_0 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 B In - 6.904 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul CFG4 Y Out 0.088 6.991 f -
|
|
start_slow_mul Net - - 0.883 - 40
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 A In - 7.874 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI036Q8[5] CFG2 Y Out 0.048 7.922 f -
|
|
un1_alu_op_sel_int Net - - 0.747 - 19
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 C In - 8.669 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNI75FRQ1_0[5] CFG4 Y Out 0.145 8.814 f -
|
|
un1_N_7_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 C In - 8.932 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.start_slow_mul_RNIH4K4P3 CFG4 Y Out 0.145 9.078 f -
|
|
un1_N_7_i Net - - 0.623 - 8
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 D In - 9.701 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a2_0 CFG4 Y Out 0.232 9.933 r -
|
|
un5_fetch_ptr_sel_0_a2_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 D In - 10.051 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2 CFG4 Y Out 0.168 10.218 r -
|
|
un5_fetch_ptr_sel_i Net - - 0.896 - 43
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 D In - 11.115 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_12_RNI9CUB8 CFG4 Y Out 0.232 11.346 f -
|
|
apb_i_req_addr_net[14] Net - - 0.650 - 10
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 C In - 11.996 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.gen_tcm0_i_decode\.un8_cpu_i_req_is_tcm0lto2 CFG3 Y Out 0.145 12.142 f -
|
|
un8_cpu_i_req_is_tcm0lt3 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 D In - 12.259 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG4 Y Out 0.232 12.491 r -
|
|
d_m5_0_1 Net - - 0.594 - 6
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 B In - 13.086 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0 CFG3 Y Out 0.083 13.169 r -
|
|
cpu_i_req_is_tcm0 Net - - 0.609 - 7
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 D In - 13.778 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_RNIGM24V2 CFG4 Y Out 0.212 13.990 f -
|
|
d_m6_i_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 C In - 14.108 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_apb_RNIGPOAJ9 CFG4 Y Out 0.148 14.256 r -
|
|
cpu_i_req_is_apb_RNIGPOAJ9 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 C In - 14.380 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.bcu_op_completing_ex_3_1 CFG3 Y Out 0.148 14.527 r -
|
|
bcu_op_completing_ex Net - - 0.686 - 13
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 D In - 15.213 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_completing_ex_3_0_1_0_RNIE6SVP CFG4 Y Out 0.212 15.425 f -
|
|
instr_m3_1_1 Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 D In - 15.543 f -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 CFG4 Y Out 0.232 15.775 r -
|
|
instr_accepted_ex Net - - 1.125 - 150
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 A In - 16.900 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIT40LK2 CFG2 Y Out 0.051 16.951 r -
|
|
instr_accepted_ex_2_1_RNIT40LK2 Net - - 0.124 - 2
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 A In - 17.075 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIQ13595 CFG2 Y Out 0.051 17.125 r -
|
|
instr_accepted_ex_2_1_RNIQ13595 Net - - 0.918 - 34
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] SLE EN In - 18.044 r -
|
|
==========================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 18.171 is 4.084(22.5%) logic and 14.087(77.5%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q rst_n[0] 0.218 -0.228
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q IOOi1 0.218 1.875
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.SELA_LANE[10] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q SELA_LANE_net_0[10] 0.218 1.907
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.O00o1[8] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q O00o1[8] 0.201 2.138
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[13] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[13] 0.218 2.184
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Ooll1 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Ooll1 0.201 2.229
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[12] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[12] 0.218 2.235
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Ioll1 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Ioll1 0.218 2.248
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.genblk1\.i1Oi1[3] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q i1Oi1[3] 0.218 2.265
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[0] 0.218 2.272
|
|
========================================================================================================================================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn CLR_FLAGS_N_arst_i 3.200 -0.228
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn CLR_FLAGS_N_arst_i 3.200 -0.228
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[4] 8.000 1.875
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[5] 8.000 1.875
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[7] 8.000 1.875
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.SWITCH_LANE PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn rst_n[0] 3.180 1.880
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.cdr_ready_reg[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn rst_n[0] 3.180 1.880
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.cdr_ready_reg[1] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn rst_n[0] 3.180 1.880
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.cdr_ready_reg[2] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn rst_n[0] 3.180 1.880
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.cdr_ready_reg[3] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn rst_n[0] 3.180 1.880
|
|
================================================================================================================================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 3.200
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.200
|
|
|
|
- Propagation time: 3.428
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.228
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] / Q
|
|
Ending point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] / ALn
|
|
The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [falling] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------------------
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] SLE Q Out 0.218 0.218 r -
|
|
rst_n[0] Net - - 1.100 - 54
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 B In - 1.318 r -
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 Y Out 0.088 1.406 f -
|
|
CLR_FLAGS_N Net - - 0.974 - 3
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 A In - 2.380 f -
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 Y Out 0.047 2.427 r -
|
|
CLR_FLAGS_N_arst_i Net - - 1.001 - 4
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] SLE ALn In - 3.428 r -
|
|
==================================================================================================================
|
|
Total path delay (propagation time + setup) of 3.428 is 0.353(10.3%) logic and 3.075(89.7%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 3.200
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 3.200
|
|
|
|
- Propagation time: 3.428
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : -0.228
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] / Q
|
|
Ending point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] / ALn
|
|
The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [falling] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
------------------------------------------------------------------------------------------------------------------
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] SLE Q Out 0.218 0.218 r -
|
|
rst_n[0] Net - - 1.100 - 54
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 B In - 1.318 r -
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 Y Out 0.088 1.406 f -
|
|
CLR_FLAGS_N Net - - 0.974 - 3
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 A In - 2.380 f -
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 Y Out 0.047 2.427 r -
|
|
CLR_FLAGS_N_arst_i Net - - 1.001 - 4
|
|
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] SLE ALn In - 3.428 r -
|
|
==================================================================================================================
|
|
Total path delay (propagation time + setup) of 3.428 is 0.353(10.3%) logic and 3.075(89.7%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 8.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 8.000
|
|
|
|
- Propagation time: 6.125
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 1.875
|
|
|
|
Number of logic level(s): 10
|
|
Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q
|
|
Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] / D
|
|
The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r -
|
|
IOOi1 Net - - 0.933 - 53
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 B In - 1.151 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 Y Out 0.088 1.239 r -
|
|
OlI11[13] Net - - 0.926 - 51
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 C In - 2.165 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 Y Out 0.148 2.313 r -
|
|
m5_2 Net - - 0.547 - 3
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 D In - 2.860 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 Y Out 0.363 3.223 r -
|
|
m13_2_1_0_y0 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 A In - 3.341 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 Y Out 0.126 3.467 r -
|
|
m13_2_1_0_y1 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 B In - 3.585 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 Y Out 0.207 3.792 r -
|
|
i0lIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 B In - 3.910 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 Y Out 0.088 3.997 r -
|
|
un8_lolIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 B In - 4.115 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.088 4.203 f -
|
|
lolIo_2 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 D In - 4.321 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.192 4.513 f -
|
|
lolIo Net - - 0.686 - 13
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.199 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.047 5.245 r -
|
|
un1_N_5_mux_0_i Net - - 0.594 - 6
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI4KONQ4 CFG4 D In - 5.840 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI4KONQ4 CFG4 Y Out 0.168 6.008 r -
|
|
lliO1_0_iv_i[4] Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] SLE D In - 6.125 r -
|
|
====================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 6.125 is 1.731(28.3%) logic and 4.395(71.7%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 8.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 8.000
|
|
|
|
- Propagation time: 6.125
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 1.875
|
|
|
|
Number of logic level(s): 10
|
|
Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q
|
|
Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] / D
|
|
The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r -
|
|
IOOi1 Net - - 0.933 - 53
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 B In - 1.151 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 Y Out 0.088 1.239 r -
|
|
OlI11[13] Net - - 0.926 - 51
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 C In - 2.165 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 Y Out 0.148 2.313 r -
|
|
m5_2 Net - - 0.547 - 3
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 D In - 2.860 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 Y Out 0.363 3.223 r -
|
|
m13_2_1_0_y0 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 A In - 3.341 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 Y Out 0.126 3.467 r -
|
|
m13_2_1_0_y1 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 B In - 3.585 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 Y Out 0.207 3.792 r -
|
|
i0lIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 B In - 3.910 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 Y Out 0.088 3.997 r -
|
|
un8_lolIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 B In - 4.115 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.088 4.203 f -
|
|
lolIo_2 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 D In - 4.321 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.192 4.513 f -
|
|
lolIo Net - - 0.686 - 13
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.199 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.047 5.245 r -
|
|
un1_N_5_mux_0_i Net - - 0.594 - 6
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU_0 CFG4 D In - 5.840 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU_0 CFG4 Y Out 0.168 6.008 r -
|
|
lliO1_0_iv_i[7] Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] SLE D In - 6.125 r -
|
|
====================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 6.125 is 1.731(28.3%) logic and 4.395(71.7%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 8.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 8.000
|
|
|
|
- Propagation time: 6.125
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 1.875
|
|
|
|
Number of logic level(s): 10
|
|
Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q
|
|
Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] / D
|
|
The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r -
|
|
IOOi1 Net - - 0.933 - 53
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 B In - 1.151 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[13] CFG3 Y Out 0.088 1.239 r -
|
|
OlI11[13] Net - - 0.926 - 51
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 C In - 2.165 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m5 CFG3 Y Out 0.148 2.313 r -
|
|
m5_2 Net - - 0.547 - 3
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 D In - 2.860 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux ARI1 Y Out 0.363 3.223 r -
|
|
m13_2_1_0_y0 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 A In - 3.341 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_0 ARI1 Y Out 0.126 3.467 r -
|
|
m13_2_1_0_y1 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 B In - 3.585 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo_0_0_1_0_.m13_2_1_0_wmux_3 ARI1 Y Out 0.207 3.792 r -
|
|
i0lIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 B In - 3.910 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un8_lolIo CFG3 Y Out 0.088 3.997 r -
|
|
un8_lolIo Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 B In - 4.115 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.088 4.203 f -
|
|
lolIo_2 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 D In - 4.321 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.192 4.513 f -
|
|
lolIo Net - - 0.686 - 13
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.199 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.047 5.245 r -
|
|
un1_N_5_mux_0_i Net - - 0.594 - 6
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU CFG4 D In - 5.840 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU CFG4 Y Out 0.168 6.008 r -
|
|
lliO1_0_iv_i[5] Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] SLE D In - 6.125 r -
|
|
====================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 6.125 is 1.731(28.3%) logic and 4.395(71.7%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[0] 0.218 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXTFIF_SYS_1.I1ol1[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q I1ol1[0] 0.218 3.957
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.IioO1[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q IioO1[0] 0.218 4.016
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.IioO1[5] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q IioO1[5] 0.201 4.033
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.IioO1[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q IioO1[1] 0.218 4.076
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[1] 0.218 4.089
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[2] 0.218 4.097
|
|
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.IioO1[6] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q IioO1[6] 0.218 4.099
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[3] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[3] 0.218 4.105
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[4] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[4] 0.218 4.113
|
|
=================================================================================================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[3] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[4] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[5] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[6] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[7] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[8] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[9] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.659
|
|
=======================================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 8.000
|
|
- Setup time: 0.127
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 7.873
|
|
|
|
- Propagation time: 4.215
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 3.659
|
|
|
|
Number of logic level(s): 27
|
|
Starting point: CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] / Q
|
|
Ending point: CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] / EN
|
|
The start point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK
|
|
The end point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------------------------------------------------------------
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] SLE Q Out 0.218 0.218 r -
|
|
Il1Io[0] Net - - 0.547 - 3
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_0 ARI1 B In - 0.765 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_0 ARI1 FCO Out 0.328 1.093 f -
|
|
Ol1Io10_a_4_cry_0 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_1 ARI1 FCI In - 1.093 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_1 ARI1 FCO Out 0.008 1.101 f -
|
|
Ol1Io10_a_4_cry_1 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_2 ARI1 FCI In - 1.101 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_2 ARI1 FCO Out 0.008 1.109 f -
|
|
Ol1Io10_a_4_cry_2 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_3 ARI1 FCI In - 1.109 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_3 ARI1 FCO Out 0.008 1.117 f -
|
|
Ol1Io10_a_4_cry_3 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_4 ARI1 FCI In - 1.117 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_4 ARI1 FCO Out 0.008 1.125 f -
|
|
Ol1Io10_a_4_cry_4 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_5 ARI1 FCI In - 1.125 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_5 ARI1 FCO Out 0.008 1.133 f -
|
|
Ol1Io10_a_4_cry_5 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_6 ARI1 FCI In - 1.133 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_6 ARI1 FCO Out 0.008 1.141 f -
|
|
Ol1Io10_a_4_cry_6 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_7 ARI1 FCI In - 1.141 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_7 ARI1 FCO Out 0.008 1.149 f -
|
|
Ol1Io10_a_4_cry_7 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_8 ARI1 FCI In - 1.149 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_8 ARI1 FCO Out 0.008 1.157 f -
|
|
Ol1Io10_a_4_cry_8 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_9 ARI1 FCI In - 1.157 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_9 ARI1 FCO Out 0.008 1.165 f -
|
|
Ol1Io10_a_4_cry_9 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10 ARI1 FCI In - 1.165 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10 ARI1 FCO Out 0.008 1.173 f -
|
|
Ol1Io10_a_4_cry_10 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_11 ARI1 FCI In - 1.173 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_11 ARI1 FCO Out 0.008 1.181 f -
|
|
Ol1Io10_a_4_cry_11 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_12 ARI1 FCI In - 1.181 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_12 ARI1 FCO Out 0.008 1.189 f -
|
|
Ol1Io10_a_4_cry_12 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_13 ARI1 FCI In - 1.189 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_13 ARI1 FCO Out 0.008 1.197 f -
|
|
Ol1Io10_a_4_cry_13 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_14 ARI1 FCI In - 1.197 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_14 ARI1 FCO Out 0.008 1.205 f -
|
|
Ol1Io10_a_4_cry_14 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_15 ARI1 FCI In - 1.205 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_15 ARI1 FCO Out 0.008 1.213 f -
|
|
Ol1Io10_a_4_cry_15 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_16 ARI1 FCI In - 1.213 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_16 ARI1 FCO Out 0.008 1.221 f -
|
|
Ol1Io10_a_4_cry_16 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_17 ARI1 FCI In - 1.221 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_17 ARI1 FCO Out 0.008 1.229 f -
|
|
Ol1Io10_a_4_cry_17 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_18 ARI1 FCI In - 1.229 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_18 ARI1 FCO Out 0.008 1.237 f -
|
|
Ol1Io10_a_4_cry_18 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19 ARI1 FCI In - 1.237 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19 ARI1 FCO Out 0.008 1.245 f -
|
|
Ol1Io10_a_4_cry_19 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_20 ARI1 FCI In - 1.245 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_20 ARI1 FCO Out 0.008 1.253 f -
|
|
Ol1Io10_a_4_cry_20 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_21 ARI1 FCI In - 1.253 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_21 ARI1 FCO Out 0.008 1.261 f -
|
|
Ol1Io10_a_4_cry_21 Net - - 0.000 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_22 ARI1 FCI In - 1.261 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_22 ARI1 S Out 0.300 1.561 r -
|
|
Ol1Io10_22 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19_RNIR5LRM CFG4 D In - 1.679 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19_RNIR5LRM CFG4 Y Out 0.168 1.847 r -
|
|
Ol1Io10_NE_19 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10_RNI818323 CFG4 D In - 1.965 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10_RNI818323 CFG4 Y Out 0.168 2.132 r -
|
|
Ol1Io10_NE_25 Net - - 0.118 - 1
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_23_RNI7FA6M5 CFG4 D In - 2.250 r -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_23_RNI7FA6M5 CFG4 Y Out 0.212 2.462 f -
|
|
Ol1Io10_NE Net - - 0.817 - 42
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io6_10_RNIEPCN26 CFG4 C In - 3.279 f -
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io6_10_RNIEPCN26 CFG4 Y Out 0.130 3.410 r -
|
|
Il1Ioe Net - - 0.805 - 27
|
|
CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] SLE EN In - 4.215 r -
|
|
=======================================================================================================================================
|
|
Total path delay (propagation time + setup) of 4.341 is 1.819(41.9%) logic and 2.523(58.1%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: System
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UTDI UTDIInt 0.000 -27.793
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG URSTB iURSTB 0.000 -26.963
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[0] UIREGInt[0] 0.000 6.205
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[2] UIREGInt[2] 0.000 6.239
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[3] UIREGInt[3] 0.000 6.263
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[4] UIREGInt[4] 0.000 6.303
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[1] UIREGInt[1] 0.000 6.305
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[6] UIREGInt[6] 0.000 6.336
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[7] UIREGInt[7] 0.000 6.568
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UDRSH UDRSHInt 0.000 6.600
|
|
========================================================================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] System SLE D N_99_i 10.000 -27.793
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] System SLE D N_110_i 10.000 -27.793
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] System SLE D N_102_i 10.000 -27.748
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] System SLE D N_113_i 10.000 -27.748
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] System SLE D N_92_i 10.000 -27.728
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] System SLE D N_97_i 10.000 -27.728
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[7] System SLE D currTapState_ns[7] 10.000 -27.728
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[9] System SLE D currTapState_ns[9] 10.000 -27.728
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] System SLE D N_108_i 10.000 -27.728
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[14] System SLE D currTapState_ns[14] 10.000 -27.728
|
|
=======================================================================================================================================================================================================================================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 10.000
|
|
|
|
- Propagation time: 37.792
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : -27.792
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] / D
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r -
|
|
UTDIInt Net - - 0.948 - 6
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 D In - 37.462 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 Y Out 0.212 37.675 f -
|
|
N_99_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] SLE D In - 37.792 f -
|
|
===========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.792 is 3.787(10.0%) logic and 34.006(90.0%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 2:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 10.000
|
|
|
|
- Propagation time: 37.792
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : -27.792
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] / D
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r -
|
|
UTDIInt Net - - 0.948 - 6
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 D In - 37.462 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 Y Out 0.212 37.675 f -
|
|
N_110_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] SLE D In - 37.792 f -
|
|
============================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.792 is 3.787(10.0%) logic and 34.006(90.0%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 3:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 10.000
|
|
|
|
- Propagation time: 37.748
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : -27.748
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] / D
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r -
|
|
UTDIInt Net - - 0.948 - 6
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 D In - 37.462 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 Y Out 0.168 37.630 r -
|
|
N_102_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] SLE D In - 37.748 r -
|
|
===========================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.748 is 3.742(9.9%) logic and 34.006(90.1%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 4:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 10.000
|
|
|
|
- Propagation time: 37.748
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : -27.748
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] / D
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r -
|
|
UTDIInt Net - - 0.948 - 6
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r -
|
|
COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 D In - 37.462 r -
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 Y Out 0.168 37.630 r -
|
|
N_113_i Net - - 0.118 - 1
|
|
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] SLE D In - 37.748 r -
|
|
============================================================================================================================================================================================================================================================================================
|
|
Total path delay (propagation time + setup) of 37.748 is 3.742(9.9%) logic and 34.006(90.1%) route.
|
|
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
|
|
|
|
|
|
Path information for path number 5:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.000
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 10.000
|
|
|
|
- Propagation time: 37.728
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : -27.728
|
|
|
|
Number of logic level(s): 36
|
|
Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI
|
|
Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r -
|
|
UTDIInt Net - - 0.948 - 6
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r -
|
|
dut_tms_int Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r -
|
|
delay_sel[1] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r -
|
|
delay_sel[2] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r -
|
|
delay_sel[3] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r -
|
|
delay_sel[4] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r -
|
|
delay_sel[5] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r -
|
|
delay_sel[6] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r -
|
|
delay_sel[7] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r -
|
|
delay_sel[8] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r -
|
|
delay_sel[9] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r -
|
|
delay_sel[10] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r -
|
|
delay_sel[11] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r -
|
|
delay_sel[12] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r -
|
|
delay_sel[13] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r -
|
|
delay_sel[14] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r -
|
|
delay_sel[15] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r -
|
|
delay_sel[16] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r -
|
|
delay_sel[17] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r -
|
|
delay_sel[18] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r -
|
|
delay_sel[19] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r -
|
|
delay_sel[20] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r -
|
|
delay_sel[21] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r -
|
|
delay_sel[22] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r -
|
|
delay_sel[23] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r -
|
|
delay_sel[24] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r -
|
|
delay_sel[25] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r -
|
|
delay_sel[26] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r -
|
|
delay_sel[27] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r -
|
|
delay_sel[28] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r -
|
|
delay_sel[29] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r -
|
|
delay_sel[30] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r -
|
|
delay_sel[31] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r -
|
|
delay_sel[32] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r -
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r -
|
|
delay_sel[33] Net - - 0.948 - 1
|
|
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r -
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COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r -
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COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15
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MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 C In - 37.462 r -
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MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.148 37.610 r -
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N_92_i Net - - 0.118 - 1
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MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.728 r -
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===========================================================================================================================================================================================================================================================================================
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Total path delay (propagation time + setup) of 37.728 is 3.723(9.9%) logic and 34.006(90.1%) route.
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Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
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##### END OF TIMING REPORT #####]
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Timing exceptions that could not be applied
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
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@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
|
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
|
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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None
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Finished final timing analysis (Real Time elapsed 0h:03m:53s; CPU Time elapsed 0h:03m:50s; Memory used current: 433MB peak: 521MB)
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Finished timing report (Real Time elapsed 0h:03m:53s; CPU Time elapsed 0h:03m:50s; Memory used current: 433MB peak: 521MB)
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---------------------------------------
|
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Resource Usage Report for top
|
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|
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Mapping to part: mpf300tfcg1152-1
|
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Cell usage:
|
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AND2 1 use
|
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BANKEN 1 use
|
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BUFD 102 uses
|
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CLKINT 6 uses
|
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DLL 1 use
|
|
HS_IO_CLK 4 uses
|
|
ICB_CLKDIV 1 use
|
|
INIT 1 use
|
|
INV 4 uses
|
|
IOD 5 uses
|
|
LANECTRL 2 uses
|
|
OR2 32 uses
|
|
OR4 1344 uses
|
|
PLL 2 uses
|
|
RCLKINT 1 use
|
|
UJTAG 1 use
|
|
CFG1 110 uses
|
|
CFG2 1957 uses
|
|
CFG3 3420 uses
|
|
CFG4 8170 uses
|
|
|
|
Carry cells:
|
|
ARI1 2102 uses - used for arithmetic functions
|
|
ARI1 233 uses - used for Wide-Mux implementation
|
|
Total ARI1 2335 uses
|
|
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|
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Sequential Cells:
|
|
SLE 7316 uses
|
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|
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DSP Blocks: 0 of 924 (0%)
|
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|
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I/O ports: 58
|
|
I/O primitives: 50
|
|
BIBUF 1 use
|
|
INBUF 4 uses
|
|
INBUF_DIFF 2 uses
|
|
OUTBUF 42 uses
|
|
OUTBUF_DIFF 1 use
|
|
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|
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Global Clock Buffers: 7
|
|
|
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RAM/ROM usage summary
|
|
Total Block RAMs (RAM1K20) : 34 of 952 (3%)
|
|
Total Block RAMs (RAM64x12) : 11 of 2772 (0%)
|
|
|
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Total LUTs: 15992
|
|
|
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Extra resources required for RAM and MACC_PA interface logic during P&R:
|
|
|
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RAM64X12 Interface Logic : SLEs = 132; LUTs = 132;
|
|
RAM1K20 Interface Logic : SLEs = 1224; LUTs = 1224;
|
|
MACC_PA Interface Logic : SLEs = 0; LUTs = 0;
|
|
MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0;
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|
|
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Total number of SLEs after P&R: 7316 + 132 + 1224 + 0 = 8672;
|
|
Total number of LUTs after P&R: 15992 + 132 + 1224 + 0 = 17348;
|
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|
Mapper successful!
|
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At Mapper Exit (Real Time elapsed 0h:03m:54s; CPU Time elapsed 0h:03m:51s; Memory used current: 197MB peak: 521MB)
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Process took 0h:03m:54s realtime, 0h:03m:51s cputime
|
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# Wed Apr 15 22:52:03 2026
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###########################################################]
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