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hdl
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simulation
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smartgen
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synthesis
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tooldata
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viewdraw
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Design.md
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ethernet_tpsram_test.prjx
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fifio3.txt
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fifo1.txt
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fifo2.txt
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fifo4.txt
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fifo5.txt
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fifo6.txt
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iog_cdr.hex
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libero_setup_info.txt
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README.md
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rising_fifo.txt
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tmp.txt
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tpsram_test_1.txt
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README.md

Ethernet-IP-Core

For Ethernet IP Cre. development and testing on Eval kit for now

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Description
For Ethernet IP Cre. development and testing on Icicle kit for now
Readme 231 MiB
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Verilog 53%
HTML 38%
omnetpp-msg 6.3%
Tcl 1.3%
Roff 0.5%
Other 0.7%