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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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67
synthesis/top_cdc.csv Normal file
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@@ -0,0 +1,67 @@
SERNO,END_INSTANCE,END_CLOCK,START_CLOCK,START_INSTANCE,CDC_TYPE,SYNCHRONIZER,NUMBER_OF_SYNCHRONIZER_FFs,SAFE_CDC,DESCRIPTION
1,PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane,PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV,PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV,PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane,False Path Constraint,NO,0,NO,Combinatorial logic detected at clock domain crossing. Enable signal for synchonizer registers does not have a safe crossing.
2,PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6:0],PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R,PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV,PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.dll_delay_code[6:0],Different Clock Domains,YES,2,NO,Enable signal for synchonizer registers does not have a safe crossing.
3,PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6:0],PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R,PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R,PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1:0],False Path Constraint,NO,0,NO,Enable signal for synchonizer registers does not have a safe crossing.
4,PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1:0],PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R,PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV,PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.dll_valid_code,Different Clock Domains,YES,2,NO,Divergence detected in the crossover path.
5,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_dmactive,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
6,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.havereset_skip_pwrup,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
7,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_halted,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
8,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_resumeack,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
9,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_havereset,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
10,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[17:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
11,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[22:20],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
12,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[31:24],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
13,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_ackhavereset,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
14,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_ndmreset,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
15,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_haltreq,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
16,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_resumereq,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
17,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_0_reg[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
18,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abs_cmd_transfer_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
19,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_valid,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
20,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_wr_en,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
21,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_valid,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
22,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_wr_en,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
23,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_state[5:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
24,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abstractcs_busy,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
25,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
26,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
27,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_addr[5:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
28,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_addr[11:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
29,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_csr_reg[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
30,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_gpr_reg[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
31,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_op_wr_data[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
32,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abstractcs_cmderr[2:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
33,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg_state[5:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
34,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.cmderr_ff[2:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
35,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_readonaddr_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
36,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_readondata_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
37,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_autoincrement_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
38,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_access_ff[2:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
39,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_busyerror_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
40,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbaddr_ff[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
41,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.prescale_counter[3:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
42,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.timeout,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
43,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_state[3:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
44,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_rd_req_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
45,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_wr_req_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
46,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbdata_ff[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
47,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.counter[7:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
48,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_busy_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
49,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_valid_int,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
50,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_resp_ready_int,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
51,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_wr_data_int[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
52,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_uar_err_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
53,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_rd_byte_en_int[3:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
54,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_wr_byte_en_int[3:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
55,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_addr_int[31:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
56,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_ba_err_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
57,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_to_err_ff,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
58,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.rd_gray_ptr_synch[1:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.rd_gray_ptr[1:0],Different Clock Domains,YES,2,NO,Divergence detected in the crossover path.
59,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr_synch[1:0],COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr[1:0],Different Clock Domains,NO,0,NO,Divergence detected in the crossover path.
60,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_ptr[0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
61,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
62,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr[1:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
63,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.rd_gray_ptr_synch[1:0],COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.rd_gray_ptr[1:0],Different Clock Domains,YES,2,NO,Divergence detected in the crossover path.
64,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.wr_gray_ptr_synch[1:0],PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.wr_gray_ptr[1:0],Different Clock Domains,NO,0,NO,Divergence detected in the crossover path.
65,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0],COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
66,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_shift_register_active_high\.gen_shift_register_active_low\.shiftDMI[40:0],COREJTAGDEBUG_Z5|iUDRCK_inferred_clock,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0,MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0],Different Clock Domains,YES,NA,Not Analyzed,Potential RAM synchronizer detected.
1 SERNO END_INSTANCE END_CLOCK START_CLOCK START_INSTANCE CDC_TYPE SYNCHRONIZER NUMBER_OF_SYNCHRONIZER_FFs SAFE_CDC DESCRIPTION
2 1 PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane False Path Constraint NO 0 NO Combinatorial logic detected at clock domain crossing. Enable signal for synchonizer registers does not have a safe crossing.
3 2 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6:0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.dll_delay_code[6:0] Different Clock Domains YES 2 NO Enable signal for synchonizer registers does not have a safe crossing.
4 3 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6:0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1:0] False Path Constraint NO 0 NO Enable signal for synchonizer registers does not have a safe crossing.
5 4 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1:0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.dll_valid_code Different Clock Domains YES 2 NO Divergence detected in the crossover path.
6 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_dmactive PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
7 6 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.havereset_skip_pwrup PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
8 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_halted PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
9 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_resumeack PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
10 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmstatus_allany_havereset PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
11 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[17:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
12 11 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[22:20] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
13 12 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg[31:24] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
14 13 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_ackhavereset PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
15 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_ndmreset PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
16 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_haltreq PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
17 16 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.dmcontrol_resumereq PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
18 17 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_0_reg[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
19 18 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abs_cmd_transfer_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
20 19 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_valid PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
21 20 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_wr_en PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
22 21 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_valid PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
23 22 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_wr_en PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
24 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_state[5:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
25 24 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abstractcs_busy PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
26 25 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
27 26 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
28 27 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_addr[5:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
29 28 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_addr[11:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
30 29 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_csr_reg[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
31 30 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.data_gpr_reg[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
32 31 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_op_wr_data[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
33 32 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.abstractcs_cmderr[2:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
34 33 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.command_reg_state[5:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
35 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.cmderr_ff[2:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
36 35 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_readonaddr_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
37 36 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_readondata_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
38 37 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_autoincrement_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
39 38 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_access_ff[2:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
40 39 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_busyerror_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
41 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbaddr_ff[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
42 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.prescale_counter[3:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
43 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.timeout PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
44 43 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_state[3:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
45 44 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_rd_req_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
46 45 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_wr_req_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
47 46 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbdata_ff[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
48 47 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.counter[7:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
49 48 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_busy_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
50 49 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_valid_int PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
51 50 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_resp_ready_int PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
52 51 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_wr_data_int[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
53 52 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_uar_err_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
54 53 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_rd_byte_en_int[3:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
55 54 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_wr_byte_en_int[3:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
56 55 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sba_req_addr_int[31:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
57 56 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_ba_err_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
58 57 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.miv_rv32_debug_du_0.miv_rv32_debug_sba_0.sbcs_to_err_ff PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
59 58 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.rd_gray_ptr_synch[1:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.rd_gray_ptr[1:0] Different Clock Domains YES 2 NO Divergence detected in the crossover path.
60 59 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr_synch[1:0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr[1:0] Different Clock Domains NO 0 NO Divergence detected in the crossover path.
61 60 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_ptr[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
62 61 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
63 62 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.wr_gray_ptr[1:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
64 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.rd_gray_ptr_synch[1:0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.rd_gray_ptr[1:0] Different Clock Domains YES 2 NO Divergence detected in the crossover path.
65 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.wr_gray_ptr_synch[1:0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.wr_gray_ptr[1:0] Different Clock Domains NO 0 NO Divergence detected in the crossover path.
66 65 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.
67 66 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_shift_register_active_high\.gen_shift_register_active_low\.shiftDMI[40:0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] Different Clock Domains YES NA Not Analyzed Potential RAM synchronizer detected.