working FIFO and TPSRAM without packet flter
This commit is contained in:
420
synthesis/synwork/layer0.duruntime
Normal file
420
synthesis/synwork/layer0.duruntime
Normal file
@@ -0,0 +1,420 @@
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Runtime Summary:
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================
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* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
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Hardware Generation Phase : 0h:00m:02s
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* Library: work, DesignUnit: miv_rv32_debug_sba
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Optimization Phase : 0h:00m:01s
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* Library: work, DesignUnit: miv_rv32_ipcore_Z19
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Hardware Generation Phase : 0h:00m:08s
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* Library: work, DesignUnit: miv_rv32_expipe_Z16
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Hardware Generation Phase : 0h:00m:01s
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Optimization Phase : 0h:00m:01s
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* Library: work, DesignUnit: miv_rv32_csr_privarch_Z15
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Hardware Generation Phase : 0h:00m:01s
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* Library: work, DesignUnit: miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1
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Optimization Phase : 0h:00m:02s
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* Library: work, DesignUnit: miv_rv32_idecode_1_1s_1s_0s
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Optimization Phase : 0h:00m:01s
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* Library: work, DesignUnit: CTSE_CORETSE_TOP_Z10
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Hardware Generation Phase : 0h:00m:08s
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* Library: work, DesignUnit: CTSE_PEMSTAT_EIM_26s_1s_0s
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Optimization Phase : 0h:00m:01s
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* Library: work, DesignUnit: CTSE_TSMAC_TOP_Z9
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Hardware Generation Phase : 0h:00m:06s
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* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_Z5
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Hardware Generation Phase : 0h:00m:01s
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* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2
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Hardware Generation Phase : 0h:00m:02s
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The following design units have negligible CPU times:
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=====================================================
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* Library: work, DesignUnit: top
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: SSDetect
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_TPSRAM_C0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: COREDELAYCODE_TIP
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: pf_init_monitor_0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_CCC_0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: PF_CCC_0_PF_CCC_0_0_PF_CCC
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: MIV_RV32_C0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_ram_singleport_lp_Z21
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_fixed_arb_3s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_rr_pri_arb_3s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_fixed_arb_2s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_rr_pri_arb_2s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_subsys_debug_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_debug_du
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_debug_sba
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Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_debug_fifo_34s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_debug_fifo_41s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_debug_dtm_jtag_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_subsys_interconnect_Z18
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_buffer_7s_2s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_50397384
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_buffer_11s_2s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_buffer_6s_2s_1s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_hart_Z17
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_gpr_ram_array_32s_6s_32s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_gpr_ram_0s_0_0s_32s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_30s_1s_536870913
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_0s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_5s_1s_0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_31s_0s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_1s_0s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_1s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_3s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_5s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_decode_0s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_priv_irq_2s_0_0
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_irq_reg_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_bcu
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1
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Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_csr_decode_1s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_idecode_1_1s_1s_0s
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Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_lsu_32s_2s_1s_2s_2s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: miv_rv32_ifu_iab_32s_2s_3s_2s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: fifo_to_tpsram_bridge
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CORETSE_0
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CORETSE_Z11
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_MSGMII_CORE_26s_0s_18s_0s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_MSGMII_CNVRXO_26s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_MSGMII_CNVRXI_26s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
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* Library: work, DesignUnit: CTSE_MSGMII_TBI_26s_0s_0s_1s
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Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PETCR_26s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_PETBM_26s_0s_1s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
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* Library: work, DesignUnit: CTSE_MSGMII_PEANX_TOP_1s_26s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
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* Library: work, DesignUnit: CTSE_PEANX_SYNC_1s_26s
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Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEREX_PCS_0s_26s_1s
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||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_R10B8B
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||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PETEX_TOP_26s_0s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_T8B10B
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_MSGMII_CNVTXO_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_MSGMII_CNVTXI_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_RX4096X36_12s_26s_1s_1s_4s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_TX2048X40_11s_26s_1s_1s_4s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_ECC_0s_26s_16s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_LINC_ECC_16s_26s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_CLKRST_26s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_SI_SAL_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_MMCXWOL_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_26s
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_EIM_26s_1s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_STORE_26s
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_SINCNF_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_SADD_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_SINCHD_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_SINC_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_LADD_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_LINC_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMSTAT_CNTRL_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_SIB_SYNC_PULSE_26s_1s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PE_MCXMAC_26s_0_0s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PECAR_26s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEHST_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PEMGT_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PE_MCXMAC_CORE_26s_0_0s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PERMC_TOP_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PERFN_TOP_26s_0s_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PETFN_TOP_26s_0s_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PECRC_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_PETMC_TOP_1s_26s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: OiOI1_26s_11s_12s_32s_2s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_SIB_SYNC_2FLP_1s_26s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXFIF_CLKRST_26s_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXFIF_HST_Z8
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_TSM_SYSREG_26s_1s_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_DECODER
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CORESPI_0
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: CORESPI_Z7
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_32s_16s_32s_16s_0_0_1_0s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_chanctrl_Z6
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_clockmux
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_fifo_16s_32s_5
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_control_16s
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: CORESPI_LIB, DesignUnit: spi_rf_32s_16s_0
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREJTAGDEBUG_C0
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: COREJTAGDEBUG_LIB, DesignUnit: corejtagdebug_bufd_34s
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CoreAPB3_0
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: COREAPB3_LIB, DesignUnit: CoreAPB3_Z1
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: COREAPB3_LIB, DesignUnit: COREAPB3_MUXPTOB3
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: Core_reset_pf
|
||||
Hardware Generation Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: Core_reset_pf_Core_reset_pf_0_CORERESET_PF
|
||||
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit
|
||||
Hardware Generation Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit
|
||||
Hardware Generation Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_subsys_pkg
|
||||
Hardware Generation Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_pkg
|
||||
Hardware Generation Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_hart_cfg_pkg
|
||||
Hardware Generation Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: ICB_CLKDIV
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: DLL
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: HS_IO_CLK
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: RCLKINT
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: LANECTRL
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: IOD
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: OUTBUF_DIFF
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: BANKEN
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: INIT
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: PLL
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: INV
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: OR2
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CFG3
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CFG2
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: OR4
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_ipcore_Z19
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_expipe_Z16
|
||||
Initial Cleanup Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: miv_rv32_csr_privarch_Z15
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: INBUF_DIFF
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_CORETSE_TOP_Z10
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CTSE_TSMAC_TOP_Z9
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: CLKINT
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: BUFD
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: UJTAG
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_Z5
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: VCC
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: GND
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: RAM1K20
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: BIBUF
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
* Library: work, DesignUnit: AND2
|
||||
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
|
||||
Reference in New Issue
Block a user