working FIFO and TPSRAM without packet flter
This commit is contained in:
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synthesis/syntmp/closed.png
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synthesis/syntmp/cmdrec_compiler.log
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synthesis/syntmp/cmdrec_fpga_mapper.log
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synthesis/syntmp/cmdrec_fpga_mapper.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -sap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -otap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.tap -omap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -multisrs -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
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relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -sap ..\top.sap -otap ..\top.tap -omap ..\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile ..\scratchproject.prs -multisrs -ovm ..\top.vm -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_prem.srd -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\top.srm -prjdir ..\ -prjname top_syn -log ..\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
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rc:1 success:1 runtime:236
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file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
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file:..\top.tap|io:o|time:0|size:-1|exec:0|csum:
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file:..\top.map|io:o|time:1776273723|size:28|exec:0|csum:
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file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
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file:..\top.vm|io:o|time:1776273719|size:6264001|exec:0|csum:
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file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
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file:..\synwork\top_prem.srd|io:i|time:1776273483|size:1522539|exec:0|csum:DB252AC6E8654F85B7F9005EEC2CBE52
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file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
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file:top.plg|io:o|time:1776273723|size:4727|exec:0|csum:
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file:..\top.srm|io:o|time:1776273714|size:28753|exec:0|csum:
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file:..\synlog\top_fpga_mapper.srr|io:o|time:1776273723|size:628611|exec:0|csum:
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file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6
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synthesis/syntmp/cmdrec_multi_srs_gen.log
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synthesis/syntmp/cmdrec_multi_srs_gen.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_multi_srs_gen.srr
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relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs ..\synwork\top_comp.srs -osyn ..\synwork\top_mult.srs -log ..\synlog\top_multi_srs_gen.srr
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rc:0 success:1 runtime:3
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file:..\synwork\top_comp.srs|io:i|time:1776273468|size:2498683|exec:0|csum:D55B0D932EA25F21DF76D09F4D077B94
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file:..\synwork\top_mult.srs|io:o|time:1776273473|size:16492|exec:0|csum:
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file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776273473|size:1172|exec:0|csum:
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file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\syn_nfilter.exe|io:i|time:1745943928|size:10549248|exec:1|csum:0E24E2994826988AAC59CDBFBC24908C
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synthesis/syntmp/cmdrec_premap.log
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synthesis/syntmp/cmdrec_premap.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -flow prepass -gcc_prepass -osrd E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -qsap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -conchk_prepass E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
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relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile ..\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -flow prepass -gcc_prepass -osrd ..\synwork\top_prem.srd -qsap ..\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm ..\top.vm -conchk_prepass ..\top_cck.rpt -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_mult.srs -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\synwork\top_prem.srd -prjdir ..\ -prjname top_syn -log ..\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
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rc:1 success:1 runtime:15
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file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
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file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
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file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
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file:..\top.vm|io:o|time:1776270794|size:6521569|exec:0|csum:
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file:..\top_cck.rpt|io:o|time:1776273487|size:16263|exec:0|csum:
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file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
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file:..\synwork\top_mult.srs|io:i|time:1776273473|size:16492|exec:0|csum:8A8FBA27CAD8D4F9ABE7B311078B4CA3
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file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
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file:top.plg|io:o|time:1776273475|size:0|exec:0|csum:
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file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
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file:..\synlog\top_premap.srr|io:o|time:1776273488|size:50209|exec:0|csum:
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file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6
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<html><body><samp><pre>
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<!@TC:1776273296>
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</pre></samp></body></html>
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synthesis/syntmp/run_option.xml
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<?xml version="1.0" encoding="utf-8"?>
|
||||
<!--
|
||||
Synopsys, Inc.
|
||||
Version V-2023.09M-5
|
||||
Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\run_option.xml
|
||||
Written on Wed Apr 15 22:44:56 2026
|
||||
|
||||
|
||||
-->
|
||||
<project_attribute_list name="Project Settings">
|
||||
<option name="project_name" display_name="Project Name">top_syn</option>
|
||||
<option name="device_name" display_name="Device Name">synthesis: Microchip PolarFire : MPF300T</option>
|
||||
<option name="impl_name" display_name="Implementation Name">synthesis</option>
|
||||
<option name="top_module" display_name="Top Module">top</option>
|
||||
<option name="retiming" display_name="Retiming">0</option>
|
||||
<option name="resource_sharing" display_name="Resource Sharing">1</option>
|
||||
<option name="maxfan" display_name="Fanout Guide">10000</option>
|
||||
<option name="disable_io_insertion" display_name="Disable I/O Insertion">0</option>
|
||||
<option name="no_sequential_opt" display_name="Disable Sequential Optimizations">0</option>
|
||||
<option name="symbolic_fsm_compiler" display_name="FSM Compiler">1</option>
|
||||
</project_attribute_list>
|
||||
|
||||
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<html>
|
||||
<head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
|
||||
<title>Project Status Summary Page</title>
|
||||
<link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
|
||||
<script type = "text/javascript" src="projectstatuspage.js"></script>
|
||||
</head>
|
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|
||||
<body style="background-color:#f0f0ff;">
|
||||
|
||||
<table style="border:none;" width="100%" ><tr> <td class="outline">
|
||||
<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead class="tablehead"><tr><th colspan="4">Project Settings</th><tr>
|
||||
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> top_syn</td> <td class="optionTitle" align="left"> Device Name</td> <td> synthesis: Microchip PolarFire : MPF300T</td> </tr>
|
||||
<tr> <td class="optionTitle" align="left"> Implementation Name</td> <td> synthesis</td> <td class="optionTitle" align="left"> Top Module</td> <td> top</td> </tr>
|
||||
</thead>
|
||||
<tbody> <tr> <td class="optionTitle" align="left"> Retiming</td> <td> 0</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
|
||||
<tr> <td class="optionTitle" align="left"> Fanout Guide</td> <td> 10000</td> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> </tr>
|
||||
<tr> <td class="optionTitle" align="left"> Disable Sequential Optimizations</td> <td> 0</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
|
||||
|
||||
</tbody>
|
||||
</table><br> <table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
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||||
<thead class="tablehead"><tr><th colspan="9">Run Status</th></tr></thead>
|
||||
<tbody>
|
||||
<tr>
|
||||
<th align="left" width="17%">Job Name</th>
|
||||
<th align="left">Status</th>
|
||||
<td class="lnote" align="center" title="Notes"></td>
|
||||
<td class="lwarn" align="center" title="Warnings"></td>
|
||||
<td class="lerror" align="center" title="Errors"></td>
|
||||
<th align="left">CPU Time</th>
|
||||
<th align="left">Real Time</th>
|
||||
<th align="left">Memory</th>
|
||||
<th align="left">Date/Time</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="optionTitle"> (compiler)</td><td>Complete</td>
|
||||
<td>236</td>
|
||||
<td>403</td>
|
||||
<td>0</td>
|
||||
<td>-</td>
|
||||
<td>02m:53s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle"> (premap)</td><td>Complete</td>
|
||||
<td>65</td>
|
||||
<td>15</td>
|
||||
<td>0</td>
|
||||
<td>0m:13s</td>
|
||||
<td>0m:13s</td>
|
||||
<td>365MB</td>
|
||||
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:48 PM</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
|
||||
<td>103</td>
|
||||
<td>120</td>
|
||||
<td>0</td>
|
||||
<td>03m:51s</td>
|
||||
<td>03m:54s</td>
|
||||
<td>521MB</td>
|
||||
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:52 PM</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td> </tbody>
|
||||
</table>
|
||||
<br>
|
||||
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
|
||||
<thead class="tablehead"><tr><th colspan="4">Area Summary</th></tr></thead>
|
||||
<tfoot> <tr> <td class="optionTitle" colspan="2"></td><td class="optionTitle" colspan="2"></td></tr>
|
||||
</tfoot>
|
||||
<tbody> <tr>
|
||||
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2335</td>
|
||||
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7316</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td title ="Total DSP Blocks used" class="optionTitle" align="left">DSP Blocks
|
||||
(dsp_used)</td> <td>0</td>
|
||||
<td title ="Total I/O Cells used" class="optionTitle" align="left">I/O Cells</td> <td>50</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td title ="Total Global Clock Buffers used" class="optionTitle" align="left">Global Clock Buffers</td> <td>7</td>
|
||||
<td title ="Total RAM1K20 used" class="optionTitle" align="left">RAM1K20
|
||||
(v_ram)</td> <td>34</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td title ="Total RAM64x12 used" class="optionTitle" align="left">RAM64x12
|
||||
(v_ram)</td> <td>11</td>
|
||||
<td title ="Total LUTs used" class="optionTitle" align="left">LUTs
|
||||
(total_luts)</td> <td>15992</td>
|
||||
</tr>
|
||||
|
||||
</tbody>
|
||||
</table><br>
|
||||
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
|
||||
<thead class="tablehead"><tr><th colspan="4">Timing Summary</th></tr></thead>
|
||||
<tfoot> <tr> <td class="optionTitle" colspan="4"></td></tr>
|
||||
</tfoot>
|
||||
<tbody>
|
||||
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
|
||||
<tr> <td align="left">COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</td><td align="left">100.0 MHz</td><td align="left">13.4 MHz</td><td align="left">-32.246</td></tr>
|
||||
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.0 MHz</td><td align="left">-5.671</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</td><td align="left">125.0 MHz</td><td align="left">116.7 MHz</td><td align="left">-0.228</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">230.3 MHz</td><td align="left">3.659</td></tr>
|
||||
<tr> <td align="left">PHY_MDC_CLOCK</td><td align="left">2.9 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">REFCLK_P</td><td align="left">125.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">REF_CLK_0</td><td align="left">50.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">TCK</td><td align="left">10.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
|
||||
<tr> <td align="left">System</td><td align="left">100.0 MHz</td><td align="left">26.5 MHz</td><td align="left">-27.793</td></tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<br>
|
||||
<br>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
78
synthesis/syntmp/top.plg
Normal file
78
synthesis/syntmp/top.plg
Normal file
@@ -0,0 +1,78 @@
|
||||
@P: Worst Slack : -32.246
|
||||
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Frequency : 13.4 MHz
|
||||
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Frequency : 100.0 MHz
|
||||
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Period : 74.491
|
||||
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Period : 10.000
|
||||
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Slack : -32.246
|
||||
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.0 MHz
|
||||
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Frequency : 80.0 MHz
|
||||
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.171
|
||||
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Period : 12.500
|
||||
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.671
|
||||
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Frequency : 116.7 MHz
|
||||
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Frequency : 125.0 MHz
|
||||
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Period : 8.569
|
||||
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Period : 8.000
|
||||
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Slack : -0.228
|
||||
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Estimated Frequency : NA
|
||||
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Requested Frequency : 100.0 MHz
|
||||
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Estimated Period : NA
|
||||
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Requested Period : 10.000
|
||||
@P: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop - Slack : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Estimated Frequency : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Requested Frequency : 625.0 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Estimated Period : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Requested Period : 1.600
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 - Slack : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Estimated Frequency : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Requested Frequency : 625.0 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Estimated Period : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Requested Period : 1.600
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 - Slack : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Estimated Frequency : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Requested Frequency : 625.0 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Estimated Period : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Requested Period : 1.600
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 - Slack : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Frequency : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Frequency : 625.0 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Period : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Period : 1.600
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Slack : NA
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 230.3 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Frequency : 125.0 MHz
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.341
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Period : 8.000
|
||||
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.659
|
||||
@P: PHY_MDC_CLOCK - Estimated Frequency : NA
|
||||
@P: PHY_MDC_CLOCK - Requested Frequency : 2.9 MHz
|
||||
@P: PHY_MDC_CLOCK - Estimated Period : NA
|
||||
@P: PHY_MDC_CLOCK - Requested Period : 350.000
|
||||
@P: PHY_MDC_CLOCK - Slack : NA
|
||||
@P: REFCLK_P - Estimated Frequency : NA
|
||||
@P: REFCLK_P - Requested Frequency : 125.0 MHz
|
||||
@P: REFCLK_P - Estimated Period : NA
|
||||
@P: REFCLK_P - Requested Period : 8.000
|
||||
@P: REFCLK_P - Slack : NA
|
||||
@P: REF_CLK_0 - Estimated Frequency : NA
|
||||
@P: REF_CLK_0 - Requested Frequency : 50.0 MHz
|
||||
@P: REF_CLK_0 - Estimated Period : NA
|
||||
@P: REF_CLK_0 - Requested Period : 20.000
|
||||
@P: REF_CLK_0 - Slack : NA
|
||||
@P: TCK - Estimated Frequency : NA
|
||||
@P: TCK - Requested Frequency : 10.0 MHz
|
||||
@P: TCK - Estimated Period : NA
|
||||
@P: TCK - Requested Period : 100.000
|
||||
@P: TCK - Slack : NA
|
||||
@P: System - Estimated Frequency : 26.5 MHz
|
||||
@P: System - Requested Frequency : 100.0 MHz
|
||||
@P: System - Estimated Period : 37.793
|
||||
@P: System - Requested Period : 10.000
|
||||
@P: System - Slack : -27.793
|
||||
@P: top Part : mpf300tfcg1152-1
|
||||
@P: top Register bits : 7316
|
||||
@P: top DSP Blocks : 0
|
||||
@P: top I/O primitives : 50
|
||||
@P: top RAM1K20 : 34
|
||||
@P: top RAM64x12 : 11
|
||||
@P: CPU Time : 0h:03m:50s
|
||||
209
synthesis/syntmp/top_cck_rpt.htm
Normal file
209
synthesis/syntmp/top_cck_rpt.htm
Normal file
@@ -0,0 +1,209 @@
|
||||
<html><body><samp><pre>
|
||||
<!@TC:1776273296>
|
||||
|
||||
Copyright (C) 1994-2023 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: V-2023.09M-5
|
||||
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
|
||||
OS: Windows 10 or later
|
||||
Hostname: SOFTWARE-PC
|
||||
|
||||
Implementation : synthesis
|
||||
|
||||
# Written on Wed Apr 15 22:48:07 2026
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "top"
|
||||
Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 15 issues in 15 out of 47 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
|
||||
System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | No paths | 10.000 | No paths
|
||||
REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
|
||||
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 | 8.000 | 3.200 | 4.800
|
||||
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
|
||||
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
|
||||
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | No paths | No paths
|
||||
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
|
||||
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp | No paths | No paths | No paths
|
||||
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
|
||||
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp | No paths | Diff grp | No paths
|
||||
PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
|
||||
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | Diff grp | No paths
|
||||
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
|
||||
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 | No paths | No paths | No paths
|
||||
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 | No paths | No paths | No paths
|
||||
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | Diff grp
|
||||
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | 10.000 | 5.000 | 5.000
|
||||
=========================================================================================================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
<a name=UnconstrainedStartEndPointsCCK60></a>Unconstrained Start/End Points</a>
|
||||
******************************
|
||||
|
||||
p:LINK_OK
|
||||
p:PHY_RST
|
||||
p:RD_BC_ERROR
|
||||
p:REFCLK_N
|
||||
p:REF_CLK_SEL
|
||||
p:RX
|
||||
p:RX_N
|
||||
p:RX_P
|
||||
p:R_DATA[0]
|
||||
p:R_DATA[1]
|
||||
p:R_DATA[2]
|
||||
p:R_DATA[3]
|
||||
p:R_DATA[4]
|
||||
p:R_DATA[5]
|
||||
p:R_DATA[6]
|
||||
p:R_DATA[7]
|
||||
p:R_DATA[8]
|
||||
p:R_DATA[9]
|
||||
p:R_DATA[10]
|
||||
p:R_DATA[11]
|
||||
p:R_DATA[12]
|
||||
p:R_DATA[13]
|
||||
p:R_DATA[14]
|
||||
p:R_DATA[15]
|
||||
p:R_DATA[16]
|
||||
p:R_DATA[17]
|
||||
p:R_DATA[18]
|
||||
p:R_DATA[19]
|
||||
p:R_DATA[20]
|
||||
p:R_DATA[21]
|
||||
p:R_DATA[22]
|
||||
p:R_DATA[23]
|
||||
p:R_DATA[24]
|
||||
p:R_DATA[25]
|
||||
p:R_DATA[26]
|
||||
p:R_DATA[27]
|
||||
p:R_DATA[28]
|
||||
p:R_DATA[29]
|
||||
p:R_DATA[30]
|
||||
p:R_DATA[31]
|
||||
p:SPISCLKO
|
||||
p:SPISDI
|
||||
p:SPISDO
|
||||
p:SPISS
|
||||
p:TDI
|
||||
p:TDO
|
||||
p:TMS
|
||||
p:TRSTB
|
||||
p:TX
|
||||
p:TX_N
|
||||
p:TX_P
|
||||
p:coma_mode
|
||||
|
||||
|
||||
<a name=InapplicableconstraintsCCK61></a>Inapplicable constraints</a>
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
<a name=ApplicableConstraintsWithIssuesCCK62></a>Applicable constraints with issues</a>
|
||||
**********************************
|
||||
|
||||
set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
set_false_path -to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]
|
||||
@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
|
||||
<a name=ConstraintsWithMatchingWildcardExpressionsCCK63></a>Constraints with matching wildcard expressions</a>
|
||||
**********************************************
|
||||
|
||||
set_false_path -from [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":46:0:46:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]" applies to objects:
|
||||
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane
|
||||
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane6_0_i4
|
||||
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane_4
|
||||
set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|expression "[get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }]" applies to objects:
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[0]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[4]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[5]
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":28:0:28:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]" applies to objects:
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[0]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[1]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[2]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[3]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[4]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[5]
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6]
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":30:0:30:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]" applies to objects:
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1]
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":31:0:31:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]" applies to objects:
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1]
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":29:0:29:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]" applies to objects:
|
||||
PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1]
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":44:0:44:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]" applies to objects:
|
||||
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1]
|
||||
set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]
|
||||
@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":43:0:43:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]" applies to objects:
|
||||
PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1]
|
||||
|
||||
<a name=LibraryReportCCK64></a>Library Report</a>
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
|
||||
</pre></samp></body></html>
|
||||
5
synthesis/syntmp/top_cck_rpt.tgl
Normal file
5
synthesis/syntmp/top_cck_rpt.tgl
Normal file
@@ -0,0 +1,5 @@
|
||||
Unconstrained Start/End Points, UnconstrainedStartEndPointsCCK60
|
||||
Inapplicable constraints, InapplicableconstraintsCCK61
|
||||
Applicable constraints with issues, ApplicableConstraintsWithIssuesCCK62
|
||||
Constraints with matching wildcard expressions, ConstraintsWithMatchingWildcardExpressionsCCK63
|
||||
Library Report, LibraryReportCCK64
|
||||
13
synthesis/syntmp/top_dsp_rpt_txt.htm
Normal file
13
synthesis/syntmp/top_dsp_rpt_txt.htm
Normal file
@@ -0,0 +1,13 @@
|
||||
<html><body><samp><pre>
|
||||
<!@TC:1776273296>
|
||||
|
||||
##### START OF DSP REPORT #####
|
||||
|
||||
SNo Instantiated Instance_Name User_Attribute MACC_Structure MACC_Name Primitive_Type DOTP P_REG(EN/ARST/SRST) A_REG(EN/ARST/SRST) B_REG(EN/ARST/SRST) C_REG(EN/ARST/SRST) D_REG(EN/ARST/SRST) SUB_REG(EN/ARST/SRST) B2_REG(EN/ARST/SRST) PortName Retiming_level RTL_reference
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
===================================================================================================================================================================================================================================================================================================================================================
|
||||
|
||||
##### END OF DSP REPORT #####
|
||||
|
||||
|
||||
</pre></samp></body></html>
|
||||
22
synthesis/syntmp/top_fanout_rpt_txt.htm
Normal file
22
synthesis/syntmp/top_fanout_rpt_txt.htm
Normal file
@@ -0,0 +1,22 @@
|
||||
<html><body><samp><pre>
|
||||
<!@TC:1776273296>
|
||||
|
||||
######## REPORT FOR HIGH FANOUT NETS ########
|
||||
|
||||
CLOCK GLOBAL THRESHOLD - 2
|
||||
ASYNC GLOBAL THRESHOLD - 800
|
||||
GLOBAL THRESHOLD - 5000
|
||||
|
||||
NET NAME CLOCK LOADS ASYNC RST LOADS SYNC RST LOADS ENABLE LOADS DATA LOADS TOTAL FANOUT GLOBAL BUFFER PRESENT
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
PF_CCC_0_0_OUT0_FABCLK_0 4701 0 0 0 0 4701 YES
|
||||
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1288 0 0 0 0 1288 YES
|
||||
PF_IOD_CDR_C0_0_RX_CLK_R 1252 0 0 0 0 1252 YES
|
||||
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0_TGT_TCK_0_i 205 0 0 0 0 205 YES
|
||||
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK 17 0 0 0 1 18 YES
|
||||
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 2 0 0 0 0 2 YES
|
||||
PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK 2 0 0 0 0 2 YES
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.CLKRST_U.hstrst 0 1649 0 0 0 1649 NO
|
||||
======================================================================================================================================================================================================
|
||||
|
||||
</pre></samp></body></html>
|
||||
226
synthesis/syntmp/top_ram_rpt_txt.htm
Normal file
226
synthesis/syntmp/top_ram_rpt_txt.htm
Normal file
@@ -0,0 +1,226 @@
|
||||
<html><body><samp><pre>
|
||||
<!@TC:1776273296>
|
||||
|
||||
##### START OF RAM REPORT #####
|
||||
|
||||
##### LSRAM REPORT #####
|
||||
|
||||
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH(A/B) LOW-POWER_MODE ECC A_DOUT_PIPE_REG(EN/ARST/SRST) B_DOUT_PIPE_REG(EN/ARST/SRST) WRITE_MODE(A/B) COMMENTS
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io[35:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_0 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_1 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_2 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_3 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_4 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_5 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_6 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
|
||||
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io[39:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_0 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_1 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_2 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_3 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
|
||||
|
||||
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
|
||||
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
|
||||
=====================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
|
||||
##### URAM REPORT #####
|
||||
|
||||
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH LOW-POWER_MODE ECC R_ADDR_REG(EN/ARST/SRST) R_DATA_PIPE_REG(EN/ARST/SRST) COMMENTS
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
|
||||
|
||||
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
|
||||
|
||||
NO CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
|
||||
CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
|
||||
|
||||
NO CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
|
||||
CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
|
||||
|
||||
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[6:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data_gen_buff_loop\[0\]\.buff_data_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
|
||||
===================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
|
||||
|
||||
##### REG/LOGIC REPORT #####
|
||||
|
||||
RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE COMMENTS
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Core_reset_pf_0.Core_reset_pf_0.dff NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_FAB_1.lI1I1_1 NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lo0l1 NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lI0l1 NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Ii0l1 NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.o10l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Il0l1 NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.oO0l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.iOOIo NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lOOIo NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.olIIo NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.O0IO1_1 NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.ilIO1_1 NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.OOOIo NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.IiiOo[7:0] NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lo1Oo[3:0] NA NA Mapping instance using registers.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.Ol1Oo NA NA Mapping instance using registers.
|
||||
|
||||
CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_out_2 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i1oIo[5:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.IooIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.lO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.IO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
|
||||
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[5:0] RAM DEFAULT RAM instance meets the required threshold for mapping using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[10:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
|
||||
|
||||
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_lsu_0.lsu_emi_req_fence_1 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
|
||||
============================================================================================================================================================================================================================================================================
|
||||
|
||||
##### END OF RAM REPORT #####
|
||||
|
||||
|
||||
</pre></samp></body></html>
|
||||
6461
synthesis/syntmp/top_srr.htm
Normal file
6461
synthesis/syntmp/top_srr.htm
Normal file
File diff suppressed because it is too large
Load Diff
60
synthesis/syntmp/top_toc.htm
Normal file
60
synthesis/syntmp/top_toc.htm
Normal file
@@ -0,0 +1,60 @@
|
||||
<html>
|
||||
<head>
|
||||
<script type="text/javascript" src="file:///E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\report\reportlog_tree.js"></script>
|
||||
<link rel="stylesheet" type="text/css" href="file:///E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\report\reportlog_tree.css" />
|
||||
</head>
|
||||
|
||||
<body style="background-color:#e0e0ff;">
|
||||
<script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
|
||||
<ul id="synthesis-menu" class="treeview" style="padding-left:12;">
|
||||
<li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">top_syn (synthesis)</b>
|
||||
<ul rel="open" style="font-size:small;">
|
||||
|
||||
<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
|
||||
<ul rel="open">
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport9" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport20" target="srrFrame" title="">Pre-mapping Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport21" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport32" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#timingReport33" target="srrFrame" title="">Timing Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#performanceSummary34" target="srrFrame" title="">Performance Summary</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockRelationships35" target="srrFrame" title="">Clock Relationships</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#interfaceInfo36" target="srrFrame" title="">Interface Information</a>
|
||||
<ul >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#inputPorts37" target="srrFrame" title="">Input Ports</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#outputPorts38" target="srrFrame" title="">Output Ports</a> </li></ul></li>
|
||||
<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
|
||||
<ul >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport39" target="srrFrame" title="">Clock: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</a>
|
||||
<ul >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#startingSlack56" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#endingSlack57" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#worstPaths58" target="srrFrame" title="">Worst Path Information</a> </li></ul></li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport43" target="srrFrame" title="">Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport47" target="srrFrame" title="">Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport51" target="srrFrame" title="">Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport55" target="srrFrame" title="">Clock: System</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (22:49 15-Apr)</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (22:51 15-Apr)</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (22:51 15-Apr)</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#resourceUsage59" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (22:51 15-Apr)</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (22:48 15-Apr)</a>
|
||||
<ul >
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#UnconstrainedStartEndPointsCCK60" target="srrFrame" title="">Unconstrained Start/End Points</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#InapplicableconstraintsCCK61" target="srrFrame" title="">Inapplicable constraints</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ApplicableConstraintsWithIssuesCCK62" target="srrFrame" title="">Applicable constraints with issues</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ConstraintsWithMatchingWildcardExpressionsCCK63" target="srrFrame" title="">Constraints with matching wildcard expressions</a> </li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#LibraryReportCCK64" target="srrFrame" title="">Library Report</a> </li></ul></li>
|
||||
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (22:52 15-Apr)</a> </li></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<script type="text/javascript"> reportLogObj.generateLog("synthesis-menu")</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
41
synthesis/syntmp/traplog.tlg
Normal file
41
synthesis/syntmp/traplog.tlg
Normal file
@@ -0,0 +1,41 @@
|
||||
@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a42256":4:7:4:9|Synthesizing work.top.gen.
|
||||
@N: CD630 :"syng0a42256":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@W: CD796 :"syng0a42256":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
|
||||
@N: CD630 :"syng0a42256":6:7:6:16|Synthesizing work.eq_element.eqn.
|
||||
@W: CD280 :"syng0a42256":15:11:15:17|Unbound component MUXCY_L mapped to black box
|
||||
@N: CD630 :"syng0a42256":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
|
||||
Post processing for work.muxcy_l.syn_black_box
|
||||
Running optimization stage 1 on MUXCY_L .......
|
||||
Finished optimization stage 1 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Post processing for work.eq_element.eqn
|
||||
Running optimization stage 1 on eq_element .......
|
||||
Finished optimization stage 1 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Post processing for work.cmp_eq.cell_level
|
||||
Running optimization stage 1 on CMP_EQ .......
|
||||
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Post processing for work.top.gen
|
||||
Running optimization stage 1 on top .......
|
||||
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Running optimization stage 2 on MUXCY_L .......
|
||||
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Running optimization stage 2 on eq_element .......
|
||||
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Running optimization stage 2 on CMP_EQ .......
|
||||
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
Running optimization stage 2 on top .......
|
||||
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
|
||||
BIN
synthesis/syntmp/traplog.tlg.db
Normal file
BIN
synthesis/syntmp/traplog.tlg.db
Normal file
Binary file not shown.
47
synthesis/syntmp/vhdlsyn1992a29252_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a29252_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 19:34:11 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn1992a42256_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a42256_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:48:40 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn1992a43376_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a43376_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Mon Apr 13 21:48:49 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn1992a45384_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a45384_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 18:35:13 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn1992a48368_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a48368_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:00:03 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn1992a50884_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn1992a50884_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 20:24:46 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(9 downto 0);
|
||||
B : in std_logic_vector(9 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (9 downto 0);
|
||||
B : in std_logic_vector (9 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (9 downto 0);
|
||||
signal tmp_B : std_logic_vector (9 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a29252_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a29252_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 19:34:19 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a42256_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a42256_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:48:48 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a43376_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a43376_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Mon Apr 13 21:48:55 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a45384_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a45384_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 18:35:18 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a48368_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a48368_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:00:10 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2479a50884_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2479a50884_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 20:24:51 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(14 downto 0);
|
||||
B : in std_logic_vector(14 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (14 downto 0);
|
||||
B : in std_logic_vector (14 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (14 downto 0);
|
||||
signal tmp_B : std_logic_vector (14 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a29252_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a29252_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 19:34:07 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a42256_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a42256_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:48:37 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a43376_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a43376_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Mon Apr 13 21:48:45 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a45384_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a45384_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 18:35:09 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a48368_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a48368_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 21:59:59 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn2735a50884_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn2735a50884_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 20:24:42 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(15 downto 0);
|
||||
B : in std_logic_vector(15 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (15 downto 0);
|
||||
B : in std_logic_vector (15 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (15 downto 0);
|
||||
signal tmp_B : std_logic_vector (15 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a29252_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a29252_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 19:34:24 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a42256_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a42256_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:48:53 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a43376_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a43376_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Mon Apr 13 21:49:00 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a45384_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a45384_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 18:35:23 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a48368_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a48368_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 22:00:16 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
47
synthesis/syntmp/vhdlsyn4998a50884_top_wrapper.vhd
Normal file
47
synthesis/syntmp/vhdlsyn4998a50884_top_wrapper.vhd
Normal file
@@ -0,0 +1,47 @@
|
||||
--
|
||||
-- Synopsys
|
||||
-- Vhdl wrapper for top level design, written on Wed Apr 15 20:24:56 2026
|
||||
--
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
library work;
|
||||
use work.genpackage.all;
|
||||
|
||||
entity wrapper_for_top is
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector(31 downto 0);
|
||||
B : in std_logic_vector(31 downto 0)
|
||||
);
|
||||
end wrapper_for_top;
|
||||
|
||||
architecture gen of wrapper_for_top is
|
||||
|
||||
component top
|
||||
port (
|
||||
EQ : out std_logic;
|
||||
A : in std_logic_vector (31 downto 0);
|
||||
B : in std_logic_vector (31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal tmp_EQ : std_logic;
|
||||
signal tmp_A : std_logic_vector (31 downto 0);
|
||||
signal tmp_B : std_logic_vector (31 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
EQ <= tmp_EQ;
|
||||
|
||||
tmp_A <= A;
|
||||
|
||||
tmp_B <= B;
|
||||
|
||||
|
||||
|
||||
u1: top port map (
|
||||
EQ => tmp_EQ,
|
||||
A => tmp_A,
|
||||
B => tmp_B
|
||||
);
|
||||
end gen;
|
||||
Reference in New Issue
Block a user