working FIFO and TPSRAM without packet flter

synthesis/synplify.log.bak.4

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+
+                               Synplify Pro (R) 
+
+                 Version V-2023.09M-5 for win64 - Apr 29, 2025 
+
+                    Copyright (c) 1988 - 2025 Synopsys, Inc.
+   This software and the associated documentation are proprietary to Synopsys,
+ Inc. This software may only be used in accordance with the terms and conditions
+ of a written license agreement with Synopsys, Inc. All other use, reproduction,
+   or distribution of this software is strictly prohibited.  Licensed Products
+     communicate with Synopsys servers for the purpose of providing software
+    updates, detecting software piracy and verifying that customers are using
+    Licensed Products in conformity with the applicable License Key for such
+  Licensed Products. Synopsys will use information gathered in connection with
+    this process to deliver software updates and pursue software pirates and
+                                   infringers.
+
+ Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
+            Inclusivity and Diversity" (Refer to article 000036315 at
+                        https://solvnetplus.synopsys.com)
+
+Starting:    E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
+Install:     E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
+Hostname:    SOFTWARE-PC
+Date:        Mon Apr 13 21:43:58 2026
+Version:     V-2023.09M-5
+
+Arguments:   -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
+ProductType: synplify_pro
+
+License checkout: synplifypro_actel
+License: synplifypro_actel node-locked 
+Licensed Vendor: actel
+License Option: actel_oem
+
+Running in Vendor Mode
+
+
+Implementation not found: synthesis
+log file: "E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr"
+Running: synthesis in foreground
+
+Running top_syn|synthesis
+
+Running Flow: compile (Compile) on top_syn|synthesis
+# Mon Apr 13 21:43:59 2026
+
+Running Flow: compile_flow (Compile Process) on top_syn|synthesis
+# Mon Apr 13 21:43:59 2026
+
+Running: compiler (Compile Input) on top_syn|synthesis
+# Mon Apr 13 21:43:59 2026
+Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
+
+compiler completed
+# Mon Apr 13 21:47:56 2026
+
+Return Code: 0
+Run Time:00h:03m:56s
+
+Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
+# Mon Apr 13 21:47:56 2026
+
+multi_srs_gen completed
+# Mon Apr 13 21:47:59 2026
+
+Return Code: 0
+Run Time:00h:00m:03s
+Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
+Complete: Compile Process on top_syn|synthesis
+
+Running: premap (Premap) on top_syn|synthesis
+# Mon Apr 13 21:47:59 2026
+
+premap completed with warnings
+# Mon Apr 13 21:48:16 2026
+
+Return Code: 1
+Run Time:00h:00m:17s
+Complete: Compile on top_syn|synthesis
+
+Running Flow: map (Map) on top_syn|synthesis
+# Mon Apr 13 21:48:16 2026
+License granted for 4 parallel jobs
+
+Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
+# Mon Apr 13 21:48:16 2026
+Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srm
+
+fpga_mapper completed with warnings
+# Mon Apr 13 21:52:16 2026
+
+Return Code: 1
+Run Time:00h:04m:00s
+Complete: Map on top_syn|synthesis
+Complete: Logic Synthesis on top_syn|synthesis
+Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\backup\top.srr
+TCL script complete: "top_syn.tcl"
+exit status=0
+exit status=0
+License checkin: synplifypro_actel