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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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simulation/modelsim.ini.sav Normal file
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[Library]
others = $MODEL_TECH/../modelsim.ini
PolarFire = E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
syncad_vhdl_lib = E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000