abhishek/Ethernet-IP-Core
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

working FIFO and TPSRAM without packet flter

Browse Source
This commit is contained in:
abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

BIN
simulation/bfmtovec.exe Normal file
View File

Binary file not shown.

BIN
simulation/bfmtovec.lin Normal file
View File

Binary file not shown.

33
simulation/bfmtovec_compile.tcl Normal file
View File

@@ -0,0 +1,33 @@
### script to compile Actel AMBA BFM source file(s) into vector file(s)
### for simulation
# 05Feb10 Production Release Version 3.0
quietly set chmod_exe "/bin/chmod"
quietly set linux_exe "./bfmtovec.lin"
quietly set windows_exe "./bfmtovec.exe"
quietly set bfm_in1 "./coreapb3_usertb_master.bfm"
quietly set bfm_out1 "./coreapb3_usertb_master.vec"
quietly set log "./bfmtovec_compile.log"
# check OS type and use appropriate executable
if {$tcl_platform(os) == "Linux"} {
echo "--- Using Linux Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe $linux_exe
if {![file executable $bfmtovec_exe]} {
quietly set cmds "exec $chmod_exe +x $bfmtovec_exe"
eval $cmds
}
} else {
echo "--- Using Windows Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe $windows_exe
}
# compile BFM source file(s) into vector output file(s)
echo "--- Compiling Actel DirectCore AMBA BFM source files ..."
quietly set cmd1 "exec $bfmtovec_exe -in $bfm_in1 -out $bfm_out1 > $log"
eval $cmd1
# print contents of log file
quietly set f [open $log]
while {[gets $f line] >= 0} {puts $line}
close $f
echo "--- Done Compiling Actel DirectCore AMBA BFM source files."

262
simulation/coreapb3_usertb_master.bfm Normal file
View File

@@ -0,0 +1,262 @@
// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: User testbench APB3 master BFM script for CoreAPB3
//
// SVN Revision Information:
// SVN $Revision: 18490 $
// SVN $Date: 2012-11-21 23:33:55 +0530 (Wed, 21 Nov 2012) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ********************************************************************
//-------------------------------------------------------------------------
// Memory Map
// Define name and base address of each resource.
//-------------------------------------------------------------------------
memmap base 0x0
// Global variables to store local copy of testbench parameters and constants
// derived from testbench parameters.
int APB_DWIDTH
int IADDR_OPTION
int APBSLOT0ENABLE
int APBSLOT1ENABLE
int APBSLOT2ENABLE
int APBSLOT3ENABLE
int APBSLOT4ENABLE
int APBSLOT5ENABLE
int APBSLOT6ENABLE
int APBSLOT7ENABLE
int APBSLOT8ENABLE
int APBSLOT9ENABLE
int APBSLOT10ENABLE
int APBSLOT11ENABLE
int APBSLOT12ENABLE
int APBSLOT13ENABLE
int APBSLOT14ENABLE
int APBSLOT15ENABLE
int MADDR_BITS
int UPR_NIBBLE_POSN
int SC_0
int SC_1
int SC_2
int SC_3
int SC_4
int SC_5
int SC_6
int SC_7
int SC_8
int SC_9
int SC_10
int SC_11
int SC_12
int SC_13
int SC_14
int SC_15
int slot_incr
int atmp
int slot_enable[16]
int slot_combine[16]
int iaddr_opt
int i
procedure main
header "CoreAPB3 Test Harness"
debug 3;
// Initialize local variables passed from testbench HDL to the
// ARGVALUE* BFM parameters.
call init_parameter_vars
// Set size of slot increment based on the MADDR_BITS parameter.
if MADDR_BITS == 12
set slot_incr 0x00000100
endif
if MADDR_BITS == 16
set slot_incr 0x00001000
endif
if MADDR_BITS == 20
set slot_incr 0x00010000
endif
if MADDR_BITS == 24
set slot_incr 0x00100000
endif
if MADDR_BITS == 28
set slot_incr 0x01000000
endif
if MADDR_BITS == 32
set slot_incr 0x10000000
endif
// Create vector for slot enable indication.
set slot_enable[0] APBSLOT0ENABLE
set slot_enable[1] APBSLOT1ENABLE
set slot_enable[2] APBSLOT2ENABLE
set slot_enable[3] APBSLOT3ENABLE
set slot_enable[4] APBSLOT4ENABLE
set slot_enable[5] APBSLOT5ENABLE
set slot_enable[6] APBSLOT6ENABLE
set slot_enable[7] APBSLOT7ENABLE
set slot_enable[8] APBSLOT8ENABLE
set slot_enable[9] APBSLOT9ENABLE
set slot_enable[10] APBSLOT10ENABLE
set slot_enable[11] APBSLOT11ENABLE
set slot_enable[12] APBSLOT12ENABLE
set slot_enable[13] APBSLOT13ENABLE
set slot_enable[14] APBSLOT14ENABLE
set slot_enable[15] APBSLOT15ENABLE
// Create vector for slot combined indication
set slot_combine[0] SC_0
set slot_combine[1] SC_1
set slot_combine[2] SC_2
set slot_combine[3] SC_3
set slot_combine[4] SC_4
set slot_combine[5] SC_5
set slot_combine[6] SC_6
set slot_combine[7] SC_7
set slot_combine[8] SC_8
set slot_combine[9] SC_9
set slot_combine[10] SC_10
set slot_combine[11] SC_11
set slot_combine[12] SC_12
set slot_combine[13] SC_13
set slot_combine[14] SC_14
set slot_combine[15] SC_15
loop i 0 15 1
// iaddr_opt is set to (i + 2) because values for IADDR_OPTION relevant
// to slots 0 to 15 run from 2 to 17.
// (IADDR_OPTION = 0 -> indirect addressing not in use.)
// (IADDR_OPTION = 1 -> indirect address sourced from IADDR port.)
set iaddr_opt i + 2
if IADDR_OPTION == iaddr_opt
if APB_DWIDTH == 8
set atmp i * slot_incr + 0x0
write b base atmp 0xdd
set atmp i * slot_incr + 0x4
write b base atmp 0xcc
set atmp i * slot_incr + 0x8
write b base atmp 0xbb
set atmp i * slot_incr + 0xc
write b base atmp 0xaa
set atmp i * slot_incr + 0x0
readcheck b base atmp 0xdd
set atmp i * slot_incr + 0x4
readcheck b base atmp 0xcc
set atmp i * slot_incr + 0x8
readcheck b base atmp 0xbb
set atmp i * slot_incr + 0xc
readcheck b base atmp 0xaa
endif
if APB_DWIDTH == 16
set atmp i * slot_incr + 0x0
write h base atmp 0xccdd
set atmp i * slot_incr + 0x4
write h base atmp 0xaabb
set atmp i * slot_incr + 0x0
readcheck h base atmp 0xccdd
set atmp i * slot_incr + 0x4
readcheck h base atmp 0xaabb
endif
if APB_DWIDTH == 32
set atmp i * slot_incr + 0x0
write w base atmp 0xaabbccdd
set atmp i * slot_incr + 0x0
readcheck w base atmp 0xaabbccdd
endif
else
# Clear write indication bits for all slaves
iowrite 0x0001ffff
iowrite 0x00000000
# Check that bits are clear
iomask 0x00000000 0x0001ffff
if slot_combine[i]
set atmp i * slot_incr + 0x0
write w base atmp 0xa5a5a5a5
readcheck w base atmp 0xa5a5a5a5
# Check that an access to slave 16 (combined slave) has occurred
iotstbit 16 1
# Clear slave access indication bit
iosetbit 16
ioclrbit 16
iotstbit 16 0
# Check that all indication bits are now zero
iomask 0x00000000 0x0001ffff
else
if slot_enable[i]
set atmp i * slot_incr + 0x0
write w base atmp 0x12345678
readcheck w base atmp 0x12345678
# Check that an access to slave i has occurred
iotstbit i 1
# Clear slave access indication bit
iosetbit i
ioclrbit i
iotstbit i 0
# Check that all indication bits are now zero
iomask 0x00000000 0x0001ffff
endif
endif
endif
endloop
return
//-------------------------------------------------------------------------
// Initialize local variables from the ARGVALUE* BFM parameters passed
// down from the testbench HDL.
//-------------------------------------------------------------------------
procedure init_parameter_vars
set APB_DWIDTH $ARGVALUE0
set IADDR_OPTION $ARGVALUE1
set APBSLOT0ENABLE $ARGVALUE2
set APBSLOT1ENABLE $ARGVALUE3
set APBSLOT2ENABLE $ARGVALUE4
set APBSLOT3ENABLE $ARGVALUE5
set APBSLOT4ENABLE $ARGVALUE6
set APBSLOT5ENABLE $ARGVALUE7
set APBSLOT6ENABLE $ARGVALUE8
set APBSLOT7ENABLE $ARGVALUE9
set APBSLOT8ENABLE $ARGVALUE10
set APBSLOT9ENABLE $ARGVALUE11
set APBSLOT10ENABLE $ARGVALUE12
set APBSLOT11ENABLE $ARGVALUE13
set APBSLOT12ENABLE $ARGVALUE14
set APBSLOT13ENABLE $ARGVALUE15
set APBSLOT14ENABLE $ARGVALUE16
set APBSLOT15ENABLE $ARGVALUE17
set MADDR_BITS $ARGVALUE18
set UPR_NIBBLE_POSN $ARGVALUE19
set SC_0 $ARGVALUE20
set SC_1 $ARGVALUE21
set SC_2 $ARGVALUE22
set SC_3 $ARGVALUE23
set SC_4 $ARGVALUE24
set SC_5 $ARGVALUE25
set SC_6 $ARGVALUE26
set SC_7 $ARGVALUE27
set SC_8 $ARGVALUE28
set SC_9 $ARGVALUE29
set SC_10 $ARGVALUE30
set SC_11 $ARGVALUE31
set SC_12 $ARGVALUE32
set SC_13 $ARGVALUE33
set SC_14 $ARGVALUE34
set SC_15 $ARGVALUE35
return

19
simulation/coreparameters.v Normal file
View File

@@ -0,0 +1,19 @@
//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:11 2026
// Parameters for CORETSE
//--------------------------------------------------------------------
parameter ECC_ENABLE = 0;
parameter FAMILY = 26;
parameter GMII_TBI = 1;
parameter HDL_license = "E";
parameter HOST_INTERFACE = 0;
parameter MDIO_PHYID = 18;
parameter PACKET_SIZE = 11;
parameter SAL = 1;
parameter SLIP_ENABLE = 0;
parameter STATS = 1;
parameter testbench = "User";
parameter TXRX_INTR_ENABLE = 1;
parameter WoL = 1;

100
simulation/coreuart_usertb_apb_master.bfm Normal file
View File

@@ -0,0 +1,100 @@
// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: Verification testbench APB master BFM script for CoreAI
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4"
// 2. Most of the behavior is driven from the BFM script for the APB master.
// Consult the Actel AMBA BFM documentation for more information.
// 3. All procedures, variables, and constants used by the 'main' procedure
// are declared in the include file "coreai_veriftb_include.bfm"
//
// History: 11/05/08 - TFB created
//
// *********************************************************************
// include constants, and miscellaneous procedures used in this main file
include "coreuart_usertb_include.bfm"
procedure main
header "User Testbench for CoreUART: BFM APB Master Test Harness"
print "(c) Copyright 2009 Actel Corporation. All rights reserved."
print "AS: 03/23/09"
call pr_underscores
debug 1 // only text strings printed
//timeout 2000000 // timeout in cycles, in case BFM stalls
//wait 1
call init_parameter_vars
wait 1
// framing error test
ifnot FIXEDMODE
call set_config 0 0 0 5 1
call set_config 1 0 0 5 1
call framing_err_test
endif
// overflow test
call overflow_test
ifnot FIXEDMODE
// TEST FOR ALL CONFIGURATIONS (matching b/w DUTs)
// configure UART1 and 2 to the same config
print "FIXEDMODE=0: testing for all configurations"
call pr_underscores
loop x 0 1 1 // parity_en
loop y 0 1 1 // parity
loop z 0 1 1 // bit_num
call set_config 0 x y 1 z
call set_config 1 x y 1 z
call data_stream
call set_config 0 x y 3 z
call set_config 1 x y 3 z
call data_stream
endloop
endloop
endloop
endif
if FIXEDMODE
// TEST FOR ONE CONFIGURATION (FIXED)
print "FIXEDMODE=1: testing for current configuration only (as follows)"
print "BAUD_VALUE:%0d" BAUD_VALUE
print "PRG_BIT8:%0d" PRG_BIT8
print "PRG_PARITY:%0d" PRG_PARITY
call data_stream
endif
// parity error test
ifnot FIXEDMODE
call parity_err_test
endif
call pr_underscores
// enable
print "End of CoreUART User testbench."
return

468
simulation/coreuart_usertb_include.bfm Normal file
View File

@@ -0,0 +1,468 @@
// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation All rights reserved
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING
//
// Description: User testbench include file for CoreAI - contains
// various constants procedures etc used by main BFM script
//
// Revision Information:
// Date Description
// 19Jan09 Production Release Version 3 0
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1 best viewed with tabstops set to "4"
//
// History:
//
// *********************************************************************
// PSEL[0] HSEL[0] used to access the AHB-to-APB bridge in the BFM_APB mod
// (for UART Transmitter)
memmap BASE1 0x10000000
// PSEL[1] HSEL[1] used to access the AHB-to-APB bridge in the BFM_APB mod
// (for UART Receiver)
memmap BASE2 0x11000000
// variables to store passed parameter values
int FAMILY
int TX_FIFO
int RX_FIFO
int FIXEDMODE
int BAUD_VALUE
int PRG_BIT8
int PRG_PARITY
int RX_LEGACY_MODE
int USE_SOFT_FIFO
// derived parameters
int FIFO_DEPTH
int TIMEOUT_VAL
int BYTE_WAIT_TIME
int BYTE_WAIT_256
int BYTE_WAIT_16
int BYTE_WAIT_8
// data variables
int rdata[256]
// other variables
int PRINT_VARS
int BITVAR
int data
// temp vars
int i j k l w x y z tc rc
int cmp
// CoreGPIO internal addresses
constant TXDATA 0x00
constant RXDATA 0x04
constant CTRL1 0x08
constant CTRL2 0x0C
constant STA 0x10
constant CRTL3 0x14
//BFM GPIN bit defs
constant RXRDY1 0
constant TXRDY1 1
constant PARITY_ERR1 2
constant OVERFLOW1 3
constant RXRDY2 4
constant TXRDY2 5
constant PARITY_ERR2 6
constant OVERFLOW2 7
//---------------------------------------------------------------------------
// procedures
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// initialize local variables from the ARGVALUE* BFM parameters passed
// down from the testbench HDL
//---------------------------------------------------------------------------
procedure init_parameter_vars
set FAMILY $ARGVALUE0
set TX_FIFO $ARGVALUE1
set RX_FIFO $ARGVALUE2
set FIXEDMODE $ARGVALUE3
set BAUD_VALUE $ARGVALUE4
set PRG_BIT8 $ARGVALUE5
set PRG_PARITY $ARGVALUE6
set RX_LEGACY_MODE $ARGVALUE7
set USE_SOFT_FIFO $ARGVALUE8
// derived parameters
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 255
endif
// check for SX or RTSX or RTAXS
// and set FIFO depth accordingly
// (these 3 have soft FIFOs)
set cmp FAMILY == 8
if cmp
set FIFO_DEPTH 15
endif
set cmp FAMILY == 9
if cmp
set FIFO_DEPTH 15
endif
// set cmp FAMILY == 12
// if cmp
// set FIFO_DEPTH 15
// endif
//check for SmartFusion2 or Igloo2 or RTG4
//and set FIFO depth accordingly
set cmp FAMILY == 19
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
set cmp FAMILY == 24
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
set cmp FAMILY == 25
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
//check for PolarFire
//and set FIFO depth accordingly
set cmp FAMILY == 26
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 255
endif
endif
//check for ProASICplus
//and set FIFO depth accordingly
set cmp FAMILY == 14
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 254
endif
endif
set BYTE_WAIT_TIME BAUD_VALUE * 250
set BYTE_WAIT_256 BYTE_WAIT_TIME * 256
set BYTE_WAIT_16 BYTE_WAIT_TIME * 16
set BYTE_WAIT_8 BYTE_WAIT_TIME * 8
set TIMEOUT_VAL BYTE_WAIT_256 + 1
timeout TIMEOUT_VAL
set PRINT_VARS 1
if PRINT_VARS
header " Begin printing variables from APB Master BFM Script ..."
print "FAMILY:%0d" FAMILY
print "TX_FIFO:%0d" TX_FIFO
print "RX_FIFO:%0d" RX_FIFO
print "FIXEDMODE:%0d" FIXEDMODE
print "BAUD_VALUE:%0d" BAUD_VALUE
print "PRG_BIT8:%0d" PRG_BIT8
print "PRG_PARITY:%0d" PRG_PARITY
print "RX_LEGACY_MODE:%0d" RX_LEGACY_MODE
print "FIFO_DEPTH:%0d" FIFO_DEPTH
header " Done printing variables from APB Master BFM Script."
header " "
endif
return
//---------------------------------------------------------------------------
// get bit number (bnum) from given wval integer
//---------------------------------------------------------------------------
procedure get_bit wval bnum
int d01
set d01 wval >> bnum
// set global BITVAR variable
set BITVAR d01 & 0x1
return
//---------------------------------------------------------------------------
// print line of underscores
//---------------------------------------------------------------------------
procedure pr_underscores
print "____________________________________________________________________"
print " "
return
//---------------------------------------------------------------------------
// test procedures
//---------------------------------------------------------------------------
procedure set_config dn pe p bv bn
int dut_num // 1 = RX(DUT2), 0 = TX(DUT1)
int par_en // 1 = enabled, 0 = disabled
int par // 1 = odd, 0 = even
int baud_val // 13-bit baud-value (split into 2 config registers)
int bit_num // 1 = 8 bits, 0 = 7 bits
// temp vars
int baud1
int baud2
int ctrl2_val
set dut_num dn
set par_en pe
set par p
set baud_val bv
set bit_num bn
print "Configuring UART:%0d with par_en:%0d parity:%0d baud_val:%0d bit_num:%0d" dut_num par_en par baud_val bit_num
// Set config regsiter data
set baud1 baud_val << 8 >> 8 // CONFIG REG 1
set baud2 baud_val >> 8 // CONFIG REG 2
set par par << 2
set par_en par_en << 1
set baud2 baud2 << 3
set ctrl2_val par
set ctrl2_val ctrl2_val | par_en
set ctrl2_val ctrl2_val | baud2
set ctrl2_val ctrl2_val | bit_num
// set base address based on DUT selected
if dut_num == 1
// write control registers
//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
write b BASE2 CTRL1 baud1
write b BASE2 CTRL2 ctrl2_val
else
// write control registers
//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
write b BASE1 CTRL1 baud1
write b BASE1 CTRL2 ctrl2_val
endif
return
procedure data_stream
call pr_underscores
print "Testing Continuous Data Stream UART1 to UART2"
set rc 0
loop tc 0 FIFO_DEPTH 1
//print "Sending byte %0d" tc
iowaitbit TXRDY1 1 // wait until TXRDY
set data tc & 0x7F // mask byte
//print "Got TXRDY %0d times" tc
write b BASE1 TXDATA data // transmit a byte
ifnot TX_FIFO
iowaitbit TXRDY1 0 // wait until TXRDY deasserted
endif
ifnot RX_FIFO // must read immediately
iowaitbit RXRDY2 1 // wait until RXRDY
//print "Receiving byte %0d" tc
readstore b BASE2 RXDATA rdata[rc] // read received byte
set rc rc + 1
endif
endloop
if RX_FIFO // test out FIFO operation
wait BYTE_WAIT_16 // wait for data to be received
loop rc 0 FIFO_DEPTH 1
iowaitbit RXRDY2 1 // wait until RXRDY
readstore b BASE2 RXDATA rdata[rc] // read received byte
endloop
endif
// check data
loop i 0 FIFO_DEPTH 1
set j i & 0x7F
if rdata[i] != j
call pr_underscores
print "TEST FAILED"
print "Expected %0d, got %0d" i rdata[i]
setfail
endif
endloop
print "Continuous data stream successfull"
call pr_underscores
return
procedure framing_err_test
call pr_underscores
print "Performing framing error test by setting input to DUT2 low"
// set the input to UART2 RX line low
// (no stop bit)
iowrite 0x01
wait BYTE_WAIT_16
ifnot RX_FIFO
// back to normal:
iowrite 0x00
wait BYTE_WAIT_16
readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
read b BASE2 RXDATA // doing a read should clear this
readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
else
readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
iowrite 0x00
// transmit a byte to clear the framing error
iowaitbit TXRDY1 1 // wait until TXRDY
write b BASE1 TXDATA 0xAA
wait BYTE_WAIT_16
readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
//loop i 0 FIFO_DEPTH 1 // probably caused an overflow,
readstore b BASE2 STA x // read status
set x x & 0x02
set cmp x == 2
while cmp
iowaitbit RXRDY2 1 // wait until RXRDY
read b BASE2 RXDATA // need to clear
iowaitbit RXRDY2 0 // wait until RXRDY clear
wait 4
readstore b BASE2 STA x // read status
set x x & 0x02
set cmp x == 2
endwhile
endif
wait 10
print "Framing error test completed"
call pr_underscores
return
procedure overflow_test
call pr_underscores
print "Overflow test"
if RX_FIFO
loop tc 0 FIFO_DEPTH 1
iowaitbit TXRDY1 1 // wait until TXRDY
set data tc & 0x7F // mask byte
write b BASE1 TXDATA data // transmit a byte
ifnot TX_FIFO
iowaitbit TXRDY1 0 // wait until TXRDY deasserted
endif
endloop
iowaitbit TXRDY1 1 // wait until TXRDY
wait BYTE_WAIT_256
iotstbit OVERFLOW2 0 // check that overflow not set
write b BASE1 TXDATA 0xab // transmit a byte (0xab)
wait BYTE_WAIT_256 // worst case: 3 blocks (BAUD_VAL=1)
wait BYTE_WAIT_256
wait BYTE_WAIT_256
iotstbit OVERFLOW2 1 // check that overflow set
// read RX data
loop rc 0 FIFO_DEPTH 1
if rc == 1
iotstbit OVERFLOW2 0 // check
endif
iowaitbit RXRDY2 1 // wait until RXRDY
readstore b BASE2 RXDATA rdata[rc] // read received byte
endloop
// check data
loop i 0 FIFO_DEPTH 1
set j i & 0x7F
if rdata[i] != j
call pr_underscores
print "TEST FAILED"
print "Expected %0d, got %0d" i rdata[i]
setfail
endif
endloop
endif
call pr_underscores
return
procedure parity_err_test
call pr_underscores
print "Performing Parity Error Test"
call set_config 0 1 0 1 1
call set_config 1 1 1 1 1
// -- transmit a byte --
iotstbit PARITY_ERR2 0 // check that parity error is 0
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xab // transmit a byte (0xab)
iowaitbit PARITY_ERR2 1 // check that parity error asserted
if RX_FIFO
iowaitbit PARITY_ERR2 0 // check that parity error deasserted
call set_config 0 1 1 1 1 // match parity
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xac // transmit a new byte (0xab)
iowaitbit RXRDY2 1 // read byte
iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
readstore b BASE2 RXDATA x // store
if x != 0xac
call pr_underscores
print "TEST FAILED"
print "Expected 0xac, got %0h" x
setfail
endif
else
// NO RX_FIFO
// clear parity error
read b BASE2 RXDATA // read should clear
wait 4
iotstbit PARITY_ERR2 0 // the parity error
call set_config 0 1 1 1 1 // match parity
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xac // transmit a new byte (0xab)
iowaitbit RXRDY2 1 // read byte
iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
readstore b BASE2 RXDATA x // store
if x != 0xac
call pr_underscores
print "TEST FAILED"
print "Expected 0xac, got %0h" x
setfail
endif
endif
print "Parity Error Test Complete"
call pr_underscores
return

10
simulation/modelsim.ini Normal file
View File

@@ -0,0 +1,10 @@
[Library]
others = $MODEL_TECH/../modelsim.ini
PolarFire = E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
syncad_vhdl_lib = E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000

10
simulation/modelsim.ini.sav Normal file
View File

@@ -0,0 +1,10 @@
[Library]
others = $MODEL_TECH/../modelsim.ini
PolarFire = E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
syncad_vhdl_lib = E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000

241
simulation/user_tb.bfm Normal file
View File

@@ -0,0 +1,241 @@
memmap master 0x10000000
memmap slave 0x11000000
constant R_control 0x00
constant R_intclear 0x04
constant R_rxdata 0x08
constant R_txdata 0x0C
constant R_intmask 0x10
constant R_intraw 0x10
constant R_control2 0x18
constant R_command 0x1C
constant R_stat 0x20
constant R_ssel 0x24
constant R_txdatal 0x28
constant R_CLK_DIV 0x2C
# R_control bits
constant B_enable 0x00000001
constant B_master 0x00000002
constant B_slave 0x00000000
constant B_intenrxovr 0x00000004
constant B_intentx 0x00000008
constant B_intentxov 0x00000010
constant B_intenrxov 0x00000020
constant B_intenurun 0x00000040
constant B_oenoff 0x00000080
# R_control2 bits
constant B_intencmd 0x00000010
constant B_intentssend 0x00000020
constant B_intendatarx 0x00000040
# R_command bits (write-only)
constant B_rxfiforst 0x00000001
constant B_txfiforst 0x00000002
# R_intclear/raw/mask bits
constant B_txint 0x00000001
constant B_rxovint 0x00000004
constant B_txurint 0x00000008
constant B_cmdint 0x00000010
constant B_ssendint 0x00000020
constant B_datarxint 0x00000040
# R_status
constant B_firstframe 0x00000001
constant B_done 0x00000002
constant B_rxempty 0x00000004
constant B_txfull 0x00000008
constant B_rxoverflow 0x00000010
constant B_txunderrun 0x00000020
constant B_ssel 0x00000040
constant B_active 0x00000080
procedure main
print "CoreSPI User testbench"
debug 0
#setup 7 1 # execute $stop at end
timeout 10000
print "********************************************************************"
print "Test1: Read Initial Register values"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "Test2: Master -> Slave : 4 Byte transfer"
print "********************************************************************"
call test_slave_rx
wait 100
print "********************************************************************"
print "Test3: Check Master TX_DONE & slave DATA_RX interrupt operation"
print "********************************************************************"
call test_interrupt_operation
print "********************************************************************"
print "Test4: Read Register values after the transfer"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "CoreSPI user testbench completed"
print "********************************************************************"
return
procedure read_reg
int i x
## Read contents of APB register block
print "CoreSPI master registers"
loop i 0x00 0x2C 4
readstore b master i x
print "Read from %08x: %08x" i x
endloop
print "CoreSPI slave registers"
loop i 0x00 0x2C 4
readstore b slave i x
print "Read from %08x: %08x" i x
endloop
return
procedure test_slave_rx
int i x
## 4 Byte transfer to test master->slave transfer
print "Enable the slave"
write w slave R_control (B_slave | B_enable)
print "Set slave up with TX data"
loop i 0x5 0x8 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
print "Configure master to Tx to slave 0"
write w master R_ssel 1
write w master R_control (B_master | B_enable)
print "Set master up with TX data"
loop i 0x01 0x03 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x04) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x04
#write b master R_CLK_DIV 0x04
#print "********************************************************************************"
#print "Dynamically configuring the clock division factor of master generated SPI clock"
#print "********************************************************************************"
## Wait for the transfer to complete
wait 1500
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
loop i 0x01 0x04 1
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0x5 0x8 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return
procedure test_interrupt_operation
int i x
print "Set slave up with TX data"
loop i 0x0A 0x0D 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
## Enable slave DATA_RX interrupt
print "Clear any pending DATA_TX raw interrupts before enabling the DATA_RX interrupt"
write b slave R_intclear 0x40
wait 100
print "Enable slave DATA_RX interrupt"
write b slave R_control2 B_intendatarx
## Enable master TX_DONE interrupt
print "Clear any pending TX_DONE raw interrupts before enabling the TX_DONE interrupt"
write b master R_intclear 0x01
wait 100
print "Enable master TX_DONE interrupt"
write w master R_control (B_master | B_enable | B_intentx)
## Load master with tx data
print "Set master up with TX data"
loop i 0x04 0x06 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x07) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x07
wait 1500
print "************************************"
print "Check master SPIINT interrupt asserted"
print "************************************"
## Check master interrupt
iotstbit 0 1
readstore b master R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "Clear master TX_DONE interrupt & check SPIINT de-asserts"
## Clear interrupt
write b master R_intclear 0x01
wait 100
## Check clear
iotstbit 0 0
print "************************************"
print "Check slave SPIINT interrupt asserted"
print "************************************"
## Check slave interrupt
iotstbit 1 1
readstore b slave R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
## Check slave
loop i 0x04 0x07
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "Wait until data is removed from the RX_FIFO"
wait 20
print "Clear slave DATA_RX interrupt and check SPIINT de-asserts"
write b slave R_intclear 0x40
wait 100
## Check clear
iotstbit 1 0
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0xA 0xD 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return