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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
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designer/top/top_delayinstance.rpt Normal file
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********************************************************************
Delay Instance Report - Date: Wed Apr 15 23:06:11 2026
Product: Designer
Release: 2025.1
Version: 2025.1.0.14
Design Name: top
Family: PolarFire
Die: MPF300TS
Package: FCG1152
********************************************************************
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+
| Type | Instance Name | Param Name | Delay Value | PDC Option Name | Editable? |
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+
| LANECTRL | PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL | RX_DQS_DELAY_VAL | 16 | RX_DQS_DELAY | No |
| LANECTRL | PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL | TX_DQS_DELAY_VAL | 1 | TX_DQS_DELAY | Yes |
| LANECTRL | PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL | RX_DQS_DELAY_VAL | 9 | RX_DQS_DELAY | No |
| LANECTRL | PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL | TX_DQS_DELAY_VAL | 1 | TX_DQS_DELAY | No |
| PLL_DELAY | PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0_DELAY | CDELAY0_SEL | 0 | DELAY | No |
| PLL_DELAY | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_DELAY | CDELAY0_SEL | 0 | DELAY | No |
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+