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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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40
designer/top/top_RAM.cfg Normal file
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set_client \
-logical_instance_name {COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0]} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}
set_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0]} \
-storage_type {SNVM} \
-content_type {INFERRED_INITIALIZED}
set_client \
-logical_instance_name {PF_TPSRAM_C0_0/PF_TPSRAM_C0_0} \
-storage_type {SNVM} \
-content_type {NO_CONTENT}