working FIFO and TPSRAM without packet flter

designer/top/top.mvn.pdc

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+# Microchip Physical design constraints file
+
+# Version: 2025.1 2025.1.0.14
+
+# Design Name:  
+
+# Input Netlist Format: EDIF 
+
+# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1 
+
+# Date generated: Wed Apr 15 22:52:34 2026 
+
+
+#
+# IO banks setting
+#
+
+set_iobank -bank_name Bank3 -vcci 3.30 -fixed true
+
+#
+# Region constraints
+#
+
+
+#
+# I/O constraints
+#
+
+set_io -port_name TCK -DIRECTION INPUT -pin_name J10
+set_io -port_name TDI -DIRECTION INPUT -pin_name K11
+set_io -port_name TDO -DIRECTION OUTPUT -pin_name K9
+set_io -port_name TMS -DIRECTION INPUT -pin_name J9
+set_io -port_name TRSTB -DIRECTION INPUT -pin_name N14
+
+#
+# Ports using Dedicated Pins
+#
+
+set_io -port_name TCK  \
+    -pin_name J10      \
+    -DIRECTION INPUT
+set_io -port_name TDI  \
+    -pin_name K11      \
+    -DIRECTION INPUT
+set_io -port_name TDO  \
+    -pin_name K9       \
+    -DIRECTION OUTPUT
+set_io -port_name TMS  \
+    -pin_name J9       \
+    -DIRECTION INPUT
+set_io -port_name TRSTB  \
+    -pin_name N14        \
+    -DIRECTION INPUT
+
+#
+# Core cell constraints
+#
+