working FIFO and TPSRAM without packet flter

This commit is contained in:
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions

12
designer/top/RAM.cfg Normal file
View File

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modified_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0} \
-storage_type {SNVM} \
-content_type {MEMORY_FILE} \
-memory_file_format {Intel-Hex} \
-memory_file {iog_cdr.hex}
modified_client \
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0} \
-storage_type {SNVM} \
-content_type {MEMORY_FILE} \
-memory_file_format {Intel-Hex} \
-memory_file {iog_cdr.hex}