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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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component/work/top/top_DRC.xml Normal file
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<?xml version="1.0" encoding="ISO-8859-1" ?>
<?xml-stylesheet type="text/xsl" href="drcss.xsl"?>
<drcreport>
<header>top</header>
<drc>
<status>E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/data/drcreport\warn.png</status>
<StatusMessage>Warning</StatusMessage>
<message> bus interface data width mismatch</message>
<detail> There is a data width mismatch between CoreAPB3_0_0:APBmslave1:PWDATAS[0-31] and CoreUARTapb_0:APB_bif:PWDATA[0-7] which may result in a loss of data.</detail>
<crossprobe>liberoaction://cross_probe/smartdesign/top/pins/CoreAPB3_0_0:APBmslave1</crossprobe>
</drc>
</drcreport>