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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./PF_TPSRAM_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./PF_TPSRAM_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/SgCore/PF_TPSRAM/1.1.108/PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./PF_TPSRAM_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="SgCore" name="PF_TPSRAM" vendor="Actel" version="1.1.108"/><configuration><configurableElement referenceId="A_DOUT_EN_PN" value="R_DATA_EN"/><configurableElement referenceId="A_DOUT_EN_POLARITY" value="2"/><configurableElement referenceId="A_DOUT_SRST_PN" value="R_DATA_SRST_N"/><configurableElement referenceId="A_DOUT_SRST_POLARITY" value="2"/><configurableElement referenceId="A_WBYTE_EN_PN" value="WBYTE_EN"/><configurableElement referenceId="BUSY_FLAG" value="0"/><configurableElement referenceId="BYTE_ENABLE_WIDTH" value="0"/><configurableElement referenceId="BYTEENABLES" value="0"/><configurableElement referenceId="CASCADE" value="0"/><configurableElement referenceId="CLK_EDGE" value="RISE"/><configurableElement referenceId="CLKS" value="1"/><configurableElement referenceId="CLOCK_PN" value="CLK"/><configurableElement referenceId="DATA_IN_PN" value="W_DATA"/><configurableElement referenceId="DATA_OUT_PN" value="R_DATA"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="IMPORT_FILE" value=""/><configurableElement referenceId="INIT_RAM" value="F"/><configurableElement referenceId="LPM_HINT" value="0"/><configurableElement referenceId="LPMTYPE" value="LPM_RAM"/><configurableElement referenceId="PMODE2" value="0"/><configurableElement referenceId="PTYPE" value="1"/><configurableElement referenceId="RADDRESS_PN" value="R_ADDR"/><configurableElement referenceId="RCLK_EDGE" value="RISE"/><configurableElement referenceId="RCLOCK_PN" value="R_CLK"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_PN" value="R_EN"/><configurableElement referenceId="RE_POLARITY" value="2"/><configurableElement referenceId="RESET_PN" value="R_DATA_ARST_N"/><configurableElement referenceId="RESET_POLARITY" value="2"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SD_EXPORT_HIDDEN_PORTS" value="false"/><configurableElement referenceId="SII_LOCK" value="0"/><configurableElement referenceId="WADDRESS_PN" value="W_ADDR"/><configurableElement referenceId="WCLK_EDGE" value="RISE"/><configurableElement referenceId="WCLOCK_PN" value="W_CLK"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_PN" value="W_EN"/><configurableElement referenceId="WE_POLARITY" value="1"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>W_EN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_DATA</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.sdb Normal file
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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:42:58 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of PF_TPSRAM_C0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_TPSRAM_C0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_TPSRAM:1.1.108} -component_name {PF_TPSRAM_C0} -params {\
"A_DOUT_EN_PN:R_DATA_EN" \
"A_DOUT_EN_POLARITY:2" \
"A_DOUT_SRST_PN:R_DATA_SRST_N" \
"A_DOUT_SRST_POLARITY:2" \
"A_WBYTE_EN_PN:WBYTE_EN" \
"BUSY_FLAG:0" \
"BYTE_ENABLE_WIDTH:0" \
"BYTEENABLES:0" \
"CASCADE:0" \
"CLK_EDGE:RISE" \
"CLKS:1" \
"CLOCK_PN:CLK" \
"DATA_IN_PN:W_DATA" \
"DATA_OUT_PN:R_DATA" \
"ECC:0" \
"IMPORT_FILE:" \
"INIT_RAM:F" \
"LPM_HINT:0" \
"LPMTYPE:LPM_RAM" \
"PMODE2:0" \
"PTYPE:1" \
"RADDRESS_PN:R_ADDR" \
"RCLK_EDGE:RISE" \
"RCLOCK_PN:R_CLK" \
"RDEPTH:1024" \
"RE_PN:R_EN" \
"RE_POLARITY:2" \
"RESET_PN:R_DATA_ARST_N" \
"RESET_POLARITY:2" \
"RWIDTH:32" \
"SII_LOCK:0" \
"WADDRESS_PN:W_ADDR" \
"WCLK_EDGE:RISE" \
"WCLOCK_PN:W_CLK" \
"WDEPTH:1024" \
"WE_PN:W_EN" \
"WE_POLARITY:1" \
"WWIDTH:32" }
# Exporting Component Description of PF_TPSRAM_C0 to TCL done
*/
// PF_TPSRAM_C0
module PF_TPSRAM_C0(
// Inputs
CLK,
R_ADDR,
W_ADDR,
W_DATA,
W_EN,
// Outputs
R_DATA
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input CLK;
input [9:0] R_ADDR;
input [9:0] W_ADDR;
input [31:0] W_DATA;
input W_EN;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] R_DATA;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire CLK;
wire [9:0] R_ADDR;
wire [31:0] R_DATA_net_0;
wire [9:0] W_ADDR;
wire [31:0] W_DATA;
wire W_EN;
wire [31:0] R_DATA_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign R_DATA_net_1 = R_DATA_net_0;
assign R_DATA[31:0] = R_DATA_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM - Actel:SgCore:PF_TPSRAM:1.1.108
PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM PF_TPSRAM_C0_0(
// Inputs
.W_EN ( W_EN ),
.CLK ( CLK ),
.W_DATA ( W_DATA ),
.W_ADDR ( W_ADDR ),
.R_ADDR ( R_ADDR ),
// Outputs
.R_DATA ( R_DATA_net_0 )
);
endmodule

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
<view>
<name>SIMULATION</name>
<fileSetRef>ANY_SIMULATION_FILESET</fileSetRef>
</view>
<view>
<name>OTHER</name>
<fileSetRef>OTHER_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
<fileSet fileSetId="ANY_SIMULATION_FILESET">
</fileSet>
<fileSet fileSetId="OTHER_FILESET">
</fileSet>
</fileSets>
</component>

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.log Normal file
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****************
Macro Parameters
****************
Name : PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM
Family : PolarFire
Output Format : VERILOG
Type : RAM
Write Block Enable Polarity : Active High
Read Block Enable Polarity : None
A_DOUT Enable Polarity : None
B_DOUT Enable Polarity : None
A_DOUT Sync-reset Polarity : None
B_DOUT Sync-reset Polarity : None
A_DOUT Async-reset Polarity : None
B_DOUT Async-reset Polarity : None
Reset Polarity : None
Read Clock Edge : Rising
Write Clock Edge : Rising
A_REN Polarity : None
B_REN Polarity : None
Write Depth : 1024
Write Width : 32
Read Depth : 1024
Read Width : 32
Portname DataIn : W_DATA
Portname DataOut : R_DATA
Portname WClock : W_CLK
Portname RClock : R_CLK
Portname WAddress : W_ADDR
Portname RAddress : R_ADDR
Portname Single Clock : CLK
Portname Single Async-reset : R_DATA_ARST_N
Portname DataAIn :
Portname DataBIn :
Portname DataAOut :
Portname DataBOut :
Portname AddressA :
Portname AddressB :
Portname CLKA :
Portname CLKB :
Portname RWA :
Portname RWB :
Portname BLKA :
Portname BLKB :
Portname A_DOUT_EN : R_DATA_EN
Portname B_DOUT_EN :
Portname A_DOUT_SRST_N : R_DATA_SRST_N
Portname B_DOUT_SRST_N :
Portname A_DOUT_ARST_N :
Portname B_DOUT_ARST_N :
Portname Write Enable : W_EN
Portname Read Enable : R_EN
Portname A_WBYTE_EN : WBYTE_EN
Portname B_WBYTE_EN :
Portname A_REN :
Portname B_REN :
LPM_HINT : 0
Device : 300
RAM Type : Two Port
Optimized for : Speed
Initialize RAM : False
Clocks : Single Read/Write Clock
Byte Enables : No
Read Pipeline A : No
Read Pipeline B : No
Write Mode A : Hold Data
Write Mode B : Hold Data
ECC Type : Disabled
Lock access : Off
ACCESS_BUSY : Disabled
Cascade Configuration:
Write Port configuration : 1024x20
Read Port configuration : 1024x20
Number of blocks depth wise: 1
Number of blocks width wise: 2
Wrote Verilog netlist to E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v.

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM(
W_DATA,
R_DATA,
W_ADDR,
R_ADDR,
W_EN,
CLK
);
input [31:0] W_DATA;
output [31:0] R_DATA;
input [9:0] W_ADDR;
input [9:0] R_ADDR;
input W_EN;
input CLK;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
wire GND_power_net1;
wire VCC_power_net1;
assign GND = GND_power_net1;
assign VCC = VCC_power_net1;
assign ADLIB_VCC = VCC_power_net1;
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 (.A_DOUT({nc0,
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 (.A_DOUT({nc24,
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
GND GND_power_inst1 (.Y(GND_power_net1));
VCC VCC_power_inst1 (.Y(VCC_power_net1));
endmodule

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/core.gen Normal file
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BATCH:T
MGNCMPL:F
MGNTIMER:F
GEN_BEHV_MODULE:F
DESDIR:E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\
DESIGN:PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM
OUTFORMAT:Verilog
A_DOUT_EN_PN:R_DATA_EN
A_DOUT_EN_POLARITY:2
A_DOUT_SRST_PN:R_DATA_SRST_N
A_DOUT_SRST_POLARITY:2
A_WBYTE_EN_PN:WBYTE_EN
BUSY_FLAG:0
BYTEENABLES:0
BYTE_ENABLE_WIDTH:0
CASCADE:0
CLKS:1
CLK_EDGE:RISE
CLOCK_PN:CLK
DATA_IN_PN:W_DATA
DATA_OUT_PN:R_DATA
ECC:0
FAM:PolarFire
IMPORT_FILE:
INIT_RAM:F
LPMTYPE:LPM_RAM
LPM_HINT:0
PMODE2:0
PTYPE:1
RADDRESS_PN:R_ADDR
RCLK_EDGE:RISE
RCLOCK_PN:R_CLK
RDEPTH:1024
RESET_PN:R_DATA_ARST_N
RESET_POLARITY:2
RE_PN:R_EN
RE_POLARITY:2
RWIDTH:32
SD_EXPORT_HIDDEN_PORTS:false
SII_LOCK:0
WADDRESS_PN:W_ADDR
WCLK_EDGE:RISE
WCLOCK_PN:W_CLK
WDEPTH:1024
WE_PN:W_EN
WE_POLARITY:1
WWIDTH:32
DEVICE:300

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 22:42:59 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : PF_TPSRAM_C0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v