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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
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component/work/CoreAPB3_0/CoreAPB3_0.cxf Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:03 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CoreAPB3_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CoreAPB3_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_0} -params {\
"APB_DWIDTH:32" \
"APBSLOT0ENABLE:true" \
"APBSLOT1ENABLE:true" \
"APBSLOT2ENABLE:true" \
"APBSLOT3ENABLE:false" \
"APBSLOT4ENABLE:false" \
"APBSLOT5ENABLE:false" \
"APBSLOT6ENABLE:false" \
"APBSLOT7ENABLE:false" \
"APBSLOT8ENABLE:false" \
"APBSLOT9ENABLE:false" \
"APBSLOT10ENABLE:false" \
"APBSLOT11ENABLE:false" \
"APBSLOT12ENABLE:false" \
"APBSLOT13ENABLE:false" \
"APBSLOT14ENABLE:false" \
"APBSLOT15ENABLE:false" \
"IADDR_OPTION:0" \
"MADDR_BITS:16" \
"SC_0:false" \
"SC_1:false" \
"SC_2:false" \
"SC_3:false" \
"SC_4:false" \
"SC_5:false" \
"SC_6:false" \
"SC_7:false" \
"SC_8:false" \
"SC_9:false" \
"SC_10:false" \
"SC_11:false" \
"SC_12:false" \
"SC_13:false" \
"SC_14:false" \
"SC_15:false" \
"UPR_NIBBLE_POSN:6" }
# Exporting Component Description of CoreAPB3_0 to TCL done
*/
// CoreAPB3_0
module CoreAPB3_0(
// Inputs
PADDR,
PENABLE,
PRDATAS0,
PRDATAS1,
PRDATAS2,
PREADYS0,
PREADYS1,
PREADYS2,
PSEL,
PSLVERRS0,
PSLVERRS1,
PSLVERRS2,
PWDATA,
PWRITE,
// Outputs
PADDRS,
PENABLES,
PRDATA,
PREADY,
PSELS0,
PSELS1,
PSELS2,
PSLVERR,
PWDATAS,
PWRITES
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [31:0] PADDR;
input PENABLE;
input [31:0] PRDATAS0;
input [31:0] PRDATAS1;
input [31:0] PRDATAS2;
input PREADYS0;
input PREADYS1;
input PREADYS2;
input PSEL;
input PSLVERRS0;
input PSLVERRS1;
input PSLVERRS2;
input [31:0] PWDATA;
input PWRITE;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] PADDRS;
output PENABLES;
output [31:0] PRDATA;
output PREADY;
output PSELS0;
output PSELS1;
output PSELS2;
output PSLVERR;
output [31:0] PWDATAS;
output PWRITES;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [31:0] PADDR;
wire PENABLE;
wire [31:0] APB3mmaster_PRDATA;
wire APB3mmaster_PREADY;
wire PSEL;
wire APB3mmaster_PSLVERR;
wire [31:0] PWDATA;
wire PWRITE;
wire [31:0] APBmslave0_PADDR;
wire APBmslave0_PENABLE;
wire [31:0] PRDATAS0;
wire PREADYS0;
wire APBmslave0_PSELx;
wire PSLVERRS0;
wire [31:0] APBmslave0_PWDATA;
wire APBmslave0_PWRITE;
wire [31:0] PRDATAS1;
wire PREADYS1;
wire APBmslave1_PSELx;
wire PSLVERRS1;
wire [31:0] PRDATAS2;
wire PREADYS2;
wire APBmslave2_PSELx;
wire PSLVERRS2;
wire [31:0] APB3mmaster_PRDATA_net_0;
wire APB3mmaster_PREADY_net_0;
wire APB3mmaster_PSLVERR_net_0;
wire [31:0] APBmslave0_PADDR_net_0;
wire APBmslave0_PSELx_net_0;
wire APBmslave0_PENABLE_net_0;
wire APBmslave0_PWRITE_net_0;
wire [31:0] APBmslave0_PWDATA_net_0;
wire APBmslave1_PSELx_net_0;
wire APBmslave2_PSELx_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
wire [31:0] IADDR_const_net_0;
wire [31:0] PRDATAS3_const_net_0;
wire [31:0] PRDATAS4_const_net_0;
wire [31:0] PRDATAS5_const_net_0;
wire [31:0] PRDATAS6_const_net_0;
wire [31:0] PRDATAS7_const_net_0;
wire [31:0] PRDATAS8_const_net_0;
wire [31:0] PRDATAS9_const_net_0;
wire [31:0] PRDATAS10_const_net_0;
wire [31:0] PRDATAS11_const_net_0;
wire [31:0] PRDATAS12_const_net_0;
wire [31:0] PRDATAS13_const_net_0;
wire [31:0] PRDATAS14_const_net_0;
wire [31:0] PRDATAS15_const_net_0;
wire [31:0] PRDATAS16_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign IADDR_const_net_0 = 32'h00000000;
assign PRDATAS3_const_net_0 = 32'h00000000;
assign PRDATAS4_const_net_0 = 32'h00000000;
assign PRDATAS5_const_net_0 = 32'h00000000;
assign PRDATAS6_const_net_0 = 32'h00000000;
assign PRDATAS7_const_net_0 = 32'h00000000;
assign PRDATAS8_const_net_0 = 32'h00000000;
assign PRDATAS9_const_net_0 = 32'h00000000;
assign PRDATAS10_const_net_0 = 32'h00000000;
assign PRDATAS11_const_net_0 = 32'h00000000;
assign PRDATAS12_const_net_0 = 32'h00000000;
assign PRDATAS13_const_net_0 = 32'h00000000;
assign PRDATAS14_const_net_0 = 32'h00000000;
assign PRDATAS15_const_net_0 = 32'h00000000;
assign PRDATAS16_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign APB3mmaster_PRDATA_net_0 = APB3mmaster_PRDATA;
assign PRDATA[31:0] = APB3mmaster_PRDATA_net_0;
assign APB3mmaster_PREADY_net_0 = APB3mmaster_PREADY;
assign PREADY = APB3mmaster_PREADY_net_0;
assign APB3mmaster_PSLVERR_net_0 = APB3mmaster_PSLVERR;
assign PSLVERR = APB3mmaster_PSLVERR_net_0;
assign APBmslave0_PADDR_net_0 = APBmslave0_PADDR;
assign PADDRS[31:0] = APBmslave0_PADDR_net_0;
assign APBmslave0_PSELx_net_0 = APBmslave0_PSELx;
assign PSELS0 = APBmslave0_PSELx_net_0;
assign APBmslave0_PENABLE_net_0 = APBmslave0_PENABLE;
assign PENABLES = APBmslave0_PENABLE_net_0;
assign APBmslave0_PWRITE_net_0 = APBmslave0_PWRITE;
assign PWRITES = APBmslave0_PWRITE_net_0;
assign APBmslave0_PWDATA_net_0 = APBmslave0_PWDATA;
assign PWDATAS[31:0] = APBmslave0_PWDATA_net_0;
assign APBmslave1_PSELx_net_0 = APBmslave1_PSELx;
assign PSELS1 = APBmslave1_PSELx_net_0;
assign APBmslave2_PSELx_net_0 = APBmslave2_PSELx;
assign PSELS2 = APBmslave2_PSELx_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CoreAPB3 - Actel:DirectCore:CoreAPB3:4.2.100
CoreAPB3 #(
.APB_DWIDTH ( 32 ),
.APBSLOT0ENABLE ( 1 ),
.APBSLOT1ENABLE ( 1 ),
.APBSLOT2ENABLE ( 1 ),
.APBSLOT3ENABLE ( 0 ),
.APBSLOT4ENABLE ( 0 ),
.APBSLOT5ENABLE ( 0 ),
.APBSLOT6ENABLE ( 0 ),
.APBSLOT7ENABLE ( 0 ),
.APBSLOT8ENABLE ( 0 ),
.APBSLOT9ENABLE ( 0 ),
.APBSLOT10ENABLE ( 0 ),
.APBSLOT11ENABLE ( 0 ),
.APBSLOT12ENABLE ( 0 ),
.APBSLOT13ENABLE ( 0 ),
.APBSLOT14ENABLE ( 0 ),
.APBSLOT15ENABLE ( 0 ),
.FAMILY ( 19 ),
.IADDR_OPTION ( 0 ),
.MADDR_BITS ( 16 ),
.SC_0 ( 0 ),
.SC_1 ( 0 ),
.SC_2 ( 0 ),
.SC_3 ( 0 ),
.SC_4 ( 0 ),
.SC_5 ( 0 ),
.SC_6 ( 0 ),
.SC_7 ( 0 ),
.SC_8 ( 0 ),
.SC_9 ( 0 ),
.SC_10 ( 0 ),
.SC_11 ( 0 ),
.SC_12 ( 0 ),
.SC_13 ( 0 ),
.SC_14 ( 0 ),
.SC_15 ( 0 ),
.UPR_NIBBLE_POSN ( 6 ) )
CoreAPB3_0_0(
// Inputs
.PRESETN ( GND_net ), // tied to 1'b0 from definition
.PCLK ( GND_net ), // tied to 1'b0 from definition
.PADDR ( PADDR ),
.PWRITE ( PWRITE ),
.PENABLE ( PENABLE ),
.PWDATA ( PWDATA ),
.PSEL ( PSEL ),
.PRDATAS0 ( PRDATAS0 ),
.PREADYS0 ( PREADYS0 ),
.PSLVERRS0 ( PSLVERRS0 ),
.PRDATAS1 ( PRDATAS1 ),
.PREADYS1 ( PREADYS1 ),
.PSLVERRS1 ( PSLVERRS1 ),
.PRDATAS2 ( PRDATAS2 ),
.PREADYS2 ( PREADYS2 ),
.PSLVERRS2 ( PSLVERRS2 ),
.PRDATAS3 ( PRDATAS3_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS3 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS3 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS4 ( PRDATAS4_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS4 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS4 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS5 ( PRDATAS5_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS5 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS5 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS6 ( PRDATAS6_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS6 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS6 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS7 ( PRDATAS7_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS7 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS7 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS8 ( PRDATAS8_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS8 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS8 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS9 ( PRDATAS9_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS9 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS9 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS10 ( PRDATAS10_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS10 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS10 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS11 ( PRDATAS11_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS11 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS11 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS12 ( PRDATAS12_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS12 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS12 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS13 ( PRDATAS13_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS13 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS13 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS14 ( PRDATAS14_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS14 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS14 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS15 ( PRDATAS15_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS15 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS15 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS16 ( PRDATAS16_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS16 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS16 ( GND_net ), // tied to 1'b0 from definition
.IADDR ( IADDR_const_net_0 ), // tied to 32'h00000000 from definition
// Outputs
.PRDATA ( APB3mmaster_PRDATA ),
.PREADY ( APB3mmaster_PREADY ),
.PSLVERR ( APB3mmaster_PSLVERR ),
.PADDRS ( APBmslave0_PADDR ),
.PWRITES ( APBmslave0_PWRITE ),
.PENABLES ( APBmslave0_PENABLE ),
.PWDATAS ( APBmslave0_PWDATA ),
.PSELS0 ( APBmslave0_PSELx ),
.PSELS1 ( APBmslave1_PSELx ),
.PSELS2 ( APBmslave2_PSELx ),
.PSELS3 ( ),
.PSELS4 ( ),
.PSELS5 ( ),
.PSELS6 ( ),
.PSELS7 ( ),
.PSELS8 ( ),
.PSELS9 ( ),
.PSELS10 ( ),
.PSELS11 ( ),
.PSELS12 ( ),
.PSELS13 ( ),
.PSELS14 ( ),
.PSELS15 ( ),
.PSELS16 ( )
);
endmodule

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component/work/CoreAPB3_0/CoreAPB3_0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:03 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CoreAPB3_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreAPB3_0/CoreAPB3_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/wave_user.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec_compile.tcl
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.exe
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.lin
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/coreapb3_usertb_master.bfm
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/coreparameters.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_main.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_ahbtoapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslaveext.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslave.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/test/user/testbench.v