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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
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component/work/CORETSE_0/CORETSE_0.cxf Normal file
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component/work/CORETSE_0/CORETSE_0.sdb Normal file
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component/work/CORETSE_0/CORETSE_0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:12 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CORETSE_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CORETSE_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CORETSE:4.0.124} -component_name {CORETSE_0} -params {\
"ECC_ENABLE:false" \
"GMII_TBI:1" \
"HOST_INTERFACE:0" \
"MDIO_PHYID:18" \
"PACKET_SIZE:11" \
"SAL:true" \
"SLIP_ENABLE:false" \
"STATS:true" \
"TXRX_INTR_ENABLE:true" \
"WoL:true" }
# Exporting Component Description of CORETSE_0 to TCL done
*/
// CORETSE_0
module CORETSE_0(
// Inputs
MDI,
MRXACPT,
MRXCLK,
MTXBYTEVALID,
MTXCLK,
MTXDAT,
MTXEOF,
MTXRDY,
MTXSOF,
PADDR,
PCLK,
PENABLE,
PRESETN,
PSEL,
PWDATA,
PWRITE,
RCG,
RXCLK,
SIGNAL_DETECT,
TBI_RX_CLK,
TBI_TX_CLK,
TXCLK,
// Outputs
ANX_STATE,
MDC,
MDO,
MDOEN,
MRXBYTEVALID,
MRXDAT,
MRXEOF,
MRXRDY,
MRXSOF,
MTXACPT,
MTXHWM,
PRDATA,
PREADY,
PSLVERR,
RCG_ERROR,
SYNC,
TBI_TX_VALID,
TCG,
TSM_CONTROL,
TSM_RX_INTR,
TSM_TX_INTR
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input MDI;
input MRXACPT;
input MRXCLK;
input [1:0] MTXBYTEVALID;
input MTXCLK;
input [31:0] MTXDAT;
input MTXEOF;
input MTXRDY;
input MTXSOF;
input [31:0] PADDR;
input PCLK;
input PENABLE;
input PRESETN;
input PSEL;
input [31:0] PWDATA;
input PWRITE;
input [9:0] RCG;
input RXCLK;
input SIGNAL_DETECT;
input TBI_RX_CLK;
input TBI_TX_CLK;
input TXCLK;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [9:0] ANX_STATE;
output MDC;
output MDO;
output MDOEN;
output [1:0] MRXBYTEVALID;
output [31:0] MRXDAT;
output MRXEOF;
output MRXRDY;
output MRXSOF;
output MTXACPT;
output MTXHWM;
output [31:0] PRDATA;
output PREADY;
output PSLVERR;
output RCG_ERROR;
output SYNC;
output TBI_TX_VALID;
output [9:0] TCG;
output [31:0] TSM_CONTROL;
output [3:0] TSM_RX_INTR;
output [3:0] TSM_TX_INTR;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [9:0] ANX_STATE_net_0;
wire [31:0] PADDR;
wire PENABLE;
wire [31:0] APBS_PRDATA;
wire APBS_PREADY;
wire PSEL;
wire APBS_PSLVERR;
wire [31:0] PWDATA;
wire PWRITE;
wire MDC_net_0;
wire MDI;
wire MDO_net_0;
wire MDOEN_net_0;
wire MRXACPT;
wire [1:0] MRXBYTEVALID_net_0;
wire MRXCLK;
wire [31:0] MRXDAT_net_0;
wire MRXEOF_net_0;
wire MRXRDY_net_0;
wire MRXSOF_net_0;
wire MTXACPT_net_0;
wire [1:0] MTXBYTEVALID;
wire MTXCLK;
wire [31:0] MTXDAT;
wire MTXEOF;
wire MTXHWM_net_0;
wire MTXRDY;
wire MTXSOF;
wire PCLK;
wire PRESETN;
wire [9:0] RCG;
wire RCG_ERROR_net_0;
wire RXCLK;
wire SIGNAL_DETECT;
wire SYNC_net_0;
wire TBI_RX_CLK;
wire TBI_TX_CLK;
wire TBI_TX_VALID_net_0;
wire [9:0] TCG_net_0;
wire [31:0] TSM_CONTROL_net_0;
wire [3:0] TSM_RX_INTR_net_0;
wire [3:0] TSM_TX_INTR_net_0;
wire TXCLK;
wire MTXACPT_net_1;
wire MTXHWM_net_1;
wire MRXRDY_net_1;
wire MRXSOF_net_1;
wire MRXEOF_net_1;
wire [31:0] MRXDAT_net_1;
wire [1:0] MRXBYTEVALID_net_1;
wire [9:0] TCG_net_1;
wire TBI_TX_VALID_net_1;
wire SYNC_net_1;
wire [9:0] ANX_STATE_net_1;
wire RCG_ERROR_net_1;
wire MDC_net_1;
wire MDO_net_1;
wire MDOEN_net_1;
wire [31:0] TSM_CONTROL_net_1;
wire [3:0] TSM_TX_INTR_net_1;
wire [3:0] TSM_RX_INTR_net_1;
wire [31:0] APBS_PRDATA_net_0;
wire APBS_PSLVERR_net_0;
wire APBS_PREADY_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [31:0] AXI4S_TTDATA_const_net_0;
wire [3:0] AXI4S_TTKEEP_const_net_0;
wire [7:0] RXD_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign AXI4S_TTDATA_const_net_0 = 32'h00000000;
assign AXI4S_TTKEEP_const_net_0 = 4'h0;
assign RXD_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MTXACPT_net_1 = MTXACPT_net_0;
assign MTXACPT = MTXACPT_net_1;
assign MTXHWM_net_1 = MTXHWM_net_0;
assign MTXHWM = MTXHWM_net_1;
assign MRXRDY_net_1 = MRXRDY_net_0;
assign MRXRDY = MRXRDY_net_1;
assign MRXSOF_net_1 = MRXSOF_net_0;
assign MRXSOF = MRXSOF_net_1;
assign MRXEOF_net_1 = MRXEOF_net_0;
assign MRXEOF = MRXEOF_net_1;
assign MRXDAT_net_1 = MRXDAT_net_0;
assign MRXDAT[31:0] = MRXDAT_net_1;
assign MRXBYTEVALID_net_1 = MRXBYTEVALID_net_0;
assign MRXBYTEVALID[1:0] = MRXBYTEVALID_net_1;
assign TCG_net_1 = TCG_net_0;
assign TCG[9:0] = TCG_net_1;
assign TBI_TX_VALID_net_1 = TBI_TX_VALID_net_0;
assign TBI_TX_VALID = TBI_TX_VALID_net_1;
assign SYNC_net_1 = SYNC_net_0;
assign SYNC = SYNC_net_1;
assign ANX_STATE_net_1 = ANX_STATE_net_0;
assign ANX_STATE[9:0] = ANX_STATE_net_1;
assign RCG_ERROR_net_1 = RCG_ERROR_net_0;
assign RCG_ERROR = RCG_ERROR_net_1;
assign MDC_net_1 = MDC_net_0;
assign MDC = MDC_net_1;
assign MDO_net_1 = MDO_net_0;
assign MDO = MDO_net_1;
assign MDOEN_net_1 = MDOEN_net_0;
assign MDOEN = MDOEN_net_1;
assign TSM_CONTROL_net_1 = TSM_CONTROL_net_0;
assign TSM_CONTROL[31:0] = TSM_CONTROL_net_1;
assign TSM_TX_INTR_net_1 = TSM_TX_INTR_net_0;
assign TSM_TX_INTR[3:0] = TSM_TX_INTR_net_1;
assign TSM_RX_INTR_net_1 = TSM_RX_INTR_net_0;
assign TSM_RX_INTR[3:0] = TSM_RX_INTR_net_1;
assign APBS_PRDATA_net_0 = APBS_PRDATA;
assign PRDATA[31:0] = APBS_PRDATA_net_0;
assign APBS_PSLVERR_net_0 = APBS_PSLVERR;
assign PSLVERR = APBS_PSLVERR_net_0;
assign APBS_PREADY_net_0 = APBS_PREADY;
assign PREADY = APBS_PREADY_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CORETSE - Actel:DirectCore:CORETSE:4.0.124
CORETSE #(
.ECC_ENABLE ( 0 ),
.FAMILY ( 26 ),
.GMII_TBI ( 1 ),
.HOST_INTERFACE ( 0 ),
.MDIO_PHYID ( 18 ),
.PACKET_SIZE ( 11 ),
.SAL ( 1 ),
.SLIP_ENABLE ( 0 ),
.STATS ( 1 ),
.TXRX_INTR_ENABLE ( 1 ),
.WoL ( 1 ) )
CORETSE_0_0(
// Inputs
.MTXCLK ( MTXCLK ),
.MTXRDY ( MTXRDY ),
.MTXSOF ( MTXSOF ),
.MTXEOF ( MTXEOF ),
.MTXDAT ( MTXDAT ),
.MTXBYTEVALID ( MTXBYTEVALID ),
.MRXCLK ( MRXCLK ),
.MRXACPT ( MRXACPT ),
.AXI4S_TCLK ( GND_net ), // tied to 1'b0 from definition
.AXI4S_TTVALID ( GND_net ), // tied to 1'b0 from definition
.AXI4S_TTDATA ( AXI4S_TTDATA_const_net_0 ), // tied to 32'h00000000 from definition
.AXI4S_TTKEEP ( AXI4S_TTKEEP_const_net_0 ), // tied to 4'h0 from definition
.AXI4S_TTLAST ( GND_net ), // tied to 1'b0 from definition
.AXI4S_ICLK ( GND_net ), // tied to 1'b0 from definition
.AXI4S_ITREADY ( GND_net ), // tied to 1'b0 from definition
.TXCLK ( TXCLK ),
.RXCLK ( RXCLK ),
.RXDV ( GND_net ), // tied to 1'b0 from definition
.RXD ( RXD_const_net_0 ), // tied to 8'h00 from definition
.RXER ( GND_net ), // tied to 1'b0 from definition
.CRS ( GND_net ), // tied to 1'b0 from definition
.COL ( GND_net ), // tied to 1'b0 from definition
.TBI_TX_CLK ( TBI_TX_CLK ),
.TBI_RX_CLK ( TBI_RX_CLK ),
.RCG ( RCG ),
.TBI_RX_VALID ( GND_net ), // tied to 1'b0 from definition
.TBI_RX_READY ( GND_net ), // tied to 1'b0 from definition
.SIGNAL_DETECT ( SIGNAL_DETECT ),
.MDI ( MDI ),
.PCLK ( PCLK ),
.PRESETN ( PRESETN ),
.PADDR ( PADDR ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PWRITE ( PWRITE ),
.PWDATA ( PWDATA ),
// Outputs
.MTXACPT ( MTXACPT_net_0 ),
.MTXHWM ( MTXHWM_net_0 ),
.MRXRDY ( MRXRDY_net_0 ),
.MRXSOF ( MRXSOF_net_0 ),
.MRXEOF ( MRXEOF_net_0 ),
.MRXDAT ( MRXDAT_net_0 ),
.MRXBYTEVALID ( MRXBYTEVALID_net_0 ),
.AXI4S_TTREADY ( ),
.AXI4S_ITVALID ( ),
.AXI4S_ITLAST ( ),
.AXI4S_ITDATA ( ),
.AXI4S_ITKEEP ( ),
.AXI4S_ITUSER ( ),
.TXEN ( ),
.TXD ( ),
.TXER ( ),
.TCG ( TCG_net_0 ),
.TBI_TX_VALID ( TBI_TX_VALID_net_0 ),
.RX_SLIP ( ),
.SYNC ( SYNC_net_0 ),
.ANX_STATE ( ANX_STATE_net_0 ),
.RCG_ERROR ( RCG_ERROR_net_0 ),
.MDC ( MDC_net_0 ),
.MDO ( MDO_net_0 ),
.MDOEN ( MDOEN_net_0 ),
.PREADY ( APBS_PREADY ),
.PRDATA ( APBS_PRDATA ),
.PSLVERR ( APBS_PSLVERR ),
.TSM_INTR ( ),
.TSM_CONTROL ( TSM_CONTROL_net_0 ),
.TSM_TX_INTR ( TSM_TX_INTR_net_0 ),
.TSM_RX_INTR ( TSM_RX_INTR_net_0 ),
.TX_ECC_SEC ( ),
.TX_ECC_DED ( ),
.RX_ECC_SEC ( ),
.RX_ECC_DED ( )
);
endmodule

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component/work/CORETSE_0/CORETSE_0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:12 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CORETSE_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/include.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CORETSE_0/CORETSE_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/coreparameters.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/mti/scripts/wave.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/testbench.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/CoreTSE_tb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/CoreTSE_AXI4S_tb.v