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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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1
component/Actel/DirectCore/CORESPI/5.2.104/CORESPI.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORESPI</name><vendor>Actel</vendor><library>DirectCore</library><version>5.2.104</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\amba_bfm\bfm_ahbtoapb.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\amba_bfm\bfm_apb.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\amba_bfm\bfm_main.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\amba_bfm\bfm_package.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\test\user\testbench.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="5"><name>mti\bfmtovec.exe</name><userFileType>unknown</userFileType></file><file fileid="6"><name>mti\bfmtovec.lin</name><userFileType>unknown</userFileType></file><file fileid="7"><name>mti\bfmtovec_compile.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="8"><name>mti\user_tb.bfm</name><userFileType>BFM</userFileType></file><file fileid="9"><name>mti\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="10"><name>rtl\vlog\core\corespi.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="11"><name>rtl\vlog\core\spi.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="12"><name>rtl\vlog\core\spi_chanctrl.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="13"><name>rtl\vlog\core\spi_clockmux.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="14"><name>rtl\vlog\core\spi_control.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\core\spi_fifo.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="16"><name>rtl\vlog\core\spi_rf.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/CORESPI/5.2.104/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:04 2026
// Parameters for CORESPI
//--------------------------------------------------------------------
parameter APB_DWIDTH = 32;
parameter CFG_CLK = 16;
parameter CFG_FIFO_DEPTH = 32;
parameter CFG_FRAME_SIZE = 16;
parameter CFG_MODE = 0;
parameter CFG_MOT_MODE = 0;
parameter CFG_MOT_SSEL = 1;
parameter CFG_NSC_OPERATION = 0;
parameter CFG_TI_JMB_FRAMES = 0;
parameter CFG_TI_NSC_CUSTOM = 0;
parameter CFG_TI_NSC_FRC = 0;
parameter HDL_license = "U";
parameter testbench = "User";

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component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.exe Normal file
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component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.lin Normal file
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component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec_compile.do Normal file
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### script to compile Actel AMBA BFM source file into vector file for simulation
# 12Jan09 Production Release Version 3.0
quietly set linux_exe "./bfmtovec.lin"
quietly set windows_exe "./bfmtovec.exe"
quietly set bfm_src_in "./user_tb.bfm"
quietly set bfm_vec_out "./user_tb.vec"
# check OS type and use appropriate executable
if {$tcl_platform(os) == "Linux"} {
echo "--- Using Linux Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.lin"
if {![file executable $bfmtovec_exe]} {
quietly set cmds "chmod +x $bfmtovec_exe"
eval $cmds
}
} else {
echo "--- Using Windows Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.exe"
}
# compile BFM source files into vector outputs
echo "--- Compiling Actel DirectCore AMBA BFM source files ..."
quietly set cmd1 "exec $bfmtovec_exe -in $bfm_src_in -out $bfm_vec_out"
eval $cmd1
echo "--- Done."

241
component/Actel/DirectCore/CORESPI/5.2.104/mti/user_tb.bfm Normal file
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memmap master 0x10000000
memmap slave 0x11000000
constant R_control 0x00
constant R_intclear 0x04
constant R_rxdata 0x08
constant R_txdata 0x0C
constant R_intmask 0x10
constant R_intraw 0x10
constant R_control2 0x18
constant R_command 0x1C
constant R_stat 0x20
constant R_ssel 0x24
constant R_txdatal 0x28
constant R_CLK_DIV 0x2C
# R_control bits
constant B_enable 0x00000001
constant B_master 0x00000002
constant B_slave 0x00000000
constant B_intenrxovr 0x00000004
constant B_intentx 0x00000008
constant B_intentxov 0x00000010
constant B_intenrxov 0x00000020
constant B_intenurun 0x00000040
constant B_oenoff 0x00000080
# R_control2 bits
constant B_intencmd 0x00000010
constant B_intentssend 0x00000020
constant B_intendatarx 0x00000040
# R_command bits (write-only)
constant B_rxfiforst 0x00000001
constant B_txfiforst 0x00000002
# R_intclear/raw/mask bits
constant B_txint 0x00000001
constant B_rxovint 0x00000004
constant B_txurint 0x00000008
constant B_cmdint 0x00000010
constant B_ssendint 0x00000020
constant B_datarxint 0x00000040
# R_status
constant B_firstframe 0x00000001
constant B_done 0x00000002
constant B_rxempty 0x00000004
constant B_txfull 0x00000008
constant B_rxoverflow 0x00000010
constant B_txunderrun 0x00000020
constant B_ssel 0x00000040
constant B_active 0x00000080
procedure main
print "CoreSPI User testbench"
debug 0
#setup 7 1 # execute $stop at end
timeout 10000
print "********************************************************************"
print "Test1: Read Initial Register values"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "Test2: Master -> Slave : 4 Byte transfer"
print "********************************************************************"
call test_slave_rx
wait 100
print "********************************************************************"
print "Test3: Check Master TX_DONE & slave DATA_RX interrupt operation"
print "********************************************************************"
call test_interrupt_operation
print "********************************************************************"
print "Test4: Read Register values after the transfer"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "CoreSPI user testbench completed"
print "********************************************************************"
return
procedure read_reg
int i x
## Read contents of APB register block
print "CoreSPI master registers"
loop i 0x00 0x2C 4
readstore b master i x
print "Read from %08x: %08x" i x
endloop
print "CoreSPI slave registers"
loop i 0x00 0x2C 4
readstore b slave i x
print "Read from %08x: %08x" i x
endloop
return
procedure test_slave_rx
int i x
## 4 Byte transfer to test master->slave transfer
print "Enable the slave"
write w slave R_control (B_slave | B_enable)
print "Set slave up with TX data"
loop i 0x5 0x8 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
print "Configure master to Tx to slave 0"
write w master R_ssel 1
write w master R_control (B_master | B_enable)
print "Set master up with TX data"
loop i 0x01 0x03 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x04) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x04
#write b master R_CLK_DIV 0x04
#print "********************************************************************************"
#print "Dynamically configuring the clock division factor of master generated SPI clock"
#print "********************************************************************************"
## Wait for the transfer to complete
wait 1500
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
loop i 0x01 0x04 1
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0x5 0x8 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return
procedure test_interrupt_operation
int i x
print "Set slave up with TX data"
loop i 0x0A 0x0D 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
## Enable slave DATA_RX interrupt
print "Clear any pending DATA_TX raw interrupts before enabling the DATA_RX interrupt"
write b slave R_intclear 0x40
wait 100
print "Enable slave DATA_RX interrupt"
write b slave R_control2 B_intendatarx
## Enable master TX_DONE interrupt
print "Clear any pending TX_DONE raw interrupts before enabling the TX_DONE interrupt"
write b master R_intclear 0x01
wait 100
print "Enable master TX_DONE interrupt"
write w master R_control (B_master | B_enable | B_intentx)
## Load master with tx data
print "Set master up with TX data"
loop i 0x04 0x06 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x07) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x07
wait 1500
print "************************************"
print "Check master SPIINT interrupt asserted"
print "************************************"
## Check master interrupt
iotstbit 0 1
readstore b master R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "Clear master TX_DONE interrupt & check SPIINT de-asserts"
## Clear interrupt
write b master R_intclear 0x01
wait 100
## Check clear
iotstbit 0 0
print "************************************"
print "Check slave SPIINT interrupt asserted"
print "************************************"
## Check slave interrupt
iotstbit 1 1
readstore b slave R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
## Check slave
loop i 0x04 0x07
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "Wait until data is removed from the RX_FIFO"
wait 20
print "Clear slave DATA_RX interrupt and check SPIINT de-asserts"
write b slave R_intclear 0x40
wait 100
## Check clear
iotstbit 1 0
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0xA 0xD 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return

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component/Actel/DirectCore/CORESPI/5.2.104/mti/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {SPI Master}
add wave -noupdate -divider APB
add wave -noupdate -format Literal /testbench/USPIM/PADDR
add wave -noupdate -format Logic /testbench/USPIM/PCLK
add wave -noupdate -format Logic /testbench/USPIM/PENABLE
add wave -noupdate -format Literal /testbench/USPIM/PRDATA
add wave -noupdate -format Logic /testbench/USPIM/PREADY
add wave -noupdate -format Logic /testbench/USPIM/PRESETN
add wave -noupdate -format Logic /testbench/USPIM/PSEL
add wave -noupdate -format Logic /testbench/USPIM/PSLVERR
add wave -noupdate -format Literal /testbench/USPIM/PWDATA
add wave -noupdate -format Logic /testbench/USPIM/PWRITE
add wave -noupdate -divider Serial
add wave -noupdate -format Logic /testbench/USPIM/SPICLKI
add wave -noupdate -format Logic /testbench/USPIM/SPIINT
add wave -noupdate -format Logic /testbench/USPIM/SPIMODE
add wave -noupdate -format Logic /testbench/USPIM/SPIOEN
add wave -noupdate -format Logic /testbench/USPIM/SPIRXAVAIL
add wave -noupdate -format Logic /testbench/USPIM/SPISCLKO
add wave -noupdate -format Logic /testbench/USPIM/SPISDI
add wave -noupdate -format Logic /testbench/USPIM/SPISDO
add wave -noupdate -format Literal /testbench/USPIM/SPISS
add wave -noupdate -format Logic /testbench/USPIM/SPISSI
add wave -noupdate -format Logic /testbench/USPIM/SPITXRFM
add wave -noupdate -divider {SPI Slave}
add wave -noupdate -divider APB
add wave -noupdate -radix hexadecimal -format Literal /testbench/USPIS/PADDR
add wave -noupdate -format Logic /testbench/USPIS/PCLK
add wave -noupdate -format Logic /testbench/USPIS/PENABLE
add wave -noupdate -format Literal /testbench/USPIS/PRDATA
add wave -noupdate -format Logic /testbench/USPIS/PREADY
add wave -noupdate -format Logic /testbench/USPIS/PRESETN
add wave -noupdate -format Logic /testbench/USPIS/PSEL
add wave -noupdate -format Logic /testbench/USPIS/PSLVERR
add wave -noupdate -format Literal /testbench/USPIS/PWDATA
add wave -noupdate -format Logic /testbench/USPIS/PWRITE
add wave -noupdate -divider Serial
add wave -noupdate -format Logic /testbench/USPIS/SPICLKI
add wave -noupdate -format Logic /testbench/USPIS/SPIINT
add wave -noupdate -format Logic /testbench/USPIS/SPIMODE
add wave -noupdate -format Logic /testbench/USPIS/SPIOEN
add wave -noupdate -format Logic /testbench/USPIS/SPIRXAVAIL
add wave -noupdate -format Logic /testbench/USPIS/SPISCLKO
add wave -noupdate -format Logic /testbench/USPIS/SPISDI
add wave -noupdate -format Logic /testbench/USPIS/SPISDO
add wave -noupdate -format Literal /testbench/USPIS/SPISS
add wave -noupdate -format Logic /testbench/USPIS/SPISSI
add wave -noupdate -format Logic /testbench/USPIS/SPITXRFM
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {44450164832 ps} 0} {{Cursor 11} {8169427 ps} 0} {{Cursor 12} {44640351578 ps} 0} {{Cursor 4} {44639015000 ps} 0}
configure wave -namecolwidth 408
configure wave -valuecolwidth 85
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {23535750 ps}

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_ahbtoapb.v Normal file
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`timescale 1 ns / 100 ps
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// AHB to APB Bridge
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
//
//
// SVN Revision Information:
// SVN $Revision: 31535 $
// SVN $Date: 2018-03-16 18:51:54 +0530 (Fri, 16 Mar 2018) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
// 28Nov07 IPB Updated to increase throughput
//
// *********************************************************************/
module CORESPI_BFM_AHB2APB (HCLK, HRESETN, HSEL, HWRITE, HADDR, HWDATA, HRDATA, HREADYIN, HREADYOUT, HTRANS, HSIZE, HBURST, HMASTLOCK, HPROT, HRESP, PSEL, PADDR, PWRITE, PENABLE, PWDATA, PRDATA, PREADY, PSLVERR);
parameter TPD = 1;
input HCLK;
input HRESETN;
input HSEL;
input HWRITE;
input[31:0] HADDR;
input[31:0] HWDATA;
output[31:0] HRDATA;
wire[31:0] HRDATA;
input HREADYIN;
output HREADYOUT;
wire HREADYOUT;
input[1:0] HTRANS;
input[2:0] HSIZE;
input[2:0] HBURST;
input HMASTLOCK;
input[3:0] HPROT;
output HRESP;
wire HRESP;
output[15:0] PSEL;
wire[15:0] PSEL;
output[31:0] PADDR;
wire[31:0] PADDR;
output PWRITE;
wire PWRITE;
output PENABLE;
wire PENABLE;
output[31:0] PWDATA;
wire[31:0] PWDATA;
input[31:0] PRDATA;
input PREADY;
input PSLVERR;
parameter[1:0] T0 = 0;
parameter[1:0] T2 = 1;
parameter[1:0] T345 = 2;
parameter[1:0] TR0 = 3;
reg[1:0] STATE;
reg HREADYOUT_P0;
reg HRESP_P0;
reg[15:0] PSEL_P0;
reg[31:0] PADDR_P0;
reg PWRITE_P0;
reg PENABLE_P0;
reg[31:0] PWDATA_P0;
wire[31:0] PWDATA_MUX;
reg DMUX;
reg PSELEN;
always @(posedge HCLK or negedge HRESETN)
begin
if (HRESETN == 1'b0)
begin
STATE <= T0 ;
HREADYOUT_P0 <= 1'b1 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
HRESP_P0 <= 1'b0 ;
DMUX <= 1'b0 ;
PSELEN <= 1'b0 ;
end
else
begin
HRESP_P0 <= 1'b0 ;
HREADYOUT_P0 <= 1'b0 ;
DMUX <= 1'b0 ;
case (STATE)
T0 :
begin
if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
begin
STATE <= T2 ;
PADDR_P0 <= HADDR ;
PWRITE_P0 <= HWRITE ;
PWDATA_P0 <= HWDATA ;
PENABLE_P0 <= 1'b0 ;
DMUX <= HWRITE ;
PSELEN <= 1'b1 ;
end
else
begin
HREADYOUT_P0 <= 1'b1 ;
end
end
T2 :
begin
PENABLE_P0 <= 1'b1 ;
STATE <= T345 ;
end
T345 :
begin
if (PREADY == 1'b1)
begin
PENABLE_P0 <= 1'b0 ;
PSELEN <= 1'b0 ;
if (PSLVERR == 1'b0)
begin
STATE <= T0 ;
if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
begin
STATE <= T2 ;
PADDR_P0 <= HADDR ;
PWRITE_P0 <= HWRITE ;
DMUX <= HWRITE ;
PSELEN <= 1'b1 ;
end
end
else
begin
HRESP_P0 <= 1'b1 ;
STATE <= TR0 ;
end
end
end
TR0 :
begin
HRESP_P0 <= 1'b1 ;
HREADYOUT_P0 <= 1'b1 ;
STATE <= T0 ;
end
endcase
if (DMUX == 1'b1)
begin
PWDATA_P0 <= HWDATA ;
end
end
end
always @(PADDR_P0 or PSELEN)
begin
PSEL_P0 <= {16{1'b0}} ;
if (PSELEN == 1'b1)
begin
begin : xhdl_3
integer i;
for(i = 0; i <= 15; i = i + 1)
begin
PSEL_P0[i] <= (PADDR_P0[27:24] == i) ;
end
end
end
end
assign PWDATA_MUX = (DMUX == 1'b1) ? HWDATA : PWDATA_P0 ;
assign #TPD HRDATA = PRDATA ;
assign #TPD HREADYOUT = HREADYOUT_P0 | (PREADY & PSELEN & PENABLE_P0 & ~PSLVERR) ;
assign #TPD HRESP = HRESP_P0 ;
assign #TPD PSEL = PSEL_P0 ;
assign #TPD PADDR = PADDR_P0 ;
assign #TPD PWRITE = PWRITE_P0 ;
assign #TPD PENABLE = PENABLE_P0 ;
assign #TPD PWDATA = PWDATA_MUX ;
endmodule

285
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_apb.v Normal file
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// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// APB Master Wrapper
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
//
//
// SVN Revision Information:
// SVN $Revision: 31535 $
// SVN $Date: 2018-03-16 18:51:54 +0530 (Fri, 16 Mar 2018) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
//
// *********************************************************************/
`timescale 1 ns / 100 ps
module CORESPI_BFM_APB (SYSCLK, SYSRSTN, PCLK, PRESETN, PADDR, PENABLE, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR, PSEL, INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT, CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY, FINISHED, FAILED);
parameter OPMODE = 0;
parameter VECTFILE = "test.vec";
parameter MAX_INSTRUCTIONS = 16384;
parameter MAX_STACK = 1024;
parameter MAX_MEMTEST = 65536;
parameter TPD = 1;
parameter DEBUGLEVEL = -1;
parameter CON_SPULSE = 0;
parameter ARGVALUE0 = 0;
parameter ARGVALUE1 = 0;
parameter ARGVALUE2 = 0;
parameter ARGVALUE3 = 0;
parameter ARGVALUE4 = 0;
parameter ARGVALUE5 = 0;
parameter ARGVALUE6 = 0;
parameter ARGVALUE7 = 0;
parameter ARGVALUE8 = 0;
parameter ARGVALUE9 = 0;
parameter ARGVALUE10 = 0;
parameter ARGVALUE11 = 0;
parameter ARGVALUE12 = 0;
parameter ARGVALUE13 = 0;
parameter ARGVALUE14 = 0;
parameter ARGVALUE15 = 0;
parameter ARGVALUE16 = 0;
parameter ARGVALUE17 = 0;
parameter ARGVALUE18 = 0;
parameter ARGVALUE19 = 0;
parameter ARGVALUE20 = 0;
parameter ARGVALUE21 = 0;
parameter ARGVALUE22 = 0;
parameter ARGVALUE23 = 0;
parameter ARGVALUE24 = 0;
parameter ARGVALUE25 = 0;
parameter ARGVALUE26 = 0;
parameter ARGVALUE27 = 0;
parameter ARGVALUE28 = 0;
parameter ARGVALUE29 = 0;
parameter ARGVALUE30 = 0;
parameter ARGVALUE31 = 0;
parameter ARGVALUE32 = 0;
parameter ARGVALUE33 = 0;
parameter ARGVALUE34 = 0;
parameter ARGVALUE35 = 0;
parameter ARGVALUE36 = 0;
parameter ARGVALUE37 = 0;
parameter ARGVALUE38 = 0;
parameter ARGVALUE39 = 0;
parameter ARGVALUE40 = 0;
parameter ARGVALUE41 = 0;
parameter ARGVALUE42 = 0;
parameter ARGVALUE43 = 0;
parameter ARGVALUE44 = 0;
parameter ARGVALUE45 = 0;
parameter ARGVALUE46 = 0;
parameter ARGVALUE47 = 0;
parameter ARGVALUE48 = 0;
parameter ARGVALUE49 = 0;
parameter ARGVALUE50 = 0;
parameter ARGVALUE51 = 0;
parameter ARGVALUE52 = 0;
parameter ARGVALUE53 = 0;
parameter ARGVALUE54 = 0;
parameter ARGVALUE55 = 0;
parameter ARGVALUE56 = 0;
parameter ARGVALUE57 = 0;
parameter ARGVALUE58 = 0;
parameter ARGVALUE59 = 0;
parameter ARGVALUE60 = 0;
parameter ARGVALUE61 = 0;
parameter ARGVALUE62 = 0;
parameter ARGVALUE63 = 0;
parameter ARGVALUE64 = 0;
parameter ARGVALUE65 = 0;
parameter ARGVALUE66 = 0;
parameter ARGVALUE67 = 0;
parameter ARGVALUE68 = 0;
parameter ARGVALUE69 = 0;
parameter ARGVALUE70 = 0;
parameter ARGVALUE71 = 0;
parameter ARGVALUE72 = 0;
parameter ARGVALUE73 = 0;
parameter ARGVALUE74 = 0;
parameter ARGVALUE75 = 0;
parameter ARGVALUE76 = 0;
parameter ARGVALUE77 = 0;
parameter ARGVALUE78 = 0;
parameter ARGVALUE79 = 0;
parameter ARGVALUE80 = 0;
parameter ARGVALUE81 = 0;
parameter ARGVALUE82 = 0;
parameter ARGVALUE83 = 0;
parameter ARGVALUE84 = 0;
parameter ARGVALUE85 = 0;
parameter ARGVALUE86 = 0;
parameter ARGVALUE87 = 0;
parameter ARGVALUE88 = 0;
parameter ARGVALUE89 = 0;
parameter ARGVALUE90 = 0;
parameter ARGVALUE91 = 0;
parameter ARGVALUE92 = 0;
parameter ARGVALUE93 = 0;
parameter ARGVALUE94 = 0;
parameter ARGVALUE95 = 0;
parameter ARGVALUE96 = 0;
parameter ARGVALUE97 = 0;
parameter ARGVALUE98 = 0;
parameter ARGVALUE99 = 0;
input SYSCLK;
input SYSRSTN;
output PCLK;
wire PCLK;
output PRESETN;
wire PRESETN;
output[31:0] PADDR;
wire[31:0] PADDR;
output PENABLE;
wire PENABLE;
output PWRITE;
wire PWRITE;
output[31:0] PWDATA;
wire[31:0] PWDATA;
input[31:0] PRDATA;
input PREADY;
input PSLVERR;
output[15:0] PSEL;
wire[15:0] PSEL;
input[255:0] INTERRUPT;
output[31:0] GP_OUT;
wire[31:0] GP_OUT;
input[31:0] GP_IN;
output EXT_WR;
wire EXT_WR;
output EXT_RD;
wire EXT_RD;
output[31:0] EXT_ADDR;
wire[31:0] EXT_ADDR;
inout[31:0] EXT_DATA;
wire[31:0] EXT_DATA;
input EXT_WAIT;
input[15:0] CON_ADDR;
inout[31:0] CON_DATA;
wire[31:0] CON_DATA;
input CON_RD;
input CON_WR;
output CON_BUSY;
wire CON_BUSY;
output FINISHED;
wire FINISHED;
output FAILED;
wire FAILED;
wire iPCLk;
wire iHCLk;
wire iHRESETN;
wire[31:0] iHADDR;
wire[2:0] iHBURST;
wire iHMASTLOCK;
wire[3:0] iHPROT;
wire[2:0] iHSIZE;
wire[1:0] iHTRANS;
wire iHWRITE;
wire[31:0] iHRDATA;
wire[31:0] iHWDATA;
wire iHREADY;
wire iHREADYIN;
wire iHREADYOUT;
wire iHRESP;
wire[15:0] iHSEL;
wire[31:0] INSTR_IN = {32{1'b0}};
CORESPI_BFM_MAIN #( OPMODE, VECTFILE, MAX_INSTRUCTIONS, MAX_STACK, MAX_MEMTEST, TPD, DEBUGLEVEL, CON_SPULSE,
ARGVALUE0, ARGVALUE1, ARGVALUE2, ARGVALUE3, ARGVALUE4, ARGVALUE5, ARGVALUE6, ARGVALUE7, ARGVALUE8, ARGVALUE9,
ARGVALUE10, ARGVALUE11, ARGVALUE12, ARGVALUE13, ARGVALUE14, ARGVALUE15, ARGVALUE16, ARGVALUE17, ARGVALUE18, ARGVALUE19,
ARGVALUE20, ARGVALUE21, ARGVALUE22, ARGVALUE23, ARGVALUE24, ARGVALUE25, ARGVALUE26, ARGVALUE27, ARGVALUE28, ARGVALUE29,
ARGVALUE30, ARGVALUE31, ARGVALUE32, ARGVALUE33, ARGVALUE34, ARGVALUE35, ARGVALUE36, ARGVALUE37, ARGVALUE38, ARGVALUE39,
ARGVALUE40, ARGVALUE41, ARGVALUE42, ARGVALUE43, ARGVALUE44, ARGVALUE45, ARGVALUE46, ARGVALUE47, ARGVALUE48, ARGVALUE49,
ARGVALUE50, ARGVALUE51, ARGVALUE52, ARGVALUE53, ARGVALUE54, ARGVALUE55, ARGVALUE56, ARGVALUE57, ARGVALUE58, ARGVALUE59,
ARGVALUE60, ARGVALUE61, ARGVALUE62, ARGVALUE63, ARGVALUE64, ARGVALUE65, ARGVALUE66, ARGVALUE67, ARGVALUE68, ARGVALUE69,
ARGVALUE70, ARGVALUE71, ARGVALUE72, ARGVALUE73, ARGVALUE74, ARGVALUE75, ARGVALUE76, ARGVALUE77, ARGVALUE78, ARGVALUE79,
ARGVALUE80, ARGVALUE81, ARGVALUE82, ARGVALUE83, ARGVALUE84, ARGVALUE85, ARGVALUE86, ARGVALUE87, ARGVALUE88, ARGVALUE89,
ARGVALUE90, ARGVALUE91, ARGVALUE92, ARGVALUE93, ARGVALUE94, ARGVALUE95, ARGVALUE96, ARGVALUE97, ARGVALUE98, ARGVALUE99
) UBFM(
.SYSCLK(SYSCLK),
.SYSRSTN(SYSRSTN),
.HADDR(iHADDR),
.HCLK(iHCLk),
.PCLK(iPCLk),
.HRESETN(iHRESETN),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HSIZE(iHSIZE),
.HTRANS(iHTRANS),
.HWRITE(iHWRITE),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADY(iHREADY),
.HRESP(iHRESP),
.HSEL(iHSEL),
.INTERRUPT(INTERRUPT),
.GP_OUT(GP_OUT),
.GP_IN(GP_IN),
.EXT_WR(EXT_WR),
.EXT_RD(EXT_RD),
.EXT_ADDR(EXT_ADDR),
.EXT_DATA(EXT_DATA),
.EXT_WAIT(EXT_WAIT),
.CON_ADDR(CON_ADDR),
.CON_DATA(CON_DATA),
.CON_RD(CON_RD),
.CON_WR(CON_WR),
.CON_BUSY(CON_BUSY),
.INSTR_OUT(),
.INSTR_IN(INSTR_IN),
.FINISHED(FINISHED),
.FAILED(FAILED)
);
assign PCLK = iPCLk ;
assign PRESETN = iHRESETN ;
CORESPI_BFM_AHB2APB #(TPD) UBRIDGE(
.HCLK(iHCLk),
.HRESETN(iHRESETN),
.HSEL(1'b1),
.HWRITE(iHWRITE),
.HADDR(iHADDR),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADYIN(iHREADY),
.HREADYOUT(iHREADY),
.HTRANS(iHTRANS),
.HSIZE(iHSIZE),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HRESP(iHRESP),
.PSEL(PSEL),
.PADDR(PADDR),
.PWRITE(PWRITE),
.PENABLE(PENABLE),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
endmodule

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_package.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// corespi.v
//
//
// SVN Revision Information:
// SVN $Revision: 31477 $
// SVN $Date: 2018-03-13 12:25:12 +0530 (Tue, 13 Mar 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94973: Repackage core as a generic core
//
// Notes:
//
//
// *********************************************************************/
module
CORESPI
( //inputs
PCLK, //system clock
PRESETN, //system reset
PADDR, //address line
PSEL, //device select
PENABLE, //enable
PWRITE, //write
PWDATA, //write data
SPISSI, //slave select
SPISDI, //serial data in
SPICLKI, //serial clock in
//outputs
PRDATA, //data read
SPIINT, //interrupt
SPISS, //slave select
SPISCLKO, //serial clock out
SPIRXAVAIL, //data ready to be read (dma mode)
SPITXRFM, //room for more (dma mode)
SPIOEN, //output enable
SPISDO, //serial data out
SPIMODE, //1 -> master, 0 -> slave,
PREADY,
PSLVERR
);
//parameter FAMILY = 15; // 94973
parameter APB_DWIDTH = 8;
parameter CFG_FRAME_SIZE = 4;
parameter CFG_FIFO_DEPTH = 4;
parameter CFG_CLK = 3;
parameter CFG_MODE = 0;
parameter CFG_MOT_MODE = 2;
parameter CFG_MOT_SSEL = 0;
parameter CFG_TI_NSC_CUSTOM = 0;
parameter CFG_TI_NSC_FRC = 0;
parameter CFG_TI_JMB_FRAMES = 0;
parameter CFG_NSC_OPERATION = 0;
//parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0; // 94973
localparam SPS = ((CFG_MODE == 2'd0) && (CFG_MOT_SSEL == 1'b1)) ? 1'b1 :
((CFG_MODE == 2'd2) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_NSC_OPERATION == 2'd2)) ? 1'b1 :
1'b0;
localparam SPO = (CFG_MODE == 2'd0) ? CFG_MOT_MODE[1] :
(((CFG_MODE == 2'd1) || (CFG_MODE == 2'd2)) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_TI_NSC_FRC == 1'b1)) ? 1'b1 :
1'b0;
localparam SPH = (CFG_MODE == 2'd0) ? CFG_MOT_MODE[0] :
((CFG_MODE == 2'd1) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_TI_JMB_FRAMES == 1'b1)) ? 1'b1 :
((CFG_MODE == 2'd2) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_NSC_OPERATION == 2'd1)) ? 1'b1 :
1'b0;
//input TESTMODE;
input PCLK;
input PRESETN;
input [6:0] PADDR;
input PSEL;
input PENABLE;
input PWRITE;
input [APB_DWIDTH-1:0] PWDATA;
input SPISSI;
input SPISDI;
input SPICLKI;
output [APB_DWIDTH-1:0] PRDATA;
output SPIINT;
output [7:0] SPISS;
output SPISCLKO;
output SPIRXAVAIL;
output SPITXRFM;
output SPIOEN;
output SPIMODE;
output SPISDO;
// AP3
output PSLVERR;
output PREADY;
wire aresetn;
wire sresetn;
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : PRESETN; //94973
//assign sresetn = (SYNC_RESET == 1) ? PRESETN : 1'b1; //94973
assign aresetn = PRESETN; // 94973
assign sresetn = 1'b1; // 94973
// tie off AP3 signals
assign PSLVERR = 1'b0;
assign PREADY = 1'b1;
spi # (
.APB_DWIDTH (APB_DWIDTH),
.CFG_FRAME_SIZE (CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH (CFG_FIFO_DEPTH),
.CFG_CLK (CFG_CLK),
.SPO (SPO),
.SPH (SPH),
.SPS (SPS),
.CFG_MODE (CFG_MODE)
//.SYNC_RESET (SYNC_RESET) // 94973
) USPI( //inputs
.PCLK(PCLK),
.PRESETN(PRESETN),
.aresetn(aresetn),
.sresetn(sresetn),
.PADDR(PADDR),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.SPISSI(SPISSI),
.SPISDI(SPISDI),
.SPICLKI(SPICLKI),
//outputs
.PRDDATA(PRDATA),
.SPIINT(SPIINT),
.SPISS(SPISS),
.SPISCLKO(SPISCLKO),
.SPIRXAVAIL(SPIRXAVAIL),
.SPITXRFM(SPITXRFM),
.SPIOEN(SPIOEN),
.SPISDO(SPISDO),
.SPIMODE(SPIMODE)
);
endmodule

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// spi.v -- top level module for spi core
//
//
// SVN Revision Information:
// SVN $Revision: 31478 $
// SVN $Date: 2018-03-13 12:27:38 +0530 (Tue, 13 Mar 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94224: Add dynamic clcok configuration feature for generated
// master SPI clock
// 94973: Repackage core as a generic core
//
// Notes:
//
//
// *********************************************************************/
module spi( //inputs
PCLK, //system clock
PRESETN, //system reset
aresetn, //Async reset signal
sresetn, //Sync reset signal
PADDR, //address line
PSEL, //device select
PENABLE, //enable
PWRITE, //write
PWDATA, //write data
SPISSI, //slave select
SPISDI, //serial data in
SPICLKI, //serial clock in
//outputs
PRDDATA, //data read
SPIINT, //interrupt
SPISS, //slave select
SPISCLKO, //serial clock out
SPIRXAVAIL, //data ready to be read (dma mode)
SPITXRFM, //room for more (dma mode)
SPIOEN, //output enable
SPISDO, //serial data out
SPIMODE //1 -> master, 0 -> slave
);
parameter APB_DWIDTH = 8;
parameter CFG_FRAME_SIZE = 4;
parameter CFG_FIFO_DEPTH = 4;
parameter CFG_CLK = 7;
parameter SPO = 0;
parameter SPH = 0;
parameter SPS = 0;
parameter CFG_MODE = 0;
//parameter SYNC_RESET = 0; // 94973
//input TESTMODE;
input PCLK;
input PRESETN;
input aresetn;
input sresetn;
input [6:0] PADDR;
input PSEL;
input PENABLE;
input PWRITE;
input [APB_DWIDTH-1:0] PWDATA;
input SPISSI;
input SPISDI;
input SPICLKI;
output [APB_DWIDTH-1:0] PRDDATA;
output SPIINT;
output [7:0] SPISS;
output SPISCLKO;
output SPIRXAVAIL;
output SPITXRFM;
output SPIOEN;
output SPIMODE;
output SPISDO;
wire [7:0] clk_div_val; // 94224
wire [APB_DWIDTH-1:0] prdata_regs;
wire [7:0] cfg_ssel;
wire cfg_master;
wire cfg_enable;
wire [2:0] cfg_cmdsize;
wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_in;
wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_out;
wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_in;
wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_out;
wire rx_fifo_empty;
wire tx_fifo_full;
wire master_ssel_out;
wire [5:0] rx_fifo_count;
wire [5:0] tx_fifo_count;
//##########################################################################################
//APB Signals
wire [6:0] PADDR32 = { PADDR[6:2], 2'b00 };
//read data: either from the register file or the fifo.
assign PRDDATA = ~(PADDR32[6:0]==7'h08) ? prdata_regs : rx_fifo_data_out;
assign SPIMODE = cfg_master;
assign SPIRXAVAIL = ~rx_fifo_empty;
assign SPITXRFM = ~tx_fifo_full;
// ----------------------------------------------------------------------------------
// Channel Outputs
//Pass the slave select to the selected devices. If no slave select asserted then everything off
reg [7:0] master_ssel_all;
assign SPISS = master_ssel_all;
integer i;
always @(*)
begin
if (cfg_enable && cfg_master)
begin
for (i=0; i<8; i=i+1)
begin
if (cfg_ssel[i])
master_ssel_all[i] = master_ssel_out;
else
master_ssel_all[i] = (CFG_MODE != 1); //Send low in TIMODE to deselect
end
end
else
begin
for (i =0; i<8; i=i+1)
master_ssel_all[i] = (CFG_MODE != 1); //Send low in TIMODE to deselect
end
end
wire ssel_both = ( cfg_master ? master_ssel_out : SPISSI );
//-----------------------------------------------------------------------------------------
// The Register Set
spi_rf # (
.APB_DWIDTH(APB_DWIDTH),
.CFG_CLK(CFG_CLK) // 94224
)
URF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.paddr (PADDR32[6:0]),
.psel (PSEL),
.penable (PENABLE),
.pwrite (PWRITE),
.wrdata (PWDATA),
.prdata (prdata_regs),
.interrupt (SPIINT),
.tx_channel_underflow (tx_channel_underflow),
.rx_channel_overflow (rx_channel_overflow),
.tx_done (tx_done),
.rx_done (rx_done),
.rx_fifo_read (rx_fifo_read),
.tx_fifo_write (tx_fifo_write),
.tx_fifo_read (tx_fifo_read),
.rx_fifo_full (rx_fifo_full),
.rx_fifo_full_next (rx_fifo_full_next),
.rx_fifo_empty (rx_fifo_empty),
.rx_fifo_empty_next (rx_fifo_empty_next),
.tx_fifo_full (tx_fifo_full),
.tx_fifo_full_next (tx_fifo_full_next),
.tx_fifo_empty (tx_fifo_empty),
.tx_fifo_empty_next (tx_fifo_empty_next),
.first_frame (first_frame_out),
.ssel (ssel_both),
.rx_pktend (rx_pktend),
.rx_cmdsize (rx_cmdsize),
.active (active),
.cfg_enable (cfg_enable),
.cfg_master (cfg_master),
.cfg_ssel (cfg_ssel),
.cfg_cmdsize (cfg_cmdsize),
.clr_txfifo (fiforsttx),
.clr_rxfifo (fiforstrx),
.cfg_frameurun (cfg_frameurun),
.cfg_oenoff (cfg_oenoff),
.clk_div_val (clk_div_val) // 94224
);
// APB side of FIFOs Control
spi_control # (
.CFG_FRAME_SIZE (CFG_FRAME_SIZE)
) UCON ( .aresetn (aresetn),
.sresetn (sresetn),
.psel (PSEL),
.penable (PENABLE),
.pwrite (PWRITE),
.paddr (PADDR32[6:0]),
.wr_data_in (PWDATA[CFG_FRAME_SIZE-1:0]), // Use only FRAME_SIZE bits for data
.cfg_master (cfg_master),
.tx_fifo_data (tx_fifo_data_in),
.tx_fifo_write (tx_fifo_write),
.tx_fifo_last (tx_fifo_last_in),
.tx_fifo_empty (tx_fifo_empty),
.rx_fifo_read (rx_fifo_read),
.rx_fifo_empty (rx_fifo_empty)
);
//Transmit Fifo
spi_fifo # (
.CFG_FRAME_SIZE (CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH (CFG_FIFO_DEPTH)
) UTXF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.fiforst (fiforsttx),
.data_in (tx_fifo_data_in),
.flag_in (tx_fifo_last_in),
.data_out (tx_fifo_data_out),
.flag_out (tx_fifo_last_out),
.read_in (tx_fifo_read),
.write_in (tx_fifo_write),
.full_out (tx_fifo_full),
.empty_out (tx_fifo_empty),
.full_next_out (tx_fifo_full_next),
.empty_next_out (tx_fifo_empty_next),
.overflow_out (not_used1),
.fifo_count (tx_fifo_count)
);
//Receive Fifo
spi_fifo # (
.CFG_FRAME_SIZE(CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH(CFG_FIFO_DEPTH)
) URXF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.fiforst (fiforstrx),
//.fifosize (cfg_fifosize),
.data_in (rx_fifo_data_in),
.write_in (rx_fifo_write),
.flag_in (rx_fifo_first_in),
.data_out (rx_fifo_data_out),
.read_in (rx_fifo_read),
.flag_out (first_frame_out),
.full_out (rx_fifo_full),
.empty_out (rx_fifo_empty),
.empty_next_out (rx_fifo_empty_next),
.full_next_out (rx_fifo_full_next),
.overflow_out (rx_channel_overflow),
.fifo_count (rx_fifo_count)
);
//Channel controll
spi_chanctrl # (
.SPH (SPH),
.SPO (SPO),
.SPS (SPS),
.CFG_MODE (CFG_MODE),
.CFG_CLKRATE (CFG_CLK),
.CFG_FRAME_SIZE (CFG_FRAME_SIZE)
//.SYNC_RESET (SYNC_RESET) // 94973
)UCC ( .pclk (PCLK),
.presetn (PRESETN),
.aresetn (aresetn),
.sresetn (sresetn),
.spi_clk_in (SPICLKI),
.spi_clk_out (SPISCLKO),
.spi_ssel_in (SPISSI),
.spi_ssel_out (master_ssel_out),
.spi_data_in (SPISDI),
.spi_data_out (SPISDO),
.spi_data_oen (SPIOEN),
.txfifo_count (tx_fifo_count),
.txfifo_empty (tx_fifo_empty),
.txfifo_read (tx_fifo_read),
.txfifo_data (tx_fifo_data_out),
.txfifo_last (tx_fifo_last_out),
.rxfifo_count (rx_fifo_count),
.rxfifo_write (rx_fifo_write),
.rxfifo_data (rx_fifo_data_in),
.rxfifo_first (rx_fifo_first_in),
.cfg_enable (cfg_enable),
.cfg_master (cfg_master),
.cfg_frameurun (cfg_frameurun),
.cfg_cmdsize (cfg_cmdsize),
.cfg_oenoff (cfg_oenoff),
.tx_alldone (tx_done),
.rx_alldone (rx_done),
.rx_pktend (rx_pktend),
.rx_cmdsize (rx_cmdsize),
.tx_underrun (tx_channel_underflow),
.active (active),
.clk_div_val (clk_div_val) // 94224
);
endmodule

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Clock Mux.
//
// SVN Revision Information:
// SVN $Revision: 23983 $
// SVN $Date: 2014-11-28 23:42:46 +0530 (Fri, 28 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
module spi_clockmux ( input sel,
input clka,
input clkb,
output reg clkout
);
always @(*)
begin
case (sel)
1'b0 : clkout = clka;
1'b1 : clkout = clkb;
default : clkout = clka;
endcase
end
endmodule

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Top level control.
//
// SVN Revision Information:
// SVN $Revision: 23983 $
// SVN $Date: 2014-11-28 23:42:46 +0530 (Fri, 28 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
module spi_control # (
parameter CFG_FRAME_SIZE = 4
)(
input aresetn,
input sresetn,
input psel,
input penable,
input pwrite,
input [6:0] paddr,
input [CFG_FRAME_SIZE-1:0] wr_data_in,
input cfg_master,
input rx_fifo_empty,
input tx_fifo_empty,
output [CFG_FRAME_SIZE-1:0] tx_fifo_data,
output tx_fifo_write,
output tx_fifo_last,
output rx_fifo_read
);
//######################################################################################################
reg tx_fifo_write_sig;
reg rx_fifo_read_sig;
reg tx_last_frame_sig;
// Output assignments.
assign tx_fifo_last = tx_last_frame_sig;
assign tx_fifo_data = wr_data_in;
assign tx_fifo_write = tx_fifo_write_sig;
assign rx_fifo_read = rx_fifo_read_sig;
// Note combinational generation of FIFO read and write signals
always @(*)
begin
//defaults
rx_fifo_read_sig = 1'b0; //default no read on rx fifo
tx_fifo_write_sig = 1'b0; //default no write on tx fifo
tx_last_frame_sig = 1'b0; //default not last frame
if (penable && psel)
begin
case (paddr) //synthesis parallel_case
6'h0C: //write to transmit fifo
begin
if (pwrite)
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
end
end
6'h08: //read from receive fifo
begin
if (~pwrite)
begin
rx_fifo_read_sig = 1'b1;
end
end
6'h28: // aliased transmit data, sets last frame bit
begin
if(pwrite)
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
tx_last_frame_sig = 1'b1; //last frame
end
end
default:
begin
end
endcase
end
end
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Synchronous Fifo
//
//
// SVN Revision Information:
// SVN $Revision: 28014 $
// SVN $Date: 2016-11-24 20:43:31 +0530 (Thu, 24 Nov 2016) $
//
// Resolved SARs
// SAR Date Who Description
//
//
// *********************************************************************/
module spi_fifo( pclk,
aresetn,
sresetn,
fiforst,
data_in,
flag_in,
data_out,
flag_out,
read_in,
write_in,
full_out,
empty_out,
full_next_out,
empty_next_out,
overflow_out,
fifo_count
);
parameter CFG_FRAME_SIZE = 4; // 4-32
parameter CFG_FIFO_DEPTH = 4; // 2,4,8,16,32
localparam PTR_WIDTH = log2(CFG_FIFO_DEPTH);
input pclk;
input aresetn;
input sresetn;
input fiforst;
input [CFG_FRAME_SIZE-1:0] data_in;
input read_in;
input write_in;
input flag_in;
output [CFG_FRAME_SIZE-1:0] data_out;
output empty_out;
output full_out;
output empty_next_out;
output full_next_out;
output overflow_out;
output flag_out;
output [5:0] fifo_count;
reg [PTR_WIDTH - 1:0] rd_pointer_d;
reg [PTR_WIDTH - 1:0] rd_pointer_q; //read pointer address
reg [PTR_WIDTH - 1:0] wr_pointer_d;
reg [PTR_WIDTH - 1:0] wr_pointer_q; //write pointer address
reg [5:0] counter_d;
reg [5:0] counter_q; //counter 5 bits
reg [CFG_FRAME_SIZE:0] fifo_mem_d[0:CFG_FIFO_DEPTH-1]; //FIFO has extra flag bit (CFG_FRAME_SIZE + 1)
reg [CFG_FRAME_SIZE:0] fifo_mem_q[0:CFG_FIFO_DEPTH-1];
reg [CFG_FRAME_SIZE:0] data_out_dx;
reg [CFG_FRAME_SIZE:0] data_out_d;
reg full_out;
reg empty_out;
reg full_next_out;
reg empty_next_out;
wire [CFG_FRAME_SIZE-1:0] data_out = data_out_d[CFG_FRAME_SIZE-1:0];
wire flag_out = data_out_d[CFG_FRAME_SIZE];
assign overflow_out = (write_in && (counter_q == CFG_FIFO_DEPTH)); /* write and fifo full */
integer i;
//------------------------------------------------------------------------------------------------------------
//infer the FIFO - no reset required
always @(posedge pclk)
begin
for (i=0; i<CFG_FIFO_DEPTH; i=i+1)
begin
fifo_mem_q[i] <= fifo_mem_d[i];
end
end
//infer the registers and register the flags
always @(posedge pclk or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
rd_pointer_q <= 0;
wr_pointer_q <= 0;
counter_q <= 0;
full_out <= 0;
empty_out <= 1;
full_next_out <= 0;
empty_next_out <= 0;
end
else
begin
rd_pointer_q <= rd_pointer_d;
wr_pointer_q <= wr_pointer_d;
counter_q <= counter_d;
full_out <= (counter_d == CFG_FIFO_DEPTH); //is next pointer equal to fifo length
empty_out <= (counter_d == 0);
full_next_out <= (counter_q == CFG_FIFO_DEPTH-1);
empty_next_out <= (counter_q == 1);
end
end
integer j;
always @(*)
begin
for (j=0; j<CFG_FIFO_DEPTH; j=j+1) // Hold old values
begin
fifo_mem_d[j] = fifo_mem_q[j];
end
if (write_in)
begin
if (counter_q != CFG_FIFO_DEPTH)
begin
fifo_mem_d[wr_pointer_q[PTR_WIDTH -1:0]][CFG_FRAME_SIZE-1:0] = data_in[CFG_FRAME_SIZE-1:0];
fifo_mem_d[wr_pointer_q[PTR_WIDTH -1:0]][CFG_FRAME_SIZE] = flag_in;
end
end
//Read - data out always available
data_out_dx = fifo_mem_q[rd_pointer_q[PTR_WIDTH - 1:0]];
end
// Perform extra read mux on Byte/Half wide reads
always @(*)
begin
// flag bits are zero if count zero
data_out_d = data_out_dx[CFG_FRAME_SIZE:0];
if (counter_q == 0) data_out_d[CFG_FRAME_SIZE] = 1'b0;
end
// Pointers and Flags
always @(*)
begin
if (fiforst==1'b1)
begin
wr_pointer_d = 0;
rd_pointer_d = 0;
counter_d = 6'b000000;
end
else
begin
//defaults
counter_d = counter_q;
rd_pointer_d = rd_pointer_q;
wr_pointer_d = wr_pointer_q;
if (read_in)
begin
if (counter_q != 0) // ignore read when empty
begin
if (~write_in) //if not writing decrement count of the number of objects in fifo else count stays the same
begin
counter_d = counter_q - 1'b1;
end
if (rd_pointer_q == CFG_FIFO_DEPTH - 1)
rd_pointer_d = 0;
else
rd_pointer_d = rd_pointer_q + 1'b1;
end
end //~read_n
if (write_in)
begin
if (counter_q != CFG_FIFO_DEPTH) // ignore write when full
begin
if (~read_in)
begin
counter_d = counter_q + 1'b1;
end
if (wr_pointer_q == CFG_FIFO_DEPTH-1)
wr_pointer_d = 0;
else
wr_pointer_d = wr_pointer_q + 1'b1;
end //~write_n
end
end
end
wire [5:0] fifo_count = counter_q;
function [31:0] log2;
input integer N;
integer tmp, res;
begin
tmp = 1;
res = 0;
while (tmp < N) begin
tmp = tmp*2;
res = res+1;
end
log2 = res;
end
endfunction
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Register file
//
//
// SVN Revision Information:
// SVN $Revision: 31320 $
// SVN $Date: 2018-02-16 12:53:27 +0530 (Fri, 16 Feb 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94224: Add dynamic clcok configuration feature for generated
// master SPI clock
//
// Notes:
//
//
// *********************************************************************/
module spi_rf # (
parameter APB_DWIDTH = 8,
parameter CFG_CLK = 7 // 94224
)( //APB Access to registers
input pclk,
input aresetn,
input sresetn,
input [6:0] paddr,
input psel,
input pwrite,
input penable,
input [APB_DWIDTH-1:0] wrdata,
output [APB_DWIDTH-1:0] prdata,
output interrupt,
//Hardware Status
input tx_channel_underflow,
input rx_channel_overflow,
input tx_done,
input rx_done,
input rx_fifo_read,
input tx_fifo_read,
input tx_fifo_write,
input rx_fifo_full,
input rx_fifo_full_next,
input rx_fifo_empty,
input rx_fifo_empty_next,
input tx_fifo_full,
input tx_fifo_full_next,
input tx_fifo_empty,
input tx_fifo_empty_next,
input first_frame,
input ssel,
input active,
input rx_pktend,
input rx_cmdsize,
//Static Configuration Outputs
output cfg_enable,
output cfg_master,
output reg [7:0] cfg_ssel,
output [2:0] cfg_cmdsize,
output cfg_oenoff,
//Strobe Outputs, will change during operation
output reg clr_txfifo,
output reg clr_rxfifo,
output cfg_frameurun,
output [7:0] clk_div_val // 94224
);
reg [7:0] control1;
reg [7:0] control2;
wire [5:0] command;
wire [7:0] int_masked;
reg [7:0] int_raw;
wire [7:0] status_byte;
reg [1:0] sticky;
reg [7:0] CLK_DIV; // 94224
reg [APB_DWIDTH-1:0] rdata;
// -----------------------------------------------------------------------------------------------------------------------
// Registers with sticky bits (The interrupt register)
assign int_masked = {
(int_raw[7] && control2[7]), // !tx_fifo_full
(int_raw[6] && control2[6]), // !rx_fifo_empty
(int_raw[5] && control2[5]), // ssend
(int_raw[4] && control2[4]), // cmdint
(int_raw[3] && control1[5]), // txunderrun
(int_raw[2] && control1[4]), // rxoverflow
(1'b0),
(int_raw[0] && control1[3]) // txdone
};
assign interrupt = int_masked[7] || int_masked[6] || int_masked[5] || int_masked[4] ||
int_masked[3] || int_masked[2] || int_masked[1] || int_masked[0] ;
// ############################################################################################################
// Create Register Values
assign status_byte = { active,
ssel,
int_raw[3],
int_raw[2],
tx_fifo_full,
rx_fifo_empty,
(sticky[0] && sticky[1]),
first_frame
};
assign command = 8'h00;
// ############################################################################################################
// Writes.
integer i;
always @(posedge pclk or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
control1 <= 8'h00;
cfg_ssel <= 8'h00;
control2 <= 8'h00;
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
int_raw <= 8'h80;
sticky <= 2'b00;
CLK_DIV <= CFG_CLK; // 94224
end
else
begin
//------------------------------------------------------------------------
// Hardware Events lower priority than CPU activities
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
//-----------------------------------------------------------------------
// CPU Writes
if (psel & pwrite & penable)
begin
case (paddr) //synthesis parallel_case
7'h00: begin
control1[7:0] <= wrdata[7:0];
end
7'h04: begin
for (i=0; i<8; i=i+1) if (wrdata[i]) int_raw[i] <= 1'b0;
end
7'h18: begin
control2 <= wrdata[7:0];
end
7'h1c: begin
clr_rxfifo <= wrdata[0];
clr_txfifo <= wrdata[1];
end
7'h24: cfg_ssel <= wrdata[7:0];
7'h2C: CLK_DIV <= wrdata[7:0]; // 94224
default: begin end
endcase
//if we were enabled don't allow various changes
end
//------------------------------------------------------------------------
// Hardware Events higher priority than CPU activities
// Sticky Status Bits
if (tx_done) sticky[0] <= 1'b1;
if (rx_done) sticky[1] <= 1'b1;
if (tx_fifo_write) sticky[0] <= 1'b0;
if (rx_fifo_read) sticky[1] <= 1'b0;
// Interrupt Settings
if (tx_done) int_raw[0] <= 1'b1;
if (rx_done) int_raw[1] <= 1'b1;
if (rx_channel_overflow) int_raw[2] <= 1'b1;
if (tx_channel_underflow) int_raw[3] <= 1'b1;
if (rx_cmdsize) int_raw[4] <= 1'b1;
if (rx_pktend) int_raw[5] <= 1'b1;
if (!rx_fifo_empty) int_raw[6] <= 1'b1;
if (!tx_fifo_full) int_raw[7] <= 1'b1;
control2[3] <= 1'b0;
end
end
// clk division value in CLK_DIV register
assign clk_div_val[7:0] = CLK_DIV[7:0]; // 94224
// 5:2 are interrupt enables
assign cfg_enable = control1[0];
assign cfg_master = control1[1];
assign cfg_frameurun = control1[6];
assign cfg_oenoff = control1[7];
assign cfg_cmdsize = control2[2:0];
// ############################################################################################################
// Reads, purely combinational of the PADDR.
localparam [APB_DWIDTH-1:0] ZEROS = {(APB_DWIDTH){1'b0}};
always @(*)
begin
if (psel)
begin
rdata = ZEROS;
case (paddr) //synthesis parallel_case
7'h00: rdata[7:0] = control1[7:0]; // control register 1
7'h04: rdata[7:0] = 8'h00; // write-only
// 0x08 assigned elsewhere
7'h0C: rdata[7:0] = 8'h00; // write-only
7'h10: rdata[7:0] = int_masked[7:0]; // masked interrupt register
7'h14: rdata[7:0] = int_raw[7:0]; // raw interrupt register
7'h18: rdata[7:0] = control2[7:0]; // control register 2
7'h20: rdata[7:0] = status_byte[7:0]; // status register
7'h24: rdata[7:0] = cfg_ssel[7:0]; // slave select register
7'h2C: rdata[7:0] = CLK_DIV[7:0]; // 94224 - dynamic clock configuration register
default: rdata = ZEROS;
endcase
end
else
rdata = ZEROS;
end
assign prdata = ( (psel && penable) ? rdata : ZEROS);
endmodule

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`timescale 1ns/1ns
// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// CoreSPI User Testbench
//
//
// SVN Revision Information:
// SVN $Revision: 23762 $
// SVN $Date: 2014-11-11 08:01:54 -0800 (Tue, 11 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
//
// *********************************************************************/
module testbench();
`include "../../../../coreparameters.v"
reg SYSCLK;
reg SYSRSTN;
wire PCLK;
wire PRESETN;
wire [31:0] PADDR;
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA;
wire [31:0] PRDATA;
wire [31:0] PRDATA_0;
wire [31:0] PRDATA_1;
wire [15:0] PSEL;
wire [255:0] INTERRUPT;
wire [31:0] GP_OUT;
wire [31:0] GP_IN;
wire FINISHED;
wire FAILED;
wire Logic0 = 1'b0;
wire Logic1 = 1'b1;
// ********************************************************************************
// Clocks and Reset
initial
begin
SYSRSTN <= 1'b0;
#100;
SYSRSTN <= 1'b1;
end
// Clock is 100MHz
always
begin
SYSCLK <= 1'b0;
#5;
SYSCLK <= 1'b1;
#5;
end
initial
begin
// wait until all BFM's are finished
wait(FINISHED === 1'b1);
$stop;
$finish;
end
// ********************************************************************************
// APB Master
CORESPI_BFM_APB #(.VECTFILE ("user_tb.vec") )
UBFM (.SYSCLK (SYSCLK),
.SYSRSTN (SYSRSTN),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA),
.PREADY (Logic1),
.PSLVERR (Logic0),
.PSEL (PSEL),
.INTERRUPT (INTERRUPT),
.GP_OUT (GP_OUT),
.GP_IN (GP_IN),
.EXT_WR (),
.EXT_RD (),
.EXT_ADDR (),
.EXT_DATA (),
.EXT_WAIT (Logic0),
.CON_ADDR (),
.CON_DATA (),
.CON_RD (Logic0),
.CON_WR (Logic0),
.CON_BUSY (),
.FINISHED (FINISHED),
.FAILED (FAILED)
);
assign PRDATA = ( PSEL[1] ? PRDATA_1 : PRDATA_0) ;
/* #############################################################################
SPIINT Output interrupt
SPISDO Output serial data out (generated by SPI as master)
SPISS[7:0] Output slave select (generated by SPI as master)
SPISCLKO Output shift clock out (generated by SPI as master)
SPISDI Input shift data in (master or slave)
SPIRXAVAIL Output request for data to be read - rx data available
SPITXRFM Output indicates transmit done - ready for more
SPISSI Input slave select (when SPI in slave mode)
SPIOEN Output output enable (when de-asserted output pad for SPISDO tri-stated). This is active when the SPI is writing output data and deactivated when there is not data to write. This signal is active high.
SPIMode Output mode: (when 1, SPI is master, when 0, SPI is slave)
*/
// ********************************************************************************
// SPI Core - Master
wire [7:0] M_SPISS;
CORESPI # (
//.FAMILY (FAMILY),
.APB_DWIDTH (32),
.CFG_FRAME_SIZE (32),
.CFG_FIFO_DEPTH (4),
.CFG_CLK (3),
.CFG_MODE (0),
.CFG_MOT_MODE (0),
.CFG_MOT_SSEL (0),
.CFG_TI_NSC_CUSTOM (0),
.CFG_TI_NSC_FRC (0),
.CFG_TI_JMB_FRAMES (0),
.CFG_NSC_OPERATION (0)
)USPIM ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[0]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_0),
.SPISSI (),
.SPISDI (S_SPISDO),
.SPICLKI (),
.SPISS (M_SPISS),
.SPISCLKO (M_SPISCLKO),
.SPIOEN (M_SPIOEN),
.SPISDO (M_SPISDO),
.SPIINT (GP_IN[0]),
.SPIRXAVAIL (),
.SPITXRFM (),
.SPIMODE (),
.PREADY (),
.PSLVERR ()
);
// ********************************************************************************
// SPI Core - Slave
wire [7:0] S_SPISS;
CORESPI # (
//.FAMILY (FAMILY),
.APB_DWIDTH (32),
.CFG_FRAME_SIZE (32),
.CFG_FIFO_DEPTH (4),
.CFG_CLK (3),
.CFG_MODE (0),
.CFG_MOT_MODE (0),
.CFG_MOT_SSEL (0),
.CFG_TI_NSC_CUSTOM (0),
.CFG_TI_NSC_FRC (0),
.CFG_TI_JMB_FRAMES (0),
.CFG_NSC_OPERATION (0)
) USPIS ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[1]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_1),
.SPISSI (M_SPISS[0]),
.SPISDI (M_SPISDO),
.SPICLKI (M_SPISCLKO),
.SPISS (),
.SPISCLKO (),
.SPIOEN (),
.SPISDO (S_SPISDO),
.SPIINT (GP_IN[1]),
.SPIRXAVAIL (),
.SPITXRFM (),
.SPIMODE (),
.PREADY (),
.PSLVERR ()
);
endmodule