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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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6
synthesis/top_scck.rpt
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@@ -12,7 +12,7 @@ Hostname: SOFTWARE-PC
Implementation : synthesis
# Written on Wed Apr 15 22:47:57 2026
# Written on Fri Apr 17 08:31:46 2026
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc"
@@ -33,7 +33,7 @@ Clock Summary
Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 4979
2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
@@ -62,7 +62,7 @@ Clock Load Summary
Clock Load Pin Seq Example Seq Example Comb Example
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 4979 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PHY_MDC_CLOCK 0 - - - -
REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)