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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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synthesis/synwork/layer0.fdep
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@@ -4,7 +4,7 @@
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\hypermods.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_objects.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_pipes.svh":1745942006
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776273292
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776394635
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_graytobinconv.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_nstagessync.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_async.v":1776257512
@@ -70,22 +70,22 @@
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_IOD_CDR_CCC_C0.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776273031
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776394591
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776273264
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776394606
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
#numinternalfiles:4
#defaultlanguage:verilog
0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog