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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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16
synthesis/syntmp/cmdrec_compiler.log
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synthesis/syntmp/cmdrec_fpga_mapper.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -sap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -otap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.tap -omap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -multisrs -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -sap ..\top.sap -otap ..\top.tap -omap ..\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile ..\scratchproject.prs -multisrs -ovm ..\top.vm -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_prem.srd -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\top.srm -prjdir ..\ -prjname top_syn -log ..\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
rc:1 success:1 runtime:236
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
rc:1 success:1 runtime:243
file:..\top.sap|io:o|time:1776394919|size:51527|exec:0|csum:
file:..\top.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\top.map|io:o|time:1776273723|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776273719|size:6264001|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_prem.srd|io:i|time:1776273483|size:1522539|exec:0|csum:DB252AC6E8654F85B7F9005EEC2CBE52
file:..\top.map|io:o|time:1776395162|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776384319|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776395157|size:6235009|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776394635|size:5771|exec:0|csum:9EDD738B22E99016375E4F77A1872003
file:..\synwork\top_prem.srd|io:i|time:1776394914|size:1529678|exec:0|csum:91328E69BFC4CE6776C8382E8503965D
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273723|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776273714|size:28753|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776273723|size:628611|exec:0|csum:
file:top.plg|io:o|time:1776395162|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776395151|size:29573|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776395162|size:618665|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

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synthesis/syntmp/cmdrec_multi_srs_gen.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_multi_srs_gen.srr
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs ..\synwork\top_comp.srs -osyn ..\synwork\top_mult.srs -log ..\synlog\top_multi_srs_gen.srr
rc:0 success:1 runtime:3
file:..\synwork\top_comp.srs|io:i|time:1776273468|size:2498683|exec:0|csum:D55B0D932EA25F21DF76D09F4D077B94
file:..\synwork\top_mult.srs|io:o|time:1776273473|size:16492|exec:0|csum:
file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776273473|size:1172|exec:0|csum:
file:..\synwork\top_comp.srs|io:i|time:1776394897|size:2499581|exec:0|csum:34E574B8FDFA67D505F4D20299B516A9
file:..\synwork\top_mult.srs|io:o|time:1776394902|size:16470|exec:0|csum:
file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776394902|size:1172|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\syn_nfilter.exe|io:i|time:1745943928|size:10549248|exec:1|csum:0E24E2994826988AAC59CDBFBC24908C

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synthesis/syntmp/cmdrec_premap.log
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -flow prepass -gcc_prepass -osrd E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -qsap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -conchk_prepass E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile ..\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -flow prepass -gcc_prepass -osrd ..\synwork\top_prem.srd -qsap ..\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm ..\top.vm -conchk_prepass ..\top_cck.rpt -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_mult.srs -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\synwork\top_prem.srd -prjdir ..\ -prjname top_syn -log ..\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
rc:1 success:1 runtime:15
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.vm|io:o|time:1776270794|size:6521569|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776273487|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_mult.srs|io:i|time:1776273473|size:16492|exec:0|csum:8A8FBA27CAD8D4F9ABE7B311078B4CA3
rc:1 success:1 runtime:17
file:..\scratchproject.prs|io:o|time:1776384319|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776394914|size:1529678|exec:0|csum:
file:..\top.sap|io:o|time:1776394919|size:51527|exec:0|csum:
file:..\top.vm|io:o|time:1776391490|size:6226755|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776394918|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776394635|size:5771|exec:0|csum:9EDD738B22E99016375E4F77A1872003
file:..\synwork\top_mult.srs|io:i|time:1776394902|size:16470|exec:0|csum:A940EB393DE3FFFAE7080C27C1364F80
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273475|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776273488|size:50209|exec:0|csum:
file:top.plg|io:o|time:1776394904|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776394914|size:1529678|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776394919|size:49976|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

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library ieee;
use ieee.std_logic_1164.all;
package genpackage is
end package genpackage;

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library ieee;
use ieee.std_logic_1164.all;
use work.genpackage.all;
entity top is
port (
EQ : out std_logic;
A : in std_logic_vector(12 downto 0);
B : in std_logic_vector(12 downto 0) );
end entity top;
architecture gen of top is
component CMP_EQ
generic (
width : integer );
port (
EQ : out std_logic;
A : in std_logic_vector;
B : in std_logic_vector );
end component;
begin
I1: CMP_EQ
generic map (
width => 13 )
port map (
EQ => EQ,
A => A,
B => B );
end architecture gen;

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<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
</pre></samp></body></html>

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###########################################################[
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
Synopsys VHDL Compiler, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @
@N|Running in 64-bit mode
@I:: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\genpkg2735a42304"
@I:: "syng0a42304"
@I:: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp2735a42304"
VHDL syntax check successful!

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Synopsys, Inc.
Version V-2023.09M-5
Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\run_option.xml
Written on Wed Apr 15 22:44:56 2026
Written on Fri Apr 17 08:27:18 2026
-->

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<td>403</td>
<td>0</td>
<td>-</td>
<td>02m:53s</td>
<td>04m:18s</td>
<td>-</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (premap)</td><td>Complete</td>
<td>65</td>
<td>64</td>
<td>15</td>
<td>0</td>
<td>0m:13s</td>
<td>0m:13s</td>
<td>365MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:48 PM</font></td>
<td>0m:15s</td>
<td>0m:15s</td>
<td>366MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
<td>103</td>
<td>102</td>
<td>120</td>
<td>0</td>
<td>03m:51s</td>
<td>03m:54s</td>
<td>521MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:52 PM</font></td>
<td>03m:58s</td>
<td>04m:02s</td>
<td>564MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:36 AM</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
@@ -74,8 +74,8 @@
<tfoot> <tr> <td class="optionTitle" colspan="2"></td><td class="optionTitle" colspan="2"></td></tr>
</tfoot>
<tbody> <tr>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2335</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7316</td>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2263</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7208</td>
</tr>
<tr>
<td title ="Total DSP Blocks used" class="optionTitle" align="left">DSP Blocks
@@ -85,13 +85,13 @@
<tr>
<td title ="Total Global Clock Buffers used" class="optionTitle" align="left">Global Clock Buffers</td> <td>7</td>
<td title ="Total RAM1K20 used" class="optionTitle" align="left">RAM1K20
(v_ram)</td> <td>34</td>
(v_ram)</td> <td>36</td>
</tr>
<tr>
<td title ="Total RAM64x12 used" class="optionTitle" align="left">RAM64x12
(v_ram)</td> <td>11</td>
<td title ="Total LUTs used" class="optionTitle" align="left">LUTs
(total_luts)</td> <td>15992</td>
(total_luts)</td> <td>15852</td>
</tr>
</tbody>
@@ -103,14 +103,14 @@
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</td><td align="left">100.0 MHz</td><td align="left">13.4 MHz</td><td align="left">-32.246</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.0 MHz</td><td align="left">-5.671</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.1 MHz</td><td align="left">-5.638</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</td><td align="left">125.0 MHz</td><td align="left">116.7 MHz</td><td align="left">-0.228</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">230.3 MHz</td><td align="left">3.659</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">225.1 MHz</td><td align="left">3.557</td></tr>
<tr> <td align="left">PHY_MDC_CLOCK</td><td align="left">2.9 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REFCLK_P</td><td align="left">125.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REF_CLK_0</td><td align="left">50.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>

18
synthesis/syntmp/top.plg
View File

@@ -4,11 +4,11 @@
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Period : 74.491
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Period : 10.000
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Slack : -32.246
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.1 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Frequency : 80.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.171
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.138
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Period : 12.500
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.671
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.638
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Frequency : 116.7 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Period : 8.569
@@ -39,11 +39,11 @@
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 230.3 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 225.1 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.341
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.443
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Period : 8.000
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.659
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.557
@P: PHY_MDC_CLOCK - Estimated Frequency : NA
@P: PHY_MDC_CLOCK - Requested Frequency : 2.9 MHz
@P: PHY_MDC_CLOCK - Estimated Period : NA
@@ -70,9 +70,9 @@
@P: System - Requested Period : 10.000
@P: System - Slack : -27.793
@P: top Part : mpf300tfcg1152-1
@P: top Register bits : 7316
@P: top Register bits : 7208
@P: top DSP Blocks : 0
@P: top I/O primitives : 50
@P: top RAM1K20 : 34
@P: top RAM1K20 : 36
@P: top RAM64x12 : 11
@P: CPU Time : 0h:03m:50s
@P: CPU Time : 0h:03m:58s

4
synthesis/syntmp/top_cck_rpt.htm
View File

@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
@@ -14,7 +14,7 @@ Hostname: SOFTWARE-PC
Implementation : synthesis
# Written on Wed Apr 15 22:48:07 2026
# Written on Fri Apr 17 08:31:58 2026
##### DESIGN INFO #######################################################

2
synthesis/syntmp/top_dsp_rpt_txt.htm
View File

@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
##### START OF DSP REPORT #####

6
synthesis/syntmp/top_fanout_rpt_txt.htm
View File

@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
######## REPORT FOR HIGH FANOUT NETS ########
@@ -9,8 +9,8 @@ GLOBAL THRESHOLD - 5000
NET NAME CLOCK LOADS ASYNC RST LOADS SYNC RST LOADS ENABLE LOADS DATA LOADS TOTAL FANOUT GLOBAL BUFFER PRESENT
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PF_CCC_0_0_OUT0_FABCLK_0 4701 0 0 0 0 4701 YES
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1288 0 0 0 0 1288 YES
PF_CCC_0_0_OUT0_FABCLK_0 4612 0 0 0 0 4612 YES
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1273 0 0 0 0 1273 YES
PF_IOD_CDR_C0_0_RX_CLK_R 1252 0 0 0 0 1252 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0_TGT_TCK_0_i 205 0 0 0 0 205 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK 17 0 0 0 1 18 YES

12
synthesis/syntmp/top_ram_rpt_txt.htm
View File

@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
##### START OF RAM REPORT #####
@@ -14,7 +14,7 @@ NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_4 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_5 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_6 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 1(1/1/1) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io[39:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_0 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_1 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
@@ -61,9 +61,13 @@ YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
=====================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### URAM REPORT #####

4368
synthesis/syntmp/top_srr.htm
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File diff suppressed because it is too large Load Diff

12
synthesis/syntmp/top_toc.htm
View File

@@ -38,19 +38,19 @@
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport47" target="srrFrame" title="">Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport51" target="srrFrame" title="">Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport55" target="srrFrame" title="">Clock: System</a> </li></ul></li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (22:49 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (08:33 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#resourceUsage59" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (22:48 15-Apr)</a>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (08:31 17-Apr)</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#UnconstrainedStartEndPointsCCK60" target="srrFrame" title="">Unconstrained Start/End Points</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#InapplicableconstraintsCCK61" target="srrFrame" title="">Inapplicable constraints</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ApplicableConstraintsWithIssuesCCK62" target="srrFrame" title="">Applicable constraints with issues</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ConstraintsWithMatchingWildcardExpressionsCCK63" target="srrFrame" title="">Constraints with matching wildcard expressions</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#LibraryReportCCK64" target="srrFrame" title="">Library Report</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (22:52 15-Apr)</a> </li></ul></li> </ul>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (08:36 17-Apr)</a> </li></ul></li> </ul>
</li>
</ul>

54
synthesis/syntmp/traplog.tlg
View File

@@ -1,24 +1,24 @@
@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a42256":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a42256":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a42256":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a42256":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a42256":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a38936":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a38936":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a38936":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a38936":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a38936":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Running optimization stage 1 on MUXCY_L .......
Finished optimization stage 1 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
@@ -27,15 +27,15 @@ Running optimization stage 1 on eq_element .......
Finished optimization stage 1 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Post processing for work.cmp_eq.cell_level
Running optimization stage 1 on CMP_EQ .......
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Post processing for work.top.gen
Running optimization stage 1 on top .......
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on MUXCY_L .......
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on eq_element .......
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on CMP_EQ .......
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on top .......
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)

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synthesis/syntmp/traplog.tlg.db
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 07:31:32 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 16:34:33 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 08:32:34 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 19:57:37 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 06:35:28 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 17:14:46 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
synthesis/syntmp/vhdlsyn1992a47704_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 05:40:16 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
synthesis/syntmp/vhdlsyn1992a49188_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 18:18:38 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
synthesis/syntmp/vhdlsyn1992a50672_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 13:33:59 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
synthesis/syntmp/vhdlsyn2479a31412_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 07:31:38 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 16:34:41 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
synthesis/syntmp/vhdlsyn2479a38936_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 08:32:40 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 19:57:44 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 06:35:35 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 17:14:54 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 05:40:22 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 18:18:45 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 13:34:06 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(14 downto 0);
B : in std_logic_vector(14 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (14 downto 0);
B : in std_logic_vector (14 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (14 downto 0);
signal tmp_B : std_logic_vector (14 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 07:31:27 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 16:34:29 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 08:32:29 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 19:57:32 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 06:35:24 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 17:14:41 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 05:40:12 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 18:18:33 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 13:33:54 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (15 downto 0);
B : in std_logic_vector (15 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (15 downto 0);
signal tmp_B : std_logic_vector (15 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 07:31:43 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 16:34:46 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 08:32:45 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 19:57:48 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 06:35:40 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 18:14:12 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(11 downto 0);
B : in std_logic_vector(11 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (11 downto 0);
B : in std_logic_vector (11 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (11 downto 0);
signal tmp_B : std_logic_vector (11 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 17:14:59 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

47
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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 05:40:27 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 18:18:51 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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--
-- Synopsys
-- Vhdl wrapper for top level design, written on Thu Apr 16 13:34:13 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (31 downto 0);
B : in std_logic_vector (31 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (31 downto 0);
signal tmp_B : std_logic_vector (31 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;