abhishek/Ethernet-IP-Core
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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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synthesis/synplify.log.bak.1
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@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 20:20:12 2026
Date: Fri Apr 17 06:30:17 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,26 +45,26 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 20:23:56 2026
# Fri Apr 17 06:34:36 2026
Return Code: 0
Run Time:00h:03m:42s
Run Time:00h:04m:17s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 20:23:56 2026
# Fri Apr 17 06:34:36 2026
multi_srs_gen completed
# Wed Apr 15 20:23:59 2026
# Fri Apr 17 06:34:39 2026
Return Code: 0
Run Time:00h:00m:03s
@@ -72,28 +72,28 @@ Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs t
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 20:23:59 2026
# Fri Apr 17 06:34:39 2026
premap completed with warnings
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
Return Code: 1
Run Time:00h:00m:14s
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 20:28:51 2026
# Fri Apr 17 06:38:46 2026
Return Code: 1
Run Time:00h:04m:38s
Run Time:00h:03m:50s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"