abhishek/Ethernet-IP-Core
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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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16
designer/top/place_route.sdc
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@@ -1,5 +1,5 @@
# Microchip Technology Inc.
# Date: 2026-Apr-15 22:52:43
# Date: 2026-Apr-17 08:36:48
# This file was generated based on the following SDC source files:
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc
@@ -50,31 +50,31 @@ set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pl
set_clock_uncertainty 0.000992228 [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -rise_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -fall_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
set_clock_uncertainty 0.00483062 [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty 0.00478087 [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PHY_MDC_CLOCK } ] -rise_to [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PHY_MDC_CLOCK } ] -fall_to [ get_clocks { PHY_MDC_CLOCK } ]
set_clock_uncertainty 0.00483062 [ get_clocks { REFCLK_P } ]
set_clock_uncertainty 0.00478087 [ get_clocks { REFCLK_P } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REFCLK_P } ] -rise_to [ get_clocks { REFCLK_P } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REFCLK_P } ] -fall_to [ get_clocks { REFCLK_P } ]
set_clock_uncertainty 0.00483062 [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty 0.00478087 [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REF_CLK_0 } ] -rise_to [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REF_CLK_0 } ] -fall_to [ get_clocks { REF_CLK_0 } ]
set_clock_uncertainty 0.00483062 [ get_clocks { TCK } ]
set_clock_uncertainty 0.00478087 [ get_clocks { TCK } ]
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { TCK } ] -rise_to [ get_clocks { TCK } ]
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { TCK } ] -fall_to [ get_clocks { TCK } ]
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]