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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.cxf
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@@ -1 +1 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./PF_TPSRAM_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./PF_TPSRAM_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/SgCore/PF_TPSRAM/1.1.108/PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./PF_TPSRAM_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="SgCore" name="PF_TPSRAM" vendor="Actel" version="1.1.108"/><configuration><configurableElement referenceId="A_DOUT_EN_PN" value="R_DATA_EN"/><configurableElement referenceId="A_DOUT_EN_POLARITY" value="2"/><configurableElement referenceId="A_DOUT_SRST_PN" value="R_DATA_SRST_N"/><configurableElement referenceId="A_DOUT_SRST_POLARITY" value="2"/><configurableElement referenceId="A_WBYTE_EN_PN" value="WBYTE_EN"/><configurableElement referenceId="BUSY_FLAG" value="0"/><configurableElement referenceId="BYTE_ENABLE_WIDTH" value="0"/><configurableElement referenceId="BYTEENABLES" value="0"/><configurableElement referenceId="CASCADE" value="0"/><configurableElement referenceId="CLK_EDGE" value="RISE"/><configurableElement referenceId="CLKS" value="1"/><configurableElement referenceId="CLOCK_PN" value="CLK"/><configurableElement referenceId="DATA_IN_PN" value="W_DATA"/><configurableElement referenceId="DATA_OUT_PN" value="R_DATA"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="IMPORT_FILE" value=""/><configurableElement referenceId="INIT_RAM" value="F"/><configurableElement referenceId="LPM_HINT" value="0"/><configurableElement referenceId="LPMTYPE" value="LPM_RAM"/><configurableElement referenceId="PMODE2" value="0"/><configurableElement referenceId="PTYPE" value="1"/><configurableElement referenceId="RADDRESS_PN" value="R_ADDR"/><configurableElement referenceId="RCLK_EDGE" value="RISE"/><configurableElement referenceId="RCLOCK_PN" value="R_CLK"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_PN" value="R_EN"/><configurableElement referenceId="RE_POLARITY" value="2"/><configurableElement referenceId="RESET_PN" value="R_DATA_ARST_N"/><configurableElement referenceId="RESET_POLARITY" value="2"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SD_EXPORT_HIDDEN_PORTS" value="false"/><configurableElement referenceId="SII_LOCK" value="0"/><configurableElement referenceId="WADDRESS_PN" value="W_ADDR"/><configurableElement referenceId="WCLK_EDGE" value="RISE"/><configurableElement referenceId="WCLOCK_PN" value="W_CLK"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_PN" value="W_EN"/><configurableElement referenceId="WE_POLARITY" value="1"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>W_EN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_ADDR</name><direction>in</direction><left>9</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_DATA</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./PF_TPSRAM_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./PF_TPSRAM_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/SgCore/PF_TPSRAM/1.1.108/PF_TPSRAM.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./PF_TPSRAM_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="SgCore" name="PF_TPSRAM" vendor="Actel" version="1.1.108"/><configuration><configurableElement referenceId="A_DOUT_EN_PN" value="R_DATA_EN"/><configurableElement referenceId="A_DOUT_EN_POLARITY" value="2"/><configurableElement referenceId="A_DOUT_SRST_PN" value="R_DATA_SRST_N"/><configurableElement referenceId="A_DOUT_SRST_POLARITY" value="2"/><configurableElement referenceId="A_WBYTE_EN_PN" value="WBYTE_EN"/><configurableElement referenceId="BUSY_FLAG" value="0"/><configurableElement referenceId="BYTE_ENABLE_WIDTH" value="0"/><configurableElement referenceId="BYTEENABLES" value="0"/><configurableElement referenceId="CASCADE" value="0"/><configurableElement referenceId="CLK_EDGE" value="RISE"/><configurableElement referenceId="CLKS" value="1"/><configurableElement referenceId="CLOCK_PN" value="CLK"/><configurableElement referenceId="DATA_IN_PN" value="W_DATA"/><configurableElement referenceId="DATA_OUT_PN" value="R_DATA"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="IMPORT_FILE" value=""/><configurableElement referenceId="INIT_RAM" value="F"/><configurableElement referenceId="LPM_HINT" value="0"/><configurableElement referenceId="LPMTYPE" value="LPM_RAM"/><configurableElement referenceId="PMODE2" value="0"/><configurableElement referenceId="PTYPE" value="1"/><configurableElement referenceId="RADDRESS_PN" value="R_ADDR"/><configurableElement referenceId="RCLK_EDGE" value="RISE"/><configurableElement referenceId="RCLOCK_PN" value="R_CLK"/><configurableElement referenceId="RDEPTH" value="2048"/><configurableElement referenceId="RE_PN" value="R_EN"/><configurableElement referenceId="RE_POLARITY" value="2"/><configurableElement referenceId="RESET_PN" value="R_DATA_ARST_N"/><configurableElement referenceId="RESET_POLARITY" value="2"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SD_EXPORT_HIDDEN_PORTS" value="false"/><configurableElement referenceId="SII_LOCK" value="0"/><configurableElement referenceId="WADDRESS_PN" value="W_ADDR"/><configurableElement referenceId="WCLK_EDGE" value="RISE"/><configurableElement referenceId="WCLOCK_PN" value="W_CLK"/><configurableElement referenceId="WDEPTH" value="2048"/><configurableElement referenceId="WE_PN" value="W_EN"/><configurableElement referenceId="WE_POLARITY" value="1"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>W_EN</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>W_ADDR</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_ADDR</name><direction>in</direction><left>10</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>R_DATA</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.sdb
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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v
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@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:42:58 2026
// Created by SmartDesign Fri Apr 17 05:34:26 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
@@ -38,7 +38,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_TPSRAM:1.1.108} -component
"RADDRESS_PN:R_ADDR" \
"RCLK_EDGE:RISE" \
"RCLOCK_PN:R_CLK" \
"RDEPTH:1024" \
"RDEPTH:2048" \
"RE_PN:R_EN" \
"RE_POLARITY:2" \
"RESET_PN:R_DATA_ARST_N" \
@@ -48,7 +48,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_TPSRAM:1.1.108} -component
"WADDRESS_PN:W_ADDR" \
"WCLK_EDGE:RISE" \
"WCLOCK_PN:W_CLK" \
"WDEPTH:1024" \
"WDEPTH:2048" \
"WE_PN:W_EN" \
"WE_POLARITY:1" \
"WWIDTH:32" }
@@ -71,8 +71,8 @@ module PF_TPSRAM_C0(
// Input
//--------------------------------------------------------------------
input CLK;
input [9:0] R_ADDR;
input [9:0] W_ADDR;
input [10:0] R_ADDR;
input [10:0] W_ADDR;
input [31:0] W_DATA;
input W_EN;
//--------------------------------------------------------------------
@@ -83,9 +83,9 @@ output [31:0] R_DATA;
// Nets
//--------------------------------------------------------------------
wire CLK;
wire [9:0] R_ADDR;
wire [10:0] R_ADDR;
wire [31:0] R_DATA_net_0;
wire [9:0] W_ADDR;
wire [10:0] W_ADDR;
wire [31:0] W_DATA;
wire W_EN;
wire [31:0] R_DATA_net_1;

10
component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.log
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@@ -20,9 +20,9 @@ Read Clock Edge : Rising
Write Clock Edge : Rising
A_REN Polarity : None
B_REN Polarity : None
Write Depth : 1024
Write Depth : 2048
Write Width : 32
Read Depth : 1024
Read Depth : 2048
Read Width : 32
Portname DataIn : W_DATA
Portname DataOut : R_DATA
@@ -72,9 +72,9 @@ Lock access : Off
ACCESS_BUSY : Disabled
Cascade Configuration:
Write Port configuration : 1024x20
Read Port configuration : 1024x20
Write Port configuration : 2048x10
Read Port configuration : 2048x10
Number of blocks depth wise: 1
Number of blocks width wise: 2
Number of blocks width wise: 4
Wrote Verilog netlist to E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v.

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component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v
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@@ -12,71 +12,119 @@ module PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM(
);
input [31:0] W_DATA;
output [31:0] R_DATA;
input [9:0] W_ADDR;
input [9:0] R_ADDR;
input [10:0] W_ADDR;
input [10:0] R_ADDR;
input W_EN;
input CLK;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , \ACCESS_BUSY[0][2] ,
\ACCESS_BUSY[0][3] , VCC, GND, ADLIB_VCC;
wire GND_power_net1;
wire VCC_power_net1;
assign GND = GND_power_net1;
assign VCC = VCC_power_net1;
assign ADLIB_VCC = VCC_power_net1;
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 (.A_DOUT({nc0,
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%2%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 (.A_DOUT({nc0,
nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11,
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc12, nc13,
nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23,
nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][2] ), .A_ADDR({
R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6],
R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1],
R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(
CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC)
, .A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8],
W_ADDR[7], W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3],
W_ADDR[2], W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({
W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, W_DATA[23], W_DATA[22],
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
W_DATA[16]}), .B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 (.A_DOUT({nc24,
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 (.A_DOUT({nc32,
nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40, nc41, nc42,
nc43, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8]}), .B_DOUT({nc44,
nc45, nc46, nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54,
nc55, nc56, nc57, nc58, nc59, nc60, nc61, nc62, nc63}),
.DB_DETECT(), .SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ),
.A_ADDR({R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7],
R_ADDR[6], R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2],
R_ADDR[1], R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC,
VCC}), .A_CLK(CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND}), .A_REN(VCC), .A_WEN({GND, GND}), .A_DOUT_EN(VCC),
.A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10],
W_ADDR[9], W_ADDR[8], W_ADDR[7], W_ADDR[6], W_ADDR[5],
W_ADDR[4], W_ADDR[3], W_ADDR[2], W_ADDR[1], W_ADDR[0], GND,
GND, GND}), .B_BLK_EN({W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
W_DATA[15], W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11],
W_DATA[10], W_DATA[9], W_DATA[8]}), .B_REN(VCC), .B_WEN({GND,
VCC}), .B_DOUT_EN(VCC), .B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(
VCC), .ECC_EN(GND), .BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}),
.A_WMODE({GND, GND}), .A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC})
, .B_WMODE({GND, GND}), .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 (.A_DOUT({nc64,
nc65, nc66, nc67, nc68, nc69, nc70, nc71, nc72, nc73, nc74,
nc75, R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc76, nc77, nc78,
nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88,
nc89, nc90, nc91, nc92, nc93, nc94, nc95}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
R_ADDR[10], R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6],
R_ADDR[5], R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1],
R_ADDR[0], GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(
CLK), .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(VCC)
, .A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8],
W_ADDR[7], W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3],
W_ADDR[2], W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({
W_EN, VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, W_DATA[7], W_DATA[6],
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
W_DATA[0]}), .B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("PF_TPSRAM_C0_0%2048-2048%32-32%SPEED%0%3%TWO-PORT%ECC_EN-0")
) PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 (.A_DOUT({nc96,
nc97, nc98, nc99, nc100, nc101, nc102, nc103, nc104, nc105,
nc106, nc107, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24]}), .B_DOUT({
nc108, nc109, nc110, nc111, nc112, nc113, nc114, nc115, nc116,
nc117, nc118, nc119, nc120, nc121, nc122, nc123, nc124, nc125,
nc126, nc127}), .DB_DETECT(), .SB_CORRECT(), .ACCESS_BUSY(
\ACCESS_BUSY[0][3] ), .A_ADDR({R_ADDR[10], R_ADDR[9],
R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5], R_ADDR[4],
R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND, GND, GND}),
.A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK), .A_DIN({GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND}), .A_REN(VCC), .A_WEN({GND, GND}),
.A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC), .A_DOUT_SRST_N(VCC),
.B_ADDR({W_ADDR[10], W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND}), .B_BLK_EN({W_EN, VCC,
VCC}), .B_CLK(CLK), .B_DIN({GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, W_DATA[31], W_DATA[30], W_DATA[29],
W_DATA[28], W_DATA[27], W_DATA[26], W_DATA[25], W_DATA[24]}),
.B_REN(VCC), .B_WEN({GND, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({GND, VCC, VCC}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({GND, VCC, VCC}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
GND GND_power_inst1 (.Y(GND_power_net1));
VCC VCC_power_inst1 (.Y(VCC_power_net1));

4
component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/core.gen
View File

@@ -30,7 +30,7 @@ PTYPE:1
RADDRESS_PN:R_ADDR
RCLK_EDGE:RISE
RCLOCK_PN:R_CLK
RDEPTH:1024
RDEPTH:2048
RESET_PN:R_DATA_ARST_N
RESET_POLARITY:2
RE_PN:R_EN
@@ -41,7 +41,7 @@ SII_LOCK:0
WADDRESS_PN:W_ADDR
WCLK_EDGE:RISE
WCLOCK_PN:W_CLK
WDEPTH:1024
WDEPTH:2048
WE_PN:W_EN
WE_POLARITY:1
WWIDTH:32

2
component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_manifest.txt
View File

@@ -1,6 +1,6 @@
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 22:42:59 2026
Date : Fri Apr 17 05:34:27 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : PF_TPSRAM_C0
Family : PolarFire

BIN
component/work/pf_init_monitor_0/pf_init_monitor_0.sdb
View File

Binary file not shown.

BIN
component/work/top/top.sdb
View File

Binary file not shown.

23
component/work/top/top.v
View File

@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:44:24 2026
// Created by SmartDesign Fri Apr 17 08:26:46 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
@@ -107,10 +107,9 @@ wire [31:0] CORETSE_0_MRXDAT;
wire CORETSE_0_MRXEOF;
wire CORETSE_0_MRXRDY;
wire CORETSE_0_MRXSOF;
wire CORETSE_0_MTXACPT;
wire [9:0] CORETSE_0_TCG;
wire fifo_to_tpsram_bridge_0_fifo_rd_en;
wire [9:0] fifo_to_tpsram_bridge_0_ram_w_addr_1;
wire [10:0] fifo_to_tpsram_bridge_0_ram_w_addr_4;
wire [31:0] fifo_to_tpsram_bridge_0_ram_w_data;
wire fifo_to_tpsram_bridge_0_ram_w_en;
wire INBUF_DIFF_0_Y;
@@ -204,7 +203,8 @@ wire [9:0] ANX_STATE_net_0;
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
wire [9:0] R_ADDR_const_net_0;
wire [31:0] MTXDAT_const_net_0;
wire [10:0] R_ADDR_const_net_0;
//--------------------------------------------------------------------
// Inverted Nets
//--------------------------------------------------------------------
@@ -230,7 +230,8 @@ wire [7:0] CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0;
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign R_ADDR_const_net_0 = 10'h000;
assign MTXDAT_const_net_0 = 32'h00000000;
assign R_ADDR_const_net_0 = 11'h000;
//--------------------------------------------------------------------
// Inversions
//--------------------------------------------------------------------
@@ -433,11 +434,11 @@ CORESPI_0 CORESPI_0_0(
CORETSE_0 CORETSE_0_inst_0(
// Inputs
.MTXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MTXRDY ( CORETSE_0_MRXRDY ),
.MTXRDY ( GND_net ),
.MTXSOF ( CORETSE_0_MRXSOF ),
.MTXEOF ( CORETSE_0_MRXEOF ),
.MRXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MRXACPT ( CORETSE_0_MTXACPT ),
.MRXACPT ( VCC_net ),
.TXCLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
.RXCLK ( PF_IOD_CDR_C0_0_RX_CLK_R ),
.TBI_TX_CLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
@@ -449,13 +450,13 @@ CORETSE_0 CORETSE_0_inst_0(
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
.PSEL ( CoreAPB3_0_0_APBmslave0_PSELx ),
.MTXDAT ( CORETSE_0_MRXDAT ),
.MTXDAT ( MTXDAT_const_net_0 ),
.MTXBYTEVALID ( CORETSE_0_MRXBYTEVALID ),
.RCG ( PF_IOD_CDR_C0_0_RX_DATA ),
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR ),
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA ),
// Outputs
.MTXACPT ( CORETSE_0_MTXACPT ),
.MTXACPT ( ),
.MTXHWM ( ),
.MRXRDY ( CORETSE_0_MRXRDY ),
.MRXSOF ( CORETSE_0_MRXSOF ),
@@ -511,7 +512,7 @@ fifo_to_tpsram_bridge fifo_to_tpsram_bridge_0(
.transfer_enable ( VCC_net ),
// Outputs
.fifo_rd_en ( fifo_to_tpsram_bridge_0_fifo_rd_en ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.ram_w_data ( fifo_to_tpsram_bridge_0_ram_w_data ),
.ram_w_en ( fifo_to_tpsram_bridge_0_ram_w_en ),
.buffer_full ( )
@@ -633,7 +634,7 @@ PF_TPSRAM_C0 PF_TPSRAM_C0_0(
.W_EN ( fifo_to_tpsram_bridge_0_ram_w_en ),
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.W_DATA ( fifo_to_tpsram_bridge_0_ram_w_data ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.R_ADDR ( R_ADDR_const_net_0 ),
// Outputs
.R_DATA ( R_DATA_net_0 )

2
component/work/top/top_manifest.txt
View File

@@ -1,6 +1,6 @@
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 22:44:25 2026
Date : Fri Apr 17 08:26:46 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : top
Family : PolarFire