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Merge pull request 'working FIFO and TPSRAM without packet flter' (#1) from development into main

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Reviewed-on: #1
This commit was merged in pull request #1.
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abhishek
2026-04-15 18:37:37 +00:00
parent 77c69687d9 e4b91625ea
commit 8050a81acd
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1
component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/CORECDR4_CNTL_TIP.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORECDR4_CNTL_TIP</name><vendor>Actel</vendor><library>DirectCore</library><version>2.0.100</version><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\corecdr4_cntl_tip.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:42:04 2026
// Parameters for CORECDR4_CNTL_TIP
//--------------------------------------------------------------------
parameter FAMILY = 26;
parameter STEP = 3;

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component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v Normal file
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/*
Clock Data Recoverary Control Training IP in CDR mode 4
*/
module CORECDR4_CNTL_TIP (
input CDR_START, // active low reset in sclk1 domain, generated from delay code TIP
input SCLK0, // [0] for RX, divclk from lanectrl
input STREAM_START, // initial flag ready or stream start from flag generator TIP or SGMII IP
input EARLY_N, // active high early flag from IOGN data eye monitor or flag generator TIP
input LATE_N, // active high late flag from IOGN data eye monitor or flag generator TIP
input DLL_VALID_CODE, // DLL delay code valid indicator from delay code TIP for clean clock domain transfer
input [ 6:0] DLL_DELAY_CODE, // DLL delay code for 90 degree from delay code TIP
output RSTN_0,
output CDR_READY, // ready indicator to SGMII IP
output CLR_FLAGS_N, // active high reset to IOGN data eye monitor
output [ 2:0] EYEWIDTH_IN_LANE, // parameterized data eye window width
output reg [10:0] SELA_LANE, // clka phase/delay setting
output reg [10:0] SELB_LANE, // clkb phase/delay setting
output reg SWITCH_LANE); // glitchless switch cdrclk to nxtclk
parameter ST_RSWT = 2'b00; // right shift switch
parameter ST_RWAT = 2'b01; // right wait for flag
parameter ST_LSWT = 2'b10; // left shift switch
parameter ST_LWAT = 2'b11; // left wait for flag
parameter STEP = 3; // jumping step
parameter COMP0_STEP = 0; // compensating step between bclk[0] and bclk[1]
parameter COMP1_STEP = 4; // compensating step between bclk[1] and bclk[2]
parameter COMP2_STEP = 1; // compensating step between bclk[2] and bclk[3]
parameter COMP3_STEP = 1; // compensating step between bclk[3] and bclk[0]
//parameter EYEWIDTH = 3'b111; // +/-7 eyewidth
parameter EYEWIDTH = 3'b001; // +/-1 eyewidth
reg [1:0] start_cnt;
reg [1:0] rst_n; // sync-off internal reset on SCLK0 domain
reg [1:0] coarse_sel; // coarse phase selection
reg [7:0] fine_sel; // fine phase selection
reg [1:0] tune_st; // state_machine
reg [3:0] cnt;
reg [1:0] early_flag; // synchronizer
reg [1:0] late_flag; // synchronizer
reg [1:0] valid_flag; // synchronizer
reg [6:0] dll_90_code; // 90 degree code from DLL synchronizer
reg clr_flag;
reg [3:0] cdr_ready_reg; // wait states for CDR_READY
wire [6:0] dll_90_code_adj1 = (coarse_sel == 2'b00) ? (dll_90_code - COMP0_STEP) : // code adjusted for skew between bclk[0] and bclk[1]
(coarse_sel == 2'b01) ? (dll_90_code + COMP1_STEP) : // code adjusted for skew between bclk[1] and bclk[2]
(coarse_sel == 2'b10) ? (dll_90_code + COMP2_STEP) : // code adjusted for skew between bclk[2] and bclk[3]
dll_90_code - COMP3_STEP; // code adjusted for skew between bclk[3] and bclk[0]
wire [6:0] dll_90_code_adj2 = (coarse_sel == 2'b01) ? (dll_90_code - COMP0_STEP) : // code adjusted for skew between bclk[0] and bclk[1]
(coarse_sel == 2'b10) ? (dll_90_code + COMP1_STEP) : // code adjusted for skew between bclk[1] and bclk[2]
(coarse_sel == 2'b11) ? (dll_90_code + COMP2_STEP) : // code adjusted for skew between bclk[2] and bclk[3]
dll_90_code - COMP3_STEP; // code adjusted for skew between bclk[3] and bclk[0]
assign RSTN_0 = rst_n[0];
assign CDR_READY = cdr_ready_reg[0]; // wait several cycles after first switch so that RX data can be pipe-cleaned
assign EYEWIDTH_IN_LANE = EYEWIDTH;
assign CLR_FLAGS_N = clr_flag | !rst_n[0]; // active high reset to IOGN data eye monitor
always @(posedge SCLK0 or negedge CDR_START) begin // RX clock
if (!CDR_START) rst_n <= 0; // async-on
else if (STREAM_START) rst_n <= {1'b1, rst_n[1]}; // sync-off after the first flags are generated
end
always @(negedge SCLK0 or negedge rst_n[0] or posedge clr_flag) begin // RX clock
if (!rst_n[0]) begin
early_flag <= 0;
late_flag <= 0;
end
else if (clr_flag) begin
early_flag <= 0;
late_flag <= 0;
end
else begin
early_flag <= {EARLY_N, early_flag[1]};
late_flag <= {LATE_N, late_flag[1]};
end
end
always @(negedge SCLK0 or negedge rst_n[0]) begin // RX clock
if (!rst_n[0]) begin
cdr_ready_reg <= 0;
valid_flag <= 2'b11;
dll_90_code <= 0;
end
else begin
if (SELA_LANE[10]) cdr_ready_reg[3] <= 1'b1; // after the first switch, the CDR is ready
cdr_ready_reg[2:0] <= cdr_ready_reg[3:1];
valid_flag <= {DLL_VALID_CODE, valid_flag[1]}; // sync
if (valid_flag[0]) dll_90_code <= DLL_DELAY_CODE; // when valid, the DLL_DELAY_CODE is guaranteed stable
end
end
always @(posedge SCLK0 or negedge rst_n[0]) begin // RX clock
if (!rst_n[0]) begin
SELA_LANE <= 0;
SELB_LANE <= 0;
end
else begin
if (clr_flag) begin
if (SELA_LANE[10]) SELA_LANE[9:0] <= {coarse_sel[1:0], fine_sel[7:0]};
if (!SELB_LANE[10]) SELB_LANE[9:0] <= {coarse_sel[1:0], fine_sel[7:0]};
end
else if (cdr_ready_reg[2:0] == 3'b110) SELA_LANE[9:0] <= {coarse_sel[1:0], fine_sel[7:0]}; // initial condition
if (SWITCH_LANE) begin
SELA_LANE[10] <= ~SELA_LANE[10]; // cdrclk_selb
SELB_LANE[10] <= ~SELB_LANE[10]; // nxtclk_sela
end
end
end
always @(negedge SCLK0 or negedge rst_n[0]) begin // RX clock
if (!rst_n[0]) begin
coarse_sel <= 0;
fine_sel <= 0;
tune_st <= ST_RSWT;
cnt <= 0;
clr_flag <= 0;
SWITCH_LANE <= 0;
end
else case (tune_st)
ST_RSWT : if (!cdr_ready_reg[3]) begin // initial condition
if (early_flag[0] || late_flag[0]) begin // initial noisy
if (early_flag[0]) coarse_sel <= coarse_sel - 1; // 90 degree ahead
fine_sel <= dll_90_code[6:1]; // 45 degree left or right shift
tune_st <= ST_LSWT;
clr_flag <= 1'b1;
cnt <= 0;
end
else if (& cnt) begin // long wait for flags in initial search
cnt <= 1;
clr_flag <= 1'b0; // no need to clear
end
else begin
cnt <= cnt + 1;
clr_flag <= 1'b0; // one cycle assertion
end
if (SWITCH_LANE) SWITCH_LANE <= 1'b0;
else if ((& cnt) && !(early_flag[0] || late_flag[0])) SWITCH_LANE <= 1'b1;
end
else begin
/*
if (cnt == 10) begin // suppressing consecutive switch
tune_st <= ST_RWAT;
cnt <= 0;
clr_flag <= 1'b1;
end
else if (cnt == 1) begin
cnt <= cnt + 1;
clr_flag <= 1'b1;
end
*/
if (cnt == 1) begin
tune_st <= ST_RWAT;
cnt <= 0;
clr_flag <= 1'b1;
end
else begin
cnt <= cnt + 1;
clr_flag <= 1'b0;
end
if (SWITCH_LANE) SWITCH_LANE <= 1'b0;
else if (cnt == 0) SWITCH_LANE <= 1'b1;
end
ST_LSWT : begin
/*
if (cnt == 10) begin // suppressing consecutive switch
tune_st <= ST_LWAT;
cnt <= 0;
clr_flag <= 1'b1;
end
else if (cnt == 1) begin
cnt <= cnt + 1;
clr_flag <= 1'b1;
end
*/
if (cnt == 1) begin
tune_st <= ST_LWAT;
cnt <= 0;
clr_flag <= 1'b1;
end
else begin
cnt <= cnt + 1;
clr_flag <= 1'b0;
end
if (SWITCH_LANE) SWITCH_LANE <= 1'b0;
else if (cnt == 0) SWITCH_LANE <= 1'b1;
end
ST_RWAT : if (late_flag[0]) begin // confirm move right after right move
if ((fine_sel + STEP) <= dll_90_code_adj1) begin // one full step later
fine_sel <= fine_sel + STEP;
end
else begin
coarse_sel <= coarse_sel + 1; // 90 degree later
fine_sel <= fine_sel + STEP - dll_90_code_adj1;
end
tune_st <= ST_RSWT;
clr_flag <= 1'b1;
end
else if (early_flag[0]) begin // confirm move left after right move
if (fine_sel >= (STEP - 1)) begin // one tap less back
fine_sel <= fine_sel - (STEP - 1);
end
else begin
coarse_sel <= coarse_sel - 1; // 90 degree ahead
fine_sel <= dll_90_code_adj2 - (STEP - 1) + fine_sel;
end
tune_st <= ST_LSWT;
clr_flag <= 1'b1;
end
else begin
clr_flag <= 1'b0;
end
ST_LWAT : if (early_flag[0]) begin // confirm move left after left move
if (fine_sel >= STEP) begin // one full step ahead
fine_sel <= fine_sel - STEP;
end
else begin
coarse_sel <= coarse_sel - 1; // 90 degree ahead
fine_sel <= dll_90_code_adj2 - STEP + fine_sel;
end
tune_st <= ST_LSWT;
clr_flag <= 1'b1;
end
else if (late_flag[0]) begin // confirm move right after left move
if ((fine_sel + STEP - 1) <= dll_90_code_adj1) begin // one tap less later
fine_sel <= fine_sel + STEP - 1;
end
else begin
coarse_sel <= coarse_sel + 1; // 90 degree later
fine_sel <= fine_sel + STEP - 1 - dll_90_code_adj1;
end
tune_st <= ST_RSWT;
clr_flag <= 1'b1;
end
else begin
clr_flag <= 1'b0;
end
endcase
end
endmodule

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component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/COREDELAYCODE_TIP.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREDELAYCODE_TIP</name><vendor>Actel</vendor><library>DirectCore</library><version>2.1.100</version><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\CoreDelayCode_TIP.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/rtl/vlog/core/CoreDelayCode_TIP.v Normal file
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module COREDELAYCODE_TIP (
input gsr_b, // async active low reset
input sclk1, // [1] for TX, clean 125MHz clock from PLL
input pll_lock, // lock flag from PLL
input dll_lock, // lock flag from DLL
input dll_delay_diff, // delay difference flag from DLL
input rxdly_oor_lane, // async glitchy overflow/underflow flag for RXDLY move up/down
output reg dll_code_upd, // update delay code in DLL
output reg [6:0] dll_delay_code, // DLL delay code
output reg dll_valid_code, // code valid flag
output reg reset_lane, // active low lane controller reset
output reg pause_lane, // pause FIFO controller for clock glitches after lane reset
output reg load_lane, // load DLL delay code to RXDLY
output reg move_lane, // move RXDLY up/down on rising edge
output direction_lane, // 1=up, 0=down
output mv_rd_dly_lane, // tie-high to always move RXDLY
output reg cdr_start); // active low reset in sclk1 domain for CDR controllers, wait for reset release, lane control clean, flag_ready, and DLL code valid
reg [1:0] rst_b; // sync-off internal reset on sclk1 domain
reg [1:0] start_cnt; // counter used in start-up
reg [1:0] lock_sync; // synchronizer of dll_lock
reg [1:0] diff_sync; // synchronizer of dll_delay_diff
reg [1:0] state; // state machine
reg [6:0] move_cnt; // move counter
wire reset_b = rst_b[0];
assign mv_rd_dly_lane = 1'b1;
assign direction_lane = 1'b0; // always counting down
always @(posedge sclk1 or negedge gsr_b) begin // TX or non-stop clock
if (!gsr_b) rst_b <= 0; // async-on
else if (pll_lock) rst_b <= {1'b1, rst_b[1]}; // sync-off
end
always @(posedge sclk1 or negedge reset_b) begin // TX clock
if (!reset_b) begin
cdr_start <= 1'b0;
reset_lane <= 1'b0; // active low reset lane controller
pause_lane <= 1'b0;
start_cnt <= 0;
lock_sync <= 0;
diff_sync <= 0;
end
else begin
lock_sync <= {dll_lock, lock_sync[1]};
diff_sync <= {dll_delay_diff, diff_sync[1]};
start_cnt <= start_cnt + 1; // always counting
if (reset_lane && (start_cnt == 2'b11)) pause_lane <= 1'b0; // free running from now on
else if (!reset_lane && (start_cnt == 2'b00)) pause_lane <= 1'b1; // pause early than reset to avoid FIFO clock glitch mess-up
else if (!reset_lane && (start_cnt == 2'b01)) reset_lane <= 1'b1; // lane controller reset release
if (reset_lane && !pause_lane && dll_valid_code) cdr_start <= 1'b1; // after the first DLL delay code is calculated, start CDR
end
end
always @(posedge sclk1 or negedge reset_b) begin // TX clock
if (!reset_b) begin
dll_code_upd <= 1'b0; // no updating delay code
dll_valid_code <= 1'b0;
dll_delay_code <= 0;
load_lane <= 1'b0;
move_lane <= 1'b0;
move_cnt <= 0;
state <= 0;
end
else if (lock_sync[0]) case (state) // after DLL lock
2'b00 : if ((&start_cnt) && (diff_sync[0] || ~cdr_start)) begin // initial state
state <= 2'b01; // after delay_diff, to load state
dll_code_upd <= 1'b1; // update DLL code
end
2'b01 : begin // load state
dll_code_upd <= 1'b0; // one cycle assertion
if (&start_cnt) begin
state <= 2'b10; // after delay_code propagation, to move state
load_lane <= 1'b1; // load DLL code to RXDLY
move_cnt <= 0;
end
end
2'b10 : begin // move state
load_lane <= 1'b0; // one cycle assertion
if (start_cnt[0]) begin
if (!rxdly_oor_lane) begin // give enough time for rxdly_oor_lane to settle
move_lane <= 1'b1; // keep moving down
move_cnt <= move_cnt + 1; // increment counter
end
else if (&start_cnt) begin // at underflow
state <= 2'b11; // after counter max, to valid state
dll_valid_code <= 1'b0; // deassert the flag for 4 cycles
end
end
else move_lane <= 1'b0; // one cycle assertion
end
2'b11 : if (&start_cnt) begin // valid state
state <= 2'b00; // after counter max, to initial state
dll_valid_code <= 1'b1; // new delay valid delay code
dll_delay_code <= move_cnt;
end
endcase
end
endmodule

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component/Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO</name><vendor>Actel</vendor><library>DirectCore</library><version>3.1.101</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\test\user\clock_driver.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\test\user\fifo_driver.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\test\user\fifo_monitor.v</name><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\test\user\g4_dp_ext_mem.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\test\user\MEM_WeqR.v</name><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\vlog\test\user\MEM_WgtR.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\vlog\test\user\MEM_WltR.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"/><fileSet fileSetId="HDL_FILESET"/></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WeqR.v Normal file
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module MEM_WeqR (
clk,
wclk,
rclk,
rst_n,
waddr,
raddr,
data,
we,
re,
q
);
// Memory parameters
parameter SYNC = 0;
parameter RAM_RW = 18;
parameter RAM_WW = 18;
parameter RAM_WD = 10;
parameter RAM_RD = 10;
parameter WRITE_ADDRESS_END = 1024;
parameter READ_ADDRESS_END = 1024;
parameter WRITE_CLK = 1;
parameter READ_CLK = 1;
parameter WRITE_ENABLE = 1;
parameter READ_ENABLE = 1;
parameter RESET_POLARITY = 0;
parameter PIPE = 1;
// local inputs
input clk;
input wclk;
input rclk;
input rst_n;
// local inputs - memory functional bus
input [RAM_WD-1:0] waddr;
input [RAM_WW-1:0] data;
input [RAM_RD-1:0] raddr;
input we;
input re;
//OUTPUTS
//======
output [RAM_RW-1:0] q;
reg [RAM_RW-1:0] q_d0, q_d1,q_d2;
wire wclk_int,rclk_int,we_int,re_int, rst_int;
wire f_wclk, f_rclk;
// ** MEM DECLARATION **
reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
integer i;
assign q = (PIPE == 1) ? q_d0 :(PIPE == 2) ? q_d1 : MEM[raddr] ;
assign f_wclk = SYNC ? clk : wclk;
assign f_rclk = SYNC ? clk : rclk;
assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
assign we_int = we;
assign re_int = re;
assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
initial
begin
//q = {RAM_RW{1'b0}};
end
always @ (posedge wclk_int or negedge rst_int)
begin
if (~rst_int) begin
end
else
begin
if (we_int=== 1'b1)
begin
MEM[waddr] = data;
end
end
end
always @ (posedge rclk_int or negedge rst_int)
begin
if (~rst_int)
begin
q_d0 <= {RAM_RD{1'b0}};
end
else
begin
if (re_int === 1'b1)
begin
q_d0 <= MEM[raddr];
end
end
end
always @ (posedge rclk_int or negedge rst_int)
begin
if (~rst_int)
begin
q_d1 <= {RAM_RD{1'b0}};
q_d2 <= {RAM_RD{1'b0}};
end
else
begin
q_d1 <= q_d0;
q_d2 <= q_d1;
end
end
endmodule

123
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WgtR.v Normal file
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module MEM_WgtR (
clk,
wclk,
rclk,
rst_n,
waddr,
raddr,
data,
we,
re,
q
);
// Memory parameters
parameter SYNC = 0;
parameter RAM_RW = 18;
parameter RAM_WW = 18;
parameter RAM_WD = 10;
parameter RAM_RD = 10;
parameter WRITE_ADDRESS_END = 1024;
parameter READ_ADDRESS_END = 1024;
parameter WRITE_CLK = 1;
parameter READ_CLK = 1;
parameter WRITE_ENABLE = 1;
parameter READ_ENABLE = 1;
parameter RESET_POLARITY = 0;
parameter PIPE = 1;
// local inputs
input clk;
input wclk;
input rclk;
input rst_n;
// local inputs - memory functional bus
input [RAM_WD-1:0] waddr;
input [RAM_WW-1:0] data;
input [RAM_RD-1:0] raddr;
input we;
input re;
//OUTPUTS
//======
output [RAM_RW-1:0] q;
wire wclk_int,rclk_int,we_int,re_int, rst_int;
wire f_wclk, f_rclk;
// ** MEM DECLARATION **
reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
integer i;
reg [RAM_RW-1:0] q;
assign f_wclk = SYNC ? clk : wclk;
assign f_rclk = SYNC ? clk : rclk;
assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
assign we_int = we;
assign re_int = re;
assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
/*
assign wclk_int = wclk;
assign rclk_int = rclk;
*/
initial
begin
q = {RAM_RW{1'b0}};
end
always @ (posedge wclk_int or negedge rst_int)
begin
if (~rst_int) begin
end
else
begin
if (we_int=== 1'b1)
begin
MEM[waddr] = data;
/*if (RAM_WW > RAM_RW) begin
MEMR[waddr*2] = data[RAM_RW-1:0];
MEMR[waddr*2+1] = data[RAM_WW-1:RAM_RW];
end*/
end
end
end
always @ (posedge rclk_int or negedge rst_int)
begin
if (~rst_int)
begin
q <= {RAM_RD{1'b0}};
end
else
begin
if (re_int === 1'b1)
begin
// if (RAM_WW > RAM_RW) begin
//q <= MEMR[raddr];
if (raddr%2 ==0)
q <= MEM[raddr/2][RAM_RW-1 :0];
else
q <= MEM[raddr/2][(RAM_WW-1):RAM_RW];
end
end
end
endmodule

114
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WltR.v Normal file
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module MEM_WltR (
clk,
wclk,
rclk,
rst_n,
waddr,
raddr,
data,
we,
re,
q
);
// Memory parameters
parameter SYNC = 0;
parameter RAM_RW = 18;
parameter RAM_WW = 18;
parameter RAM_WD = 10;
parameter RAM_RD = 10;
parameter WRITE_ADDRESS_END = 1024;
parameter READ_ADDRESS_END = 1024;
parameter WRITE_CLK = 1;
parameter READ_CLK = 1;
parameter WRITE_ENABLE = 1;
parameter READ_ENABLE = 1;
parameter RESET_POLARITY = 0;
parameter PIPE = 1;
// local inputs
input clk;
input wclk;
input rclk;
input rst_n;
// local inputs - memory functional bus
input [RAM_WD-1:0] waddr;
input [RAM_WW-1:0] data;
input [RAM_RD-1:0] raddr;
input we;
input re;
//OUTPUTS
//======
output [RAM_RW-1:0] q;
wire wclk_int,rclk_int,we_int,re_int, rst_int;
wire f_wclk, f_rclk;
// ** MEM DECLARATION **
reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
integer i;
reg [RAM_RW-1:0] q;
assign f_wclk = SYNC ? clk : wclk;
assign f_rclk = SYNC ? clk : rclk;
assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
assign we_int = we;
assign re_int = re;
assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
/*
assign wclk_int = wclk;
assign rclk_int = rclk;
*/
initial
begin
q = {RAM_RW{1'b0}};
end
always @ (posedge wclk_int or negedge rst_int)
begin
if (~rst_int) begin
end
else
begin
if (we_int=== 1'b1)
begin
MEM[waddr] = data;
end
end
end
always @ (posedge rclk_int or negedge rst_int)
begin
if (~rst_int)
begin
q <= {RAM_RD{1'b0}};
end
else
begin
if (re_int === 1'b1)
begin
//(RAM_WW < RAM_RW)
q <= {MEM[raddr*2+1],MEM[raddr*2]};
end
end
end
endmodule

58
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/clock_driver.v Normal file
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@@ -0,0 +1,58 @@
`timescale 1 ns / 100 ps
module clock_driver ( clk1, wclk1, rclk1);
output clk1;
output wclk1,rclk1;
parameter CLKPERIOD = 15;
parameter WCLKPERIOD = 15;
parameter RCLKPERIOD = 15;
reg clk1, wclk1, rclk1;
reg enable;
initial begin
clk1 = 1'b0;
wclk1 = 1'b0;
rclk1 = 1'b0;
enable = 1'b1;
end
always @(clk1 or enable)
begin
if (enable)
clk1 <= #(CLKPERIOD) ~clk1;
end
always @(wclk1 or enable)
begin
if (enable)
wclk1 <= #(WCLKPERIOD) ~wclk1;
end
always @(rclk1 or enable)
begin
if (enable)
rclk1 <= #(RCLKPERIOD) ~rclk1;
end
task clk_on;
begin
enable = 1'b1;
end
endtask
task clk_off;
begin
enable = 1'b0;
end
endtask
endmodule // clock_driver

459
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_driver.v Normal file
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@@ -0,0 +1,459 @@
`timescale 1 ns / 100 ps
module fifo_driver (
// inputs
clk,
wclk,
rclk,
waddr,
raddr,
full,
empty,
dvld,
q,
// outputs
reset,
we,
re,
wdata
);
parameter SYNC = 0;
parameter CTRL_TYPE = 1;
parameter WRITE_WIDTH = 18;
parameter WRITE_DEPTH = 1024;
parameter FULL_WRITE_DEPTH = 10;
parameter READ_WIDTH = 18;
parameter READ_DEPTH = 1024;
parameter FULL_READ_DEPTH = 10;
parameter WE_POLARITY = 1;
parameter RE_POLARITY = 1;
parameter RESET_POLARITY = 0;
parameter RCLK_EDGE = 1;
parameter WCLK_EDGE = 1;
parameter ESTOP = 1;
parameter FSTOP = 1;
parameter PIPE = 1;
parameter ECC = 0;
parameter PREFETCH = 1;
parameter FWFT = 0;
input clk;
input wclk;
input rclk;
input full;
input empty;
input dvld;
input [FULL_WRITE_DEPTH-1 :0] waddr;
input [FULL_READ_DEPTH-1 :0] raddr;
input [READ_WIDTH-1 :0] q;
output reset;
output we;
output re;
output [WRITE_WIDTH-1:0] wdata;
reg check_q;
reg reset;
reg we;
reg re;
reg [FULL_READ_DEPTH :0] rdepth;
reg [FULL_WRITE_DEPTH:0] wdepth;
reg [FULL_READ_DEPTH-1 :0] raddr_top;
integer i,j,k,m;
integer cnt, cnt_rd, cnt_eq, rderr_cnt;
reg [WRITE_WIDTH-1:0] wdata;
reg [WRITE_WIDTH-1:0] mem_arrayA [0:(2<<FULL_WRITE_DEPTH)];
reg [READ_WIDTH-1:0] mem_arrayB [0:(2<<FULL_READ_DEPTH)];
wire f_wclk,f_rclk,fifo_wclk,fifo_rclk, fifo_reset;
assign f_wclk = SYNC ? clk : wclk;
assign f_rclk = SYNC ? clk : rclk;
assign fifo_wclk = WCLK_EDGE ? f_wclk : ~f_wclk;
assign fifo_rclk = SYNC ? RCLK_EDGE ? f_rclk : ~f_rclk : RCLK_EDGE ? f_rclk : ~f_rclk;
assign fifo_reset = RESET_POLARITY ? ~reset : reset;
initial begin
rderr_cnt = 0;
if (RESET_POLARITY) begin
reset = 1'b1;
end else begin
reset = 1'b0;
end
check_q = 1'b0;
if (WE_POLARITY == 1'b1)
we <= 1'b1;
else
we <= 1'b0;
if (RE_POLARITY == 1'b1)
re <= 1'b1;
else
re <= 1'b0;
end
initial begin
if (WRITE_WIDTH > READ_WIDTH) begin
for(cnt = 0; cnt < WRITE_DEPTH; cnt = cnt + 1) begin
//mem_arrayA[cnt] = $random;
mem_arrayA[cnt] = cnt;
//$display("memory array A = %h", mem_arrayA[cnt]);
end
end
else if (READ_WIDTH > WRITE_WIDTH ) begin
for(cnt_rd = 0; cnt_rd < READ_DEPTH; cnt_rd = cnt_rd + 1) begin
//mem_arrayA[cnt_rd] = $random;
mem_arrayA[cnt_rd] = cnt_rd;
//$display("memory array A = %h", mem_arrayA[cnt_rd]);
end
end
else begin
for(cnt_eq = 0; cnt_eq < WRITE_DEPTH; cnt_eq = cnt_eq + 1) begin
//mem_arrayA[cnt_eq] = $random;
mem_arrayA[cnt_eq] = cnt_eq;
//$display("memory array A = %h", mem_arrayA[cnt_eq]);
end
end
end
task reset_asserted;
begin
if (RESET_POLARITY)
reset = 1'b1;
else
reset = 1'b0;
end
endtask
task reset_negated;
begin
if (RESET_POLARITY)
reset = 1'b0;
else
reset = 1'b1;
end
endtask
task initialize;
begin
if (WE_POLARITY == 1'b1)
we <= 1'b1;
else
we <= 1'b0;
if (RE_POLARITY == 1'b1)
re <= 1'b1;
else
re <= 1'b0;
end
endtask
task write_assert;
begin
@ (posedge fifo_wclk);
if (WE_POLARITY == 1'b1)
we <= 1'b0;
else
we <= 1'b1;
end
endtask
task write_deassert;
begin
// @ (posedge fifo_wclk);
if (WE_POLARITY == 1'b1)
we <= 1'b1;
else
we <= 1'b0;
end
endtask
reg active;
task push;
input[(FULL_WRITE_DEPTH) :0] fifo_wdepth;
begin
wdepth = fifo_wdepth;
if (full == 1 && FSTOP == 0 )begin
write_assert;
#1;
wdata = mem_arrayA[waddr];
mem_arrayB[waddr] = mem_arrayA[waddr];
end
else begin
for (i=0;i<=wdepth; i=i+1)
begin
write_assert;
#1;
//wdata = mem_arrayA[waddr];
wdata = mem_arrayA[i];
if (WRITE_WIDTH < READ_WIDTH) begin
mem_arrayB[waddr] = {mem_arrayA[waddr*2+1],mem_arrayA[waddr*2]};
end
else if (WRITE_WIDTH > READ_WIDTH) begin
//mem_arrayB[waddr*2] = wdata[READ_WIDTH-1:0];
//mem_arrayB[waddr*2+1] = wdata[WRITE_WIDTH-1:READ_WIDTH];
end
else
mem_arrayB[waddr] = mem_arrayA[waddr];
end
write_deassert;
end
end
endtask
task read_assert;
begin
@ (posedge fifo_rclk);
if (RE_POLARITY == 1'b1)
re <= 1'b0;
else
re <= 1'b1;
end
endtask
reg [FULL_READ_DEPTH-1 :0] raddr_t1,raddr_t2,raddr_t3,raddr_t4 ;
always @ (posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
raddr_t1<=0;
raddr_t2 <=0;
raddr_t3 <=0;
raddr_t4 <=0;
end
else begin
if ((re == 1 && RE_POLARITY == 1'b0) || (re == 0 && RE_POLARITY == 1'b1)) begin
raddr_t1 <=raddr;
raddr_t2 <=raddr_t1;
raddr_t3 <=raddr_t2;
raddr_t4 <=raddr_t3;
end
end
end
always @ (posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
raddr_top <=0;
end
else begin
if ((re == 1 && RE_POLARITY == 1'b0) || (re == 0 && RE_POLARITY == 1'b1)) begin
raddr_top <= raddr_top + 1;
end
end
end
task read_deassert;
begin
// @ (posedge fifo_rclk);
if (RE_POLARITY == 1'b1)
re <= 1'b1;
else
re <= 1'b0;
end
endtask
wire [FULL_READ_DEPTH-1 :0] raddr_temp1,raddr_temp2 ;
assign raddr_temp1 = (raddr <=1) ? 0 : (raddr-1);
assign raddr_temp2 = (raddr <=2) ? 0 : (raddr-2);
task pop;
input[(FULL_READ_DEPTH) :0] fifo_rdepth;
reg [FULL_READ_DEPTH-1 :0] raddr_temp;
begin
rdepth = fifo_rdepth;
active =0;
read_assert;
repeat(PIPE) @ (posedge fifo_rclk);
if(ECC == 1) begin repeat(ECC) @ (posedge fifo_rclk); end
for (k=0 ;k<rdepth-1;k=k+1)
begin
if (empty == 0) begin
@ (posedge fifo_rclk);
if (WRITE_WIDTH < READ_WIDTH) begin
if((mem_arrayB[raddr_temp] != q))
begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
end
end
else if (WRITE_WIDTH > READ_WIDTH) begin
if (PREFETCH == 1)begin
if (mem_arrayB[raddr_temp] != q)
begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr_temp]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr_temp]);
end
end
else begin //if(PREFETCH == 0 && mem_arrayB[raddr_temp] != q)
if (mem_arrayB[raddr_temp] != q)
begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
end
end
end
else begin // (WRITE_WIDTH == READ_WIDTH)
if ((PREFETCH == 1 || FWFT == 1) && CTRL_TYPE == 1)begin
if((mem_arrayB[raddr_top] !== q))
begin
check_q = ~check_q;
$display ("ERROR: TIME = %t At Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr_top, q , mem_arrayB[raddr_top]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr_t1]);
end
end
else if ((PREFETCH == 1 || FWFT == 1) && CTRL_TYPE != 1)begin
if((mem_arrayB[raddr] !== q))
begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr]);
end
end
else begin
if (PIPE == 2 && ECC == 0 ) begin
if((mem_arrayB[raddr_t2] !== q)) begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
end
end
else if (PIPE == 2 && ECC == 1 && CTRL_TYPE !==1) begin
if((mem_arrayB[raddr_t3] !== q)) begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_t3 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t3, q , mem_arrayB[raddr_t3]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
end
end
else if (PIPE == 2 && (ECC == 1 || ECC == 0) && CTRL_TYPE ==1) begin
if((mem_arrayB[raddr_t2] !== q)) begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
end
end
else if (PIPE == 2 && ECC == 2 ) begin
if((mem_arrayB[raddr_t2] !== q)) begin
check_q = ~check_q;
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
end
end
else if (PIPE == 1 && ECC== 0 ) begin
if((mem_arrayB[raddr_t1] !== q)) begin
check_q = ~check_q;
$display ($realtime, "ERROR: At Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
end
end
else if (PIPE == 1 && ECC== 1 && CTRL_TYPE!=1) begin
if((mem_arrayB[raddr_t2] !== q)) begin
check_q = ~check_q;
$display ($realtime, "ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2 , q , mem_arrayB[raddr_t2]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
end
end
else if (PIPE == 1 && ECC== 2) begin
if((mem_arrayB[raddr_t1] !== q)) begin
check_q = ~check_q;
$display ($realtime, "ERROR: At Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
end
end
else if (PIPE == 1 && (ECC== 1 || ECC ==0) && CTRL_TYPE==1) begin
if((mem_arrayB[raddr_t1] !== q)) begin
check_q = ~check_q;
$display ($realtime, "ERROR: Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
end
end
else begin
if((mem_arrayB[raddr] !== q)) begin
check_q = ~check_q;
$display ("ERROR: else At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr]);
rderr_cnt = rderr_cnt + 1;
end
else begin
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr]);
end
end
end
end
end
end
if (rderr_cnt == 0)
$display ( "At", $time, " PASS: FIFO Q output match \n");
end
endtask
endmodule // fifo_driver

819
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_monitor.v Normal file
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@@ -0,0 +1,819 @@
`timescale 1ns / 100ps
module fifo_monitor (
clk,
rclk,
wclk,
reset,
we,
re,
wcnt,
rcnt,
full,
afull,
empty,
aempty,
underflow,
overflow,
dvld,
wack
);
parameter SYNC = 0;
parameter PIPE = 1;
parameter PREFETCH = 1;
parameter FWFT = 1;
parameter WRITE_WIDTH = 18;
parameter WRITE_DEPTH = 10;
parameter FULL_WRITE_DEPTH = 1024;
parameter READ_WIDTH = 18;
parameter READ_DEPTH = 10;
parameter FULL_READ_DEPTH = 1024;
parameter AFVAL = 508;
parameter AEVAL = 4;
parameter AE_STATIC_EN = 1;
parameter AF_STATIC_EN = 1;
parameter ESTOP = 1;
parameter FSTOP = 1;
parameter OVERFLOW_EN = 1;
parameter UNDERFLOW_EN = 1;
parameter WRCNT_EN = 1;
parameter RDCNT_EN = 1;
parameter RCLK_EDGE = 1;
parameter WCLK_EDGE = 1;
parameter RE_POLARITY = 0;
parameter WE_POLARITY = 0;
parameter READ_DVALID = 0;
parameter WRITE_ACK = 0;
parameter RESET_POLARITY = 0;
input clk;
input rclk;
input wclk;
input reset;
input we;
input re;
input [WRITE_DEPTH:0] wcnt;
input [READ_DEPTH:0] rcnt;
input full;
input afull;
input empty;
input aempty;
input underflow;
input overflow;
input dvld;
input wack;
reg [WRITE_DEPTH:0] wptr;
reg [READ_DEPTH:0] rptr;
reg [WRITE_DEPTH:0] wptr_r;
reg [READ_DEPTH:0] rptr_r;
reg full_r, full_reg;
reg afull_r;
reg empty_r,empty_rt,empty_reg;
reg empty_r_fwft1;
reg empty_r_fwft2;
reg empty_r_fwft3;
reg aempty_r;
reg underflow_r;
reg overflow_r;
reg underflow_w;
reg overflow_w;
reg DVLD_d0,DVLD_d1,DVLD_d2;
reg wack_r;
reg [WRITE_DEPTH : 0] wptr_d1sync;
reg [WRITE_DEPTH : 0] wptr_d2sync;
reg [WRITE_DEPTH : 0] wptr_d3sync;
reg [WRITE_DEPTH : 0] wptr_d4sync;
reg [READ_DEPTH : 0] rptr_d1sync;
reg [READ_DEPTH : 0] rptr_d2sync;
reg [READ_DEPTH : 0] rptr_d3sync;
reg [READ_DEPTH : 0] rptr_d4sync;
wire f_wclk;
wire f_rclk;
wire fifo_wclk;
wire fifo_rclk;
wire fifo_we;
wire fifo_re;
wire fifo_reset;
wire [WRITE_DEPTH:0] tb_wcnt;
wire [READ_DEPTH:0] tb_rcnt;
wire tb_full;
wire tb_afull;
wire tb_empty;
wire tb_empty_int;
wire tb_aempty;
wire tb_underflow;
wire tb_overflow;
wire tb_dvld;
wire tb_wack;
wire [WRITE_DEPTH:0] wdiff_bus;
wire [READ_DEPTH:0] rdiff_bus;
wire full_w;
wire afull_w;
wire empty_w;
wire aempty_w;
wire aempty_w_assert;
wire aempty_w_deassert;
wire aempty_w_int;
wire temp;
wire dvld;
event check_wcnt;
event check_rcnt;
event check_full;
event check_afull;
event check_empty;
event check_aempty;
event check_overflow;
event check_underflow;
event check_dvld;
event check_wack;
integer err_cnt;
reg observe;
wire full_w_async;
wire full_w_sync;
reg [READ_DEPTH:0] sc_r;
initial
begin
err_cnt = 0;
end
assign f_wclk = SYNC ? clk : wclk;
assign f_rclk = SYNC ? clk : rclk;
assign fifo_wclk = WCLK_EDGE ? f_wclk : ~f_wclk;
assign fifo_rclk = SYNC ? WCLK_EDGE ? f_rclk : ~f_rclk : RCLK_EDGE ? f_rclk : ~f_rclk;
assign fifo_we = WE_POLARITY ? ~we : we;
assign fifo_re = RE_POLARITY ? ~re : re;
assign fifo_reset = RESET_POLARITY ? ~reset : reset;
assign wdiff_bus = SYNC ? (wptr - rptr) : (wptr - rptr_d4sync);
assign rdiff_bus = SYNC ? (wptr - rptr) : (wptr_d4sync- rptr);
//************************ Final output and flag assignments *******************************************/
assign tb_wcnt = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? wdiff_bus : wptr_r ;
assign tb_rcnt = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? rdiff_bus : rptr_r;
assign tb_full = SYNC ? full_w_sync : full_r;
assign tb_afull = SYNC ? (fifo_we ? afull_w : afull_r) : afull_r;
assign tb_empty_int = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? empty_w: empty_r ;
assign tb_empty = ((FWFT == 1) || (PREFETCH == 1)) ? (tb_empty_int | empty_r_fwft3) : tb_empty_int ;
assign tb_aempty = aempty_r;
assign tb_underflow = (SYNC == 1) ? underflow_w : underflow_r;
assign tb_overflow = overflow_r;
assign tb_dvld = (PIPE == 1) ? DVLD_d0 : (PIPE == 2) ? DVLD_d1 : (fifo_re && !empty);
assign tb_wack = wack_r;
//******************************************************************************************************/
//june 13
// assign full_w = (wdiff_bus >= (FULL_WRITE_DEPTH)) ;
assign full_w = SYNC ? full_w_sync : full_w_async;
assign full_w_sync = ( sc_r == (FULL_WRITE_DEPTH)) ;
assign full_w_async = we ? (wdiff_bus >= (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH)) ; // june 13
assign afull_w = SYNC ? (wdiff_bus >= AFVAL) : (wdiff_bus >= AFVAL-1);
assign empty_w = SYNC ? 0>= rdiff_bus : fifo_re ? (rdiff_bus<=1) : (rdiff_bus == 0) ;
assign aempty_w_assert = AEVAL >= rdiff_bus;
assign aempty_w_deassert = (AEVAL-1) >= rdiff_bus;
assign aempty_w_int = fifo_re ? aempty_w_assert : aempty_w_deassert;
assign aempty_w = aempty_w_int;
assign temp = (wptr >= FULL_WRITE_DEPTH-1 && rptr >= (FULL_READ_DEPTH -1)) ? 1 : 0;
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
wptr <= 0;
observe = 0;
end
else if(fifo_we == 1'b1 && full_r == 1'b0) begin
wptr <= wptr + 1;
end
end
// june 13
always @(negedge fifo_reset or posedge fifo_wclk)
begin
if (!fifo_reset) begin
sc_r <= 0;
end
else if ( fifo_we ^ fifo_re) begin
if(fifo_we == 1'b1) begin
sc_r <= (sc_r + 1);
end
else if(fifo_re == 1'b1) begin
sc_r <= (sc_r - 1);
end
end
end
always @(posedge fifo_rclk or negedge fifo_reset )
begin
if (!fifo_reset) begin
rptr <= 0;
observe = 0;
end
else if (fifo_re == 1'b1 && empty_reg == 1'b0 ) begin
rptr <= rptr + 1;
end
end
if (SYNC == 0) begin
if (WRITE_WIDTH > READ_WIDTH) begin
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
wptr_d1sync<= 0;
wptr_d2sync<= 0;
wptr_d3sync<= 0;
wptr_d4sync<= 0;
end
else begin
wptr_d1sync<= wptr;
wptr_d2sync<= wptr_d1sync;
wptr_d3sync<= wptr_d2sync;
if (wptr_d3sync < WRITE_WIDTH) begin
wptr_d4sync<= ((wptr_d3sync)*(WRITE_WIDTH/READ_WIDTH));
end
end
end
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
rptr_d1sync<= 0;
rptr_d2sync<= 0;
rptr_d3sync<= 0;
rptr_d4sync<= 0;
end
else begin
rptr_d1sync<= rptr;
rptr_d2sync<= rptr_d1sync;
rptr_d3sync<= rptr_d2sync;
if (rptr_d3sync < FULL_READ_DEPTH) begin
rptr_d4sync<= ((rptr_d3sync) /(WRITE_WIDTH/READ_WIDTH));
end
end
end
end
/*******************************************/
else if (WRITE_WIDTH < READ_WIDTH) begin
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
wptr_d1sync<= 0;
wptr_d2sync<= 0;
wptr_d3sync<= 0;
wptr_d4sync<= 0;
end
else begin
wptr_d1sync<= wptr;
wptr_d2sync<= wptr_d1sync;
wptr_d3sync<= wptr_d2sync;
if (wptr_d3sync <= FULL_WRITE_DEPTH) begin
wptr_d4sync<= ((wptr_d3sync)/(READ_WIDTH/WRITE_WIDTH));
end
end
end
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
rptr_d1sync<= 0;
rptr_d2sync<= 0;
rptr_d3sync<= 0;
rptr_d4sync<= 0;
end
else begin
rptr_d1sync<= rptr;
rptr_d2sync<= rptr_d1sync;
rptr_d3sync<= rptr_d2sync;
if (rptr_d3sync < READ_WIDTH) begin
rptr_d4sync<= ((rptr_d3sync)*(READ_WIDTH/WRITE_WIDTH));
end
end
end
end
/*******************************************/
else begin //(WRITE_WIDTH == READ_WIDTH)
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
wptr_d1sync<= 0;
wptr_d2sync<= 0;
wptr_d3sync<= 0;
wptr_d4sync<= 0;
end
else begin
wptr_d1sync<= wptr;
wptr_d2sync<= wptr_d1sync;
wptr_d3sync<= wptr_d2sync;
wptr_d4sync<= wptr_d3sync;
end
end
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if (!fifo_reset) begin
rptr_d1sync<= 0;
rptr_d2sync<= 0;
rptr_d3sync<= 0;
rptr_d4sync<= 0;
end
else begin
rptr_d1sync<= rptr;
rptr_d2sync<= rptr_d1sync;
rptr_d3sync<= rptr_d2sync;
rptr_d4sync<= rptr_d3sync;
end
end
end
end
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
full_reg <= 0;
end
else
full_reg <= full_r;
end
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
empty_reg <= 0;
end
else
empty_reg <= empty_r;
end
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
full_r <= 1'b0;
afull_r <= 1'b0;
wptr_r <= 0;
overflow_r <= 1'b0;
end
else begin
full_r <= full_w;
afull_r <= afull_w;
wptr_r <= wdiff_bus;
if(fifo_we == 1'b1 && full_reg == 1'b1 && OVERFLOW_EN == 1) begin
overflow_r <= 1'b1;
end
else begin
overflow_r <= 1'b0;
end
if(fifo_we == 1'b1 && full_w == 1'b1 && OVERFLOW_EN == 1) begin
overflow_w <= 1'b1;
end
else begin
overflow_w <= 1'b0;
end
end
end
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
empty_r <= 1'b1;
empty_r_fwft1 <= 1'b1;
empty_r_fwft2 <= 1'b1;
empty_r_fwft3 <= 1'b1;
empty_rt <= 1'b1;
aempty_r <= 1'b1;
rptr_r <= 0;
end
else begin
empty_r <= empty_w;
empty_r_fwft1 <= empty_r;
empty_r_fwft2 <= empty_r_fwft1;
empty_r_fwft3 <= empty_r_fwft2;
empty_rt <= empty_w;
aempty_r <= aempty_w;
rptr_r <= rdiff_bus;
end
end
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
underflow_r <= 1'b0;
underflow_w <= 1'b0;
end
else begin
if(fifo_re == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1 && SYNC == 0) begin
underflow_r <= 1'b1;
end
else begin
underflow_r <= 1'b0;
end
if(fifo_re == 1'b1 && empty_w == 1'b1 && UNDERFLOW_EN == 1 && SYNC == 1) begin
underflow_w <= 1'b1;
end
else begin
underflow_w <= 1'b0;
end
end
end
reg underflow_start, overflow_start;
always @(posedge underflow_w or underflow_r or negedge fifo_reset)
begin
if(!fifo_reset) begin
underflow_start <=0;
end
else begin
underflow_start <=1;
end
end
always @(posedge overflow_w or underflow_r or negedge fifo_reset)
begin
if(!fifo_reset) begin
overflow_start <=0;
end
else begin
overflow_start <=1;
end
end
always @(posedge fifo_rclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
DVLD_d0 <=0;
DVLD_d1 <=0;
DVLD_d2 <=0;
end
else begin
DVLD_d0 <=(fifo_re && !empty);
DVLD_d1 <=DVLD_d0;
DVLD_d2 <=DVLD_d1;
end
end
always @(posedge fifo_wclk or negedge fifo_reset)
begin
if(!fifo_reset) begin
wack_r <=0;
end
else begin
wack_r <=(fifo_we && !full_r);
end
end
/**************** EVENT geneartion whenever flag asserted ************************************/
always @(tb_dvld or dvld)
begin
if ((fifo_reset ==1) && READ_DVALID == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH))
#1
-> check_dvld;
end
always @(tb_wack or wack)
begin
if ((fifo_reset ==1) && WRITE_ACK == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH))
#1
-> check_wack;
end
always @(tb_wcnt or wcnt)
begin
if ((fifo_reset ==1) && WRCNT_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_wcnt;
end
always @(tb_rcnt or rcnt)
begin
if ((fifo_reset == 1) && RDCNT_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_rcnt;
end
always @(tb_full or full)
begin
if ((fifo_reset == 1) && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_full;
end
always @(tb_afull or afull)
begin
if ((fifo_reset == 1) && AF_STATIC_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_afull;
end
always @(tb_empty or empty )
begin
if (fifo_reset == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_empty;
end
always @(tb_aempty or aempty)
begin
if ((fifo_reset == 1) && AE_STATIC_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_aempty;
end
always @(tb_overflow or overflow)
begin
if ((fifo_reset == 1) && OVERFLOW_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_overflow;
end
always @(tb_underflow or underflow)
begin
if ((fifo_reset == 1) && UNDERFLOW_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
#1
-> check_underflow;
end
/************************** Checker placed to compare with DUT signal status v/s expected signal status *********************/
always @(check_wack)
begin
//check_wack_out(tb_wack);
end
always @(check_dvld)
begin
//check_dvld_out(tb_dvld);
end
always @(check_wcnt)
begin
//check_wcnt_out(tb_wcnt);
end
always @(check_rcnt)
begin
//check_rcnt_out(tb_rcnt);
end
always @(check_full)
begin
check_full_flag(tb_full);
end
always @(check_afull)
begin
check_afull_flag(tb_afull);
end
always @(check_empty)
begin
check_empty_flag(tb_empty);
end
always @(check_aempty)
begin
check_aempty_flag(tb_aempty);
end
always @(check_overflow)
begin
check_overflow_flag(tb_overflow);
end
always @(check_underflow)
begin
check_underflow_flag(tb_underflow);
end
/******************************* TASKS ********************************************************/
task check_reset;
input expected_value;
begin
#1
$display("fifo reset = %b", fifo_reset);
if (fifo_reset != expected_value)
begin
$display("ERROR: fifo reset = %b - expected value= %b", fifo_reset, expected_value);
end
end
endtask
task check_wack_out;
input expected_value;
begin
#1
if ((wack !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo wack = %d - expected value= %d ",$time, wack , expected_value);
err_cnt = err_cnt +1;
end
else
$display ( "At", $time, " PASS: WACK match \n");
end
endtask
task check_dvld_out;
input expected_value;
begin
#1
if ((dvld !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo dvld = %d - expected value= %d ",$time, dvld , expected_value);
err_cnt = err_cnt +1;
end
else
$display ( "At", $time, " PASS: DVLD match \n");
end
endtask
task check_wcnt_out;
input[WRITE_DEPTH:0] expected_value;
begin
#1
if ((wcnt !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo write_count = %d - expected value= %d ",$time, wcnt , expected_value);
err_cnt = err_cnt +1;
end
else
$display ( "At", $time, " PASS: write_count match \n");
end
endtask
task check_rcnt_out;
input[READ_DEPTH:0] expected_value;
begin
#1
if ((rcnt !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo read_count = %d - expected value= %d ",$time, rcnt , expected_value);
err_cnt = err_cnt +1;
end
else
$display ( "At", $time, " PASS: read_count match \n");
end
endtask
task check_full_flag;
input expected_value;
begin
#1
if ((full !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo full flag = %b - expected value= %b ",$time, full , expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: FULL flag match \n");
end
endtask
task check_afull_flag;
input expected_value;
begin
#1
if ((afull !== expected_value) && (underflow_start ==0 && overflow_start == 0) ) begin
$display("ERROR: At %t fifo afull flag = %b - expected value = %b ",$time ,afull, expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: AFULL flag match \n");
end
endtask
task check_empty_flag;
input expected_value;
begin
#2
if ((empty !== expected_value) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo empty flag = %b - expected value = %b ",$time, empty, expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: EMPTY flag match \n");
end
endtask
task check_aempty_flag;
input expected_value;
begin
#1
if ((aempty !== expected_value) && (underflow_start ==0 && overflow_start == 0)) begin
$display("ERROR: At %t fifo aempty flag = %b - expected value = %b",$time ,aempty, expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: AEMPTY flag match \n");
end
endtask
task check_overflow_flag;
input expected_value;
begin
#1
if (overflow !== expected_value ) begin
$display("ERROR: At %t fifo overflow flag = %b - expected value = %b", $time, overflow, expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: OVERFLOW flag match \n");
end
endtask
task check_underflow_flag;
input expected_value;
begin
#1
if (underflow !== expected_value) begin
$display("ERROR: At %t fifo underflow flag = %b - expected value = %b", $time, underflow, expected_value);
err_cnt = err_cnt +1;
observe = ~observe;
end
else
$display ( "At", $time, " PASS: UNDERFLOW flag match \n");
end
endtask
endmodule

114
component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/g4_dp_ext_mem.v Normal file
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module g4_dp_ext_mem (
clk,
wclk,
rclk,
rst_n,
waddr,
raddr,
data,
we,
re,
q
);
// Memory parameters
parameter SYNC = 0;
parameter RAM_RW = 18;
parameter RAM_WW = 18;
parameter RAM_WD = 10;
parameter RAM_RD = 10;
parameter WRITE_ADDRESS_END = 1024;
parameter READ_ADDRESS_END = 1024;
parameter WRITE_CLK = 1;
parameter READ_CLK = 1;
parameter WRITE_ENABLE = 1;
parameter READ_ENABLE = 1;
parameter RESET_POLARITY = 0;
parameter PIPE = 1;
// local inputs
input clk;
input wclk;
input rclk;
input rst_n;
// local inputs - memory functional bus
input [RAM_WD-1:0] waddr;
input [RAM_WW-1:0] data;
input [RAM_RD-1:0] raddr;
input we;
input re;
//OUTPUTS
//======
output [RAM_RW-1:0] q;
generate
if (RAM_RW > RAM_WW) begin
MEM_WltR #(
.SYNC(SYNC),
.RAM_WW(RAM_WW),
.RAM_RW(RAM_RW),
.RAM_WD(RAM_WD),
.RAM_RD(RAM_RD),
.READ_ADDRESS_END(READ_ADDRESS_END),
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
.WRITE_CLK(WRITE_CLK),
.READ_CLK(READ_CLK),
.WRITE_ENABLE(WRITE_ENABLE),
.READ_ENABLE(READ_ENABLE),
.RESET_POLARITY(RESET_POLARITY),
.PIPE(PIPE)
)
inst0 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
end
else if (RAM_RW < RAM_WW) begin
MEM_WgtR #(
.SYNC(SYNC),
.RAM_WW(RAM_WW),
.RAM_RW(RAM_RW),
.RAM_WD(RAM_WD),
.RAM_RD(RAM_RD),
.READ_ADDRESS_END(READ_ADDRESS_END),
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
.WRITE_CLK(WRITE_CLK),
.READ_CLK(READ_CLK),
.WRITE_ENABLE(WRITE_ENABLE),
.READ_ENABLE(READ_ENABLE),
.RESET_POLARITY(RESET_POLARITY),
.PIPE(PIPE)
)
inst1 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
end
else if (RAM_RW == RAM_WW) begin
MEM_WeqR # (
.SYNC(SYNC),
.RAM_WW(RAM_WW),
.RAM_RW(RAM_RW),
.RAM_WD(RAM_WD),
.RAM_RD(RAM_RD),
.READ_ADDRESS_END(READ_ADDRESS_END),
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
.WRITE_CLK(WRITE_CLK),
.READ_CLK(READ_CLK),
.WRITE_ENABLE(WRITE_ENABLE),
.READ_ENABLE(READ_ENABLE),
.RESET_POLARITY(RESET_POLARITY),
.PIPE(PIPE)
)
inst2 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
end
endgenerate
endmodule

1
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/COREJTAGDEBUG.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREJTAGDEBUG</name><vendor>Actel</vendor><library>DirectCore</library><version>4.0.100</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\test\corejtagdebug_host_emulator.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\test\corejtagdebug_jtag_tap.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\test\corejtagdebug_testbench.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>COREJTAGDEBUG_TESTBENCH</ModuleUnderTest><SimulationTime>-all</SimulationTime></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="3"><name>mti\corejtagdebug_wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>core\corejtagdebug.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="5"><name>core\corejtagdebug_ujtag_wrapper.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="6"><name>core\corejtagdebug_uj_jtag.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="7"><name>core\corejtagdebug_bufd.v</name><logicalName>COREJTAGDEBUG_LIB</logicalName><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

672
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug.v Normal file
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@@ -0,0 +1,672 @@
// ****************************************************************************/
// ****************************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2017 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description:
//
// SVN Revision Information:
// SVN $Revision: 37981 $
// SVN $Date: 2021-04-09 11:16:51 +0100 (Fri, 09 Apr 2021) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ****************************************************************************/
module COREJTAGDEBUG (
input TCK,
input TMS,
input TDI,
input TRSTB,
input UTRSTB_SEC,
input EN_SEC,
input TDI_SEC,
output UTRSTB,
output UTMS,
output TDO,
output TGT_TCK_0,
output TGT_TMS_0,
output TGT_TDI_0,
output TGT_TRSTN_0,
output TGT_TRST_0,
input TGT_TDO_0,
output TGT_TCK_1,
output TGT_TMS_1,
output TGT_TDI_1,
output TGT_TRSTN_1,
output TGT_TRST_1,
input TGT_TDO_1,
output TGT_TCK_2,
output TGT_TMS_2,
output TGT_TDI_2,
output TGT_TRSTN_2,
output TGT_TRST_2,
input TGT_TDO_2,
output TGT_TCK_3,
output TGT_TMS_3,
output TGT_TDI_3,
output TGT_TRSTN_3,
output TGT_TRST_3,
input TGT_TDO_3,
output TGT_TCK_4,
output TGT_TMS_4,
output TGT_TDI_4,
output TGT_TRSTN_4,
output TGT_TRST_4,
input TGT_TDO_4,
output TGT_TCK_5,
output TGT_TMS_5,
output TGT_TDI_5,
output TGT_TRSTN_5,
output TGT_TRST_5,
input TGT_TDO_5,
output TGT_TCK_6,
output TGT_TMS_6,
output TGT_TDI_6,
output TGT_TRSTN_6,
output TGT_TRST_6,
input TGT_TDO_6,
output TGT_TCK_7,
output TGT_TMS_7,
output TGT_TDI_7,
output TGT_TRSTN_7,
output TGT_TRST_7,
input TGT_TDO_7,
output TGT_TCK_8,
output TGT_TMS_8,
output TGT_TDI_8,
output TGT_TRSTN_8,
output TGT_TRST_8,
input TGT_TDO_8,
output TGT_TCK_9,
output TGT_TMS_9,
output TGT_TDI_9,
output TGT_TRSTN_9,
output TGT_TRST_9,
input TGT_TDO_9,
output TGT_TCK_10,
output TGT_TMS_10,
output TGT_TDI_10,
output TGT_TRSTN_10,
output TGT_TRST_10,
input TGT_TDO_10,
output TGT_TCK_11,
output TGT_TMS_11,
output TGT_TDI_11,
output TGT_TRSTN_11,
output TGT_TRST_11,
input TGT_TDO_11,
output TGT_TCK_12,
output TGT_TMS_12,
output TGT_TDI_12,
output TGT_TRSTN_12,
output TGT_TRST_12,
input TGT_TDO_12,
output TGT_TCK_13,
output TGT_TMS_13,
output TGT_TDI_13,
output TGT_TRSTN_13,
output TGT_TRST_13,
input TGT_TDO_13,
output TGT_TCK_14,
output TGT_TMS_14,
output TGT_TDI_14,
output TGT_TRSTN_14,
output TGT_TRST_14,
input TGT_TDO_14,
output TGT_TCK_15,
output TGT_TMS_15,
output TGT_TDI_15,
output TGT_TRSTN_15,
output TGT_TRST_15,
input TGT_TDO_15,
input UJTAG_BYPASS_TCK_0/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TMS_0/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TDI_0/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TRSTB_0/* synthesis syn_keep = 1 */,
output UJTAG_BYPASS_TDO_0/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TCK_1/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TMS_1/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TDI_1/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TRSTB_1/* synthesis syn_keep = 1 */,
output UJTAG_BYPASS_TDO_1/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TCK_2/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TMS_2/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TDI_2/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TRSTB_2/* synthesis syn_keep = 1 */,
output UJTAG_BYPASS_TDO_2/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TCK_3/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TMS_3/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TDI_3/* synthesis syn_keep = 1 */,
input UJTAG_BYPASS_TRSTB_3/* synthesis syn_keep = 1 */,
output UJTAG_BYPASS_TDO_3/* synthesis syn_keep = 1 */
);
////////////////////////////////////////////////////////////////////////////////
// Parameters
////////////////////////////////////////////////////////////////////////////////
parameter FAMILY = 19;
parameter NUM_DEBUG_TGTS = 16;
parameter TGT_ACTIVE_HIGH_RESET_0 = 1'b0;
parameter [7:0] IR_CODE_TGT_0 = 8'h55;
parameter TGT_ACTIVE_HIGH_RESET_1 = 1'b0;
parameter [7:0] IR_CODE_TGT_1 = 8'h56;
parameter TGT_ACTIVE_HIGH_RESET_2 = 1'b0;
parameter [7:0] IR_CODE_TGT_2 = 8'h57;
parameter TGT_ACTIVE_HIGH_RESET_3 = 1'b0;
parameter [7:0] IR_CODE_TGT_3 = 8'h58;
parameter TGT_ACTIVE_HIGH_RESET_4 = 1'b0;
parameter [7:0] IR_CODE_TGT_4 = 8'h59;
parameter TGT_ACTIVE_HIGH_RESET_5 = 1'b0;
parameter [7:0] IR_CODE_TGT_5 = 8'h5A;
parameter TGT_ACTIVE_HIGH_RESET_6 = 1'b0;
parameter [7:0] IR_CODE_TGT_6 = 8'h5B;
parameter TGT_ACTIVE_HIGH_RESET_7 = 1'b0;
parameter [7:0] IR_CODE_TGT_7 = 8'h5C;
parameter TGT_ACTIVE_HIGH_RESET_8 = 1'b0;
parameter [7:0] IR_CODE_TGT_8 = 8'h5D;
parameter TGT_ACTIVE_HIGH_RESET_9 = 1'b0;
parameter [7:0] IR_CODE_TGT_9 = 8'h5E;
parameter TGT_ACTIVE_HIGH_RESET_10 = 1'b0;
parameter [7:0] IR_CODE_TGT_10 = 8'h5F;
parameter TGT_ACTIVE_HIGH_RESET_11 = 1'b0;
parameter [7:0] IR_CODE_TGT_11 = 8'h60;
parameter TGT_ACTIVE_HIGH_RESET_12 = 1'b0;
parameter [7:0] IR_CODE_TGT_12 = 8'h61;
parameter TGT_ACTIVE_HIGH_RESET_13 = 1'b0;
parameter [7:0] IR_CODE_TGT_13 = 8'h62;
parameter TGT_ACTIVE_HIGH_RESET_14 = 1'b0;
parameter [7:0] IR_CODE_TGT_14 = 8'h63;
parameter TGT_ACTIVE_HIGH_RESET_15 = 1'b0;
parameter [7:0] IR_CODE_TGT_15 = 8'h64;
parameter UJTAG_BYPASS = 1'b0;
parameter [0:0] UJTAG_SEC_EN = 1'b0;
////////////////////////////////////////////////////////////////////////////////
// Internal signals
////////////////////////////////////////////////////////////////////////////////
wire UTDO;
wire [NUM_DEBUG_TGTS-1:0] UTDODriven;
wire iUDRCK;
//wire UDRCKInt;
wire iURSTB;
wire iURSTB_inv;
//wire URSTBInt;
//wire URSTBInvInt;
wire UDRCAPInt;
wire UDRSHInt;
wire UDRUPDInt;
wire [7:0] UIREGInt;
wire UTDIInt;
wire [15:0] TGT_TDOInt_All;
wire [NUM_DEBUG_TGTS-1:0] TGT_TDOInt;
wire [NUM_DEBUG_TGTS-1:0] UTDOInt;
wire [NUM_DEBUG_TGTS-1:0] UTDODRVInt;
wire [NUM_DEBUG_TGTS-1:0] TGT_TCKInt;
wire [NUM_DEBUG_TGTS-1:0] TGT_TCKInt_Y;
wire [NUM_DEBUG_TGTS-1:0] TGT_TCKInt_Glb;
wire [NUM_DEBUG_TGTS-1:0] TGT_TRSTXInt_Glb;
wire [NUM_DEBUG_TGTS-1:0] TGT_TMSInt;
wire [NUM_DEBUG_TGTS-1:0] TGT_TDIInt;
genvar idx;
////////////////////////////////////////////////////////////////////////////////
// Constants
////////////////////////////////////////////////////////////////////////////////
localparam DELAY_NUM = 34;
localparam [127:0] IR_CODE_TGT = {
IR_CODE_TGT_15, IR_CODE_TGT_14, IR_CODE_TGT_13, IR_CODE_TGT_12,
IR_CODE_TGT_11, IR_CODE_TGT_10, IR_CODE_TGT_9, IR_CODE_TGT_8,
IR_CODE_TGT_7, IR_CODE_TGT_6, IR_CODE_TGT_5, IR_CODE_TGT_4,
IR_CODE_TGT_3, IR_CODE_TGT_2, IR_CODE_TGT_1, IR_CODE_TGT_0
};
localparam [15:0] TGT_ACTIVE_HIGH_RESET = {
TGT_ACTIVE_HIGH_RESET_15[0], TGT_ACTIVE_HIGH_RESET_14[0], TGT_ACTIVE_HIGH_RESET_13[0], TGT_ACTIVE_HIGH_RESET_12[0],
TGT_ACTIVE_HIGH_RESET_11[0], TGT_ACTIVE_HIGH_RESET_10[0], TGT_ACTIVE_HIGH_RESET_9[0], TGT_ACTIVE_HIGH_RESET_8[0],
TGT_ACTIVE_HIGH_RESET_7[0], TGT_ACTIVE_HIGH_RESET_6[0], TGT_ACTIVE_HIGH_RESET_5[0], TGT_ACTIVE_HIGH_RESET_4[0],
TGT_ACTIVE_HIGH_RESET_3[0], TGT_ACTIVE_HIGH_RESET_2[0], TGT_ACTIVE_HIGH_RESET_1[0], TGT_ACTIVE_HIGH_RESET_0[0]
};
// Some families have a subtly different UJTAG macro - one that has a
// UIREG[7:0] port instead of eight separate ports ranging from UIREG0
// to UIREG7.
localparam USE_NEW_UJTAG = (FAMILY == 19) ? 1 : // SmartFusion2
(FAMILY == 24) ? 1 : // IGLOO2
(FAMILY == 25) ? 1 : // RTG4
((FAMILY == 26) & (!UJTAG_SEC_EN)) ? 1 : 0 ; // PolarFire
// When using multiple UJTAG instances in a design a specific wrapper is needed
// for G4 and G5( and later ) devices. This parameter is used to make sure that
// the correct UJTAG instance is used for each family.
localparam USE_UJTAG_WRAPPER = (FAMILY == 19) ? 1 : // SmartFusion2
(FAMILY == 24) ? 1 : // IGLOO2
(FAMILY == 25) ? 1 :0; // RTG4
localparam USE_UJTAG_SEC = ((UJTAG_SEC_EN) & (FAMILY == 26)) ? 1 : 0 ; // PolarFire
////////////////////////////////////////////////////////////////////////////////
// Instantiate one UJTAG macro instance
////////////////////////////////////////////////////////////////////////////////
generate
if (!UJTAG_BYPASS)
begin
if(USE_UJTAG_SEC)
begin
//--------UJTAG_SEC
UJTAG_SEC UJTAG_SEC_0(
// Inputs
.UTDO ( UTDO ),
.UTRSTB_SEC ( UTRSTB_SEC ),
.EN_SEC ( EN_SEC ),
.TDI_SEC ( TDI_SEC ),
.TCK ( TCK ),
.TRSTB ( TRSTB ),
.TDI ( TDI ),
.TMS ( TMS ),
// Outputs
.UDRCAP ( UDRCAPInt ),
.UDRSH ( UDRSHInt ),
.UDRUPD ( UDRUPDInt ),
.UIREG ( UIREGInt[7:0] ),
.URSTB ( iURSTB ),
.UTDI ( UTDIInt ),
.UTRSTB ( UTRSTB ),
.UTMS ( UTMS ),
.TDO ( TDO ),
.UDRCK ( iUDRCK )
);
end
else if (USE_NEW_UJTAG)
begin
if (USE_UJTAG_WRAPPER)
begin
UJTAG_WRAPPER UJTAG_inst(
// Inputs
.UTDO (UTDO),
.TDI (TDI),
.TMS (TMS),
.TCK (TCK),
.TRSTB (TRSTB),
// Outputs
.UDRCAP (UDRCAPInt),
.UDRSH (UDRSHInt),
.UDRUPD (UDRUPDInt),
.UIREG (UIREGInt[7:0]),
.URSTB (iURSTB),
.UDRCK (iUDRCK),
.UTDI (UTDIInt),
.TDO (TDO)
);
end
else
begin
UJTAG UJTAG_inst(
// Inputs
.UTDO (UTDO),
.TDI (TDI),
.TMS (TMS),
.TCK (TCK),
.TRSTB (TRSTB),
// Outputs
.UDRCAP (UDRCAPInt),
.UDRSH (UDRSHInt),
.UDRUPD (UDRUPDInt),
.UIREG (UIREGInt[7:0]),
.URSTB (iURSTB),
.UDRCK (iUDRCK),
.UTDI (UTDIInt),
.TDO (TDO)
);
end
end
else
begin
UJTAG UJTAG_inst(
// Inputs
.UTDO (UTDO),
.TDI (TDI),
.TMS (TMS),
.TCK (TCK),
.TRSTB (TRSTB),
// Outputs
.UDRCAP (UDRCAPInt),
.UDRSH (UDRSHInt),
.UDRUPD (UDRUPDInt),
.UIREG7 (UIREGInt[7]),
.UIREG6 (UIREGInt[6]),
.UIREG5 (UIREGInt[5]),
.UIREG4 (UIREGInt[4]),
.UIREG3 (UIREGInt[3]),
.UIREG2 (UIREGInt[2]),
.UIREG1 (UIREGInt[1]),
.UIREG0 (UIREGInt[0]),
.URSTB (iURSTB),
.UDRCK (iUDRCK),
.UTDI (UTDIInt),
.TDO (TDO)
);
end
end
endgenerate
// Use a low-skew resource for routing the clock between the UJTAG
// macro and the uj_jtag tunneling logic sequential elements.
/*CLKINT UDRCK_GLB(
.A (iUDRCK),
.Y (UDRCKInt)
);
CLKINT URSTB_GLB(
.A (iURSTB),
.Y (URSTBInt)
);*/
generate
if (!UJTAG_BYPASS)
begin
wire [NUM_DEBUG_TGTS-1:0] dut_trst_int;
wire [NUM_DEBUG_TGTS-1:0] dut_trst_delay;
if (TGT_ACTIVE_HIGH_RESET[NUM_DEBUG_TGTS-1:0] != {NUM_DEBUG_TGTS{1'b0}})
begin
// Some debug targets require an active-high reset source. Invert
// the reset and promote it to a global.
assign iURSTB_inv = ~iURSTB;
/*CLKINT URSTB_INV_GLB(
.A (iURSTB_inv),
.Y (URSTBInvInt)
);*/
end
for (idx = 0; idx < NUM_DEBUG_TGTS; idx = idx + 1)
begin
if (TGT_ACTIVE_HIGH_RESET[idx])
begin
assign dut_trst_int[idx] = iURSTB_inv; //URSTBInvInt;
end
else
begin
assign dut_trst_int[idx] = iURSTB; //URSTBInt;
end
// Delay Buffers added for Polarfire to resolve minimum timing violations
corejtagdebug_bufd #(.DELAY_NUM(DELAY_NUM)) BUFD_TRST (.A(dut_trst_int[idx]), .Y(dut_trst_delay[idx]));
assign TGT_TRSTXInt_Glb[idx] = (FAMILY == 26) ? dut_trst_delay[idx] : dut_trst_int[idx];
end
end
endgenerate
generate
if (!UJTAG_BYPASS)
begin
if (NUM_DEBUG_TGTS > 1)
begin
// Instate multiple COREJTAGDEBUG_UJ_JTAG module instances, one per
// debug target
for (idx = 0; idx < NUM_DEBUG_TGTS; idx = idx + 1)
begin
COREJTAGDEBUG_UJ_JTAG #(
.DELAY_NUM (DELAY_NUM),
.FAMILY (FAMILY),
.IR_CODE_TGT (IR_CODE_TGT[((idx+1)*8)-1:idx*8])
) UJ_JTAG (
// UJTAG inputs
.UDRCK (iUDRCK), //(UDRCKInt),
.URSTB (iURSTB), //(URSTBInt),
.UDRCAP (UDRCAPInt),
.UDRSH (UDRSHInt),
.UDRUPD (UDRUPDInt),
.UIREG (UIREGInt),
.UTDI (UTDIInt),
// TGT JTAG inputs
.DUT_TDO (TGT_TDOInt[idx]),
// UJTAG outputs
.UTDO (UTDOInt[idx]),
.UTDODRV (UTDODRVInt[idx]),
// TGT outputs
.DUT_TCK (TGT_TCKInt[idx]), //ts : Removed CLKINT since this is now taken care by Libero
.DUT_TMS (TGT_TMSInt[idx]),
.DUT_TDI (TGT_TDIInt[idx])
);
// CLKINT added for Polarfire to resolve minimum timing violations
CLKINT TGT_TCK_GLB (
.A (TGT_TCKInt[idx]),
.Y (TGT_TCKInt_Y[idx])
);
assign TGT_TCKInt_Glb[idx]= ((FAMILY == 25) || (FAMILY == 26)) ? TGT_TCKInt_Y[idx] : TGT_TCKInt[idx];
end
end
else
begin
// Instantiate a single uj_jtag module instance
COREJTAGDEBUG_UJ_JTAG #(
.DELAY_NUM (DELAY_NUM),
.FAMILY (FAMILY),
.IR_CODE_TGT (IR_CODE_TGT)
) UJ_JTAG (
// UJTAG inputs
.UDRCK (iUDRCK), //(UDRCKInt),
.URSTB (iURSTB), //(URSTBInt),
.UDRCAP (UDRCAPInt),
.UDRSH (UDRSHInt),
.UDRUPD (UDRUPDInt),
.UIREG (UIREGInt),
.UTDI (UTDIInt),
// TGT JTAG inputs
.DUT_TDO (TGT_TDOInt),
// UJTAG outputs
.UTDO (UTDOInt),
.UTDODRV (UTDODRVInt),
// TGT outputs
.DUT_TCK (TGT_TCKInt), //ts : Removed CLKINT since this is now taken care by Libero
.DUT_TMS (TGT_TMSInt),
.DUT_TDI (TGT_TDIInt)
);
// Each debug target's clock is promoted to a separate low-skew
// routing resource as clock gating is implemented in the uj_jtag
// tunnel controller to prevent TDI assertions from upsetting the
// targets TAP FSM during the length fields of the tunnel packet.
// CLKINT added for Polarfire to resolve minimum timing violations
CLKINT TGT_TCK_GLB (
.A (TGT_TCKInt),
.Y (TGT_TCKInt_Y)
);
assign TGT_TCKInt_Glb = ((FAMILY == 25) || (FAMILY == 26)) ? TGT_TCKInt_Y : TGT_TCKInt;
end
end
endgenerate
generate
if (!UJTAG_BYPASS)
begin
assign UTDODriven = UTDOInt[NUM_DEBUG_TGTS-1:0] & UTDODRVInt[NUM_DEBUG_TGTS-1:0];
assign UTDO = |UTDODriven[NUM_DEBUG_TGTS-1:0];
assign {TGT_TCK_15, TGT_TCK_14, TGT_TCK_13, TGT_TCK_12, TGT_TCK_11,
TGT_TCK_10, TGT_TCK_9, TGT_TCK_8, TGT_TCK_7, TGT_TCK_6,
TGT_TCK_5, TGT_TCK_4, TGT_TCK_3, TGT_TCK_2, TGT_TCK_1,
TGT_TCK_0} = {{16-NUM_DEBUG_TGTS{1'b0}}, TGT_TCKInt_Glb[NUM_DEBUG_TGTS-1:0]};
assign {TGT_TMS_15, TGT_TMS_14, TGT_TMS_13, TGT_TMS_12, TGT_TMS_11,
TGT_TMS_10, TGT_TMS_9, TGT_TMS_8, TGT_TMS_7, TGT_TMS_6,
TGT_TMS_5, TGT_TMS_4, TGT_TMS_3, TGT_TMS_2, TGT_TMS_1,
TGT_TMS_0} = {{16-NUM_DEBUG_TGTS{1'b0}}, TGT_TMSInt[NUM_DEBUG_TGTS-1:0]};
assign {TGT_TDI_15, TGT_TDI_14, TGT_TDI_13, TGT_TDI_12, TGT_TDI_11,
TGT_TDI_10, TGT_TDI_9, TGT_TDI_8, TGT_TDI_7, TGT_TDI_6,
TGT_TDI_5, TGT_TDI_4, TGT_TDI_3, TGT_TDI_2, TGT_TDI_1,
TGT_TDI_0} = {{16-NUM_DEBUG_TGTS{1'b0}}, TGT_TDIInt[NUM_DEBUG_TGTS-1:0]};
assign {TGT_TRSTN_15, TGT_TRSTN_14, TGT_TRSTN_13, TGT_TRSTN_12, TGT_TRSTN_11,
TGT_TRSTN_10, TGT_TRSTN_9, TGT_TRSTN_8, TGT_TRSTN_7, TGT_TRSTN_6,
TGT_TRSTN_5, TGT_TRSTN_4, TGT_TRSTN_3, TGT_TRSTN_2, TGT_TRSTN_1,
TGT_TRSTN_0} = {{16-NUM_DEBUG_TGTS{1'b0}}, TGT_TRSTXInt_Glb[NUM_DEBUG_TGTS-1:0]};
assign {TGT_TRST_15, TGT_TRST_14, TGT_TRST_13, TGT_TRST_12, TGT_TRST_11,
TGT_TRST_10, TGT_TRST_9, TGT_TRST_8, TGT_TRST_7, TGT_TRST_6,
TGT_TRST_5, TGT_TRST_4, TGT_TRST_3, TGT_TRST_2, TGT_TRST_1,
TGT_TRST_0} = {{16-NUM_DEBUG_TGTS{1'b0}}, TGT_TRSTXInt_Glb[NUM_DEBUG_TGTS-1:0]};
end
endgenerate
generate
if (!UJTAG_BYPASS)
begin
assign TGT_TDOInt_All = {TGT_TDO_15, TGT_TDO_14, TGT_TDO_13, TGT_TDO_12,
TGT_TDO_11, TGT_TDO_10, TGT_TDO_9, TGT_TDO_8,
TGT_TDO_7, TGT_TDO_6, TGT_TDO_5, TGT_TDO_4,
TGT_TDO_3, TGT_TDO_2, TGT_TDO_1, TGT_TDO_0};
assign TGT_TDOInt[NUM_DEBUG_TGTS-1:0] = TGT_TDOInt_All[NUM_DEBUG_TGTS-1:0];
end
endgenerate
//GPIO JTAG
generate
if (UJTAG_BYPASS)
begin
if(NUM_DEBUG_TGTS <= 1)
begin
assign TGT_TCK_0 = UJTAG_BYPASS_TCK_0;
assign TGT_TMS_0 = UJTAG_BYPASS_TMS_0;
assign TGT_TDI_0 = UJTAG_BYPASS_TDI_0;
assign TGT_TRSTN_0 = UJTAG_BYPASS_TRSTB_0;
assign TGT_TRST_0 = !UJTAG_BYPASS_TRSTB_0;
assign UJTAG_BYPASS_TDO_0 = TGT_TDO_0;
end
else if(NUM_DEBUG_TGTS == 2)
begin
assign TGT_TCK_0 = UJTAG_BYPASS_TCK_0;
assign TGT_TMS_0 = UJTAG_BYPASS_TMS_0;
assign TGT_TDI_0 = UJTAG_BYPASS_TDI_0;
assign TGT_TRSTN_0 = UJTAG_BYPASS_TRSTB_0;
assign TGT_TRST_0 = !UJTAG_BYPASS_TRSTB_0;
assign UJTAG_BYPASS_TDO_0 = TGT_TDO_0;
assign TGT_TCK_1 = UJTAG_BYPASS_TCK_1;
assign TGT_TMS_1 = UJTAG_BYPASS_TMS_1;
assign TGT_TDI_1 = UJTAG_BYPASS_TDI_1;
assign TGT_TRSTN_1 = UJTAG_BYPASS_TRSTB_1;
assign TGT_TRST_1 = !UJTAG_BYPASS_TRSTB_1;
assign UJTAG_BYPASS_TDO_1 = TGT_TDO_1;
end
else if(NUM_DEBUG_TGTS == 3)
begin
assign TGT_TCK_0 = UJTAG_BYPASS_TCK_0;
assign TGT_TMS_0 = UJTAG_BYPASS_TMS_0;
assign TGT_TDI_0 = UJTAG_BYPASS_TDI_0;
assign TGT_TRSTN_0 = UJTAG_BYPASS_TRSTB_0;
assign TGT_TRST_0 = !UJTAG_BYPASS_TRSTB_0;
assign UJTAG_BYPASS_TDO_0 = TGT_TDO_0;
assign TGT_TCK_1 = UJTAG_BYPASS_TCK_1;
assign TGT_TMS_1 = UJTAG_BYPASS_TMS_1;
assign TGT_TDI_1 = UJTAG_BYPASS_TDI_1;
assign TGT_TRSTN_1 = UJTAG_BYPASS_TRSTB_1;
assign TGT_TRST_1 = !UJTAG_BYPASS_TRSTB_1;
assign UJTAG_BYPASS_TDO_1 = TGT_TDO_1;
assign TGT_TCK_2 = UJTAG_BYPASS_TCK_2;
assign TGT_TMS_2 = UJTAG_BYPASS_TMS_2;
assign TGT_TDI_2 = UJTAG_BYPASS_TDI_2;
assign TGT_TRSTN_2 = UJTAG_BYPASS_TRSTB_2;
assign TGT_TRST_2 = !UJTAG_BYPASS_TRSTB_2;
assign UJTAG_BYPASS_TDO_2 = TGT_TDO_2;
end
else
begin
assign TGT_TCK_0 = UJTAG_BYPASS_TCK_0;
assign TGT_TMS_0 = UJTAG_BYPASS_TMS_0;
assign TGT_TDI_0 = UJTAG_BYPASS_TDI_0;
assign TGT_TRSTN_0 = UJTAG_BYPASS_TRSTB_0;
assign TGT_TRST_0 = !UJTAG_BYPASS_TRSTB_0;
assign UJTAG_BYPASS_TDO_0 = TGT_TDO_0;
assign TGT_TCK_1 = UJTAG_BYPASS_TCK_1;
assign TGT_TMS_1 = UJTAG_BYPASS_TMS_1;
assign TGT_TDI_1 = UJTAG_BYPASS_TDI_1;
assign TGT_TRSTN_1 = UJTAG_BYPASS_TRSTB_1;
assign TGT_TRST_1 = !UJTAG_BYPASS_TRSTB_1;
assign UJTAG_BYPASS_TDO_1 = TGT_TDO_1;
assign TGT_TCK_2 = UJTAG_BYPASS_TCK_2;
assign TGT_TMS_2 = UJTAG_BYPASS_TMS_2;
assign TGT_TDI_2 = UJTAG_BYPASS_TDI_2;
assign TGT_TRSTN_2 = UJTAG_BYPASS_TRSTB_2;
assign TGT_TRST_2 = !UJTAG_BYPASS_TRSTB_2;
assign UJTAG_BYPASS_TDO_2 = TGT_TDO_2;
assign TGT_TCK_3 = UJTAG_BYPASS_TCK_3;
assign TGT_TMS_3 = UJTAG_BYPASS_TMS_3;
assign TGT_TDI_3 = UJTAG_BYPASS_TDI_3;
assign TGT_TRSTN_3 = UJTAG_BYPASS_TRSTB_3;
assign TGT_TRST_3 = !UJTAG_BYPASS_TRSTB_3;
assign UJTAG_BYPASS_TDO_3 = TGT_TDO_3;
end
end
endgenerate
endmodule // COREJTAGDEBUG

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// ****************************************************************************/
// ****************************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2019 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description:
//
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ****************************************************************************/
module corejtagdebug_bufd( A, Y);
parameter DELAY_NUM = 0;
input A;
output Y;
wire [DELAY_NUM:0] delay_sel;
genvar idx;
// Assign
assign delay_sel[0] = A;
assign Y = delay_sel[DELAY_NUM];
for (idx = 0; idx < DELAY_NUM; idx = idx + 1)
begin : bufd_gen
BUFD BUFD_BLK (.A(delay_sel[ idx]), .Y(delay_sel[ idx+1]));
end
endmodule

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//----------------------------------------------------------------------------
//
// Copyright (C) 1999-2005 First Silicon Solutions, Inc. All rights reserved.
//
// This source file is unpublished, proprietary information of First Silicon
// Solutions, Inc.
//
// It may be used per limitations as defined under applicable non-dislosure
// agreements and provided that this copyright statement is not removed
// from the file. The code contained herein is not to be distributed,
// in whole or in part, without prior written permission from First Silicon
// Solutions, Inc. First Silicon Solutions distributes this source file
// "as is" and does not guarantee applicability to any given application.
// Please send all questions and comments (including any and all discovered
// errors) on this source file to support@fs2.com.
//
// Module:
// uj_jtag: Conversion from UJTAG to JTAG within Actel APA / PA3 devices.
//
// $Log: uj_jtag.v,v $
// Revision 1.2 2005/12/21 22:19:01 ernie
// - Added gpin and gpout general-purpose I/O. These are addressable through
// UJTAG to control on-chip resources such as reset or test modes.
// - Adjustments to support going into pause states in the middle of shifts.
//
// Revision 1.1 2005/08/31 16:33:32 ernie
// Initial revision
//
// $Id: uj_jtag.v 1 2007-09-24 16:19:02Z ciaran.murphy $
//
//----------------------------------------------------------------------------
//-------------------//
// //
// INLCUDE FILES //
// //
//-------------------//
//-------------------//
// //
// MODULE DEFINITION //
// //
//-------------------//
`timescale 1ns/10ps
module COREJTAGDEBUG_UJ_JTAG (
// UJTAG port (to I/O)
UIREG,
URSTB,
UDRUPD,
UDRCK,
UDRCAP,
UDRSH,
UTDI,
UTDO,
UTDODRV,
// JTAG port (to DUT)
DUT_TCK,
DUT_TMS,
DUT_TDI,
DUT_TDO
);
parameter FAMILY = 26;
parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0;
parameter DELAY_NUM = 12;
parameter [7:0] IR_CODE_TGT = 8'h55;
localparam [7:0] NUM_LEAD_PAD_BITS = 8'b0;
localparam [7:0] NUM_TRAIL_PAD_BITS = 8'b0;
input [7:0] UIREG; // Current contents of chip's IR register
input URSTB; // JTAG reset (active low)
input UDRUPD; // JTAG TAP is in Update-DR state
input UDRCK; // shift clock
input UDRCAP; // JTAG TAP is in Capture-DR state
input UDRSH; // JTAG TAP is in Shift-DR state
input UTDI; // serial data from host
output UTDO; // serial data to host
output UTDODRV; // enable for tdo (asserted when this module is addressed)
output DUT_TCK; // JTAG clock
output DUT_TMS; // JTAG mode select
output DUT_TDI; // JTAG serial data to DUT
input DUT_TDO; // General-purpose addressable static inputs
//-------------------//
// //
//THEORY OF OPERATION//
// //
//-------------------//
//
// UJTAG is the fabric side of the chip's built-in hard-logic JTAG TAP. A
// range of IR codes are reserved for user logic. The IR code of this module
// should be different from other modules that might be attached to UJTAG.
// When this module is addressed by loading its IR code, then this module
// will assert its UTDODRV signal. In a multi-core system, UTDODRV and UTDO
// from each module are combined such that the addressed module drives UTDO
// into the actual UJTAG block. Example three-core system:
//
// assign UTDO = (UTDODRV0 & UTDO0) | (UTDODRV1 & UTDO1) | (UTDODRV2 & UTDO2);
//
// A typical JTAG instrument has both an IR and DR, yet UTAG only gives access
// to a DR scan. A prefix added to the beginning of each DR scan provides TAP
// state traversal information which is driven onto TMS prior to the shift.
// A UJTAG DR scan consists of 3 to 6 phases:
//
// 1. 3-bit length field
// 2. tms traversal of 0 to 6 clocks. Typically ends in Shift.
// 3. 6-bit length field
// 4. tdi shift of 0 to 63 clocks, ending in the Exit1 state.
// 5. 3-bit length field
// 6. tms traversal of 0 to 7 clocks. Typically ends in Idle.
//
// The prefix serves to traverse the TAP state machine to the Shift-IR or
// Shift-DR state prior to the shift. Following the shift, the suffix
// traversal can be used to move the TAP from Exit1 to Pause, Idle, Update,
// or any other state.
//
// Example: Starting in Idle, traverse to Shift-IR, scan 8 bits, then to Idle.
// IR <- IR_CODE_TGT to address this module
// DR <- {2'b01, The exit sequence (1, 0) Exit1-IR -> Update-IR -> Idle
// 3'd2, indicate 2 bits of exit sequence
// 8'b55, The value you want to scan into IR
// 6'd8, indicate 8 bits of shift
// 4'b0011, The enter sequence (1, 1, 0, 0) Idle->Shift-IR
// 3'd4} (first) indicate 4 bits of enter sequence
//
// DUT_TCK is a gated version of UDRCK and must be routed using low-skew resources.
// UDRCK is used in this module only but skew must still be addressed.
//
//-------------------//
// //
// LOCAL VARIABLES //
// //
//-------------------//
reg [4:0] state; // track progress through DR scan phases
reg [5:0] count; // bit counter for enter, shift, and exit
wire [5:0] countnext; // combinational computation of next count state
wire countnextzero; // combinational computation of next count state
reg tckgo; // TCK gating signal
wire DUT_TDI; // TDI output to DUT
wire DUT_TMS; // TMS output to DUT
reg UTDO; // Registered output to send to UJTAG
reg UTDODRV; // Registered decoder output for UTDO
reg endofshift; // Internal detection of end of shift, latched on falling edge
reg pauselow; // Gate to force DUT_TCK low when exiting shift to pause
reg tmsenb; // Synchronize on input
wire areset;
wire sreset;
wire dut_tms_int;
wire dut_tdi_int;
wire dut_tms_delay;
wire dut_tdi_delay;
`define STATE_WAITING 5'b00000
`define STATE_ENTERC0 5'b00100
`define STATE_ENTERC1 5'b00101
`define STATE_ENTERC2 5'b00110
`define STATE_ENTER 5'b00111
`define STATE_SHIFTC0 5'b01001
`define STATE_SHIFTC1 5'b01010
`define STATE_SHIFTC2 5'b01011
`define STATE_SHIFTC3 5'b01100
`define STATE_SHIFTC4 5'b01101
`define STATE_SHIFTC5 5'b01110
`define STATE_SHIFT 5'b01111
`define STATE_EXITC0 5'b10100
`define STATE_EXITC1 5'b10101
`define STATE_EXITC2 5'b10110
`define STATE_EXIT 5'b10111
`define STATE_GPIO0 5'b10000
`define STATE_GPIO1 5'b10001
`define STATE_GPIO2 5'b10010
`define STATE_GPIO3 5'b10011
`define STATE_ENTRY_PAD 5'b11000
`define STATE_EXIT_PAD 5'b11001
//-------------------//
// //
// EXECUTABLE CODE //
// //
//-------------------//
assign areset = (SYNC_RESET==1) ? 1'b1 : URSTB;
assign sreset = (SYNC_RESET==1) ? URSTB : 1'b1;
assign countnext =
(&state[2:0]) ? (count - 6'b000001) // run mode (state == xx111)
: (state[4:3] == 2'b01) ? {UTDI, count[5:1]} // shift load mode
: {3'b000, UTDI, count[2:1]}; // enter/exit load mode
assign countnextzero = (countnext == 6'b000000);
assign dut_tms_int = (tmsenb & UTDI) // enter/exit
| (endofshift); // shift -> exit1
assign dut_tdi_int = UTDI;
assign DUT_TMS = (FAMILY == 26) ? dut_tms_delay : dut_tms_int;
assign DUT_TDI = (FAMILY == 26) ? dut_tdi_delay : dut_tdi_int;
// Delay Buffers added for Polarfire to resolve minimum timing violations
corejtagdebug_bufd #(.DELAY_NUM(DELAY_NUM)) BUFD_TMS (.A(dut_tms_int), .Y(dut_tms_delay));
corejtagdebug_bufd #(.DELAY_NUM(DELAY_NUM)) BUFD_TDI (.A(dut_tdi_int), .Y(dut_tdi_delay));
always @(posedge UDRCK or negedge areset) begin
if (!areset || !sreset) begin
tckgo <= 1'b0;
state <= `STATE_WAITING;
count <= 6'b000000;
end else begin
case (state)
`STATE_WAITING:
begin
tckgo <= 1'b0;
count <= 6'b000000;
if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
if (NUM_LEAD_PAD_BITS == 0) state <= `STATE_ENTERC0;
else begin
count <= NUM_LEAD_PAD_BITS;
state <= `STATE_ENTRY_PAD;
end
end else state <= `STATE_WAITING;
end
`STATE_ENTERC0,
`STATE_ENTERC1,
`STATE_SHIFTC0,
`STATE_SHIFTC1,
`STATE_SHIFTC2,
`STATE_SHIFTC3,
`STATE_SHIFTC4,
`STATE_EXITC0,
`STATE_EXITC1:
begin
tckgo <= 1'b0;
if (UDRSH) begin
count <= countnext;
state <= state + 5'b00001;
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
state <= `STATE_WAITING; // premature exit
end
end
`STATE_ENTERC2:
begin
if (UDRSH) begin
if (countnextzero) begin
tckgo <= 1'b0;
count <= countnext;
state <= `STATE_SHIFTC0; // enter count is zero
end else if (countnext[2:0] == 3'b111) begin // GPIO exchange
tckgo <= 1'b0;
count <= 6'b0;
state <= `STATE_GPIO0;
end else begin
tckgo <= 1'b1;
count <= countnext;
state <= state + 5'b00001; // do the enter sequence
end
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
state <= `STATE_WAITING; // premature exit
end
end
`STATE_SHIFTC5:
begin
if (UDRSH) begin
tckgo <= &state[2:1] & ~countnextzero;
count <= countnext;
if (countnextzero) state <= `STATE_EXITC0; // shift count is zero
else state <= state + 5'b00001; // do the shift sequence
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
tckgo <= 1'b0;
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
tckgo <= 1'b0;
state <= `STATE_WAITING; // premature exit
end
end
`STATE_EXITC2:
begin
if (UDRSH) begin
tckgo <= &state[2:1] & ~countnextzero;
count <= countnext;
if (countnextzero) state <= `STATE_WAITING; // exit count is zero
else state <= state + 5'b00001;
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
tckgo <= 1'b0;
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
tckgo <= 1'b0;
state <= `STATE_WAITING; // premature exit
end
end
`STATE_ENTER:
begin
if (UDRSH) begin
tckgo <= ~countnextzero;
count <= countnext;
if (countnextzero) state <= `STATE_SHIFTC0; // done with traversal
else state <= `STATE_ENTER; // still traversing
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
tckgo <= 1'b0;
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
tckgo <= 1'b0;
state <= `STATE_WAITING; // premature exit
end
end
`STATE_SHIFT:
begin
if (UDRSH) begin
tckgo <= ~countnextzero;
count <= countnext;
if (countnextzero) state <= `STATE_EXITC0; // done with shift
else state <= `STATE_SHIFT; // still shifting
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
tckgo <= 1'b0;
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
tckgo <= 1'b0;
state <= `STATE_WAITING; // premature exit
end
end
`STATE_EXIT:
begin
if (UDRSH) begin
tckgo <= ~countnextzero;
count <= countnext;
if (countnextzero) begin
if (NUM_TRAIL_PAD_BITS == 0) state <= `STATE_WAITING; // done with shift
else state <= `STATE_EXIT_PAD;
end else state <= `STATE_EXIT; // still shifting
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
tckgo <= 1'b0;
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
tckgo <= 1'b0;
state <= `STATE_WAITING; // premature exit
end
end
`STATE_ENTRY_PAD:
begin
tckgo <= 1'b0;
if (UDRSH) begin
count <= count - 1'b1;
if (count - 1'b1 == 6'b000000) state <= `STATE_ENTERC0;
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
state <= `STATE_WAITING; // done
end
end
`STATE_EXIT_PAD:
begin
tckgo <= 1'b0;
if (UDRSH) begin
count <= count - 1'b1;
if (count - 1'b1 == 6'b000000) state <= `STATE_WAITING;
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
state <= `STATE_WAITING; // done
end
end
`STATE_GPIO0, `STATE_GPIO1, `STATE_GPIO2, `STATE_GPIO3:
begin
tckgo <= 1'b0;
if (UDRSH) begin
count[5:0] <= {2'b00, UTDI, count[3:1]};
if (~&state[1:0]) state <= state + 5'b00001; // hold in GPIO3
end else if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else if (UDRUPD) begin
state <= `STATE_WAITING; // done
end
end
default:
begin
tckgo <= 1'b0;
count <= 6'b000000;
if ((UIREG == IR_CODE_TGT) && UDRCAP) begin
state <= `STATE_ENTERC0; // new scan began somehow
end else begin
state <= `STATE_WAITING;
end
end
endcase
end
end
//
// Falling edge needed to drive TMS to DUT correctly
//
always @(negedge UDRCK or negedge areset) begin
if (!areset || !sreset) begin
endofshift <= 1'b0;
tmsenb <= 1'b0;
end else begin
tmsenb <= ~(state[4:3] == 2'b01);
endofshift <= (state == `STATE_SHIFT) && countnextzero;
end
end
//
// Tck gating logic
//
// Allow tck to go low with UDRCK when tckgo.
// Negative logic here avoids glitches on rising edges of UDRCK as tckgo changes.
//
always @(posedge UDRCK or negedge areset) begin
if (!areset || !sreset) begin
pauselow <= 1'b0;
end else begin
if (~UDRSH) pauselow <= 1'b1;
else if (tckgo) pauselow <= 1'b0;
end
end
assign DUT_TCK = ~(pauselow | ~UDRSH | (tckgo & ~UDRCK));
//
// TDO logic
//
// TDO comes from DUT on falling edge. Latch here on rising edge and
// supply to UJTAG. UJTAG then delays until the next falling edge.
// Host app must take this one-clock delay into account and supply
// at least one exit clock after the shift in order to finish the scan.
//
always @(posedge UDRCK or negedge areset) begin
if (!areset || !sreset) begin
UTDO <= 1'b0;
UTDODRV <= 1'b0;
end else begin
if (UDRSH)
UTDO <= (state[4:2] == 3'b100) ? count[0] // Read of gpin
: DUT_TDO; // DUT JTAG exchange
UTDODRV <= (UIREG == IR_CODE_TGT) ? 1'b1 : 1'b0;
end
end
endmodule

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/******************************************************************************
Copyright (c) 2015-2017, 2019 Synopsys, Inc.
This model and the associated documentation are proprietary to Synopsys, Inc.
This model may only be used in accordance with the terms and conditions of a
written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this model is strictly prohibited.
*******************************************************************************
Title : Wrapper for the UJTAG module in Microsemi FPGA devices
Project : Identify
*******************************************************************************
Description: Drop-in replacement for Microsemi's UJTAG module, to provide
UJTAG access to the user's design even if it is instrumented
using Identify.
*******************************************************************************
Usage: - Instantiate UJTAG_WRAPPER instead of UJTAG in your user design
(irrespective of whether you are going to instrument the
design or not).
NOTES: - Two UJTAG OPCODEs are reserved for usage by Identify:
UIREG[5:1] = 5'b00001 and
UIREG[5:1] = 5'b00010.
- Furthermore, UIREG[6] is used by Identify as 'enable'
signal.
- Add this ujtag_wrapper.v file to the list of HDL source files
in your Synplify Pro project.
- If you do want to debug the design using Identify, then
you have to `define IDENTIFY_DEBUG_IMPL.
You can also do this directly in Synplify Pro:
set_option -hdl_define -set IDENTIFY_DEBUG_IMPL
*******************************************************************************
File : ujtag_wrapper.v
Author : jalb
Created : 2015/03/13
Last update: 2019/02/20
*******************************************************************************
$Id: ujtag_wrapper.v,v 1.1 2017/09/20 07:38:42 jalb Exp jalb $
******************************************************************************/
module UJTAG_WRAPPER (
// Inputs
UTDO,
TDI,
TMS,
TCK,
TRSTB,
// Outputs
UDRCAP,
UDRSH,
UDRUPD,
UIREG,
URSTB,
UDRCK,
UTDI,
TDO
);
input UTDO;
input TDI;
input TMS;
input TCK;
input TRSTB;
output UDRCAP;
output UDRSH;
output UDRUPD;
output [7:0] UIREG;
output URSTB;
output UDRCK;
output UTDI;
output TDO;
`ifndef IDENTIFY_DEBUG_IMPL
//------ The original UJTAG module
UJTAG UJTAG_inst(
// Inputs
.UTDO ( UTDO ),
.TDI ( TDI ),
.TMS ( TMS ),
.TCK ( TCK ),
.TRSTB ( TRSTB ),
// Outputs
.UDRCAP ( UDRCAP ),
.UDRSH ( UDRSH ),
.UDRUPD ( UDRUPD ),
.UIREG ( UIREG ),
.URSTB ( URSTB ),
.UDRCK ( UDRCK ),
.UTDI ( UTDI ),
.TDO ( TDO )
);
`else
wire utdo_wire /* synthesis syn_keep=1 */ ;
wire tdi_wire /* synthesis syn_keep=1 */ ;
wire tms_wire /* synthesis syn_keep=1 */ ;
wire tck_wire /* synthesis syn_keep=1 */ ;
wire trstb_wire /* synthesis syn_keep=1 */ ;
assign utdo_wire = UTDO ;
assign tdi_wire = TDI;
assign tms_wire = TMS;
assign tck_wire = TCK;
assign trstb_wire = TRSTB;
// Hyper-connects to connect to the hyper-sources in the JTAG interface of the Identify IP core
syn_hyper_connect_internal hyperc_ujtag_wrapper_uireg(UIREG) /* synthesis tag="ujtag_wrapper_uireg" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_uireg.w = 8;
syn_hyper_connect_internal hyperc_ujtag_wrapper_urstb(URSTB) /* synthesis tag="ujtag_wrapper_urstb" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_urstb.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_udrupd(UDRUPD) /* synthesis tag="ujtag_wrapper_udrupd" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_udrupd.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_udrck(UDRCK) /* synthesis tag="ujtag_wrapper_udrck" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_udrck.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_udrcap(UDRCAP) /* synthesis tag="ujtag_wrapper_udrcap" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_udrcap.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_udrsh(UDRSH) /* synthesis tag="ujtag_wrapper_udrsh" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_udrsh.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_utdi(UTDI) /* synthesis tag="ujtag_wrapper_utdi" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_utdi.w = 1;
syn_hyper_source_internal hypers_ujtag_wrapper_utdo(utdo_wire) /* synthesis tag="ujtag_wrapper_utdo" .hyper_delete_level=100 */;
defparam hypers_ujtag_wrapper_utdo.w = 1;
// ... and ditto for the FPGA-level JTAG ports:
syn_hyper_source_internal hypers_ujtag_wrapper_tdi(tdi_wire) /* synthesis tag="ujtag_wrapper_tdi" .hyper_delete_level=100 */;
defparam hypers_ujtag_wrapper_tdi.w = 1;
syn_hyper_source_internal hypers_ujtag_wrapper_tms(tms_wire) /* synthesis tag="ujtag_wrapper_tms" .hyper_delete_level=100 */;
defparam hypers_ujtag_wrapper_tms.w = 1;
syn_hyper_source_internal hypers_ujtag_wrapper_tck(tck_wire) /* synthesis tag="ujtag_wrapper_tck" .hyper_delete_level=100 */;
defparam hypers_ujtag_wrapper_tck.w = 1;
syn_hyper_source_internal hypers_ujtag_wrapper_trstb(trstb_wire) /* synthesis tag="ujtag_wrapper_trstb" .hyper_delete_level=100 */;
defparam hypers_ujtag_wrapper_trstb.w = 1;
syn_hyper_connect_internal hyperc_ujtag_wrapper_tdo(TDO) /* synthesis tag="ujtag_wrapper_tdo" .hyper_connect_after_level=60 */;
defparam hyperc_ujtag_wrapper_tdo.w = 1;
`endif
endmodule // UJTAG_WRAPPER

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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:01 2026
// Parameters for COREJTAGDEBUG
//--------------------------------------------------------------------
parameter FAMILY = 26;
parameter IR_CODE_TGT_0 = 'h55;
parameter IR_CODE_TGT_1 = 'h56;
parameter IR_CODE_TGT_2 = 'h57;
parameter IR_CODE_TGT_3 = 'h58;
parameter IR_CODE_TGT_4 = 'h59;
parameter IR_CODE_TGT_5 = 'h5a;
parameter IR_CODE_TGT_6 = 'h5b;
parameter IR_CODE_TGT_7 = 'h5c;
parameter IR_CODE_TGT_8 = 'h5d;
parameter IR_CODE_TGT_9 = 'h5e;
parameter IR_CODE_TGT_10 = 'h5f;
parameter IR_CODE_TGT_11 = 'h60;
parameter IR_CODE_TGT_12 = 'h61;
parameter IR_CODE_TGT_13 = 'h62;
parameter IR_CODE_TGT_14 = 'h63;
parameter IR_CODE_TGT_15 = 'h64;
parameter NUM_DEBUG_TGTS = 1;
parameter Testbench = "User";
parameter TGT_ACTIVE_HIGH_RESET_0 = 0;
parameter TGT_ACTIVE_HIGH_RESET_1 = 0;
parameter TGT_ACTIVE_HIGH_RESET_2 = 0;
parameter TGT_ACTIVE_HIGH_RESET_3 = 0;
parameter TGT_ACTIVE_HIGH_RESET_4 = 0;
parameter TGT_ACTIVE_HIGH_RESET_5 = 0;
parameter TGT_ACTIVE_HIGH_RESET_6 = 0;
parameter TGT_ACTIVE_HIGH_RESET_7 = 0;
parameter TGT_ACTIVE_HIGH_RESET_8 = 0;
parameter TGT_ACTIVE_HIGH_RESET_9 = 0;
parameter TGT_ACTIVE_HIGH_RESET_10 = 0;
parameter TGT_ACTIVE_HIGH_RESET_11 = 0;
parameter TGT_ACTIVE_HIGH_RESET_12 = 0;
parameter TGT_ACTIVE_HIGH_RESET_13 = 0;
parameter TGT_ACTIVE_HIGH_RESET_14 = 0;
parameter TGT_ACTIVE_HIGH_RESET_15 = 0;
parameter UJTAG_BYPASS = 0;
parameter UJTAG_SEC_EN = 0;

40
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/mti/corejtagdebug_wave.do Normal file
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## ****************************************************************************#
## Microsemi Corporation Proprietary and Confidential
## Copyright 2017 Microsemi Corporation. All rights reserved.
##
## ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
## ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
## IN ADVANCE IN WRITING.
##
## Description:
##
## SVN Revision Information:
## SVN $Revision: 37550 $
## SVN $Date: 2021-01-27 16:55:15 +0000 (Wed, 27 Jan 2021) $
##
## Resolved SARs
## SAR Date Who Description
##
## Notes:
##
## ****************************************************************************#
add wave -divider CoreJTAGDebug_TAP_I/F
add wave -radix hexadecimal -label TRSTB COREJTAGDEBUG_TESTBENCH/UUT/TRSTB
add wave -radix hexadecimal -label TCK COREJTAGDEBUG_TESTBENCH/UUT//TCK
add wave -radix hexadecimal -label TMS COREJTAGDEBUG_TESTBENCH/UUT/TMS
add wave -radix hexadecimal -label TDI COREJTAGDEBUG_TESTBENCH/UUT/TDI
add wave -radix hexadecimal -label TDO COREJTAGDEBUG_TESTBENCH/UUT/TDO
for {set idx 0} {$idx < 16} {incr idx} {
add wave -divider [subst CoreJTAGDebug_Target_${idx}_I/F]
add wave -radix hexadecimal -label [subst TGT_TRSTN_${idx}] COREJTAGDEBUG_TESTBENCH/UUT/[subst TGT_TRSTN_${idx}]
add wave -radix hexadecimal -label [subst TGT_TCK_${idx}] COREJTAGDEBUG_TESTBENCH/UUT/[subst TGT_TCK_${idx}]
add wave -radix hexadecimal -label [subst TGT_TMS_${idx}] COREJTAGDEBUG_TESTBENCH/UUT/[subst TGT_TMS_${idx}]
add wave -radix hexadecimal -label [subst TGT_TDI_${idx}] COREJTAGDEBUG_TESTBENCH/UUT/[subst TGT_TDI_${idx}]
add wave -radix hexadecimal -label [subst TGT_TDO_${idx}] COREJTAGDEBUG_TESTBENCH/UUT/[subst TGT_TDO_${idx}]
}
configure wave -namecolwidth 160
configure wave -valuecolwidth 40
WaveRestoreZoom {0 ns} {7000 ns}

283
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_host_emulator.v Normal file
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// ****************************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2017 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description:
//
// SVN Revision Information:
// SVN $Revision: 29839 $
// SVN $Date: 2017-05-16 16:23:16 +0100 (Tue, 16 May 2017) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ****************************************************************************/
`timescale 1ns/1ps
module COREJTAGDEBUG_HOST_EMULATOR (
// Inputs
TCK,
TRSTB,
TDI,
// Outputs
TMS,
TDO
);
////////////////////////////////////////////////////////////////////////////////
// Parameters
////////////////////////////////////////////////////////////////////////////////
parameter IR_CODE_TGT = 8'h55;
parameter IR_SCAN_LEN = 5;
parameter DR_SCAN_LEN = 32;
////////////////////////////////////////////////////////////////////////////////
// Port directions
////////////////////////////////////////////////////////////////////////////////
// Inputs
input TCK;
input TRSTB;
input TDI;
// Outputs
output reg TMS = 1'b1;
output reg TDO = 1'b0;
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task exit_tst_logic_reset;
begin
@(negedge TCK);
TMS <= 1'b0; // Goto "run test idle"
@(negedge TCK);
end
endtask
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task ir_capture;
begin
@(negedge TCK);
TMS <= 1'b1; // Goto "Select DR scan"
@(negedge TCK);
TMS <= 1'b1; // Goto "Select IR scan"
@(negedge TCK);
TMS <= 1'b0; // Goto "Capture IR"
@(negedge TCK);
TMS <= 1'b1; // Goto "exit 1 IR"
@(negedge TCK);
TMS <= 1'b1; // Goto "update IR"
@(negedge TCK);
TMS <= 1'b0; // Goto "run test idle"
end
endtask
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task ir_shift;
input [31:0] num_of_bits;
input [31:0] data;
integer bitCnt;
begin
@(negedge TCK);
TMS <= 1'b1; // Goto "Select DR scan"
@(negedge TCK);
TMS <= 1'b1; // Goto "Select IR scan"
@(negedge TCK);
TMS <= 1'b0; // Goto "Capture IR"
@(negedge TCK);
TMS <= 1'b0; // Goto "Shift IR"
@(negedge TCK);
for (bitCnt = 0; bitCnt < num_of_bits; bitCnt = bitCnt + 1)
begin
if (bitCnt == num_of_bits-1)
begin
TMS <= 1'b1; // Goto "exit 1 IR"
end
else
begin
TMS <= 1'b0; // Goto "Shift IR"
end
TDO <= data[bitCnt];
@(negedge TCK);
end
TMS <= 1'b1; // Goto "update IR"
@(negedge TCK);
TMS <= 1'b0; // Goto "run test idle"
@(negedge TCK);
end
endtask
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task dr_capture;
begin
@(negedge TCK);
TMS <= 1'b1; // Goto "Select DR scan"
@(negedge TCK);
TMS <= 1'b0; // Goto "Capture DR"
@(negedge TCK);
TMS <= 1'b1; // Goto "exit 1 DR"
@(negedge TCK);
TMS <= 1'b1; // Goto "update DR"
@(negedge TCK);
TMS <= 1'b0; // Goto "run test idle"
end
endtask
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task dr_shift;
input [31:0] num_of_bits;
input [88:0] data;
integer bitCnt;
begin
@(negedge TCK);
TMS <= 1'b1; // Goto "Select DR scan"
@(negedge TCK);
TMS <= 1'b0; // Goto "Capture DR"
@(negedge TCK);
TMS <= 1'b0; // Goto "Shift DR"
@(negedge TCK);
for (bitCnt = 0; bitCnt < num_of_bits; bitCnt = bitCnt + 1)
begin
if (bitCnt == num_of_bits-1)
begin
TMS <= 1'b1; // Goto "exit 1 DR"
end
else
begin
TMS <= 1'b0; // Goto "Shift DR"
end
TDO <= data[bitCnt];
@(negedge TCK);
end
TMS <= 1'b1; // Goto "update DR"
@(negedge TCK);
TMS <= 1'b0; // Goto "run test idle"
@(negedge TCK);
end
endtask
////////////////////////////////////////////////////////////////////////////////
//
////////////////////////////////////////////////////////////////////////////////
task tunnelled_ir_scan;
input [IR_SCAN_LEN-1:0] data;
reg [2:0] in_trav_len;
reg [6:0] in_trav_data;
reg [2:0] out_trav_len;
reg [6:0] out_trav_data;
reg [5:0] payload_data_len;
begin
in_trav_len = 3'b100;
in_trav_data = 4'b0011; // Brings us from "run_test_idle" to "shift IR"
out_trav_len = 3'b010;
out_trav_data = 2'b01; // Brings us from "exit 1 IR" to "run_test_idle"
payload_data_len = IR_SCAN_LEN;
dr_shift
( (12+(in_trav_len+payload_data_len+out_trav_len)),
{
out_trav_data[1:0],
out_trav_len[2:0],
data[IR_SCAN_LEN-1:0],
payload_data_len[5:0],
in_trav_data[3:0],
in_trav_len[2:0]
}
);
end
endtask
////////////////////////////////////////////////////////////////////////////////
// Performs a tunnelled DR scan with 32-bits of payload data
////////////////////////////////////////////////////////////////////////////////
task tunnelled_dr_scan;
input [DR_SCAN_LEN-1:0] data;
reg [2:0] in_trav_len;
reg [6:0] in_trav_data;
reg [2:0] out_trav_len;
reg [6:0] out_trav_data;
reg [5:0] payload_data_len;
begin
in_trav_len = 3'b011;
in_trav_data = 3'b001; // Brings us from "run_test_idle" to "shift DR"
out_trav_len = 3'b010;
out_trav_data = 2'b01; // Brings us from "exit 1 DR" to "run_test_idle"
payload_data_len = DR_SCAN_LEN;
dr_shift
( (12+(in_trav_len+payload_data_len+out_trav_len)),
{
out_trav_data[1:0],
out_trav_len[2:0],
data[DR_SCAN_LEN-1:0],
payload_data_len[5:0],
in_trav_data[2:0],
in_trav_len[2:0]
}
);
end
endtask
////////////////////////////////////////////////////////////////////////////////
// Tunnelled exit from "test_logic_reset" to "run_test_idle"
////////////////////////////////////////////////////////////////////////////////
task tunnelled_exit_tst_logic_reset;
reg [2:0] in_trav_length;
reg [2:0] in_tms_trav;
reg [2:0] out_trav_length;
begin
in_trav_length = 3'b001;
in_tms_trav = 1'b0; // Brings us from "test_logic_reset" to "run_test_idle"
out_trav_length = 3'b000;
dr_shift(13, {out_trav_length, 6'd0, in_tms_trav, in_trav_length});
end
endtask
////////////////////////////////////////////////////////////////////////////////
// CoreJTAGDebug User Testbench
////////////////////////////////////////////////////////////////////////////////
always
begin
$display ("##########################################################");
$display ("## CoreJTAGDebug User Testbench");
$display ("##########################################################");
// Wait for the reset de-assertion
@(posedge TRSTB);
// Wait for the reset to propogate through
@(negedge TCK);
@(negedge TCK);
// Bring JTAG TAP FSM to "run test idle" state
exit_tst_logic_reset;
#300;
// IR Scan to UJTAG so that uireg[7:0] has the IR_CODE to match the
// IR_CODE of the uj_jtag tunnel controller inside CoreJTAGDebug
ir_shift('d8, IR_CODE_TGT[7:0]);
$display ($time, "IR Shift complete to address the uj_ujtag tunnel controller");
#300;
tunnelled_exit_tst_logic_reset;
$display ($time, "Tunnelled reset complete");
#300;
tunnelled_ir_scan(5'b00001);
$display ($time, "Tunnelled IR scan to get the ID code from the target TAP");
#300;
$display ($time, "Push through zeros in the tunnelled DR scan to read the ID code of the target TAP");
tunnelled_dr_scan(32'b0);
#500;
$stop;
end
endmodule // COREJTAGDEBUG_HOST_EMULATOR

285
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_jtag_tap.v Normal file
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// ****************************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2017 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description:
//
// SVN Revision Information:
// SVN $Revision: 29839 $
// SVN $Date: 2017-05-16 16:23:16 +0100 (Tue, 16 May 2017) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ****************************************************************************/
module COREJTAGDEBUG_JTAG_TAP (
// Inputs
TCK,
TRSTB,
TMS,
TDI,
// Outputs
TDO
);
////////////////////////////////////////////////////////////////////////////////
// Parameters
////////////////////////////////////////////////////////////////////////////////
parameter DR_REG_WIDTH = 5;
parameter IR_REG_WIDTH = 5;
parameter ACTIVE_HIGH_RESET = 0;
////////////////////////////////////////////////////////////////////////////////
// Port directions
////////////////////////////////////////////////////////////////////////////////
input TCK;
input TRSTB;
input TMS;
input TDI;
output TDO;
////////////////////////////////////////////////////////////////////////////////
// Constants
////////////////////////////////////////////////////////////////////////////////
// State Machine encoding
localparam TEST_LOGIC_RESET = 4'h0;
localparam RUN_TEST_IDLE = 4'h1;
localparam SELECT_DR = 4'h2;
localparam CAPTURE_DR = 4'h3;
localparam SHIFT_DR = 4'h4;
localparam EXIT1_DR = 4'h5;
localparam PAUSE_DR = 4'h6;
localparam EXIT2_DR = 4'h7;
localparam UPDATE_DR = 4'h8;
localparam SELECT_IR = 4'h9;
localparam CAPTURE_IR = 4'hA;
localparam SHIFT_IR = 4'hB;
localparam EXIT1_IR = 4'hC;
localparam PAUSE_IR = 4'hD;
localparam EXIT2_IR = 4'hE;
localparam UPDATE_IR = 4'hF;
// Supported instructions
localparam [IR_REG_WIDTH-1:0] BYPASS_INSTR = {(IR_REG_WIDTH){1'b1}};
localparam [IR_REG_WIDTH-1:0] ID_CODE_INSTR = {{(IR_REG_WIDTH-1){1'b0}}, 1'b1};
// TAP ID code
localparam [DR_REG_WIDTH-1:0] ID_CODE = 'hDEADC001;
////////////////////////////////////////////////////////////////////////////////
// Internal signal declarations
////////////////////////////////////////////////////////////////////////////////
reg [3:0] currTapState;
reg [3:0] nextTapState;
wire irShift;
wire drShift;
wire irCapture;
wire drCapture;
wire irUpdate;
wire drUpdate;
reg [DR_REG_WIDTH-1:0] shiftReg;
reg [IR_REG_WIDTH-1:0] irReg;
////////////////////////////////////////////////////////////////////////////////
// TAP Control FSM
////////////////////////////////////////////////////////////////////////////////
// Current state register
generate
if (ACTIVE_HIGH_RESET == 1)
begin
always @ (posedge TCK or posedge TRSTB)
begin
if (TRSTB)
begin
currTapState <= TEST_LOGIC_RESET;
end
else
begin
currTapState <= nextTapState;
end
end
end
else
begin
always @ (posedge TCK or negedge TRSTB)
begin
if (!TRSTB)
begin
currTapState <= TEST_LOGIC_RESET;
end
else
begin
currTapState <= nextTapState;
end
end
end
endgenerate
// Combinatorial outputs
assign drCapture = (currTapState == CAPTURE_DR) ? 1'b1 : 1'b0;
assign drShift = (currTapState == SHIFT_DR) ? 1'b1 : 1'b0;
assign drUpdate = (currTapState == UPDATE_DR) ? 1'b1 : 1'b0;
assign irCapture = (currTapState == CAPTURE_IR) ? 1'b1 : 1'b0;
assign irShift = (currTapState == SHIFT_IR) ? 1'b1 : 1'b0;
assign irUpdate = (currTapState == UPDATE_IR) ? 1'b1 : 1'b0;
// Next state combinatorial logic
always @ (*)
begin
case (currTapState)
TEST_LOGIC_RESET: nextTapState = (!TMS) ? RUN_TEST_IDLE : currTapState;
RUN_TEST_IDLE: nextTapState = (TMS) ? SELECT_DR : currTapState;
SELECT_DR: nextTapState = (!TMS) ? CAPTURE_DR : SELECT_IR;
CAPTURE_DR: nextTapState = (TMS) ? EXIT1_DR : SHIFT_DR;
SHIFT_DR: nextTapState = (TMS) ? EXIT1_DR : currTapState;
EXIT1_DR: nextTapState = (TMS) ? UPDATE_DR : PAUSE_DR;
PAUSE_DR: nextTapState = (TMS) ? EXIT2_DR : currTapState;
EXIT2_DR: nextTapState = (TMS) ? UPDATE_DR : SHIFT_DR;
UPDATE_DR: nextTapState = (TMS) ? SELECT_DR : RUN_TEST_IDLE;
SELECT_IR: nextTapState = (TMS) ? TEST_LOGIC_RESET : CAPTURE_IR;
CAPTURE_IR: nextTapState = (TMS) ? EXIT1_IR : SHIFT_IR;
SHIFT_IR: nextTapState = (TMS) ? EXIT1_IR : currTapState;
EXIT1_IR: nextTapState = (!TMS) ? PAUSE_IR : UPDATE_IR;
PAUSE_IR: nextTapState = (TMS) ? EXIT2_IR : currTapState;
EXIT2_IR: nextTapState = (TMS) ? UPDATE_IR : SHIFT_IR;
UPDATE_IR: nextTapState = (TMS) ? SELECT_DR : RUN_TEST_IDLE;
endcase
end
////////////////////////////////////////////////////////////////////////////////
// Shift register
////////////////////////////////////////////////////////////////////////////////
generate
if (ACTIVE_HIGH_RESET == 1)
begin
always @ (posedge TCK or posedge TRSTB)
begin
if (TRSTB)
begin
shiftReg <= {DR_REG_WIDTH{1'b0}};
end
else
begin
if (irCapture)
begin
shiftReg <= {{(DR_REG_WIDTH-1){1'b0}}, 1'b1};
end
else if (drCapture)
begin
if (irReg == ID_CODE_INSTR)
begin
shiftReg <= ID_CODE;
end
end
else if (irShift | drShift)
begin
shiftReg <= {TDI, shiftReg[(DR_REG_WIDTH-1):1]};
end
else
begin
shiftReg <= shiftReg;
end
end
end
end
else
begin
always @ (posedge TCK or negedge TRSTB)
begin
if (!TRSTB)
begin
shiftReg <= {DR_REG_WIDTH{1'b0}};
end
else
begin
if (irCapture)
begin
shiftReg <= {{(DR_REG_WIDTH-1){1'b0}}, 1'b1};
end
else if (drCapture)
begin
if (irReg == ID_CODE_INSTR)
begin
shiftReg <= ID_CODE;
end
end
else if (irShift | drShift)
begin
shiftReg <= {TDI, shiftReg[(DR_REG_WIDTH-1):1]};
end
else
begin
shiftReg <= shiftReg;
end
end
end
end
endgenerate
assign TDO = (irReg == BYPASS_INSTR) ? shiftReg[(DR_REG_WIDTH-1)] : shiftReg[0];
////////////////////////////////////////////////////////////////////////////////
// IR register
////////////////////////////////////////////////////////////////////////////////
generate
if (ACTIVE_HIGH_RESET == 1)
begin
always @ (posedge TCK or posedge TRSTB)
begin
if (TRSTB)
begin
irReg <= {IR_REG_WIDTH{1'b0}};
end
else
begin
if (irCapture)
begin
irReg <= {{(IR_REG_WIDTH-1){1'b0}}, 1'b1};
end
else if (irUpdate)
begin
irReg <= shiftReg[DR_REG_WIDTH-1:DR_REG_WIDTH-IR_REG_WIDTH];
end
else
begin
irReg <= irReg;
end
end
end
end
else
begin
always @ (posedge TCK or negedge TRSTB)
begin
if (!TRSTB)
begin
irReg <= {IR_REG_WIDTH{1'b0}};
end
else
begin
if (irCapture)
begin
irReg <= {{(IR_REG_WIDTH-1){1'b0}}, 1'b1};
end
else if (irUpdate)
begin
irReg <= shiftReg[DR_REG_WIDTH-1:DR_REG_WIDTH-IR_REG_WIDTH];
end
else
begin
irReg <= irReg;
end
end
end
end
endgenerate
endmodule // COREJTAGDEBUG_JTAG_TAP

315
component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_testbench.v Normal file
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// ****************************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2017 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description:
//
// SVN Revision Information:
// SVN $Revision: 37981 $
// SVN $Date: 2021-04-09 11:16:51 +0100 (Fri, 09 Apr 2021) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ****************************************************************************/
`timescale 1ns/1ps
module COREJTAGDEBUG_TESTBENCH ();
////////////////////////////////////////////////////////////////////////////////
// Parameters
////////////////////////////////////////////////////////////////////////////////
localparam CLK_HP = 20;
localparam IR_REG_WIDTH = 5;
localparam DR_REG_WIDTH = 32;
parameter UJTAG_SEC_EN = 0;
parameter FAMILY = 19;
parameter NUM_DEBUG_TGTS = 16;
parameter TGT_ACTIVE_HIGH_RESET_0 = 1'b0;
parameter [7:0] IR_CODE_TGT_0 = 8'h55;
parameter TGT_ACTIVE_HIGH_RESET_1 = 1'b0;
parameter [7:0] IR_CODE_TGT_1 = 8'h56;
parameter TGT_ACTIVE_HIGH_RESET_2 = 1'b0;
parameter [7:0] IR_CODE_TGT_2 = 8'h57;
parameter TGT_ACTIVE_HIGH_RESET_3 = 1'b0;
parameter [7:0] IR_CODE_TGT_3 = 8'h58;
parameter TGT_ACTIVE_HIGH_RESET_4 = 1'b0;
parameter [7:0] IR_CODE_TGT_4 = 8'h59;
parameter TGT_ACTIVE_HIGH_RESET_5 = 1'b0;
parameter [7:0] IR_CODE_TGT_5 = 8'h5A;
parameter TGT_ACTIVE_HIGH_RESET_6 = 1'b0;
parameter [7:0] IR_CODE_TGT_6 = 8'h5B;
parameter TGT_ACTIVE_HIGH_RESET_7 = 1'b0;
parameter [7:0] IR_CODE_TGT_7 = 8'h5C;
parameter TGT_ACTIVE_HIGH_RESET_8 = 1'b0;
parameter [7:0] IR_CODE_TGT_8 = 8'h5D;
parameter TGT_ACTIVE_HIGH_RESET_9 = 1'b0;
parameter [7:0] IR_CODE_TGT_9 = 8'h5E;
parameter TGT_ACTIVE_HIGH_RESET_10 = 1'b0;
parameter [7:0] IR_CODE_TGT_10 = 8'h5F;
parameter TGT_ACTIVE_HIGH_RESET_11 = 1'b0;
parameter [7:0] IR_CODE_TGT_11 = 8'h60;
parameter TGT_ACTIVE_HIGH_RESET_12 = 1'b0;
parameter [7:0] IR_CODE_TGT_12 = 8'h61;
parameter TGT_ACTIVE_HIGH_RESET_13 = 1'b0;
parameter [7:0] IR_CODE_TGT_13 = 8'h62;
parameter TGT_ACTIVE_HIGH_RESET_14 = 1'b0;
parameter [7:0] IR_CODE_TGT_14 = 8'h63;
parameter TGT_ACTIVE_HIGH_RESET_15 = 1'b0;
parameter [7:0] IR_CODE_TGT_15 = 8'h64;
////////////////////////////////////////////////////////////////////////////////
// Internal signals
////////////////////////////////////////////////////////////////////////////////
reg TCK = 1'b0;
reg TRSTB = 1'b0;
wire TMS;
wire TDO;
wire TDI;
wire [15:0] TGT_TCK;
wire [15:0] TGT_TMS;
wire [15:0] TGT_TDI;
wire [15:0] TGT_TRST_N;
wire [15:0] TGT_TDO;
genvar tgt_idx;
////////////////////////////////////////////////////////////////////////////////
// Constants
////////////////////////////////////////////////////////////////////////////////
localparam [15:0] TGT_ACTIVE_HIGH_RESET = {
TGT_ACTIVE_HIGH_RESET_15[0], TGT_ACTIVE_HIGH_RESET_14[0], TGT_ACTIVE_HIGH_RESET_13[0], TGT_ACTIVE_HIGH_RESET_12[0],
TGT_ACTIVE_HIGH_RESET_11[0], TGT_ACTIVE_HIGH_RESET_10[0], TGT_ACTIVE_HIGH_RESET_9[0], TGT_ACTIVE_HIGH_RESET_8[0],
TGT_ACTIVE_HIGH_RESET_7[0], TGT_ACTIVE_HIGH_RESET_6[0], TGT_ACTIVE_HIGH_RESET_5[0], TGT_ACTIVE_HIGH_RESET_4[0],
TGT_ACTIVE_HIGH_RESET_3[0], TGT_ACTIVE_HIGH_RESET_2[0], TGT_ACTIVE_HIGH_RESET_1[0], TGT_ACTIVE_HIGH_RESET_0[0]
};
////////////////////////////////////////////////////////////////////////////////
// Clock & reset generation
////////////////////////////////////////////////////////////////////////////////
always
begin
#CLK_HP TCK <= ~TCK;
end
initial
begin
@(posedge TCK);
@(posedge TCK);
TRSTB <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////
// Instantiate JTAG master
////////////////////////////////////////////////////////////////////////////////
COREJTAGDEBUG_HOST_EMULATOR #(
.IR_SCAN_LEN (IR_REG_WIDTH),
.DR_SCAN_LEN (DR_REG_WIDTH),
.IR_CODE_TGT (IR_CODE_TGT_0)
) JTAG_M (
// Inputs
.TCK (TCK),
.TRSTB (TRSTB),
.TDI (TDI),
// Outputs
.TMS (TMS),
.TDO (TDO)
);
////////////////////////////////////////////////////////////////////////////////
// Instantiate CoreJTAGDebug
////////////////////////////////////////////////////////////////////////////////
COREJTAGDEBUG #(
.UJTAG_SEC_EN (UJTAG_SEC_EN),
.FAMILY (FAMILY),
.NUM_DEBUG_TGTS (NUM_DEBUG_TGTS),
.TGT_ACTIVE_HIGH_RESET_0 (TGT_ACTIVE_HIGH_RESET_0),
.IR_CODE_TGT_0 (IR_CODE_TGT_0),
.TGT_ACTIVE_HIGH_RESET_1 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_1 (IR_CODE_TGT_1),
.TGT_ACTIVE_HIGH_RESET_2 (TGT_ACTIVE_HIGH_RESET_2),
.IR_CODE_TGT_2 (IR_CODE_TGT_2),
.TGT_ACTIVE_HIGH_RESET_3 (TGT_ACTIVE_HIGH_RESET_3),
.IR_CODE_TGT_3 (IR_CODE_TGT_3),
.TGT_ACTIVE_HIGH_RESET_4 (TGT_ACTIVE_HIGH_RESET_4),
.IR_CODE_TGT_4 (IR_CODE_TGT_4),
.TGT_ACTIVE_HIGH_RESET_5 (TGT_ACTIVE_HIGH_RESET_5),
.IR_CODE_TGT_5 (IR_CODE_TGT_5),
.TGT_ACTIVE_HIGH_RESET_6 (TGT_ACTIVE_HIGH_RESET_6),
.IR_CODE_TGT_6 (IR_CODE_TGT_6),
.TGT_ACTIVE_HIGH_RESET_7 (TGT_ACTIVE_HIGH_RESET_7),
.IR_CODE_TGT_7 (IR_CODE_TGT_7),
.TGT_ACTIVE_HIGH_RESET_8 (TGT_ACTIVE_HIGH_RESET_8),
.IR_CODE_TGT_8 (IR_CODE_TGT_8),
.TGT_ACTIVE_HIGH_RESET_9 (TGT_ACTIVE_HIGH_RESET_9),
.IR_CODE_TGT_9 (IR_CODE_TGT_9),
.TGT_ACTIVE_HIGH_RESET_10 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_10 (IR_CODE_TGT_10),
.TGT_ACTIVE_HIGH_RESET_11 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_11 (IR_CODE_TGT_11),
.TGT_ACTIVE_HIGH_RESET_12 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_12 (IR_CODE_TGT_12),
.TGT_ACTIVE_HIGH_RESET_13 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_13 (IR_CODE_TGT_13),
.TGT_ACTIVE_HIGH_RESET_14 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_14 (IR_CODE_TGT_14),
.TGT_ACTIVE_HIGH_RESET_15 (TGT_ACTIVE_HIGH_RESET_1),
.IR_CODE_TGT_15 (IR_CODE_TGT_15)
) UUT (
.TCK (TCK),
.TMS (TMS),
.TDI (TDO),
.TRSTB (TRSTB),
.TDO (TDI),
.TGT_TCK_0 (TGT_TCK[0]),
.TGT_TMS_0 (TGT_TMS[0]),
.TGT_TDI_0 (TGT_TDI[0]),
.TGT_TRSTN_0 (TGT_TRST_N[0]),
.TGT_TRST_0 (),
.TGT_TDO_0 (TGT_TDO[0]),
.TGT_TCK_1 (TGT_TCK[1]),
.TGT_TMS_1 (TGT_TMS[1]),
.TGT_TDI_1 (TGT_TDI[1]),
.TGT_TRSTN_1 (TGT_TRST_N[1]),
.TGT_TRST_1 (),
.TGT_TDO_1 (TGT_TDO[1]),
.TGT_TCK_2 (TGT_TCK[2]),
.TGT_TMS_2 (TGT_TMS[2]),
.TGT_TDI_2 (TGT_TDI[2]),
.TGT_TRSTN_2 (TGT_TRST_N[2]),
.TGT_TRST_2 (),
.TGT_TDO_2 (TGT_TDO[2]),
.TGT_TCK_3 (TGT_TCK[3]),
.TGT_TMS_3 (TGT_TMS[3]),
.TGT_TDI_3 (TGT_TDI[3]),
.TGT_TRSTN_3 (TGT_TRST_N[3]),
.TGT_TRST_3 (),
.TGT_TDO_3 (TGT_TDO[3]),
.TGT_TCK_4 (TGT_TCK[4]),
.TGT_TMS_4 (TGT_TMS[4]),
.TGT_TDI_4 (TGT_TDI[4]),
.TGT_TRSTN_4 (TGT_TRST_N[4]),
.TGT_TRST_4 (),
.TGT_TDO_4 (TGT_TDO[4]),
.TGT_TCK_5 (TGT_TCK[5]),
.TGT_TMS_5 (TGT_TMS[5]),
.TGT_TDI_5 (TGT_TDI[5]),
.TGT_TRSTN_5 (TGT_TRST_N[5]),
.TGT_TRST_5 (),
.TGT_TDO_5 (TGT_TDO[5]),
.TGT_TCK_6 (TGT_TCK[6]),
.TGT_TMS_6 (TGT_TMS[6]),
.TGT_TDI_6 (TGT_TDI[6]),
.TGT_TRSTN_6 (TGT_TRST_N[6]),
.TGT_TRST_6 (),
.TGT_TDO_6 (TGT_TDO[6]),
.TGT_TCK_7 (TGT_TCK[7]),
.TGT_TMS_7 (TGT_TMS[7]),
.TGT_TDI_7 (TGT_TDI[7]),
.TGT_TRSTN_7 (TGT_TRST_N[7]),
.TGT_TRST_7 (),
.TGT_TDO_7 (TGT_TDO[7]),
.TGT_TCK_8 (TGT_TCK[8]),
.TGT_TMS_8 (TGT_TMS[8]),
.TGT_TDI_8 (TGT_TDI[8]),
.TGT_TRSTN_8 (TGT_TRST_N[8]),
.TGT_TRST_8 (),
.TGT_TDO_8 (TGT_TDO[8]),
.TGT_TCK_9 (TGT_TCK[9]),
.TGT_TMS_9 (TGT_TMS[9]),
.TGT_TDI_9 (TGT_TDI[9]),
.TGT_TRSTN_9 (TGT_TRST_N[9]),
.TGT_TRST_9 (),
.TGT_TDO_9 (TGT_TDO[9]),
.TGT_TCK_10 (TGT_TCK[10]),
.TGT_TMS_10 (TGT_TMS[10]),
.TGT_TDI_10 (TGT_TDI[10]),
.TGT_TRSTN_10 (TGT_TRST_N[10]),
.TGT_TRST_10 (),
.TGT_TDO_10 (TGT_TDO[10]),
.TGT_TCK_11 (TGT_TCK[11]),
.TGT_TMS_11 (TGT_TMS[11]),
.TGT_TDI_11 (TGT_TDI[11]),
.TGT_TRSTN_11 (TGT_TRST_N[11]),
.TGT_TRST_11 (),
.TGT_TDO_11 (TGT_TDO[11]),
.TGT_TCK_12 (TGT_TCK[12]),
.TGT_TMS_12 (TGT_TMS[12]),
.TGT_TDI_12 (TGT_TDI[12]),
.TGT_TRSTN_12 (TGT_TRST_N[12]),
.TGT_TRST_12 (),
.TGT_TDO_12 (TGT_TDO[12]),
.TGT_TCK_13 (TGT_TCK[13]),
.TGT_TMS_13 (TGT_TMS[13]),
.TGT_TDI_13 (TGT_TDI[13]),
.TGT_TRSTN_13 (TGT_TRST_N[13]),
.TGT_TRST_13 (),
.TGT_TDO_13 (TGT_TDO[13]),
.TGT_TCK_14 (TGT_TCK[14]),
.TGT_TMS_14 (TGT_TMS[14]),
.TGT_TDI_14 (TGT_TDI[14]),
.TGT_TRSTN_14 (TGT_TRST_N[14]),
.TGT_TRST_14 (),
.TGT_TDO_14 (TGT_TDO[14]),
.TGT_TCK_15 (TGT_TCK[15]),
.TGT_TMS_15 (TGT_TMS[15]),
.TGT_TDI_15 (TGT_TDI[15]),
.TGT_TRSTN_15 (TGT_TRST_N[15]),
.TGT_TRST_15 (),
.TGT_TDO_15 (TGT_TDO[15]),
.UJTAG_BYPASS_TCK_0 (1'b0),
.UJTAG_BYPASS_TMS_0 (1'b0),
.UJTAG_BYPASS_TDI_0 (1'b0),
.UJTAG_BYPASS_TRSTB_0 (1'b0),
.UJTAG_BYPASS_TDO_0 (),
.UJTAG_BYPASS_TCK_1 (1'b0),
.UJTAG_BYPASS_TMS_1 (1'b0),
.UJTAG_BYPASS_TDI_1 (1'b0),
.UJTAG_BYPASS_TRSTB_1 (1'b0),
.UJTAG_BYPASS_TDO_1 (),
.UJTAG_BYPASS_TCK_2 (1'b0),
.UJTAG_BYPASS_TMS_2 (1'b0),
.UJTAG_BYPASS_TDI_2 (1'b0),
.UJTAG_BYPASS_TRSTB_2 (1'b0),
.UJTAG_BYPASS_TDO_2 (),
.UJTAG_BYPASS_TCK_3 (1'b0),
.UJTAG_BYPASS_TMS_3 (1'b0),
.UJTAG_BYPASS_TDI_3 (1'b0),
.UJTAG_BYPASS_TRSTB_3 (1'b0),
.UJTAG_BYPASS_TDO_3 (),
.UTRSTB_SEC (1'b1),
.EN_SEC (1'b0),
.TDI_SEC (1'b1)
.UTRSTB ( ),
.UTMS ( )
);
////////////////////////////////////////////////////////////////////////////////
// JTAG Slave TAP instantiations
////////////////////////////////////////////////////////////////////////////////
generate
for (tgt_idx =0; tgt_idx < NUM_DEBUG_TGTS; tgt_idx = tgt_idx + 1'b1)
begin
COREJTAGDEBUG_JTAG_TAP # (
.IR_REG_WIDTH (IR_REG_WIDTH),
.DR_REG_WIDTH (DR_REG_WIDTH),
.ACTIVE_HIGH_RESET (TGT_ACTIVE_HIGH_RESET[tgt_idx])
) TGT_TAP (
// Inputs
.TCK (TGT_TCK[tgt_idx]),
.TRSTB (TGT_TRST_N[tgt_idx]),
.TMS (TGT_TMS[tgt_idx]),
.TDI (TGT_TDI[tgt_idx]),
// Outputs
.TDO (TGT_TDO[tgt_idx])
);
end
endgenerate
endmodule // COREJTAGDEBUG_TESTBENCH

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component/Actel/DirectCore/CORERESET_PF/2.3.100/CORERESET_PF.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORERESET_PF</name><vendor>Actel</vendor><library>DirectCore</library><version>2.3.100</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"/><fileSet fileSetId="HDL_FILESET"/></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/CORESPI/5.2.104/CORESPI.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORESPI</name><vendor>Actel</vendor><library>DirectCore</library><version>5.2.104</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\amba_bfm\bfm_ahbtoapb.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\amba_bfm\bfm_apb.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\amba_bfm\bfm_main.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\amba_bfm\bfm_package.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\test\user\testbench.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="5"><name>mti\bfmtovec.exe</name><userFileType>unknown</userFileType></file><file fileid="6"><name>mti\bfmtovec.lin</name><userFileType>unknown</userFileType></file><file fileid="7"><name>mti\bfmtovec_compile.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="8"><name>mti\user_tb.bfm</name><userFileType>BFM</userFileType></file><file fileid="9"><name>mti\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="10"><name>rtl\vlog\core\corespi.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="11"><name>rtl\vlog\core\spi.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="12"><name>rtl\vlog\core\spi_chanctrl.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="13"><name>rtl\vlog\core\spi_clockmux.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="14"><name>rtl\vlog\core\spi_control.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\core\spi_fifo.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="16"><name>rtl\vlog\core\spi_rf.v</name><logicalName>CORESPI_LIB</logicalName><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

19
component/Actel/DirectCore/CORESPI/5.2.104/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:04 2026
// Parameters for CORESPI
//--------------------------------------------------------------------
parameter APB_DWIDTH = 32;
parameter CFG_CLK = 16;
parameter CFG_FIFO_DEPTH = 32;
parameter CFG_FRAME_SIZE = 16;
parameter CFG_MODE = 0;
parameter CFG_MOT_MODE = 0;
parameter CFG_MOT_SSEL = 1;
parameter CFG_NSC_OPERATION = 0;
parameter CFG_TI_JMB_FRAMES = 0;
parameter CFG_TI_NSC_CUSTOM = 0;
parameter CFG_TI_NSC_FRC = 0;
parameter HDL_license = "U";
parameter testbench = "User";

BIN
component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.exe Normal file
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BIN
component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.lin Normal file
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23
component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec_compile.do Normal file
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### script to compile Actel AMBA BFM source file into vector file for simulation
# 12Jan09 Production Release Version 3.0
quietly set linux_exe "./bfmtovec.lin"
quietly set windows_exe "./bfmtovec.exe"
quietly set bfm_src_in "./user_tb.bfm"
quietly set bfm_vec_out "./user_tb.vec"
# check OS type and use appropriate executable
if {$tcl_platform(os) == "Linux"} {
echo "--- Using Linux Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.lin"
if {![file executable $bfmtovec_exe]} {
quietly set cmds "chmod +x $bfmtovec_exe"
eval $cmds
}
} else {
echo "--- Using Windows Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.exe"
}
# compile BFM source files into vector outputs
echo "--- Compiling Actel DirectCore AMBA BFM source files ..."
quietly set cmd1 "exec $bfmtovec_exe -in $bfm_src_in -out $bfm_vec_out"
eval $cmd1
echo "--- Done."

241
component/Actel/DirectCore/CORESPI/5.2.104/mti/user_tb.bfm Normal file
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memmap master 0x10000000
memmap slave 0x11000000
constant R_control 0x00
constant R_intclear 0x04
constant R_rxdata 0x08
constant R_txdata 0x0C
constant R_intmask 0x10
constant R_intraw 0x10
constant R_control2 0x18
constant R_command 0x1C
constant R_stat 0x20
constant R_ssel 0x24
constant R_txdatal 0x28
constant R_CLK_DIV 0x2C
# R_control bits
constant B_enable 0x00000001
constant B_master 0x00000002
constant B_slave 0x00000000
constant B_intenrxovr 0x00000004
constant B_intentx 0x00000008
constant B_intentxov 0x00000010
constant B_intenrxov 0x00000020
constant B_intenurun 0x00000040
constant B_oenoff 0x00000080
# R_control2 bits
constant B_intencmd 0x00000010
constant B_intentssend 0x00000020
constant B_intendatarx 0x00000040
# R_command bits (write-only)
constant B_rxfiforst 0x00000001
constant B_txfiforst 0x00000002
# R_intclear/raw/mask bits
constant B_txint 0x00000001
constant B_rxovint 0x00000004
constant B_txurint 0x00000008
constant B_cmdint 0x00000010
constant B_ssendint 0x00000020
constant B_datarxint 0x00000040
# R_status
constant B_firstframe 0x00000001
constant B_done 0x00000002
constant B_rxempty 0x00000004
constant B_txfull 0x00000008
constant B_rxoverflow 0x00000010
constant B_txunderrun 0x00000020
constant B_ssel 0x00000040
constant B_active 0x00000080
procedure main
print "CoreSPI User testbench"
debug 0
#setup 7 1 # execute $stop at end
timeout 10000
print "********************************************************************"
print "Test1: Read Initial Register values"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "Test2: Master -> Slave : 4 Byte transfer"
print "********************************************************************"
call test_slave_rx
wait 100
print "********************************************************************"
print "Test3: Check Master TX_DONE & slave DATA_RX interrupt operation"
print "********************************************************************"
call test_interrupt_operation
print "********************************************************************"
print "Test4: Read Register values after the transfer"
print "********************************************************************"
call read_reg
print "********************************************************************"
print "CoreSPI user testbench completed"
print "********************************************************************"
return
procedure read_reg
int i x
## Read contents of APB register block
print "CoreSPI master registers"
loop i 0x00 0x2C 4
readstore b master i x
print "Read from %08x: %08x" i x
endloop
print "CoreSPI slave registers"
loop i 0x00 0x2C 4
readstore b slave i x
print "Read from %08x: %08x" i x
endloop
return
procedure test_slave_rx
int i x
## 4 Byte transfer to test master->slave transfer
print "Enable the slave"
write w slave R_control (B_slave | B_enable)
print "Set slave up with TX data"
loop i 0x5 0x8 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
print "Configure master to Tx to slave 0"
write w master R_ssel 1
write w master R_control (B_master | B_enable)
print "Set master up with TX data"
loop i 0x01 0x03 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x04) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x04
#write b master R_CLK_DIV 0x04
#print "********************************************************************************"
#print "Dynamically configuring the clock division factor of master generated SPI clock"
#print "********************************************************************************"
## Wait for the transfer to complete
wait 1500
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
loop i 0x01 0x04 1
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0x5 0x8 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return
procedure test_interrupt_operation
int i x
print "Set slave up with TX data"
loop i 0x0A 0x0D 1
write w slave R_txdata i
print "Slave TX byte : %08x" i
endloop
## Enable slave DATA_RX interrupt
print "Clear any pending DATA_TX raw interrupts before enabling the DATA_RX interrupt"
write b slave R_intclear 0x40
wait 100
print "Enable slave DATA_RX interrupt"
write b slave R_control2 B_intendatarx
## Enable master TX_DONE interrupt
print "Clear any pending TX_DONE raw interrupts before enabling the TX_DONE interrupt"
write b master R_intclear 0x01
wait 100
print "Enable master TX_DONE interrupt"
write w master R_control (B_master | B_enable | B_intentx)
## Load master with tx data
print "Set master up with TX data"
loop i 0x04 0x06 1
write w master R_txdata i
print "Master TX byte : %08x" i
endloop
print "Write last byte(0x07) to the tx_datal register to terminate the transfer"
write w master R_txdatal 0x07
wait 1500
print "************************************"
print "Check master SPIINT interrupt asserted"
print "************************************"
## Check master interrupt
iotstbit 0 1
readstore b master R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "Clear master TX_DONE interrupt & check SPIINT de-asserts"
## Clear interrupt
write b master R_intclear 0x01
wait 100
## Check clear
iotstbit 0 0
print "************************************"
print "Check slave SPIINT interrupt asserted"
print "************************************"
## Check slave interrupt
iotstbit 1 1
readstore b slave R_intmask x
print "Masked Interrupt Register read as: %08x" x
print "************************************"
print "Check contents of slave RX FIFO"
print "************************************"
## Check slave
loop i 0x04 0x07
readstore w slave R_rxdata x
print "Read %08x" x
compare x i
endloop
print "Wait until data is removed from the RX_FIFO"
wait 20
print "Clear slave DATA_RX interrupt and check SPIINT de-asserts"
write b slave R_intclear 0x40
wait 100
## Check clear
iotstbit 1 0
print "************************************"
print "Check contents of master RX FIFO"
print "************************************"
loop i 0xA 0xD 1
readstore w master R_rxdata x
print "Read %08x" x
compare x i
endloop
return

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component/Actel/DirectCore/CORESPI/5.2.104/mti/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {SPI Master}
add wave -noupdate -divider APB
add wave -noupdate -format Literal /testbench/USPIM/PADDR
add wave -noupdate -format Logic /testbench/USPIM/PCLK
add wave -noupdate -format Logic /testbench/USPIM/PENABLE
add wave -noupdate -format Literal /testbench/USPIM/PRDATA
add wave -noupdate -format Logic /testbench/USPIM/PREADY
add wave -noupdate -format Logic /testbench/USPIM/PRESETN
add wave -noupdate -format Logic /testbench/USPIM/PSEL
add wave -noupdate -format Logic /testbench/USPIM/PSLVERR
add wave -noupdate -format Literal /testbench/USPIM/PWDATA
add wave -noupdate -format Logic /testbench/USPIM/PWRITE
add wave -noupdate -divider Serial
add wave -noupdate -format Logic /testbench/USPIM/SPICLKI
add wave -noupdate -format Logic /testbench/USPIM/SPIINT
add wave -noupdate -format Logic /testbench/USPIM/SPIMODE
add wave -noupdate -format Logic /testbench/USPIM/SPIOEN
add wave -noupdate -format Logic /testbench/USPIM/SPIRXAVAIL
add wave -noupdate -format Logic /testbench/USPIM/SPISCLKO
add wave -noupdate -format Logic /testbench/USPIM/SPISDI
add wave -noupdate -format Logic /testbench/USPIM/SPISDO
add wave -noupdate -format Literal /testbench/USPIM/SPISS
add wave -noupdate -format Logic /testbench/USPIM/SPISSI
add wave -noupdate -format Logic /testbench/USPIM/SPITXRFM
add wave -noupdate -divider {SPI Slave}
add wave -noupdate -divider APB
add wave -noupdate -radix hexadecimal -format Literal /testbench/USPIS/PADDR
add wave -noupdate -format Logic /testbench/USPIS/PCLK
add wave -noupdate -format Logic /testbench/USPIS/PENABLE
add wave -noupdate -format Literal /testbench/USPIS/PRDATA
add wave -noupdate -format Logic /testbench/USPIS/PREADY
add wave -noupdate -format Logic /testbench/USPIS/PRESETN
add wave -noupdate -format Logic /testbench/USPIS/PSEL
add wave -noupdate -format Logic /testbench/USPIS/PSLVERR
add wave -noupdate -format Literal /testbench/USPIS/PWDATA
add wave -noupdate -format Logic /testbench/USPIS/PWRITE
add wave -noupdate -divider Serial
add wave -noupdate -format Logic /testbench/USPIS/SPICLKI
add wave -noupdate -format Logic /testbench/USPIS/SPIINT
add wave -noupdate -format Logic /testbench/USPIS/SPIMODE
add wave -noupdate -format Logic /testbench/USPIS/SPIOEN
add wave -noupdate -format Logic /testbench/USPIS/SPIRXAVAIL
add wave -noupdate -format Logic /testbench/USPIS/SPISCLKO
add wave -noupdate -format Logic /testbench/USPIS/SPISDI
add wave -noupdate -format Logic /testbench/USPIS/SPISDO
add wave -noupdate -format Literal /testbench/USPIS/SPISS
add wave -noupdate -format Logic /testbench/USPIS/SPISSI
add wave -noupdate -format Logic /testbench/USPIS/SPITXRFM
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {44450164832 ps} 0} {{Cursor 11} {8169427 ps} 0} {{Cursor 12} {44640351578 ps} 0} {{Cursor 4} {44639015000 ps} 0}
configure wave -namecolwidth 408
configure wave -valuecolwidth 85
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {23535750 ps}

195
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_ahbtoapb.v Normal file
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`timescale 1 ns / 100 ps
// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// AHB to APB Bridge
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
//
//
// SVN Revision Information:
// SVN $Revision: 31535 $
// SVN $Date: 2018-03-16 18:51:54 +0530 (Fri, 16 Mar 2018) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
// 28Nov07 IPB Updated to increase throughput
//
// *********************************************************************/
module CORESPI_BFM_AHB2APB (HCLK, HRESETN, HSEL, HWRITE, HADDR, HWDATA, HRDATA, HREADYIN, HREADYOUT, HTRANS, HSIZE, HBURST, HMASTLOCK, HPROT, HRESP, PSEL, PADDR, PWRITE, PENABLE, PWDATA, PRDATA, PREADY, PSLVERR);
parameter TPD = 1;
input HCLK;
input HRESETN;
input HSEL;
input HWRITE;
input[31:0] HADDR;
input[31:0] HWDATA;
output[31:0] HRDATA;
wire[31:0] HRDATA;
input HREADYIN;
output HREADYOUT;
wire HREADYOUT;
input[1:0] HTRANS;
input[2:0] HSIZE;
input[2:0] HBURST;
input HMASTLOCK;
input[3:0] HPROT;
output HRESP;
wire HRESP;
output[15:0] PSEL;
wire[15:0] PSEL;
output[31:0] PADDR;
wire[31:0] PADDR;
output PWRITE;
wire PWRITE;
output PENABLE;
wire PENABLE;
output[31:0] PWDATA;
wire[31:0] PWDATA;
input[31:0] PRDATA;
input PREADY;
input PSLVERR;
parameter[1:0] T0 = 0;
parameter[1:0] T2 = 1;
parameter[1:0] T345 = 2;
parameter[1:0] TR0 = 3;
reg[1:0] STATE;
reg HREADYOUT_P0;
reg HRESP_P0;
reg[15:0] PSEL_P0;
reg[31:0] PADDR_P0;
reg PWRITE_P0;
reg PENABLE_P0;
reg[31:0] PWDATA_P0;
wire[31:0] PWDATA_MUX;
reg DMUX;
reg PSELEN;
always @(posedge HCLK or negedge HRESETN)
begin
if (HRESETN == 1'b0)
begin
STATE <= T0 ;
HREADYOUT_P0 <= 1'b1 ;
PADDR_P0 <= {32{1'b0}} ;
PWDATA_P0 <= {32{1'b0}} ;
PWRITE_P0 <= 1'b0 ;
PENABLE_P0 <= 1'b0 ;
HRESP_P0 <= 1'b0 ;
DMUX <= 1'b0 ;
PSELEN <= 1'b0 ;
end
else
begin
HRESP_P0 <= 1'b0 ;
HREADYOUT_P0 <= 1'b0 ;
DMUX <= 1'b0 ;
case (STATE)
T0 :
begin
if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
begin
STATE <= T2 ;
PADDR_P0 <= HADDR ;
PWRITE_P0 <= HWRITE ;
PWDATA_P0 <= HWDATA ;
PENABLE_P0 <= 1'b0 ;
DMUX <= HWRITE ;
PSELEN <= 1'b1 ;
end
else
begin
HREADYOUT_P0 <= 1'b1 ;
end
end
T2 :
begin
PENABLE_P0 <= 1'b1 ;
STATE <= T345 ;
end
T345 :
begin
if (PREADY == 1'b1)
begin
PENABLE_P0 <= 1'b0 ;
PSELEN <= 1'b0 ;
if (PSLVERR == 1'b0)
begin
STATE <= T0 ;
if (HSEL == 1'b1 & HREADYIN == 1'b1 & (HTRANS[1]) == 1'b1)
begin
STATE <= T2 ;
PADDR_P0 <= HADDR ;
PWRITE_P0 <= HWRITE ;
DMUX <= HWRITE ;
PSELEN <= 1'b1 ;
end
end
else
begin
HRESP_P0 <= 1'b1 ;
STATE <= TR0 ;
end
end
end
TR0 :
begin
HRESP_P0 <= 1'b1 ;
HREADYOUT_P0 <= 1'b1 ;
STATE <= T0 ;
end
endcase
if (DMUX == 1'b1)
begin
PWDATA_P0 <= HWDATA ;
end
end
end
always @(PADDR_P0 or PSELEN)
begin
PSEL_P0 <= {16{1'b0}} ;
if (PSELEN == 1'b1)
begin
begin : xhdl_3
integer i;
for(i = 0; i <= 15; i = i + 1)
begin
PSEL_P0[i] <= (PADDR_P0[27:24] == i) ;
end
end
end
end
assign PWDATA_MUX = (DMUX == 1'b1) ? HWDATA : PWDATA_P0 ;
assign #TPD HRDATA = PRDATA ;
assign #TPD HREADYOUT = HREADYOUT_P0 | (PREADY & PSELEN & PENABLE_P0 & ~PSLVERR) ;
assign #TPD HRESP = HRESP_P0 ;
assign #TPD PSEL = PSEL_P0 ;
assign #TPD PADDR = PADDR_P0 ;
assign #TPD PWRITE = PWRITE_P0 ;
assign #TPD PENABLE = PENABLE_P0 ;
assign #TPD PWDATA = PWDATA_MUX ;
endmodule

285
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_apb.v Normal file
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// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: AMBA BFMs
// APB Master Wrapper
//
// Revision Information:
// Date Description
// 01Sep07 Initial Release
// 14Sep07 Updated for 1.2 functionality
// 25Sep07 Updated for 1.3 functionality
// 09Nov07 Updated for 1.4 functionality
//
//
// SVN Revision Information:
// SVN $Revision: 31535 $
// SVN $Date: 2018-03-16 18:51:54 +0530 (Fri, 16 Mar 2018) $
//
//
// Resolved SARs
// SAR Date Who Description
//
//
// Notes:
//
// *********************************************************************/
`timescale 1 ns / 100 ps
module CORESPI_BFM_APB (SYSCLK, SYSRSTN, PCLK, PRESETN, PADDR, PENABLE, PWRITE, PWDATA, PRDATA, PREADY, PSLVERR, PSEL, INTERRUPT, GP_OUT, GP_IN, EXT_WR, EXT_RD, EXT_ADDR, EXT_DATA, EXT_WAIT, CON_ADDR, CON_DATA, CON_RD, CON_WR, CON_BUSY, FINISHED, FAILED);
parameter OPMODE = 0;
parameter VECTFILE = "test.vec";
parameter MAX_INSTRUCTIONS = 16384;
parameter MAX_STACK = 1024;
parameter MAX_MEMTEST = 65536;
parameter TPD = 1;
parameter DEBUGLEVEL = -1;
parameter CON_SPULSE = 0;
parameter ARGVALUE0 = 0;
parameter ARGVALUE1 = 0;
parameter ARGVALUE2 = 0;
parameter ARGVALUE3 = 0;
parameter ARGVALUE4 = 0;
parameter ARGVALUE5 = 0;
parameter ARGVALUE6 = 0;
parameter ARGVALUE7 = 0;
parameter ARGVALUE8 = 0;
parameter ARGVALUE9 = 0;
parameter ARGVALUE10 = 0;
parameter ARGVALUE11 = 0;
parameter ARGVALUE12 = 0;
parameter ARGVALUE13 = 0;
parameter ARGVALUE14 = 0;
parameter ARGVALUE15 = 0;
parameter ARGVALUE16 = 0;
parameter ARGVALUE17 = 0;
parameter ARGVALUE18 = 0;
parameter ARGVALUE19 = 0;
parameter ARGVALUE20 = 0;
parameter ARGVALUE21 = 0;
parameter ARGVALUE22 = 0;
parameter ARGVALUE23 = 0;
parameter ARGVALUE24 = 0;
parameter ARGVALUE25 = 0;
parameter ARGVALUE26 = 0;
parameter ARGVALUE27 = 0;
parameter ARGVALUE28 = 0;
parameter ARGVALUE29 = 0;
parameter ARGVALUE30 = 0;
parameter ARGVALUE31 = 0;
parameter ARGVALUE32 = 0;
parameter ARGVALUE33 = 0;
parameter ARGVALUE34 = 0;
parameter ARGVALUE35 = 0;
parameter ARGVALUE36 = 0;
parameter ARGVALUE37 = 0;
parameter ARGVALUE38 = 0;
parameter ARGVALUE39 = 0;
parameter ARGVALUE40 = 0;
parameter ARGVALUE41 = 0;
parameter ARGVALUE42 = 0;
parameter ARGVALUE43 = 0;
parameter ARGVALUE44 = 0;
parameter ARGVALUE45 = 0;
parameter ARGVALUE46 = 0;
parameter ARGVALUE47 = 0;
parameter ARGVALUE48 = 0;
parameter ARGVALUE49 = 0;
parameter ARGVALUE50 = 0;
parameter ARGVALUE51 = 0;
parameter ARGVALUE52 = 0;
parameter ARGVALUE53 = 0;
parameter ARGVALUE54 = 0;
parameter ARGVALUE55 = 0;
parameter ARGVALUE56 = 0;
parameter ARGVALUE57 = 0;
parameter ARGVALUE58 = 0;
parameter ARGVALUE59 = 0;
parameter ARGVALUE60 = 0;
parameter ARGVALUE61 = 0;
parameter ARGVALUE62 = 0;
parameter ARGVALUE63 = 0;
parameter ARGVALUE64 = 0;
parameter ARGVALUE65 = 0;
parameter ARGVALUE66 = 0;
parameter ARGVALUE67 = 0;
parameter ARGVALUE68 = 0;
parameter ARGVALUE69 = 0;
parameter ARGVALUE70 = 0;
parameter ARGVALUE71 = 0;
parameter ARGVALUE72 = 0;
parameter ARGVALUE73 = 0;
parameter ARGVALUE74 = 0;
parameter ARGVALUE75 = 0;
parameter ARGVALUE76 = 0;
parameter ARGVALUE77 = 0;
parameter ARGVALUE78 = 0;
parameter ARGVALUE79 = 0;
parameter ARGVALUE80 = 0;
parameter ARGVALUE81 = 0;
parameter ARGVALUE82 = 0;
parameter ARGVALUE83 = 0;
parameter ARGVALUE84 = 0;
parameter ARGVALUE85 = 0;
parameter ARGVALUE86 = 0;
parameter ARGVALUE87 = 0;
parameter ARGVALUE88 = 0;
parameter ARGVALUE89 = 0;
parameter ARGVALUE90 = 0;
parameter ARGVALUE91 = 0;
parameter ARGVALUE92 = 0;
parameter ARGVALUE93 = 0;
parameter ARGVALUE94 = 0;
parameter ARGVALUE95 = 0;
parameter ARGVALUE96 = 0;
parameter ARGVALUE97 = 0;
parameter ARGVALUE98 = 0;
parameter ARGVALUE99 = 0;
input SYSCLK;
input SYSRSTN;
output PCLK;
wire PCLK;
output PRESETN;
wire PRESETN;
output[31:0] PADDR;
wire[31:0] PADDR;
output PENABLE;
wire PENABLE;
output PWRITE;
wire PWRITE;
output[31:0] PWDATA;
wire[31:0] PWDATA;
input[31:0] PRDATA;
input PREADY;
input PSLVERR;
output[15:0] PSEL;
wire[15:0] PSEL;
input[255:0] INTERRUPT;
output[31:0] GP_OUT;
wire[31:0] GP_OUT;
input[31:0] GP_IN;
output EXT_WR;
wire EXT_WR;
output EXT_RD;
wire EXT_RD;
output[31:0] EXT_ADDR;
wire[31:0] EXT_ADDR;
inout[31:0] EXT_DATA;
wire[31:0] EXT_DATA;
input EXT_WAIT;
input[15:0] CON_ADDR;
inout[31:0] CON_DATA;
wire[31:0] CON_DATA;
input CON_RD;
input CON_WR;
output CON_BUSY;
wire CON_BUSY;
output FINISHED;
wire FINISHED;
output FAILED;
wire FAILED;
wire iPCLk;
wire iHCLk;
wire iHRESETN;
wire[31:0] iHADDR;
wire[2:0] iHBURST;
wire iHMASTLOCK;
wire[3:0] iHPROT;
wire[2:0] iHSIZE;
wire[1:0] iHTRANS;
wire iHWRITE;
wire[31:0] iHRDATA;
wire[31:0] iHWDATA;
wire iHREADY;
wire iHREADYIN;
wire iHREADYOUT;
wire iHRESP;
wire[15:0] iHSEL;
wire[31:0] INSTR_IN = {32{1'b0}};
CORESPI_BFM_MAIN #( OPMODE, VECTFILE, MAX_INSTRUCTIONS, MAX_STACK, MAX_MEMTEST, TPD, DEBUGLEVEL, CON_SPULSE,
ARGVALUE0, ARGVALUE1, ARGVALUE2, ARGVALUE3, ARGVALUE4, ARGVALUE5, ARGVALUE6, ARGVALUE7, ARGVALUE8, ARGVALUE9,
ARGVALUE10, ARGVALUE11, ARGVALUE12, ARGVALUE13, ARGVALUE14, ARGVALUE15, ARGVALUE16, ARGVALUE17, ARGVALUE18, ARGVALUE19,
ARGVALUE20, ARGVALUE21, ARGVALUE22, ARGVALUE23, ARGVALUE24, ARGVALUE25, ARGVALUE26, ARGVALUE27, ARGVALUE28, ARGVALUE29,
ARGVALUE30, ARGVALUE31, ARGVALUE32, ARGVALUE33, ARGVALUE34, ARGVALUE35, ARGVALUE36, ARGVALUE37, ARGVALUE38, ARGVALUE39,
ARGVALUE40, ARGVALUE41, ARGVALUE42, ARGVALUE43, ARGVALUE44, ARGVALUE45, ARGVALUE46, ARGVALUE47, ARGVALUE48, ARGVALUE49,
ARGVALUE50, ARGVALUE51, ARGVALUE52, ARGVALUE53, ARGVALUE54, ARGVALUE55, ARGVALUE56, ARGVALUE57, ARGVALUE58, ARGVALUE59,
ARGVALUE60, ARGVALUE61, ARGVALUE62, ARGVALUE63, ARGVALUE64, ARGVALUE65, ARGVALUE66, ARGVALUE67, ARGVALUE68, ARGVALUE69,
ARGVALUE70, ARGVALUE71, ARGVALUE72, ARGVALUE73, ARGVALUE74, ARGVALUE75, ARGVALUE76, ARGVALUE77, ARGVALUE78, ARGVALUE79,
ARGVALUE80, ARGVALUE81, ARGVALUE82, ARGVALUE83, ARGVALUE84, ARGVALUE85, ARGVALUE86, ARGVALUE87, ARGVALUE88, ARGVALUE89,
ARGVALUE90, ARGVALUE91, ARGVALUE92, ARGVALUE93, ARGVALUE94, ARGVALUE95, ARGVALUE96, ARGVALUE97, ARGVALUE98, ARGVALUE99
) UBFM(
.SYSCLK(SYSCLK),
.SYSRSTN(SYSRSTN),
.HADDR(iHADDR),
.HCLK(iHCLk),
.PCLK(iPCLk),
.HRESETN(iHRESETN),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HSIZE(iHSIZE),
.HTRANS(iHTRANS),
.HWRITE(iHWRITE),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADY(iHREADY),
.HRESP(iHRESP),
.HSEL(iHSEL),
.INTERRUPT(INTERRUPT),
.GP_OUT(GP_OUT),
.GP_IN(GP_IN),
.EXT_WR(EXT_WR),
.EXT_RD(EXT_RD),
.EXT_ADDR(EXT_ADDR),
.EXT_DATA(EXT_DATA),
.EXT_WAIT(EXT_WAIT),
.CON_ADDR(CON_ADDR),
.CON_DATA(CON_DATA),
.CON_RD(CON_RD),
.CON_WR(CON_WR),
.CON_BUSY(CON_BUSY),
.INSTR_OUT(),
.INSTR_IN(INSTR_IN),
.FINISHED(FINISHED),
.FAILED(FAILED)
);
assign PCLK = iPCLk ;
assign PRESETN = iHRESETN ;
CORESPI_BFM_AHB2APB #(TPD) UBRIDGE(
.HCLK(iHCLk),
.HRESETN(iHRESETN),
.HSEL(1'b1),
.HWRITE(iHWRITE),
.HADDR(iHADDR),
.HWDATA(iHWDATA),
.HRDATA(iHRDATA),
.HREADYIN(iHREADY),
.HREADYOUT(iHREADY),
.HTRANS(iHTRANS),
.HSIZE(iHSIZE),
.HBURST(iHBURST),
.HMASTLOCK(iHMASTLOCK),
.HPROT(iHPROT),
.HRESP(iHRESP),
.PSEL(PSEL),
.PADDR(PADDR),
.PWRITE(PWRITE),
.PENABLE(PENABLE),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR)
);
endmodule

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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_main.v Normal file
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1133
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_package.v Normal file
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component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// corespi.v
//
//
// SVN Revision Information:
// SVN $Revision: 31477 $
// SVN $Date: 2018-03-13 12:25:12 +0530 (Tue, 13 Mar 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94973: Repackage core as a generic core
//
// Notes:
//
//
// *********************************************************************/
module
CORESPI
( //inputs
PCLK, //system clock
PRESETN, //system reset
PADDR, //address line
PSEL, //device select
PENABLE, //enable
PWRITE, //write
PWDATA, //write data
SPISSI, //slave select
SPISDI, //serial data in
SPICLKI, //serial clock in
//outputs
PRDATA, //data read
SPIINT, //interrupt
SPISS, //slave select
SPISCLKO, //serial clock out
SPIRXAVAIL, //data ready to be read (dma mode)
SPITXRFM, //room for more (dma mode)
SPIOEN, //output enable
SPISDO, //serial data out
SPIMODE, //1 -> master, 0 -> slave,
PREADY,
PSLVERR
);
//parameter FAMILY = 15; // 94973
parameter APB_DWIDTH = 8;
parameter CFG_FRAME_SIZE = 4;
parameter CFG_FIFO_DEPTH = 4;
parameter CFG_CLK = 3;
parameter CFG_MODE = 0;
parameter CFG_MOT_MODE = 2;
parameter CFG_MOT_SSEL = 0;
parameter CFG_TI_NSC_CUSTOM = 0;
parameter CFG_TI_NSC_FRC = 0;
parameter CFG_TI_JMB_FRAMES = 0;
parameter CFG_NSC_OPERATION = 0;
//parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0; // 94973
localparam SPS = ((CFG_MODE == 2'd0) && (CFG_MOT_SSEL == 1'b1)) ? 1'b1 :
((CFG_MODE == 2'd2) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_NSC_OPERATION == 2'd2)) ? 1'b1 :
1'b0;
localparam SPO = (CFG_MODE == 2'd0) ? CFG_MOT_MODE[1] :
(((CFG_MODE == 2'd1) || (CFG_MODE == 2'd2)) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_TI_NSC_FRC == 1'b1)) ? 1'b1 :
1'b0;
localparam SPH = (CFG_MODE == 2'd0) ? CFG_MOT_MODE[0] :
((CFG_MODE == 2'd1) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_TI_JMB_FRAMES == 1'b1)) ? 1'b1 :
((CFG_MODE == 2'd2) && (CFG_TI_NSC_CUSTOM == 1'b1) && (CFG_NSC_OPERATION == 2'd1)) ? 1'b1 :
1'b0;
//input TESTMODE;
input PCLK;
input PRESETN;
input [6:0] PADDR;
input PSEL;
input PENABLE;
input PWRITE;
input [APB_DWIDTH-1:0] PWDATA;
input SPISSI;
input SPISDI;
input SPICLKI;
output [APB_DWIDTH-1:0] PRDATA;
output SPIINT;
output [7:0] SPISS;
output SPISCLKO;
output SPIRXAVAIL;
output SPITXRFM;
output SPIOEN;
output SPIMODE;
output SPISDO;
// AP3
output PSLVERR;
output PREADY;
wire aresetn;
wire sresetn;
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : PRESETN; //94973
//assign sresetn = (SYNC_RESET == 1) ? PRESETN : 1'b1; //94973
assign aresetn = PRESETN; // 94973
assign sresetn = 1'b1; // 94973
// tie off AP3 signals
assign PSLVERR = 1'b0;
assign PREADY = 1'b1;
spi # (
.APB_DWIDTH (APB_DWIDTH),
.CFG_FRAME_SIZE (CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH (CFG_FIFO_DEPTH),
.CFG_CLK (CFG_CLK),
.SPO (SPO),
.SPH (SPH),
.SPS (SPS),
.CFG_MODE (CFG_MODE)
//.SYNC_RESET (SYNC_RESET) // 94973
) USPI( //inputs
.PCLK(PCLK),
.PRESETN(PRESETN),
.aresetn(aresetn),
.sresetn(sresetn),
.PADDR(PADDR),
.PSEL(PSEL),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA),
.SPISSI(SPISSI),
.SPISDI(SPISDI),
.SPICLKI(SPICLKI),
//outputs
.PRDDATA(PRDATA),
.SPIINT(SPIINT),
.SPISS(SPISS),
.SPISCLKO(SPISCLKO),
.SPIRXAVAIL(SPIRXAVAIL),
.SPITXRFM(SPITXRFM),
.SPIOEN(SPIOEN),
.SPISDO(SPISDO),
.SPIMODE(SPIMODE)
);
endmodule

331
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v Normal file
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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// spi.v -- top level module for spi core
//
//
// SVN Revision Information:
// SVN $Revision: 31478 $
// SVN $Date: 2018-03-13 12:27:38 +0530 (Tue, 13 Mar 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94224: Add dynamic clcok configuration feature for generated
// master SPI clock
// 94973: Repackage core as a generic core
//
// Notes:
//
//
// *********************************************************************/
module spi( //inputs
PCLK, //system clock
PRESETN, //system reset
aresetn, //Async reset signal
sresetn, //Sync reset signal
PADDR, //address line
PSEL, //device select
PENABLE, //enable
PWRITE, //write
PWDATA, //write data
SPISSI, //slave select
SPISDI, //serial data in
SPICLKI, //serial clock in
//outputs
PRDDATA, //data read
SPIINT, //interrupt
SPISS, //slave select
SPISCLKO, //serial clock out
SPIRXAVAIL, //data ready to be read (dma mode)
SPITXRFM, //room for more (dma mode)
SPIOEN, //output enable
SPISDO, //serial data out
SPIMODE //1 -> master, 0 -> slave
);
parameter APB_DWIDTH = 8;
parameter CFG_FRAME_SIZE = 4;
parameter CFG_FIFO_DEPTH = 4;
parameter CFG_CLK = 7;
parameter SPO = 0;
parameter SPH = 0;
parameter SPS = 0;
parameter CFG_MODE = 0;
//parameter SYNC_RESET = 0; // 94973
//input TESTMODE;
input PCLK;
input PRESETN;
input aresetn;
input sresetn;
input [6:0] PADDR;
input PSEL;
input PENABLE;
input PWRITE;
input [APB_DWIDTH-1:0] PWDATA;
input SPISSI;
input SPISDI;
input SPICLKI;
output [APB_DWIDTH-1:0] PRDDATA;
output SPIINT;
output [7:0] SPISS;
output SPISCLKO;
output SPIRXAVAIL;
output SPITXRFM;
output SPIOEN;
output SPIMODE;
output SPISDO;
wire [7:0] clk_div_val; // 94224
wire [APB_DWIDTH-1:0] prdata_regs;
wire [7:0] cfg_ssel;
wire cfg_master;
wire cfg_enable;
wire [2:0] cfg_cmdsize;
wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_in;
wire [CFG_FRAME_SIZE-1:0] tx_fifo_data_out;
wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_in;
wire [CFG_FRAME_SIZE-1:0] rx_fifo_data_out;
wire rx_fifo_empty;
wire tx_fifo_full;
wire master_ssel_out;
wire [5:0] rx_fifo_count;
wire [5:0] tx_fifo_count;
//##########################################################################################
//APB Signals
wire [6:0] PADDR32 = { PADDR[6:2], 2'b00 };
//read data: either from the register file or the fifo.
assign PRDDATA = ~(PADDR32[6:0]==7'h08) ? prdata_regs : rx_fifo_data_out;
assign SPIMODE = cfg_master;
assign SPIRXAVAIL = ~rx_fifo_empty;
assign SPITXRFM = ~tx_fifo_full;
// ----------------------------------------------------------------------------------
// Channel Outputs
//Pass the slave select to the selected devices. If no slave select asserted then everything off
reg [7:0] master_ssel_all;
assign SPISS = master_ssel_all;
integer i;
always @(*)
begin
if (cfg_enable && cfg_master)
begin
for (i=0; i<8; i=i+1)
begin
if (cfg_ssel[i])
master_ssel_all[i] = master_ssel_out;
else
master_ssel_all[i] = (CFG_MODE != 1); //Send low in TIMODE to deselect
end
end
else
begin
for (i =0; i<8; i=i+1)
master_ssel_all[i] = (CFG_MODE != 1); //Send low in TIMODE to deselect
end
end
wire ssel_both = ( cfg_master ? master_ssel_out : SPISSI );
//-----------------------------------------------------------------------------------------
// The Register Set
spi_rf # (
.APB_DWIDTH(APB_DWIDTH),
.CFG_CLK(CFG_CLK) // 94224
)
URF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.paddr (PADDR32[6:0]),
.psel (PSEL),
.penable (PENABLE),
.pwrite (PWRITE),
.wrdata (PWDATA),
.prdata (prdata_regs),
.interrupt (SPIINT),
.tx_channel_underflow (tx_channel_underflow),
.rx_channel_overflow (rx_channel_overflow),
.tx_done (tx_done),
.rx_done (rx_done),
.rx_fifo_read (rx_fifo_read),
.tx_fifo_write (tx_fifo_write),
.tx_fifo_read (tx_fifo_read),
.rx_fifo_full (rx_fifo_full),
.rx_fifo_full_next (rx_fifo_full_next),
.rx_fifo_empty (rx_fifo_empty),
.rx_fifo_empty_next (rx_fifo_empty_next),
.tx_fifo_full (tx_fifo_full),
.tx_fifo_full_next (tx_fifo_full_next),
.tx_fifo_empty (tx_fifo_empty),
.tx_fifo_empty_next (tx_fifo_empty_next),
.first_frame (first_frame_out),
.ssel (ssel_both),
.rx_pktend (rx_pktend),
.rx_cmdsize (rx_cmdsize),
.active (active),
.cfg_enable (cfg_enable),
.cfg_master (cfg_master),
.cfg_ssel (cfg_ssel),
.cfg_cmdsize (cfg_cmdsize),
.clr_txfifo (fiforsttx),
.clr_rxfifo (fiforstrx),
.cfg_frameurun (cfg_frameurun),
.cfg_oenoff (cfg_oenoff),
.clk_div_val (clk_div_val) // 94224
);
// APB side of FIFOs Control
spi_control # (
.CFG_FRAME_SIZE (CFG_FRAME_SIZE)
) UCON ( .aresetn (aresetn),
.sresetn (sresetn),
.psel (PSEL),
.penable (PENABLE),
.pwrite (PWRITE),
.paddr (PADDR32[6:0]),
.wr_data_in (PWDATA[CFG_FRAME_SIZE-1:0]), // Use only FRAME_SIZE bits for data
.cfg_master (cfg_master),
.tx_fifo_data (tx_fifo_data_in),
.tx_fifo_write (tx_fifo_write),
.tx_fifo_last (tx_fifo_last_in),
.tx_fifo_empty (tx_fifo_empty),
.rx_fifo_read (rx_fifo_read),
.rx_fifo_empty (rx_fifo_empty)
);
//Transmit Fifo
spi_fifo # (
.CFG_FRAME_SIZE (CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH (CFG_FIFO_DEPTH)
) UTXF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.fiforst (fiforsttx),
.data_in (tx_fifo_data_in),
.flag_in (tx_fifo_last_in),
.data_out (tx_fifo_data_out),
.flag_out (tx_fifo_last_out),
.read_in (tx_fifo_read),
.write_in (tx_fifo_write),
.full_out (tx_fifo_full),
.empty_out (tx_fifo_empty),
.full_next_out (tx_fifo_full_next),
.empty_next_out (tx_fifo_empty_next),
.overflow_out (not_used1),
.fifo_count (tx_fifo_count)
);
//Receive Fifo
spi_fifo # (
.CFG_FRAME_SIZE(CFG_FRAME_SIZE),
.CFG_FIFO_DEPTH(CFG_FIFO_DEPTH)
) URXF ( .pclk (PCLK),
.aresetn (aresetn),
.sresetn (sresetn),
.fiforst (fiforstrx),
//.fifosize (cfg_fifosize),
.data_in (rx_fifo_data_in),
.write_in (rx_fifo_write),
.flag_in (rx_fifo_first_in),
.data_out (rx_fifo_data_out),
.read_in (rx_fifo_read),
.flag_out (first_frame_out),
.full_out (rx_fifo_full),
.empty_out (rx_fifo_empty),
.empty_next_out (rx_fifo_empty_next),
.full_next_out (rx_fifo_full_next),
.overflow_out (rx_channel_overflow),
.fifo_count (rx_fifo_count)
);
//Channel controll
spi_chanctrl # (
.SPH (SPH),
.SPO (SPO),
.SPS (SPS),
.CFG_MODE (CFG_MODE),
.CFG_CLKRATE (CFG_CLK),
.CFG_FRAME_SIZE (CFG_FRAME_SIZE)
//.SYNC_RESET (SYNC_RESET) // 94973
)UCC ( .pclk (PCLK),
.presetn (PRESETN),
.aresetn (aresetn),
.sresetn (sresetn),
.spi_clk_in (SPICLKI),
.spi_clk_out (SPISCLKO),
.spi_ssel_in (SPISSI),
.spi_ssel_out (master_ssel_out),
.spi_data_in (SPISDI),
.spi_data_out (SPISDO),
.spi_data_oen (SPIOEN),
.txfifo_count (tx_fifo_count),
.txfifo_empty (tx_fifo_empty),
.txfifo_read (tx_fifo_read),
.txfifo_data (tx_fifo_data_out),
.txfifo_last (tx_fifo_last_out),
.rxfifo_count (rx_fifo_count),
.rxfifo_write (rx_fifo_write),
.rxfifo_data (rx_fifo_data_in),
.rxfifo_first (rx_fifo_first_in),
.cfg_enable (cfg_enable),
.cfg_master (cfg_master),
.cfg_frameurun (cfg_frameurun),
.cfg_cmdsize (cfg_cmdsize),
.cfg_oenoff (cfg_oenoff),
.tx_alldone (tx_done),
.rx_alldone (rx_done),
.rx_pktend (rx_pktend),
.rx_cmdsize (rx_cmdsize),
.tx_underrun (tx_channel_underflow),
.active (active),
.clk_div_val (clk_div_val) // 94224
);
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Clock Mux.
//
// SVN Revision Information:
// SVN $Revision: 23983 $
// SVN $Date: 2014-11-28 23:42:46 +0530 (Fri, 28 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
module spi_clockmux ( input sel,
input clka,
input clkb,
output reg clkout
);
always @(*)
begin
case (sel)
1'b0 : clkout = clka;
1'b1 : clkout = clkb;
default : clkout = clka;
endcase
end
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Top level control.
//
// SVN Revision Information:
// SVN $Revision: 23983 $
// SVN $Date: 2014-11-28 23:42:46 +0530 (Fri, 28 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
//
// *********************************************************************/
module spi_control # (
parameter CFG_FRAME_SIZE = 4
)(
input aresetn,
input sresetn,
input psel,
input penable,
input pwrite,
input [6:0] paddr,
input [CFG_FRAME_SIZE-1:0] wr_data_in,
input cfg_master,
input rx_fifo_empty,
input tx_fifo_empty,
output [CFG_FRAME_SIZE-1:0] tx_fifo_data,
output tx_fifo_write,
output tx_fifo_last,
output rx_fifo_read
);
//######################################################################################################
reg tx_fifo_write_sig;
reg rx_fifo_read_sig;
reg tx_last_frame_sig;
// Output assignments.
assign tx_fifo_last = tx_last_frame_sig;
assign tx_fifo_data = wr_data_in;
assign tx_fifo_write = tx_fifo_write_sig;
assign rx_fifo_read = rx_fifo_read_sig;
// Note combinational generation of FIFO read and write signals
always @(*)
begin
//defaults
rx_fifo_read_sig = 1'b0; //default no read on rx fifo
tx_fifo_write_sig = 1'b0; //default no write on tx fifo
tx_last_frame_sig = 1'b0; //default not last frame
if (penable && psel)
begin
case (paddr) //synthesis parallel_case
6'h0C: //write to transmit fifo
begin
if (pwrite)
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
end
end
6'h08: //read from receive fifo
begin
if (~pwrite)
begin
rx_fifo_read_sig = 1'b1;
end
end
6'h28: // aliased transmit data, sets last frame bit
begin
if(pwrite)
begin
tx_fifo_write_sig = 1'b1; //write to the fifo
tx_last_frame_sig = 1'b1; //last frame
end
end
default:
begin
end
endcase
end
end
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Synchronous Fifo
//
//
// SVN Revision Information:
// SVN $Revision: 28014 $
// SVN $Date: 2016-11-24 20:43:31 +0530 (Thu, 24 Nov 2016) $
//
// Resolved SARs
// SAR Date Who Description
//
//
// *********************************************************************/
module spi_fifo( pclk,
aresetn,
sresetn,
fiforst,
data_in,
flag_in,
data_out,
flag_out,
read_in,
write_in,
full_out,
empty_out,
full_next_out,
empty_next_out,
overflow_out,
fifo_count
);
parameter CFG_FRAME_SIZE = 4; // 4-32
parameter CFG_FIFO_DEPTH = 4; // 2,4,8,16,32
localparam PTR_WIDTH = log2(CFG_FIFO_DEPTH);
input pclk;
input aresetn;
input sresetn;
input fiforst;
input [CFG_FRAME_SIZE-1:0] data_in;
input read_in;
input write_in;
input flag_in;
output [CFG_FRAME_SIZE-1:0] data_out;
output empty_out;
output full_out;
output empty_next_out;
output full_next_out;
output overflow_out;
output flag_out;
output [5:0] fifo_count;
reg [PTR_WIDTH - 1:0] rd_pointer_d;
reg [PTR_WIDTH - 1:0] rd_pointer_q; //read pointer address
reg [PTR_WIDTH - 1:0] wr_pointer_d;
reg [PTR_WIDTH - 1:0] wr_pointer_q; //write pointer address
reg [5:0] counter_d;
reg [5:0] counter_q; //counter 5 bits
reg [CFG_FRAME_SIZE:0] fifo_mem_d[0:CFG_FIFO_DEPTH-1]; //FIFO has extra flag bit (CFG_FRAME_SIZE + 1)
reg [CFG_FRAME_SIZE:0] fifo_mem_q[0:CFG_FIFO_DEPTH-1];
reg [CFG_FRAME_SIZE:0] data_out_dx;
reg [CFG_FRAME_SIZE:0] data_out_d;
reg full_out;
reg empty_out;
reg full_next_out;
reg empty_next_out;
wire [CFG_FRAME_SIZE-1:0] data_out = data_out_d[CFG_FRAME_SIZE-1:0];
wire flag_out = data_out_d[CFG_FRAME_SIZE];
assign overflow_out = (write_in && (counter_q == CFG_FIFO_DEPTH)); /* write and fifo full */
integer i;
//------------------------------------------------------------------------------------------------------------
//infer the FIFO - no reset required
always @(posedge pclk)
begin
for (i=0; i<CFG_FIFO_DEPTH; i=i+1)
begin
fifo_mem_q[i] <= fifo_mem_d[i];
end
end
//infer the registers and register the flags
always @(posedge pclk or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
rd_pointer_q <= 0;
wr_pointer_q <= 0;
counter_q <= 0;
full_out <= 0;
empty_out <= 1;
full_next_out <= 0;
empty_next_out <= 0;
end
else
begin
rd_pointer_q <= rd_pointer_d;
wr_pointer_q <= wr_pointer_d;
counter_q <= counter_d;
full_out <= (counter_d == CFG_FIFO_DEPTH); //is next pointer equal to fifo length
empty_out <= (counter_d == 0);
full_next_out <= (counter_q == CFG_FIFO_DEPTH-1);
empty_next_out <= (counter_q == 1);
end
end
integer j;
always @(*)
begin
for (j=0; j<CFG_FIFO_DEPTH; j=j+1) // Hold old values
begin
fifo_mem_d[j] = fifo_mem_q[j];
end
if (write_in)
begin
if (counter_q != CFG_FIFO_DEPTH)
begin
fifo_mem_d[wr_pointer_q[PTR_WIDTH -1:0]][CFG_FRAME_SIZE-1:0] = data_in[CFG_FRAME_SIZE-1:0];
fifo_mem_d[wr_pointer_q[PTR_WIDTH -1:0]][CFG_FRAME_SIZE] = flag_in;
end
end
//Read - data out always available
data_out_dx = fifo_mem_q[rd_pointer_q[PTR_WIDTH - 1:0]];
end
// Perform extra read mux on Byte/Half wide reads
always @(*)
begin
// flag bits are zero if count zero
data_out_d = data_out_dx[CFG_FRAME_SIZE:0];
if (counter_q == 0) data_out_d[CFG_FRAME_SIZE] = 1'b0;
end
// Pointers and Flags
always @(*)
begin
if (fiforst==1'b1)
begin
wr_pointer_d = 0;
rd_pointer_d = 0;
counter_d = 6'b000000;
end
else
begin
//defaults
counter_d = counter_q;
rd_pointer_d = rd_pointer_q;
wr_pointer_d = wr_pointer_q;
if (read_in)
begin
if (counter_q != 0) // ignore read when empty
begin
if (~write_in) //if not writing decrement count of the number of objects in fifo else count stays the same
begin
counter_d = counter_q - 1'b1;
end
if (rd_pointer_q == CFG_FIFO_DEPTH - 1)
rd_pointer_d = 0;
else
rd_pointer_d = rd_pointer_q + 1'b1;
end
end //~read_n
if (write_in)
begin
if (counter_q != CFG_FIFO_DEPTH) // ignore write when full
begin
if (~read_in)
begin
counter_d = counter_q + 1'b1;
end
if (wr_pointer_q == CFG_FIFO_DEPTH-1)
wr_pointer_d = 0;
else
wr_pointer_d = wr_pointer_q + 1'b1;
end //~write_n
end
end
end
wire [5:0] fifo_count = counter_q;
function [31:0] log2;
input integer N;
integer tmp, res;
begin
tmp = 1;
res = 0;
while (tmp < N) begin
tmp = tmp*2;
res = res+1;
end
log2 = res;
end
endfunction
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// SPI Register file
//
//
// SVN Revision Information:
// SVN $Revision: 31320 $
// SVN $Date: 2018-02-16 12:53:27 +0530 (Fri, 16 Feb 2018) $
//
// Resolved SARs
// SAR Date Who Description
// 94224: Add dynamic clcok configuration feature for generated
// master SPI clock
//
// Notes:
//
//
// *********************************************************************/
module spi_rf # (
parameter APB_DWIDTH = 8,
parameter CFG_CLK = 7 // 94224
)( //APB Access to registers
input pclk,
input aresetn,
input sresetn,
input [6:0] paddr,
input psel,
input pwrite,
input penable,
input [APB_DWIDTH-1:0] wrdata,
output [APB_DWIDTH-1:0] prdata,
output interrupt,
//Hardware Status
input tx_channel_underflow,
input rx_channel_overflow,
input tx_done,
input rx_done,
input rx_fifo_read,
input tx_fifo_read,
input tx_fifo_write,
input rx_fifo_full,
input rx_fifo_full_next,
input rx_fifo_empty,
input rx_fifo_empty_next,
input tx_fifo_full,
input tx_fifo_full_next,
input tx_fifo_empty,
input tx_fifo_empty_next,
input first_frame,
input ssel,
input active,
input rx_pktend,
input rx_cmdsize,
//Static Configuration Outputs
output cfg_enable,
output cfg_master,
output reg [7:0] cfg_ssel,
output [2:0] cfg_cmdsize,
output cfg_oenoff,
//Strobe Outputs, will change during operation
output reg clr_txfifo,
output reg clr_rxfifo,
output cfg_frameurun,
output [7:0] clk_div_val // 94224
);
reg [7:0] control1;
reg [7:0] control2;
wire [5:0] command;
wire [7:0] int_masked;
reg [7:0] int_raw;
wire [7:0] status_byte;
reg [1:0] sticky;
reg [7:0] CLK_DIV; // 94224
reg [APB_DWIDTH-1:0] rdata;
// -----------------------------------------------------------------------------------------------------------------------
// Registers with sticky bits (The interrupt register)
assign int_masked = {
(int_raw[7] && control2[7]), // !tx_fifo_full
(int_raw[6] && control2[6]), // !rx_fifo_empty
(int_raw[5] && control2[5]), // ssend
(int_raw[4] && control2[4]), // cmdint
(int_raw[3] && control1[5]), // txunderrun
(int_raw[2] && control1[4]), // rxoverflow
(1'b0),
(int_raw[0] && control1[3]) // txdone
};
assign interrupt = int_masked[7] || int_masked[6] || int_masked[5] || int_masked[4] ||
int_masked[3] || int_masked[2] || int_masked[1] || int_masked[0] ;
// ############################################################################################################
// Create Register Values
assign status_byte = { active,
ssel,
int_raw[3],
int_raw[2],
tx_fifo_full,
rx_fifo_empty,
(sticky[0] && sticky[1]),
first_frame
};
assign command = 8'h00;
// ############################################################################################################
// Writes.
integer i;
always @(posedge pclk or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
control1 <= 8'h00;
cfg_ssel <= 8'h00;
control2 <= 8'h00;
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
int_raw <= 8'h80;
sticky <= 2'b00;
CLK_DIV <= CFG_CLK; // 94224
end
else
begin
//------------------------------------------------------------------------
// Hardware Events lower priority than CPU activities
clr_rxfifo <= 1'b0;
clr_txfifo <= 1'b0;
//-----------------------------------------------------------------------
// CPU Writes
if (psel & pwrite & penable)
begin
case (paddr) //synthesis parallel_case
7'h00: begin
control1[7:0] <= wrdata[7:0];
end
7'h04: begin
for (i=0; i<8; i=i+1) if (wrdata[i]) int_raw[i] <= 1'b0;
end
7'h18: begin
control2 <= wrdata[7:0];
end
7'h1c: begin
clr_rxfifo <= wrdata[0];
clr_txfifo <= wrdata[1];
end
7'h24: cfg_ssel <= wrdata[7:0];
7'h2C: CLK_DIV <= wrdata[7:0]; // 94224
default: begin end
endcase
//if we were enabled don't allow various changes
end
//------------------------------------------------------------------------
// Hardware Events higher priority than CPU activities
// Sticky Status Bits
if (tx_done) sticky[0] <= 1'b1;
if (rx_done) sticky[1] <= 1'b1;
if (tx_fifo_write) sticky[0] <= 1'b0;
if (rx_fifo_read) sticky[1] <= 1'b0;
// Interrupt Settings
if (tx_done) int_raw[0] <= 1'b1;
if (rx_done) int_raw[1] <= 1'b1;
if (rx_channel_overflow) int_raw[2] <= 1'b1;
if (tx_channel_underflow) int_raw[3] <= 1'b1;
if (rx_cmdsize) int_raw[4] <= 1'b1;
if (rx_pktend) int_raw[5] <= 1'b1;
if (!rx_fifo_empty) int_raw[6] <= 1'b1;
if (!tx_fifo_full) int_raw[7] <= 1'b1;
control2[3] <= 1'b0;
end
end
// clk division value in CLK_DIV register
assign clk_div_val[7:0] = CLK_DIV[7:0]; // 94224
// 5:2 are interrupt enables
assign cfg_enable = control1[0];
assign cfg_master = control1[1];
assign cfg_frameurun = control1[6];
assign cfg_oenoff = control1[7];
assign cfg_cmdsize = control2[2:0];
// ############################################################################################################
// Reads, purely combinational of the PADDR.
localparam [APB_DWIDTH-1:0] ZEROS = {(APB_DWIDTH){1'b0}};
always @(*)
begin
if (psel)
begin
rdata = ZEROS;
case (paddr) //synthesis parallel_case
7'h00: rdata[7:0] = control1[7:0]; // control register 1
7'h04: rdata[7:0] = 8'h00; // write-only
// 0x08 assigned elsewhere
7'h0C: rdata[7:0] = 8'h00; // write-only
7'h10: rdata[7:0] = int_masked[7:0]; // masked interrupt register
7'h14: rdata[7:0] = int_raw[7:0]; // raw interrupt register
7'h18: rdata[7:0] = control2[7:0]; // control register 2
7'h20: rdata[7:0] = status_byte[7:0]; // status register
7'h24: rdata[7:0] = cfg_ssel[7:0]; // slave select register
7'h2C: rdata[7:0] = CLK_DIV[7:0]; // 94224 - dynamic clock configuration register
default: rdata = ZEROS;
endcase
end
else
rdata = ZEROS;
end
assign prdata = ( (psel && penable) ? rdata : ZEROS);
endmodule

220
component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/test/user/testbench.v Normal file
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`timescale 1ns/1ns
// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2014 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
//
// CoreSPI User Testbench
//
//
// SVN Revision Information:
// SVN $Revision: 23762 $
// SVN $Date: 2014-11-11 08:01:54 -0800 (Tue, 11 Nov 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
//
// *********************************************************************/
module testbench();
`include "../../../../coreparameters.v"
reg SYSCLK;
reg SYSRSTN;
wire PCLK;
wire PRESETN;
wire [31:0] PADDR;
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA;
wire [31:0] PRDATA;
wire [31:0] PRDATA_0;
wire [31:0] PRDATA_1;
wire [15:0] PSEL;
wire [255:0] INTERRUPT;
wire [31:0] GP_OUT;
wire [31:0] GP_IN;
wire FINISHED;
wire FAILED;
wire Logic0 = 1'b0;
wire Logic1 = 1'b1;
// ********************************************************************************
// Clocks and Reset
initial
begin
SYSRSTN <= 1'b0;
#100;
SYSRSTN <= 1'b1;
end
// Clock is 100MHz
always
begin
SYSCLK <= 1'b0;
#5;
SYSCLK <= 1'b1;
#5;
end
initial
begin
// wait until all BFM's are finished
wait(FINISHED === 1'b1);
$stop;
$finish;
end
// ********************************************************************************
// APB Master
CORESPI_BFM_APB #(.VECTFILE ("user_tb.vec") )
UBFM (.SYSCLK (SYSCLK),
.SYSRSTN (SYSRSTN),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA),
.PREADY (Logic1),
.PSLVERR (Logic0),
.PSEL (PSEL),
.INTERRUPT (INTERRUPT),
.GP_OUT (GP_OUT),
.GP_IN (GP_IN),
.EXT_WR (),
.EXT_RD (),
.EXT_ADDR (),
.EXT_DATA (),
.EXT_WAIT (Logic0),
.CON_ADDR (),
.CON_DATA (),
.CON_RD (Logic0),
.CON_WR (Logic0),
.CON_BUSY (),
.FINISHED (FINISHED),
.FAILED (FAILED)
);
assign PRDATA = ( PSEL[1] ? PRDATA_1 : PRDATA_0) ;
/* #############################################################################
SPIINT Output interrupt
SPISDO Output serial data out (generated by SPI as master)
SPISS[7:0] Output slave select (generated by SPI as master)
SPISCLKO Output shift clock out (generated by SPI as master)
SPISDI Input shift data in (master or slave)
SPIRXAVAIL Output request for data to be read - rx data available
SPITXRFM Output indicates transmit done - ready for more
SPISSI Input slave select (when SPI in slave mode)
SPIOEN Output output enable (when de-asserted output pad for SPISDO tri-stated). This is active when the SPI is writing output data and deactivated when there is not data to write. This signal is active high.
SPIMode Output mode: (when 1, SPI is master, when 0, SPI is slave)
*/
// ********************************************************************************
// SPI Core - Master
wire [7:0] M_SPISS;
CORESPI # (
//.FAMILY (FAMILY),
.APB_DWIDTH (32),
.CFG_FRAME_SIZE (32),
.CFG_FIFO_DEPTH (4),
.CFG_CLK (3),
.CFG_MODE (0),
.CFG_MOT_MODE (0),
.CFG_MOT_SSEL (0),
.CFG_TI_NSC_CUSTOM (0),
.CFG_TI_NSC_FRC (0),
.CFG_TI_JMB_FRAMES (0),
.CFG_NSC_OPERATION (0)
)USPIM ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[0]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_0),
.SPISSI (),
.SPISDI (S_SPISDO),
.SPICLKI (),
.SPISS (M_SPISS),
.SPISCLKO (M_SPISCLKO),
.SPIOEN (M_SPIOEN),
.SPISDO (M_SPISDO),
.SPIINT (GP_IN[0]),
.SPIRXAVAIL (),
.SPITXRFM (),
.SPIMODE (),
.PREADY (),
.PSLVERR ()
);
// ********************************************************************************
// SPI Core - Slave
wire [7:0] S_SPISS;
CORESPI # (
//.FAMILY (FAMILY),
.APB_DWIDTH (32),
.CFG_FRAME_SIZE (32),
.CFG_FIFO_DEPTH (4),
.CFG_CLK (3),
.CFG_MODE (0),
.CFG_MOT_MODE (0),
.CFG_MOT_SSEL (0),
.CFG_TI_NSC_CUSTOM (0),
.CFG_TI_NSC_FRC (0),
.CFG_TI_JMB_FRAMES (0),
.CFG_NSC_OPERATION (0)
) USPIS ( //.TESTMODE (1'b0),
.PCLK (PCLK),
.PRESETN (PRESETN),
.PADDR (PADDR[6:0]),
.PSEL (PSEL[1]),
.PENABLE (PENABLE),
.PWRITE (PWRITE),
.PWDATA (PWDATA),
.PRDATA (PRDATA_1),
.SPISSI (M_SPISS[0]),
.SPISDI (M_SPISDO),
.SPICLKI (M_SPISCLKO),
.SPISS (),
.SPISCLKO (),
.SPIOEN (),
.SPISDO (S_SPISDO),
.SPIINT (GP_IN[1]),
.SPIRXAVAIL (),
.SPITXRFM (),
.SPIMODE (),
.PREADY (),
.PSLVERR ()
);
endmodule

1
component/Actel/DirectCore/CORETSE/4.0.124/CORETSE.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORETSE</name><vendor>Actel</vendor><library>DirectCore</library><version>4.0.124</version><fileSets><fileSet fileSetId="DESIGNER_FILESET"><file fileid="0"><name>Constraints\CoreTSE.sdc</name><userFileType>SDC</userFileType></file><file fileid="1"><name>Constraints\CoreTSE_mdc.sdc</name><userFileType>SDC</userFileType></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="2"><name>rtl\vlog\test\user\tbi\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime></vendorExtensions></file><file fileid="3"><name>rtl\vlog\test\user\tbi\CoreTSE_tb.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="5"><name>coreparameters.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>mti\scripts\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="7"><name>rtl\vlog\core_evaluation\CoreTSE.v</name><userFileType>Verilog</userFileType></file><file fileid="8"><name>rtl\vlog\core_evaluation\include.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>DESIGNER_FILESET</fileSetRef><name>DESIGNER</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

27
component/Actel/DirectCore/CORETSE/4.0.124/Constraints/CoreTSE.sdc Normal file
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set GMII 0
if {$GMII == 1} {
create_clock -name PCLK -period 12.5 [get_ports {PCLK}]
create_clock -name MTXCLK -period 12.5 [get_ports {MTXCLK}]
create_clock -name MRXCLK -period 12.5 [get_ports {MRXCLK}]
create_clock -name TXCLK -period 8 [get_ports {TXCLK}]
create_clock -name RXCLK -period 8 [get_ports {RXCLK}]
set_clock_groups -asynchronous -group {TXCLK } \
-group {RXCLK } \
-group {PCLK} \
-group {MTXCLK MRXCLK}
} else {
create_clock -name PCLK -period 12.5 [get_ports {PCLK}]
create_clock -name MTXCLK -period 12.5 [get_ports {MTXCLK}]
create_clock -name MRXCLK -period 12.5 [get_ports {MRXCLK}]
create_clock -name TXCLK -period 8 [get_ports {TXCLK}]
create_clock -name RXCLK -period 8 [get_ports {RXCLK}]
create_clock -name TBI_TX_CLK -period 8 [get_ports {TBI_TX_CLK}]
create_clock -name TBI_RX_CLK -period 8 [get_ports {TBI_RX_CLK}]
set_clock_groups -asynchronous -group {TXCLK TBI_TX_CLK} \
-group {RXCLK TBI_RX_CLK} \
-group {PCLK MGMT_CLK} \
-group {MTXCLK MRXCLK}
}
set_false_path -through [ get_nets {CORETSE_C0_0/CORETSE_C0_0/PRESETN } ]

1
component/Actel/DirectCore/CORETSE/4.0.124/Constraints/CoreTSE_mdc.sdc Normal file
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create_generated_clock -name {MGMT_CLK} -add -master_clock PCLK -divide_by 8 -source [ get_ports { PCLK } ] [ get_pins { CORETSE_C0_0/CORETSE_C0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/mdc } ]

19
component/Actel/DirectCore/CORETSE/4.0.124/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:11 2026
// Parameters for CORETSE
//--------------------------------------------------------------------
parameter ECC_ENABLE = 0;
parameter FAMILY = 26;
parameter GMII_TBI = 1;
parameter HDL_license = "E";
parameter HOST_INTERFACE = 0;
parameter MDIO_PHYID = 18;
parameter PACKET_SIZE = 11;
parameter SAL = 1;
parameter SLIP_ENABLE = 0;
parameter STATS = 1;
parameter testbench = "User";
parameter TXRX_INTR_ENABLE = 1;
parameter WoL = 1;

103
component/Actel/DirectCore/CORETSE/4.0.124/mti/scripts/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/FAMILY
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/GMII_TBI
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/PACKET_SIZE
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/SAL
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/WoL
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/STATS
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/MDIO_PHYID
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/SLIP_ENABLE
add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/RXLEN_CNT
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXCLK
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXRDY
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXACPT
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXSOF
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXEOF
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXDAT
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXBYTEVALID
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXCFRM
add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXHWM
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXCLK
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXRDY
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXACPT
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXSOF
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXEOF
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXDAT
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXBYTEVALID
add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXLEN
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/GTXCLK
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXCLK
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXCLK
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXEN
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXD
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXER
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXDV
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXD
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXER
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/CRS
add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/COL
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_TX_CLK
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_CLK
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TCG
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RCG
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_TX_VALID
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_VALID
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_READY
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/SIGNAL_DETECT
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RX_SLIP
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/SYNC
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/ANX_STATE
add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RCG_ERROR
add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDC
add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDI
add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDO
add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDOEN
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PCLK
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PRESETN
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PADDR
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PSEL
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PENABLE
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PWRITE
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PWDATA
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PREADY
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PRDATA
add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PSLVERR
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TCLK
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTVALID
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTREADY
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTSOF
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTEOF
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTDATA
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTKEEP
add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTLAST
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ICLK
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITVALID
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITLAST
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITREADY
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITSOF
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITEOF
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITDATA
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITKEEP
add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITUSER
add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/TSM_INTR
add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/TSM_CONTROL
add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/STBP
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
quietly wave cursor active 0
configure wave -namecolwidth 227
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {241501050 ps}

41423
component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v Normal file
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File diff suppressed because it is too large Load Diff

167
component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/include.v Normal file
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//`define MCXMAC_SGMII_ON //Default mode enabled
//`define MCXMAC_SAL_ON //enable SAL support in tsMac
//`define MCXMAC_PTP_ON //enable PTP support in tsMac
//`define MCXMAC_STATS_ON //enable Stats counter module
//`define MCXMAC_WOL_ON //enable WakeOnLane feature of MAC core
//`define MSGMII_PARALLEL_COMMA_ALIGNMENT //enable sgmii-CommaDetect logic
//`define TABITS 12 //mac-fifo TxBuffer addr-width, For depth of the fifo
//`define RABITS 12 //mac-fifo RxBuffer addr-width, For depth of the fifo
//`define MII_PHYID 5'h1E //Address of local MDIO target, for registers in SGMII module
//`define FPGA_TIMING_CLOSER
`define HST_SELECT_MAHBE 3'b011 // HSTADX range 0x180 - 0x19C
`define HST_SELECT_PTP 3'b100 // HSTADX range 0x200 - 0x27F
`define HST_SELECT_EEE 5'b10_100 // HSTADX range 0x280 - 0x29F
`define HST_SELECT_AVB 5'b10_101 // HSTADX range 0x2A0 - 0x
// MAHBe address map
`define ADDR_LEF_TXCTRL 0
`define ADDR_LEF_TXDESC 1
`define ADDR_LEF_TXSTAT 2
`define ADDR_LEF_RXCTRL 3
`define ADDR_LEF_RXDESC 4
`define ADDR_LEF_RXSTAT 5
`define ADDR_LEF_IMASK 6
`define ADDR_LEF_INTR 7
`define ADDR_AVB_TXCTRL 8
`define ADDR_AVB_TXDESC 9
`define ADDR_AVB_TXSTAT 10
`define ADDR_AVB_RXCTRL 11
`define ADDR_AVB_RXDESC 12
`define ADDR_AVB_RXSTAT 13
`define ADDR_AVB_IMASK 14
`define ADDR_AVB_INTR 15
//============================================
// for 1 queue
//============================================
`define ADDR_TX_CMD_REG 0
`define ADDR_TX_CDP_0 1
`define ADDR_TX_STS_REG 2
`define ADDR_RX_CMD_REG 3
`define ADDR_RX_CDP_0 4
`define ADDR_RX_STS_REG 5
// `ifdef SGDMA_AXI_ON
`define ADDR_IMASK 6
`define ADDR_INTR 7
// //`endif
// `ifdef SGDMA_AHB_ON
//`define ADDR_IMASK 6
//`define ADDR_INTR 7
`define H_IDLE 2'b00 // idle transfer
`define H_BUSY 2'b01 // busy transfer
`define H_NONSEQ 2'b10 // non-sequential transfer
`define H_SEQ 2'b11 // sequential transfer
// AHB responses
`define H_OKAY 2'b00 // transfer completed successfully
`define H_ERROR 2'b01 // an error has occurred
`define H_RETRY 2'b10 // transfer cannot be completed yet
`define H_SPLIT 2'b11 // split (not used in this design)
// AHB size encodings
`define H_BYTE 2'b00 // byte wide
`define H_HWORD 2'b01 // half-word (16-bits) wide
`define H_WORD 2'b10 // word (32-bits) wide
`define MAX_PKT_SIZE 1536 // maximum packet size
//======================================================================
// Sibridge Technologies
// Proprietary and Confidential
// All Rights Reserved
//======================================================================
// FILE : $Source: $
// REVISION : $Revision: 46073 $
// LAST UPDATE : $Date: 2024-02-13 12:34:42 +0530 (Tue, 13 Feb 2024) $
//======================================================================
// AUTHOR : Sibridge Technologies
// MODULE NAME : ptp_hstif
// DESCRIPTION : PTP-1588 Module Host Interface which interacts with the AHB
// target Interface. All the Registers and FIFOs are implemented in this module.
//======================================================================
//`define ASYNC_RESET // Type of reset used for FIFO used in ptp_hstif.
//Register Address Map.
`define TS_RD_REG1_ADDR 5'b00000
`define TS_RD_REG2_ADDR 5'b00001
`define TS_RD_REG3_ADDR 5'b00010
`define TS_WR_REG1_ADDR 5'b00011
`define TS_WR_REG2_ADDR 5'b00100
`define TS_WR_REG3_ADDR 5'b00101
`define EVNT1_REG1_ADDR 5'b00110
`define EVNT1_REG2_ADDR 5'b00111
`define EVNT1_REG3_ADDR 5'b01000
`define EVNT2_REG1_ADDR 5'b01001
`define EVNT2_REG2_ADDR 5'b01010
`define EVNT2_REG3_ADDR 5'b01011
`define EVNT1_PLS_WDTH_REG_ADDR 5'b01100
`define EVNT2_PLS_WDTH_REG_ADDR 5'b01101
`define CMD_REG_ADDR 5'b01110
`define CNFG_REG_ADDR 5'b01111
`define INTRPT_REG_ADDR 5'b10000
`define INTRPT_MASK_REG_ADDR 5'b10001
`define RTC_CLK1SEL_REG_ADDR 5'b10010
`define RTC_CLK2SEL_REG_ADDR 5'b10011
`define RX_RCRD_FIFO_ADDR 5'b10100
`define TX_RCRD_FIFO_ADDR 5'b10101
`define ADJST_REG_ADDR 5'b10110
`define LT0L_REG_ADDR 5'b10111
`define LT0M_REG_ADDR 5'b11000
`define LT1L_REG_ADDR 5'b11001
`define LT1M_REG_ADDR 5'b11010
`define LT2L_REG_ADDR 5'b11011
`define LT2M_REG_ADDR 5'b11100
//Register Fields.
`define FLD_INTRP_REG_PPS 0 // Time stamp write interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_MODE_ERR 1 // MODE ERROR interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_TS_WRDONE 2 // TS WRITE DONE interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_TX_RCRDDONE 3 // PTP MSG TRANSMIT DONE interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_RX_RCRDDONE 4 // PTP MSG RECEIVE DONE interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_TX_THSHLD 5 // TX FIFO THRSHLD FULL interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_RX_THSHLD 6 // RX FIFO THRSHLD FULL interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_LTOINT 7 // LATCH 0 interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_LT1INT 8 // LATCH 1 interrupt bit in INTERRUPT REG.
`define FLD_INTRP_REG_LT2INT 9 // LATCH 2 interrupt bit in INTERRUPT REG.
`define FLD_INTRP_MASK_REG_INT_EN 0 // Glabal interupt Mask.
`define FLD_INTRP_MASK_REG_PPS 1 // Time stamp write interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_MODE_ERR 2 // MODE ERROR interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_TS_WRDONE 3 // TS WRITE DONE interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_TX_RCRDDONE 4 // PTP MSG TRANSMIT DONE interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_RX_RCRDDONE 5 // PTP MSG RECEIVE DONE interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_TX_THSHLD 6 // TX FIFO THRSHLD FULL interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_RX_THSHLD 7 // RX FIFO THRSHLD FULL interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_LTOINT 8 // LATCH 0 interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_LT1INT 9 // LATCH 1 interrupt mask bit in INTERRUPT MASK REG.
`define FLD_INTRP_MASK_REG_LT2INT 10 // LATCH 2 interrupt mask bit in INTERRUPT MASK REG.
`define FLD_CNFG_REG_EN 0 // MODULE ENABLE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_RTCEN 1 // RTC ENABLE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_MODE 2 // MODE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_WRCMDEN 3 // TIME STAMP WRITE COMMAND ENABLE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_EVNT1_TRGEN 4 // TIME TRIGGERED EVENT1 ENBALE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_EVNT2_TRGEN 5 // TIME TRIGGERED EVENT2 ENBALE bit in CONFIGURATION REG.
`define FLD_CNFG_REG_RTCFREQ 6 // FREQ of REAL TIME COUNTER. 0 - 125 MHz, 1 - 250 MHz
`define FLD_CNFG_REG_TSWRMODE 7 // MODE OF TIME STAMP WRITE 0 - On Rising Edge of 1Hz CLK, 1 - DONOT wait for 1Hz clock rising edge.
`define FLD_CNFG_REG_DRIFTCRCT 8 // MODE OF TIME STAMP WRITE 0 - On Rising Edge of 1Hz CLK, 1 - DONOT wait for 1Hz clock rising edge.
`define FLD_CNFG_REG_LT0EN 9 // RTC LATCH 0 ENABLE BIT.
`define FLD_CNFG_REG_LT1EN 10 // RTC LATCH 1 ENABLE BIT.
`define FLD_CNFG_REG_LT2EN 11 // RTC LATCH 2 ENABLE BIT.
`define FLD_CNFG_REG_SFTRST 12 // SOFT RESET FOR PTP MODULE.
`define FLD_CMD_REG_TSWRCMD 0 // TIME STAMP WRITE COMMAND bit in COMMAND REG.
`define FLD_ADJST_REG_EN 0 // RTC FREQUENCY ADJUSTMENT ENABLE BIT.
`define FLD_ADJST_REG_VLU_LSB 1 // RTC FREQUENCY ADJUSTMENT VALUE LSB.
`define FLD_ADJST_REG_VLU_MSB 7 // RTC FREQUENCY ADJUSTMENT VALUE MSB.
`define FLD_ADJST_REG_FREQ_LSB 8 // RTC FREQUENCY ADJUSTMENT FREQUENCY VALUE LSB.
`define FLD_ADJST_REG_FREQ_MSB 31 // RTC FREQUENCY ADJUSTMENT FREQUENCY VALUE MSB.
//`define ASYNC_1HZ_CLK // Represents 1Hz clock is asynchronous to RTC clock.

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// **************************************************************************
// Microchip Corporation Proprietary and Confidential
// Copyright 2021 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description : CoreTSE testbench top level module for TBI mode.
//
// SVN Revision Information :
// SVN $Revision : $
// SVN $Date : $
//
// Revision Information :
// Date SAR Description
//
// Notes :
//
// **************************************************************************
`timescale 1 ns / 100 ps
// ==========================================================================
// testbench
// ==========================================================================
module testbench ;
// --------------------------------------------------------------------------
// coreparameters file
`include "coreparameters.v"
// --------------------------------------------------------------------------
// Internal Signal
wire ftclk ;
wire ftrdy ;
wire ftacpt ;
wire ftsof ;
wire fteof ;
wire [31:0] ftdat ;
wire [ 1:0] ftdatnvld ;
wire ftcfrm ;
wire fthwm ;
wire frclk ;
wire frrdy ;
wire fracpt ;
wire frsof ;
wire freof ;
wire [31:0] frdat ;
wire [ 1:0] frdatnvld ;
reg [ 1:0] frdatnvld_axi4s ;
wire mac_tx_clk;
wire mac_rx_clk;
wire axi4s_tclk ;
wire axi4s_ttvalid ;
wire axi4s_ttready ;
wire axi4s_ttsof ;
wire axi4s_tteof ;
wire [31:0] axi4s_ttdata ;
reg [ 3:0] axi4s_ttkeep ;
wire axi4s_ttlast ;
wire axi4s_iclk ;
wire axi4s_itvalid ;
wire axi4s_itready ;
wire axi4s_itsof ;
wire axi4s_iteof ;
wire [31:0] axi4s_itdata ;
reg [ 3:0] axi4s_itkeep ;
wire axi4s_itlast ;
wire [ 7:0] axi4s_ituser ;
wire tx_clk ;
wire rx_clk ;
wire tbi_tx_clk ;
wire tbi_rx_clk ;
wire [ 9:0] tcg_dut ;
wire [ 9:0] rcg_dut ;
wire mdc ;
wire mdi ;
wire mdo ;
wire mdoen ;
wire pclk ;
wire presetn ;
wire [31:0] paddr ;
wire psel ;
wire penable ;
wire pwrite ;
wire [31:0] pwdata ;
wire pready ;
wire [31:0] prdata ;
wire pslverr ;
wire rstbp ;
reg axi4s_itsop_det_en = 1'b1;
// --------------------------------------------------------------------------
// DUT Instantiation
CORETSE
# (
.FAMILY ( FAMILY ) ,
.GMII_TBI ( GMII_TBI ) ,
.PACKET_SIZE ( PACKET_SIZE ) ,
.SAL ( SAL ) ,
.WoL ( WoL ) ,
.STATS ( STATS ) ,
.MDIO_PHYID ( MDIO_PHYID ) ,
.SLIP_ENABLE ( SLIP_ENABLE ) ,
.ECC_ENABLE ( ECC_ENABLE ) ,
.TXRX_INTR_ENABLE ( TXRX_INTR_ENABLE ) ,
.HOST_INTERFACE ( HOST_INTERFACE )
) dut_top (
.MTXCLK ( mac_tx_clk ) ,
.MTXRDY ( ftrdy ) ,
.MTXACPT ( ftacpt ) ,
.MTXSOF ( ftsof ) ,
.MTXEOF ( fteof ) ,
.MTXDAT ( ftdat ) ,
.MTXBYTEVALID ( ftdatnvld ) ,
.MTXCFRM ( ftcfrm ) ,
.MTXHWM ( fthwm ) ,
.MRXCLK ( mac_rx_clk ) ,
.MRXRDY ( frrdy ) ,
.MRXACPT ( fracpt ) ,
.MRXSOF ( frsof ) ,
.MRXEOF ( freof ) ,
.MRXDAT ( frdat ) ,
.MRXBYTEVALID ( frdatnvld ) ,
.AXI4S_TCLK ( axi4s_tclk ) ,
.AXI4S_TTVALID ( axi4s_ttvalid ) ,
.AXI4S_TTREADY ( axi4s_ttready ) ,
//.AXI4S_TTSOF ( axi4s_ttsof ) ,
//.AXI4S_TTEOF ( axi4s_tteof ) ,
.AXI4S_TTDATA ( axi4s_ttdata ) ,
.AXI4S_TTKEEP ( axi4s_ttkeep ) ,
.AXI4S_TTLAST ( axi4s_ttlast ) ,
.AXI4S_ICLK ( axi4s_iclk ) ,
.AXI4S_ITVALID ( axi4s_itvalid ) ,
.AXI4S_ITREADY ( axi4s_itready ) ,
//.AXI4S_ITSOF ( axi4s_itsof ) ,
//.AXI4S_ITEOF ( axi4s_iteof ) ,
.AXI4S_ITDATA ( axi4s_itdata ) ,
.AXI4S_ITKEEP ( axi4s_itkeep ) ,
.AXI4S_ITLAST ( axi4s_itlast ) ,
.AXI4S_ITUSER ( axi4s_ituser ) ,
//.GTXCLK ( ) ,
.TXCLK ( tx_clk ) ,
.RXCLK ( rx_clk ) ,
.TXEN ( ) ,
.TXD ( ) ,
.TXER ( ) ,
.RXDV ( ) ,
.RXD ( ) ,
.RXER ( ) ,
.CRS ( ) ,
.COL ( ) ,
.TBI_TX_CLK ( tbi_tx_clk ) ,
.TBI_RX_CLK ( tbi_rx_clk ) ,
.TCG ( tcg_dut ) ,
.RCG ( rcg_dut ) ,
.TBI_TX_VALID ( ) ,
.TBI_RX_VALID ( ) ,
.TBI_RX_READY ( 1'b1 ) ,
.SIGNAL_DETECT ( 1'b1 ) ,
.RX_SLIP ( ) ,
.SYNC ( ) ,
.ANX_STATE ( ) ,
.RCG_ERROR ( ) ,
.MDC ( mdc ) ,
.MDI ( mdi ) ,
.MDO ( mdo ) ,
.MDOEN ( mdoen ) ,
.PCLK ( pclk ) ,
.PRESETN ( presetn ) ,
.PADDR ( paddr ) ,
.PSEL ( psel ) ,
.PENABLE ( penable ) ,
.PWRITE ( pwrite ) ,
.PWDATA ( pwdata ) ,
.PRDATA ( prdata ) ,
.PSLVERR ( pslverr ) ,
.PREADY ( pready ) ,
.TSM_INTR ( ) ,
.TSM_CONTROL ( ) ,
.FAULT_DET ( )
//.STBP ( rstbp )
) ;
// --------------------------------------------------------------------------
// Frame Generator and Checker Instantiation
generate if (HOST_INTERFACE == 0) begin : NATIVE
CoreTSE_tb
# (
.MDIO_PHYID ( MDIO_PHYID )
) frame_gen_chk (
.ftclk ( ftclk ) ,
.ftrdy ( ftrdy ) ,
.ftacpt ( ftacpt ) ,
.ftsof ( ftsof ) ,
.fteof ( fteof ) ,
.ftdat ( ftdat ) ,
.ftdatnvld ( ftdatnvld ) ,
.fthwm ( fthwm ) ,
.ftcfrm ( ftcfrm ) ,
.frclk ( frclk ) ,
.frrdy ( frrdy ) ,
.fracpt ( fracpt ) ,
.frsof ( frsof ) ,
.freof ( freof ) ,
.frdat ( frdat ) ,
.frdatnvld ( frdatnvld ) ,
.tx_clk ( tx_clk ) ,
.rx_clk ( rx_clk ) ,
.tbi_tx_clk ( tbi_tx_clk ) ,
.tbi_rx_clk ( tbi_rx_clk ) ,
.tcg_dut ( tcg_dut ) ,
.rcg_dut ( rcg_dut ) ,
.mdc ( mdc ) ,
.mdi ( mdi ) ,
.mdo ( mdo ) ,
.mdoen ( mdoen ) ,
.pclk ( pclk ) ,
.presetn ( presetn ) ,
.paddr ( paddr ) ,
.psel ( psel ) ,
.penable ( penable ) ,
.pwrite ( pwrite ) ,
.pwdata ( pwdata ) ,
.pready ( pready ) ,
.prdata ( prdata ) ,
.pslverr ( pslverr ) ,
.rstbp ( rstbp )
) ;
assign mac_tx_clk = ftclk ;
assign mac_rx_clk = frclk ;
assign axi4s_tclk = 0 ;
assign axi4s_ttvalid = ftrdy ;
assign axi4s_ttsof = ftsof ;
assign axi4s_tteof = fteof ;
assign axi4s_ttdata = ftdat ;
assign axi4s_ttkeep = 4'd0 ;
assign axi4s_ttlast = 1'd0 ;
assign axi4s_iclk = 0 ;
assign axi4s_itready = fracpt ;
end else begin : AXI4Stream
CoreTSE_AXI4S_tb
# (
.MDIO_PHYID ( MDIO_PHYID )
) frame_gen_chk (
.ftclk ( ftclk ) ,
.ftrdy ( ftrdy ) ,
.ftacpt ( axi4s_ttready ) ,
.ftsof ( ftsof ) ,
.fteof ( fteof ) ,
.ftdat ( ftdat ) ,
.ftdatnvld ( ftdatnvld ) ,
.fthwm ( fthwm ) ,
.ftcfrm ( ftcfrm ) ,
.frclk ( frclk ) ,
.frrdy ( axi4s_itvalid ) ,
.fracpt ( axi4s_itready ) ,
.frsof ( axi4s_itsof ) ,
.freof ( axi4s_iteof ) ,
.frdat ( axi4s_itdata ) ,
.frdatnvld ( frdatnvld_axi4s ) ,
.tx_clk ( tx_clk ) ,
.rx_clk ( rx_clk ) ,
.tbi_tx_clk ( tbi_tx_clk ) ,
.tbi_rx_clk ( tbi_rx_clk ) ,
.tcg_dut ( tcg_dut ) ,
.rcg_dut ( rcg_dut ) ,
.mdc ( mdc ) ,
.mdi ( mdi ) ,
.mdo ( mdo ) ,
.mdoen ( mdoen ) ,
.pclk ( pclk ) ,
.presetn ( presetn ) ,
.paddr ( paddr ) ,
.psel ( psel ) ,
.penable ( penable ) ,
.pwrite ( pwrite ) ,
.pwdata ( pwdata ) ,
.pready ( pready ) ,
.prdata ( prdata ) ,
.pslverr ( pslverr ) ,
.rstbp ( rstbp )
) ;
assign mac_tx_clk = 0 ;
assign mac_rx_clk = 0 ;
assign axi4s_tclk = ftclk ;
assign axi4s_ttvalid = ftrdy ;
assign axi4s_ttsof = ftsof ;
assign axi4s_tteof = fteof ;
assign axi4s_ttdata = ftdat ;
always @(*) begin
case(ftdatnvld)
4'b0001 : frdatnvld_axi4s = 2'b11;
4'b0011 : frdatnvld_axi4s = 2'b10;
4'b0111 : frdatnvld_axi4s = 2'b01;
default : frdatnvld_axi4s = 2'b00;
endcase
end
always @(*) begin
case(ftdatnvld)
2'b11 : axi4s_ttkeep = 4'b0001;
2'b10 : axi4s_ttkeep = 4'b0011;
2'b01 : axi4s_ttkeep = 4'b0111;
default : axi4s_ttkeep = 4'b1111;
endcase
end
assign axi4s_ttlast = fteof ;
assign axi4s_iclk = frclk ;
assign axi4s_itready = fracpt ;
// Initiator SOF & EOF Generation
always @(posedge axi4s_iclk) begin
if (axi4s_itsof & axi4s_itready)
axi4s_itsop_det_en <= 1'b0;
else if (axi4s_itlast & axi4s_itready)
axi4s_itsop_det_en <= 1'b1;
end
assign axi4s_itsof = axi4s_itsop_det_en & axi4s_itvalid;
assign axi4s_iteof = axi4s_itvalid & axi4s_itlast;
end
endgenerate
endmodule
// --------------------------------------------------------------------------

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component/Actel/DirectCore/CoreAPB3/4.2.100/CoreAPB3.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CoreAPB3</name><vendor>Actel</vendor><library>DirectCore</library><version>4.2.100</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file><file fileid="1"><name>rtl\vlog\amba_bfm\bfm_main.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\amba_bfm\bfm_ahbtoapb.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\amba_bfm\bfm_apb.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\amba_bfm\bfm_apbslaveext.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\vlog\amba_bfm\bfm_apbslave.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\vlog\test\user\testbench.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="7"><name>mti\scripts\wave_user.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="8"><name>mti\scripts\bfmtovec_compile.tcl</name><userFileType>tclSource</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file><file fileid="9"><name>mti\scripts\bfmtovec.exe</name><userFileType>unknown</userFileType></file><file fileid="10"><name>mti\scripts\bfmtovec.lin</name><userFileType>unknown</userFileType></file><file fileid="11"><name>mti\scripts\coreapb3_usertb_master.bfm</name><userFileType>BFM</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="12"><name>rtl\vlog\core\coreapb3.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="13"><name>rtl\vlog\core\coreapb3_muxptob3.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file><file fileid="14"><name>rtl\vlog\core\coreapb3_iaddr_reg.v</name><logicalName>COREAPB3_LIB</logicalName><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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component/Actel/DirectCore/CoreAPB3/4.2.100/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:03 2026
// Parameters for CoreAPB3
//--------------------------------------------------------------------
parameter APB_DWIDTH = 32;
parameter APBSLOT0ENABLE = 1;
parameter APBSLOT1ENABLE = 1;
parameter APBSLOT2ENABLE = 1;
parameter APBSLOT3ENABLE = 0;
parameter APBSLOT4ENABLE = 0;
parameter APBSLOT5ENABLE = 0;
parameter APBSLOT6ENABLE = 0;
parameter APBSLOT7ENABLE = 0;
parameter APBSLOT8ENABLE = 0;
parameter APBSLOT9ENABLE = 0;
parameter APBSLOT10ENABLE = 0;
parameter APBSLOT11ENABLE = 0;
parameter APBSLOT12ENABLE = 0;
parameter APBSLOT13ENABLE = 0;
parameter APBSLOT14ENABLE = 0;
parameter APBSLOT15ENABLE = 0;
parameter FAMILY = 19;
parameter HDL_license = "U";
parameter IADDR_OPTION = 0;
parameter MADDR_BITS = 16;
parameter SC_0 = 0;
parameter SC_1 = 0;
parameter SC_2 = 0;
parameter SC_3 = 0;
parameter SC_4 = 0;
parameter SC_5 = 0;
parameter SC_6 = 0;
parameter SC_7 = 0;
parameter SC_8 = 0;
parameter SC_9 = 0;
parameter SC_10 = 0;
parameter SC_11 = 0;
parameter SC_12 = 0;
parameter SC_13 = 0;
parameter SC_14 = 0;
parameter SC_15 = 0;
parameter testbench = "User";
parameter UPR_NIBBLE_POSN = 6;

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component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.exe Normal file
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component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.lin Normal file
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component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec_compile.tcl Normal file
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### script to compile Actel AMBA BFM source file(s) into vector file(s)
### for simulation
# 05Feb10 Production Release Version 3.0
quietly set chmod_exe "/bin/chmod"
quietly set linux_exe "./bfmtovec.lin"
quietly set windows_exe "./bfmtovec.exe"
quietly set bfm_in1 "./coreapb3_usertb_master.bfm"
quietly set bfm_out1 "./coreapb3_usertb_master.vec"
quietly set log "./bfmtovec_compile.log"
# check OS type and use appropriate executable
if {$tcl_platform(os) == "Linux"} {
echo "--- Using Linux Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe $linux_exe
if {![file executable $bfmtovec_exe]} {
quietly set cmds "exec $chmod_exe +x $bfmtovec_exe"
eval $cmds
}
} else {
echo "--- Using Windows Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe $windows_exe
}
# compile BFM source file(s) into vector output file(s)
echo "--- Compiling Actel DirectCore AMBA BFM source files ..."
quietly set cmd1 "exec $bfmtovec_exe -in $bfm_in1 -out $bfm_out1 > $log"
eval $cmd1
# print contents of log file
quietly set f [open $log]
while {[gets $f line] >= 0} {puts $line}
close $f
echo "--- Done Compiling Actel DirectCore AMBA BFM source files."

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component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/coreapb3_usertb_master.bfm Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: User testbench APB3 master BFM script for CoreAPB3
//
// SVN Revision Information:
// SVN $Revision: 18490 $
// SVN $Date: 2012-11-21 23:33:55 +0530 (Wed, 21 Nov 2012) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ********************************************************************
//-------------------------------------------------------------------------
// Memory Map
// Define name and base address of each resource.
//-------------------------------------------------------------------------
memmap base 0x0
// Global variables to store local copy of testbench parameters and constants
// derived from testbench parameters.
int APB_DWIDTH
int IADDR_OPTION
int APBSLOT0ENABLE
int APBSLOT1ENABLE
int APBSLOT2ENABLE
int APBSLOT3ENABLE
int APBSLOT4ENABLE
int APBSLOT5ENABLE
int APBSLOT6ENABLE
int APBSLOT7ENABLE
int APBSLOT8ENABLE
int APBSLOT9ENABLE
int APBSLOT10ENABLE
int APBSLOT11ENABLE
int APBSLOT12ENABLE
int APBSLOT13ENABLE
int APBSLOT14ENABLE
int APBSLOT15ENABLE
int MADDR_BITS
int UPR_NIBBLE_POSN
int SC_0
int SC_1
int SC_2
int SC_3
int SC_4
int SC_5
int SC_6
int SC_7
int SC_8
int SC_9
int SC_10
int SC_11
int SC_12
int SC_13
int SC_14
int SC_15
int slot_incr
int atmp
int slot_enable[16]
int slot_combine[16]
int iaddr_opt
int i
procedure main
header "CoreAPB3 Test Harness"
debug 3;
// Initialize local variables passed from testbench HDL to the
// ARGVALUE* BFM parameters.
call init_parameter_vars
// Set size of slot increment based on the MADDR_BITS parameter.
if MADDR_BITS == 12
set slot_incr 0x00000100
endif
if MADDR_BITS == 16
set slot_incr 0x00001000
endif
if MADDR_BITS == 20
set slot_incr 0x00010000
endif
if MADDR_BITS == 24
set slot_incr 0x00100000
endif
if MADDR_BITS == 28
set slot_incr 0x01000000
endif
if MADDR_BITS == 32
set slot_incr 0x10000000
endif
// Create vector for slot enable indication.
set slot_enable[0] APBSLOT0ENABLE
set slot_enable[1] APBSLOT1ENABLE
set slot_enable[2] APBSLOT2ENABLE
set slot_enable[3] APBSLOT3ENABLE
set slot_enable[4] APBSLOT4ENABLE
set slot_enable[5] APBSLOT5ENABLE
set slot_enable[6] APBSLOT6ENABLE
set slot_enable[7] APBSLOT7ENABLE
set slot_enable[8] APBSLOT8ENABLE
set slot_enable[9] APBSLOT9ENABLE
set slot_enable[10] APBSLOT10ENABLE
set slot_enable[11] APBSLOT11ENABLE
set slot_enable[12] APBSLOT12ENABLE
set slot_enable[13] APBSLOT13ENABLE
set slot_enable[14] APBSLOT14ENABLE
set slot_enable[15] APBSLOT15ENABLE
// Create vector for slot combined indication
set slot_combine[0] SC_0
set slot_combine[1] SC_1
set slot_combine[2] SC_2
set slot_combine[3] SC_3
set slot_combine[4] SC_4
set slot_combine[5] SC_5
set slot_combine[6] SC_6
set slot_combine[7] SC_7
set slot_combine[8] SC_8
set slot_combine[9] SC_9
set slot_combine[10] SC_10
set slot_combine[11] SC_11
set slot_combine[12] SC_12
set slot_combine[13] SC_13
set slot_combine[14] SC_14
set slot_combine[15] SC_15
loop i 0 15 1
// iaddr_opt is set to (i + 2) because values for IADDR_OPTION relevant
// to slots 0 to 15 run from 2 to 17.
// (IADDR_OPTION = 0 -> indirect addressing not in use.)
// (IADDR_OPTION = 1 -> indirect address sourced from IADDR port.)
set iaddr_opt i + 2
if IADDR_OPTION == iaddr_opt
if APB_DWIDTH == 8
set atmp i * slot_incr + 0x0
write b base atmp 0xdd
set atmp i * slot_incr + 0x4
write b base atmp 0xcc
set atmp i * slot_incr + 0x8
write b base atmp 0xbb
set atmp i * slot_incr + 0xc
write b base atmp 0xaa
set atmp i * slot_incr + 0x0
readcheck b base atmp 0xdd
set atmp i * slot_incr + 0x4
readcheck b base atmp 0xcc
set atmp i * slot_incr + 0x8
readcheck b base atmp 0xbb
set atmp i * slot_incr + 0xc
readcheck b base atmp 0xaa
endif
if APB_DWIDTH == 16
set atmp i * slot_incr + 0x0
write h base atmp 0xccdd
set atmp i * slot_incr + 0x4
write h base atmp 0xaabb
set atmp i * slot_incr + 0x0
readcheck h base atmp 0xccdd
set atmp i * slot_incr + 0x4
readcheck h base atmp 0xaabb
endif
if APB_DWIDTH == 32
set atmp i * slot_incr + 0x0
write w base atmp 0xaabbccdd
set atmp i * slot_incr + 0x0
readcheck w base atmp 0xaabbccdd
endif
else
# Clear write indication bits for all slaves
iowrite 0x0001ffff
iowrite 0x00000000
# Check that bits are clear
iomask 0x00000000 0x0001ffff
if slot_combine[i]
set atmp i * slot_incr + 0x0
write w base atmp 0xa5a5a5a5
readcheck w base atmp 0xa5a5a5a5
# Check that an access to slave 16 (combined slave) has occurred
iotstbit 16 1
# Clear slave access indication bit
iosetbit 16
ioclrbit 16
iotstbit 16 0
# Check that all indication bits are now zero
iomask 0x00000000 0x0001ffff
else
if slot_enable[i]
set atmp i * slot_incr + 0x0
write w base atmp 0x12345678
readcheck w base atmp 0x12345678
# Check that an access to slave i has occurred
iotstbit i 1
# Clear slave access indication bit
iosetbit i
ioclrbit i
iotstbit i 0
# Check that all indication bits are now zero
iomask 0x00000000 0x0001ffff
endif
endif
endif
endloop
return
//-------------------------------------------------------------------------
// Initialize local variables from the ARGVALUE* BFM parameters passed
// down from the testbench HDL.
//-------------------------------------------------------------------------
procedure init_parameter_vars
set APB_DWIDTH $ARGVALUE0
set IADDR_OPTION $ARGVALUE1
set APBSLOT0ENABLE $ARGVALUE2
set APBSLOT1ENABLE $ARGVALUE3
set APBSLOT2ENABLE $ARGVALUE4
set APBSLOT3ENABLE $ARGVALUE5
set APBSLOT4ENABLE $ARGVALUE6
set APBSLOT5ENABLE $ARGVALUE7
set APBSLOT6ENABLE $ARGVALUE8
set APBSLOT7ENABLE $ARGVALUE9
set APBSLOT8ENABLE $ARGVALUE10
set APBSLOT9ENABLE $ARGVALUE11
set APBSLOT10ENABLE $ARGVALUE12
set APBSLOT11ENABLE $ARGVALUE13
set APBSLOT12ENABLE $ARGVALUE14
set APBSLOT13ENABLE $ARGVALUE15
set APBSLOT14ENABLE $ARGVALUE16
set APBSLOT15ENABLE $ARGVALUE17
set MADDR_BITS $ARGVALUE18
set UPR_NIBBLE_POSN $ARGVALUE19
set SC_0 $ARGVALUE20
set SC_1 $ARGVALUE21
set SC_2 $ARGVALUE22
set SC_3 $ARGVALUE23
set SC_4 $ARGVALUE24
set SC_5 $ARGVALUE25
set SC_6 $ARGVALUE26
set SC_7 $ARGVALUE27
set SC_8 $ARGVALUE28
set SC_9 $ARGVALUE29
set SC_10 $ARGVALUE30
set SC_11 $ARGVALUE31
set SC_12 $ARGVALUE32
set SC_13 $ARGVALUE33
set SC_14 $ARGVALUE34
set SC_15 $ARGVALUE35
return

28
component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/wave_user.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {top testbench sigs}
add wave -noupdate -format Logic -radix hexadecimal /testbench/*
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2000574000 ps} 0}
configure wave -namecolwidth 206
configure wave -valuecolwidth 40
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {4830 ns}
# get rid of annoying VHDL Warning messages about arithmetic operands
# and numeric_std warnings ...
quietly set StdArithNoWarnings 1
quietly set NumericStdNoWarnings 1
# this is needed for VHDL sim
when {stopsim == 1} {stop}

816
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_ahbtoapb.v Normal file
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`timescale 1ns/100ps
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 11864 $
// SVN $Date: 2010-01-22 12:21:45 +0530 (Fri, 22 Jan 2010) $
module
COREAPB3_BFMA1l1OII
(
HCLK
,
HRESETN
,
HSEL
,
HWRITE
,
HADDR
,
HWDATA
,
HRDATA
,
HREADYIN
,
HREADYOUT
,
HTRANS
,
HSIZE
,
HBURST
,
HMASTLOCK
,
HPROT
,
HRESP
,
PSEL
,
PADDR
,
PWRITE
,
PENABLE
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
)
;
parameter
TPD
=
1
;
input
HCLK
;
input
HRESETN
;
input
HSEL
;
input
HWRITE
;
input
[
31
:
0
]
HADDR
;
input
[
31
:
0
]
HWDATA
;
output
[
31
:
0
]
HRDATA
;
wire
[
31
:
0
]
HRDATA
;
input
HREADYIN
;
output
HREADYOUT
;
wire
HREADYOUT
;
input
[
1
:
0
]
HTRANS
;
input
[
2
:
0
]
HSIZE
;
input
[
2
:
0
]
HBURST
;
input
HMASTLOCK
;
input
[
3
:
0
]
HPROT
;
output
HRESP
;
wire
HRESP
;
output
[
15
:
0
]
PSEL
;
wire
[
15
:
0
]
PSEL
;
output
[
31
:
0
]
PADDR
;
wire
[
31
:
0
]
PADDR
;
output
PWRITE
;
wire
PWRITE
;
output
PENABLE
;
wire
PENABLE
;
output
[
31
:
0
]
PWDATA
;
wire
[
31
:
0
]
PWDATA
;
input
[
31
:
0
]
PRDATA
;
input
PREADY
;
input
PSLVERR
;
parameter
[
1
:
0
]
BFMA1OOIII
=
0
;
parameter
[
1
:
0
]
BFMA1IOIII
=
1
;
parameter
[
1
:
0
]
BFMA1lOIII
=
2
;
parameter
[
1
:
0
]
BFMA1OIIII
=
3
;
reg
[
1
:
0
]
BFMA1IIIII
;
reg
BFMA1lIIII
;
reg
BFMA1OlIII
;
reg
[
15
:
0
]
BFMA1IlIII
;
reg
[
31
:
0
]
BFMA1llIII
;
reg
BFMA1O0III
;
reg
BFMA1I0III
;
reg
[
31
:
0
]
BFMA1l0III
;
wire
[
31
:
0
]
BFMA1O1III
;
reg
BFMA1I1III
;
reg
BFMA1l1III
;
always
@
(
posedge
HCLK
or
negedge
HRESETN
)
begin
if
(
HRESETN
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1OlIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
end
else
begin
BFMA1OlIII
<=
1
'b
0
;
BFMA1lIIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
case
(
BFMA1IIIII
)
BFMA1OOIII
:
begin
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1l0III
<=
HWDATA
;
BFMA1I0III
<=
1
'b
0
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
else
begin
BFMA1lIIII
<=
1
'b
1
;
end
end
BFMA1IOIII
:
begin
BFMA1I0III
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1lOIII
;
end
BFMA1lOIII
:
begin
if
(
PREADY
==
1
'b
1
)
begin
BFMA1I0III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
if
(
PSLVERR
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
end
else
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OIIII
;
end
end
end
BFMA1OIIII
:
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OOIII
;
end
endcase
if
(
BFMA1I1III
==
1
'b
1
)
begin
BFMA1l0III
<=
HWDATA
;
end
end
end
always
@
(
BFMA1llIII
or
BFMA1l1III
)
begin
BFMA1IlIII
<=
{
16
{
1
'b
0
}
}
;
if
(
BFMA1l1III
==
1
'b
1
)
begin
begin
:
BFMA1IO10
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1IlIII
[
BFMA1I0I0
]
<=
(
BFMA1llIII
[
27
:
24
]
==
BFMA1I0I0
)
;
end
end
end
end
assign
BFMA1O1III
=
(
BFMA1I1III
==
1
'b
1
)
?
HWDATA
:
BFMA1l0III
;
assign
#
TPD
HRDATA
=
PRDATA
;
assign
#
TPD
HREADYOUT
=
BFMA1lIIII
|
(
PREADY
&
BFMA1l1III
&
BFMA1I0III
&
~
PSLVERR
)
;
assign
#
TPD
HRESP
=
BFMA1OlIII
;
assign
#
TPD
PSEL
=
BFMA1IlIII
;
assign
#
TPD
PADDR
=
BFMA1llIII
;
assign
#
TPD
PWRITE
=
BFMA1O0III
;
assign
#
TPD
PENABLE
=
BFMA1I0III
;
assign
#
TPD
PWDATA
=
BFMA1O1III
;
endmodule

1434
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apb.v Normal file
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component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslave.v Normal file
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6140
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslaveext.v Normal file
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20978
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_main.v Normal file
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606
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v Normal file
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@@ -0,0 +1,606 @@
// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2011 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreAPB3 - AMBA APB3 bus fabric
// Instantiates the following modules:
// COREAPB3_MUXPTOB3
// coreapb3_iaddr_reg
//
// Revision Information:
// Date Description
// ---- -----------------------------------------
// 05Feb10 Production Release Version 3.0
//
// SVN Revision Information:
// SVN $Revision: 23124 $
// SVN $Date: 2014-07-17 20:01:27 +0530 (Thu, 17 Jul 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4" (tabs used throughout file)
//
// *********************************************************************/
`timescale 1ns/1ps
module CoreAPB3 #(
parameter [5:0]APB_DWIDTH = 32,
parameter IADDR_OPTION = 0,
parameter [0:0]APBSLOT0ENABLE = 1,
parameter [0:0]APBSLOT1ENABLE = 1,
parameter [0:0]APBSLOT2ENABLE = 1,
parameter [0:0]APBSLOT3ENABLE = 1,
parameter [0:0]APBSLOT4ENABLE = 1,
parameter [0:0]APBSLOT5ENABLE = 1,
parameter [0:0]APBSLOT6ENABLE = 1,
parameter [0:0]APBSLOT7ENABLE = 1,
parameter [0:0]APBSLOT8ENABLE = 1,
parameter [0:0]APBSLOT9ENABLE = 1,
parameter [0:0]APBSLOT10ENABLE = 1,
parameter [0:0]APBSLOT11ENABLE = 1,
parameter [0:0]APBSLOT12ENABLE = 1,
parameter [0:0]APBSLOT13ENABLE = 1,
parameter [0:0]APBSLOT14ENABLE = 1,
parameter [0:0]APBSLOT15ENABLE = 1,
parameter [0:0]SC_0 = 0,
parameter [0:0]SC_1 = 0,
parameter [0:0]SC_2 = 0,
parameter [0:0]SC_3 = 0,
parameter [0:0]SC_4 = 0,
parameter [0:0]SC_5 = 0,
parameter [0:0]SC_6 = 0,
parameter [0:0]SC_7 = 0,
parameter [0:0]SC_8 = 0,
parameter [0:0]SC_9 = 0,
parameter [0:0]SC_10 = 0,
parameter [0:0]SC_11 = 0,
parameter [0:0]SC_12 = 0,
parameter [0:0]SC_13 = 0,
parameter [0:0]SC_14 = 0,
parameter [0:0]SC_15 = 0,
parameter [5:0]MADDR_BITS = 32,
parameter [3:0]UPR_NIBBLE_POSN = 7,
parameter FAMILY = 19,
parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0
)
(
input [31:0] IADDR,
input PRESETN,
input PCLK,
input [31:0] PADDR,
input PWRITE,
input PENABLE,
input PSEL,
input [31:0] PWDATA,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output reg [31:0] PADDRS,
output wire PWRITES,
output wire PENABLES,
output wire [31:0] PWDATAS,
output wire PSELS0,
output wire PSELS1,
output wire PSELS2,
output wire PSELS3,
output wire PSELS4,
output wire PSELS5,
output wire PSELS6,
output wire PSELS7,
output wire PSELS8,
output wire PSELS9,
output wire PSELS10,
output wire PSELS11,
output wire PSELS12,
output wire PSELS13,
output wire PSELS14,
output wire PSELS15,
output reg PSELS16,
input [31:0] PRDATAS0,
input [31:0] PRDATAS1,
input [31:0] PRDATAS2,
input [31:0] PRDATAS3,
input [31:0] PRDATAS4,
input [31:0] PRDATAS5,
input [31:0] PRDATAS6,
input [31:0] PRDATAS7,
input [31:0] PRDATAS8,
input [31:0] PRDATAS9,
input [31:0] PRDATAS10,
input [31:0] PRDATAS11,
input [31:0] PRDATAS12,
input [31:0] PRDATAS13,
input [31:0] PRDATAS14,
input [31:0] PRDATAS15,
input [31:0] PRDATAS16,
input PREADYS0,
input PREADYS1,
input PREADYS2,
input PREADYS3,
input PREADYS4,
input PREADYS5,
input PREADYS6,
input PREADYS7,
input PREADYS8,
input PREADYS9,
input PREADYS10,
input PREADYS11,
input PREADYS12,
input PREADYS13,
input PREADYS14,
input PREADYS15,
input PREADYS16,
input PSLVERRS0,
input PSLVERRS1,
input PSLVERRS2,
input PSLVERRS3,
input PSLVERRS4,
input PSLVERRS5,
input PSLVERRS6,
input PSLVERRS7,
input PSLVERRS8,
input PSLVERRS9,
input PSLVERRS10,
input PSLVERRS11,
input PSLVERRS12,
input PSLVERRS13,
input PSLVERRS14,
input PSLVERRS15,
input PSLVERRS16
);
localparam IADDR_NOTINUSE = 0;
localparam IADDR_EXTERNAL = 1;
localparam IADDR_SLOT0 = 2;
localparam IADDR_SLOT1 = 3;
localparam IADDR_SLOT2 = 4;
localparam IADDR_SLOT3 = 5;
localparam IADDR_SLOT4 = 6;
localparam IADDR_SLOT5 = 7;
localparam IADDR_SLOT6 = 8;
localparam IADDR_SLOT7 = 9;
localparam IADDR_SLOT8 = 10;
localparam IADDR_SLOT9 = 11;
localparam IADDR_SLOT10 = 12;
localparam IADDR_SLOT11 = 13;
localparam IADDR_SLOT12 = 14;
localparam IADDR_SLOT13 = 15;
localparam IADDR_SLOT14 = 16;
localparam IADDR_SLOT15 = 17;
localparam [15:0] SL0 = (APBSLOT0ENABLE || SC_0 || (IADDR_OPTION == IADDR_SLOT0 )) * (2**0);
localparam [15:0] SL1 = (APBSLOT1ENABLE || SC_1 || (IADDR_OPTION == IADDR_SLOT1 )) * (2**1);
localparam [15:0] SL2 = (APBSLOT2ENABLE || SC_2 || (IADDR_OPTION == IADDR_SLOT2 )) * (2**2);
localparam [15:0] SL3 = (APBSLOT3ENABLE || SC_3 || (IADDR_OPTION == IADDR_SLOT3 )) * (2**3);
localparam [15:0] SL4 = (APBSLOT4ENABLE || SC_4 || (IADDR_OPTION == IADDR_SLOT4 )) * (2**4);
localparam [15:0] SL5 = (APBSLOT5ENABLE || SC_5 || (IADDR_OPTION == IADDR_SLOT5 )) * (2**5);
localparam [15:0] SL6 = (APBSLOT6ENABLE || SC_6 || (IADDR_OPTION == IADDR_SLOT6 )) * (2**6);
localparam [15:0] SL7 = (APBSLOT7ENABLE || SC_7 || (IADDR_OPTION == IADDR_SLOT7 )) * (2**7);
localparam [15:0] SL8 = (APBSLOT8ENABLE || SC_8 || (IADDR_OPTION == IADDR_SLOT8 )) * (2**8);
localparam [15:0] SL9 = (APBSLOT9ENABLE || SC_9 || (IADDR_OPTION == IADDR_SLOT9 )) * (2**9);
localparam [15:0] SL10 = (APBSLOT10ENABLE || SC_10 || (IADDR_OPTION == IADDR_SLOT10)) * (2**10);
localparam [15:0] SL11 = (APBSLOT11ENABLE || SC_11 || (IADDR_OPTION == IADDR_SLOT11)) * (2**11);
localparam [15:0] SL12 = (APBSLOT12ENABLE || SC_12 || (IADDR_OPTION == IADDR_SLOT12)) * (2**12);
localparam [15:0] SL13 = (APBSLOT13ENABLE || SC_13 || (IADDR_OPTION == IADDR_SLOT13)) * (2**13);
localparam [15:0] SL14 = (APBSLOT14ENABLE || SC_14 || (IADDR_OPTION == IADDR_SLOT14)) * (2**14);
localparam [15:0] SL15 = (APBSLOT15ENABLE || SC_15 || (IADDR_OPTION == IADDR_SLOT15)) * (2**15);
localparam [15:0]SC = {
SC_15,
SC_14,
SC_13,
SC_12,
SC_11,
SC_10,
SC_9,
SC_8,
SC_7,
SC_6,
SC_5,
SC_4,
SC_3,
SC_2,
SC_1,
SC_0
};
localparam [15:0] SC_qual = SC
& {
(IADDR_OPTION != IADDR_SLOT15),
(IADDR_OPTION != IADDR_SLOT14),
(IADDR_OPTION != IADDR_SLOT13),
(IADDR_OPTION != IADDR_SLOT12),
(IADDR_OPTION != IADDR_SLOT11),
(IADDR_OPTION != IADDR_SLOT10),
(IADDR_OPTION != IADDR_SLOT9 ),
(IADDR_OPTION != IADDR_SLOT8 ),
(IADDR_OPTION != IADDR_SLOT7 ),
(IADDR_OPTION != IADDR_SLOT6 ),
(IADDR_OPTION != IADDR_SLOT5 ),
(IADDR_OPTION != IADDR_SLOT4 ),
(IADDR_OPTION != IADDR_SLOT3 ),
(IADDR_OPTION != IADDR_SLOT2 ),
(IADDR_OPTION != IADDR_SLOT1 ),
(IADDR_OPTION != IADDR_SLOT0 )
};
wire [31:0] iPRDATA;
wire [31:0] iPRDATAS0;
wire [31:0] iPRDATAS1;
wire [31:0] iPRDATAS2;
wire [31:0] iPRDATAS3;
wire [31:0] iPRDATAS4;
wire [31:0] iPRDATAS5;
wire [31:0] iPRDATAS6;
wire [31:0] iPRDATAS7;
wire [31:0] iPRDATAS8;
wire [31:0] iPRDATAS9;
wire [31:0] iPRDATAS10;
wire [31:0] iPRDATAS11;
wire [31:0] iPRDATAS12;
wire [31:0] iPRDATAS13;
wire [31:0] iPRDATAS14;
wire [31:0] iPRDATAS15;
wire [31:0] IA_PRDATA;
wire [15:0] iPREADYS;
wire [15:0] iPSLVERRS;
reg [15:0] iPSELS_raw;
reg [15:0] iPSELS;
wire [3:0] slotSel;
wire [31:0] IADDR_REG;
wire [31:0] infill;
wire [31:0] infill_upr;
wire [31:0] TieOffLo32;
wire TieOffHi;
wire TieOffLo;
assign TieOffLo32 = 32'b0;
assign TieOffHi = 1'b1;
assign TieOffLo = 1'b0;
assign PWRITES = PWRITE;
assign PENABLES = PENABLE;
assign PWDATAS = PWDATA[31:0];
assign slotSel = PADDR[MADDR_BITS-1:MADDR_BITS-4];
always @ (*)
begin
if (PSEL == 1'b1)
begin
case (slotSel)
4'b0000: iPSELS_raw = SL0;
4'b0001: iPSELS_raw = SL1;
4'b0010: iPSELS_raw = SL2;
4'b0011: iPSELS_raw = SL3;
4'b0100: iPSELS_raw = SL4;
4'b0101: iPSELS_raw = SL5;
4'b0110: iPSELS_raw = SL6;
4'b0111: iPSELS_raw = SL7;
4'b1000: iPSELS_raw = SL8;
4'b1001: iPSELS_raw = SL9;
4'b1010: iPSELS_raw = SL10;
4'b1011: iPSELS_raw = SL11;
4'b1100: iPSELS_raw = SL12;
4'b1101: iPSELS_raw = SL13;
4'b1110: iPSELS_raw = SL14;
4'b1111: iPSELS_raw = SL15;
default: iPSELS_raw = 16'b0000000000000000;
endcase
iPSELS[15:0] = iPSELS_raw & ~SC_qual;
PSELS16 = |(iPSELS_raw & SC_qual);
end
else
begin
iPSELS = 16'b0000000000000000;
PSELS16 = 1'b0;
end
end
generate
begin: g_tieoffs
if (IADDR_OPTION == IADDR_SLOT0) assign iPRDATAS0[31:0] = IA_PRDATA[31:0];
else if (APBSLOT0ENABLE) assign iPRDATAS0[31:0] = PRDATAS0[31:0];
else assign iPRDATAS0[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT1) assign iPRDATAS1[31:0] = IA_PRDATA[31:0];
else if (APBSLOT1ENABLE) assign iPRDATAS1[31:0] = PRDATAS1[31:0];
else assign iPRDATAS1[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT2) assign iPRDATAS2[31:0] = IA_PRDATA[31:0];
else if (APBSLOT2ENABLE) assign iPRDATAS2[31:0] = PRDATAS2[31:0];
else assign iPRDATAS2[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT3) assign iPRDATAS3[31:0] = IA_PRDATA[31:0];
else if (APBSLOT3ENABLE) assign iPRDATAS3[31:0] = PRDATAS3[31:0];
else assign iPRDATAS3[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT4) assign iPRDATAS4[31:0] = IA_PRDATA[31:0];
else if (APBSLOT4ENABLE) assign iPRDATAS4[31:0] = PRDATAS4[31:0];
else assign iPRDATAS4[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT5) assign iPRDATAS5[31:0] = IA_PRDATA[31:0];
else if (APBSLOT5ENABLE) assign iPRDATAS5[31:0] = PRDATAS5[31:0];
else assign iPRDATAS5[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT6) assign iPRDATAS6[31:0] = IA_PRDATA[31:0];
else if (APBSLOT6ENABLE) assign iPRDATAS6[31:0] = PRDATAS6[31:0];
else assign iPRDATAS6[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT7) assign iPRDATAS7[31:0] = IA_PRDATA[31:0];
else if (APBSLOT7ENABLE) assign iPRDATAS7[31:0] = PRDATAS7[31:0];
else assign iPRDATAS7[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT8) assign iPRDATAS8[31:0] = IA_PRDATA[31:0];
else if (APBSLOT8ENABLE) assign iPRDATAS8[31:0] = PRDATAS8[31:0];
else assign iPRDATAS8[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT9) assign iPRDATAS9[31:0] = IA_PRDATA[31:0];
else if (APBSLOT9ENABLE) assign iPRDATAS9[31:0] = PRDATAS9[31:0];
else assign iPRDATAS9[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT10) assign iPRDATAS10[31:0] = IA_PRDATA[31:0];
else if (APBSLOT10ENABLE) assign iPRDATAS10[31:0] = PRDATAS10[31:0];
else assign iPRDATAS10[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT11) assign iPRDATAS11[31:0] = IA_PRDATA[31:0];
else if (APBSLOT11ENABLE) assign iPRDATAS11[31:0] = PRDATAS11[31:0];
else assign iPRDATAS11[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT12) assign iPRDATAS12[31:0] = IA_PRDATA[31:0];
else if (APBSLOT12ENABLE) assign iPRDATAS12[31:0] = PRDATAS12[31:0];
else assign iPRDATAS12[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT13) assign iPRDATAS13[31:0] = IA_PRDATA[31:0];
else if (APBSLOT13ENABLE) assign iPRDATAS13[31:0] = PRDATAS13[31:0];
else assign iPRDATAS13[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT14) assign iPRDATAS14[31:0] = IA_PRDATA[31:0];
else if (APBSLOT14ENABLE) assign iPRDATAS14[31:0] = PRDATAS14[31:0];
else assign iPRDATAS14[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT15) assign iPRDATAS15[31:0] = IA_PRDATA[31:0];
else if (APBSLOT15ENABLE) assign iPRDATAS15[31:0] = PRDATAS15[31:0];
else assign iPRDATAS15[31:0] = TieOffLo32;
if (IADDR_OPTION == IADDR_SLOT0) assign iPREADYS[ 0] = TieOffHi;
else if (APBSLOT0ENABLE) assign iPREADYS[ 0] = PREADYS0;
else assign iPREADYS[ 0] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT1) assign iPREADYS[ 1] = TieOffHi;
else if (APBSLOT1ENABLE) assign iPREADYS[ 1] = PREADYS1;
else assign iPREADYS[ 1] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT2) assign iPREADYS[ 2] = TieOffHi;
else if (APBSLOT2ENABLE) assign iPREADYS[ 2] = PREADYS2;
else assign iPREADYS[ 2] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT3) assign iPREADYS[ 3] = TieOffHi;
else if (APBSLOT3ENABLE) assign iPREADYS[ 3] = PREADYS3;
else assign iPREADYS[ 3] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT4) assign iPREADYS[ 4] = TieOffHi;
else if (APBSLOT4ENABLE) assign iPREADYS[ 4] = PREADYS4;
else assign iPREADYS[ 4] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT5) assign iPREADYS[ 5] = TieOffHi;
else if (APBSLOT5ENABLE) assign iPREADYS[ 5] = PREADYS5;
else assign iPREADYS[ 5] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT6) assign iPREADYS[ 6] = TieOffHi;
else if (APBSLOT6ENABLE) assign iPREADYS[ 6] = PREADYS6;
else assign iPREADYS[ 6] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT7) assign iPREADYS[ 7] = TieOffHi;
else if (APBSLOT7ENABLE) assign iPREADYS[ 7] = PREADYS7;
else assign iPREADYS[ 7] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT8) assign iPREADYS[ 8] = TieOffHi;
else if (APBSLOT8ENABLE) assign iPREADYS[ 8] = PREADYS8;
else assign iPREADYS[ 8] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT9) assign iPREADYS[ 9] = TieOffHi;
else if (APBSLOT9ENABLE) assign iPREADYS[ 9] = PREADYS9;
else assign iPREADYS[ 9] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT10) assign iPREADYS[10] = TieOffHi;
else if (APBSLOT10ENABLE) assign iPREADYS[10] = PREADYS10;
else assign iPREADYS[10] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT11) assign iPREADYS[11] = TieOffHi;
else if (APBSLOT11ENABLE) assign iPREADYS[11] = PREADYS11;
else assign iPREADYS[11] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT12) assign iPREADYS[12] = TieOffHi;
else if (APBSLOT12ENABLE) assign iPREADYS[12] = PREADYS12;
else assign iPREADYS[12] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT13) assign iPREADYS[13] = TieOffHi;
else if (APBSLOT13ENABLE) assign iPREADYS[13] = PREADYS13;
else assign iPREADYS[13] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT14) assign iPREADYS[14] = TieOffHi;
else if (APBSLOT14ENABLE) assign iPREADYS[14] = PREADYS14;
else assign iPREADYS[14] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT15) assign iPREADYS[15] = TieOffHi;
else if (APBSLOT15ENABLE) assign iPREADYS[15] = PREADYS15;
else assign iPREADYS[15] = TieOffHi;
if (IADDR_OPTION == IADDR_SLOT0) assign iPSLVERRS[ 0] = TieOffLo;
else if (APBSLOT0ENABLE) assign iPSLVERRS[ 0] = PSLVERRS0;
else assign iPSLVERRS[ 0] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT1) assign iPSLVERRS[ 1] = TieOffLo;
else if (APBSLOT1ENABLE) assign iPSLVERRS[ 1] = PSLVERRS1;
else assign iPSLVERRS[ 1] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT2) assign iPSLVERRS[ 2] = TieOffLo;
else if (APBSLOT2ENABLE) assign iPSLVERRS[ 2] = PSLVERRS2;
else assign iPSLVERRS[ 2] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT3) assign iPSLVERRS[ 3] = TieOffLo;
else if (APBSLOT3ENABLE) assign iPSLVERRS[ 3] = PSLVERRS3;
else assign iPSLVERRS[ 3] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT4) assign iPSLVERRS[ 4] = TieOffLo;
else if (APBSLOT4ENABLE) assign iPSLVERRS[ 4] = PSLVERRS4;
else assign iPSLVERRS[ 4] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT5) assign iPSLVERRS[ 5] = TieOffLo;
else if (APBSLOT5ENABLE) assign iPSLVERRS[ 5] = PSLVERRS5;
else assign iPSLVERRS[ 5] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT6) assign iPSLVERRS[ 6] = TieOffLo;
else if (APBSLOT6ENABLE) assign iPSLVERRS[ 6] = PSLVERRS6;
else assign iPSLVERRS[ 6] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT7) assign iPSLVERRS[ 7] = TieOffLo;
else if (APBSLOT7ENABLE) assign iPSLVERRS[ 7] = PSLVERRS7;
else assign iPSLVERRS[ 7] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT8) assign iPSLVERRS[ 8] = TieOffLo;
else if (APBSLOT8ENABLE) assign iPSLVERRS[ 8] = PSLVERRS8;
else assign iPSLVERRS[ 8] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT9) assign iPSLVERRS[ 9] = TieOffLo;
else if (APBSLOT9ENABLE) assign iPSLVERRS[ 9] = PSLVERRS9;
else assign iPSLVERRS[ 9] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT10) assign iPSLVERRS[10] = TieOffLo;
else if (APBSLOT10ENABLE) assign iPSLVERRS[10] = PSLVERRS10;
else assign iPSLVERRS[10] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT11) assign iPSLVERRS[11] = TieOffLo;
else if (APBSLOT11ENABLE) assign iPSLVERRS[11] = PSLVERRS11;
else assign iPSLVERRS[11] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT12) assign iPSLVERRS[12] = TieOffLo;
else if (APBSLOT12ENABLE) assign iPSLVERRS[12] = PSLVERRS12;
else assign iPSLVERRS[12] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT13) assign iPSLVERRS[13] = TieOffLo;
else if (APBSLOT13ENABLE) assign iPSLVERRS[13] = PSLVERRS13;
else assign iPSLVERRS[13] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT14) assign iPSLVERRS[14] = TieOffLo;
else if (APBSLOT14ENABLE) assign iPSLVERRS[14] = PSLVERRS14;
else assign iPSLVERRS[14] = TieOffLo;
if (IADDR_OPTION == IADDR_SLOT15) assign iPSLVERRS[15] = TieOffLo;
else if (APBSLOT15ENABLE) assign iPSLVERRS[15] = PSLVERRS15;
else assign iPSLVERRS[15] = TieOffLo;
end
endgenerate
COREAPB3_MUXPTOB3 u_mux_p_to_b3 (
.PSELS ({PSELS16, iPSELS[15:0]}),
.PRDATAS0 (iPRDATAS0[31:0]),
.PRDATAS1 (iPRDATAS1[31:0]),
.PRDATAS2 (iPRDATAS2[31:0]),
.PRDATAS3 (iPRDATAS3[31:0]),
.PRDATAS4 (iPRDATAS4[31:0]),
.PRDATAS5 (iPRDATAS5[31:0]),
.PRDATAS6 (iPRDATAS6[31:0]),
.PRDATAS7 (iPRDATAS7[31:0]),
.PRDATAS8 (iPRDATAS8[31:0]),
.PRDATAS9 (iPRDATAS9[31:0]),
.PRDATAS10 (iPRDATAS10[31:0]),
.PRDATAS11 (iPRDATAS11[31:0]),
.PRDATAS12 (iPRDATAS12[31:0]),
.PRDATAS13 (iPRDATAS13[31:0]),
.PRDATAS14 (iPRDATAS14[31:0]),
.PRDATAS15 (iPRDATAS15[31:0]),
.PRDATAS16 (PRDATAS16[31:0]),
.PREADYS ({PREADYS16, iPREADYS[15:0]}),
.PSLVERRS ({PSLVERRS16, iPSLVERRS[15:0]}),
.PREADY (PREADY),
.PSLVERR (PSLVERR),
.PRDATA (iPRDATA[31:0])
);
assign PRDATA[31:0] = iPRDATA[31:0];
generate
begin: g_psels
if (IADDR_OPTION == IADDR_SLOT0 ) assign PSELS0 = 1'b0; else assign PSELS0 = iPSELS[ 0];
if (IADDR_OPTION == IADDR_SLOT1 ) assign PSELS1 = 1'b0; else assign PSELS1 = iPSELS[ 1];
if (IADDR_OPTION == IADDR_SLOT2 ) assign PSELS2 = 1'b0; else assign PSELS2 = iPSELS[ 2];
if (IADDR_OPTION == IADDR_SLOT3 ) assign PSELS3 = 1'b0; else assign PSELS3 = iPSELS[ 3];
if (IADDR_OPTION == IADDR_SLOT4 ) assign PSELS4 = 1'b0; else assign PSELS4 = iPSELS[ 4];
if (IADDR_OPTION == IADDR_SLOT5 ) assign PSELS5 = 1'b0; else assign PSELS5 = iPSELS[ 5];
if (IADDR_OPTION == IADDR_SLOT6 ) assign PSELS6 = 1'b0; else assign PSELS6 = iPSELS[ 6];
if (IADDR_OPTION == IADDR_SLOT7 ) assign PSELS7 = 1'b0; else assign PSELS7 = iPSELS[ 7];
if (IADDR_OPTION == IADDR_SLOT8 ) assign PSELS8 = 1'b0; else assign PSELS8 = iPSELS[ 8];
if (IADDR_OPTION == IADDR_SLOT9 ) assign PSELS9 = 1'b0; else assign PSELS9 = iPSELS[ 9];
if (IADDR_OPTION == IADDR_SLOT10) assign PSELS10 = 1'b0; else assign PSELS10 = iPSELS[10];
if (IADDR_OPTION == IADDR_SLOT11) assign PSELS11 = 1'b0; else assign PSELS11 = iPSELS[11];
if (IADDR_OPTION == IADDR_SLOT12) assign PSELS12 = 1'b0; else assign PSELS12 = iPSELS[12];
if (IADDR_OPTION == IADDR_SLOT13) assign PSELS13 = 1'b0; else assign PSELS13 = iPSELS[13];
if (IADDR_OPTION == IADDR_SLOT14) assign PSELS14 = 1'b0; else assign PSELS14 = iPSELS[14];
if (IADDR_OPTION == IADDR_SLOT15) assign PSELS15 = 1'b0; else assign PSELS15 = iPSELS[15];
end
endgenerate
generate
begin: g_iaddr_reg
if (IADDR_OPTION == IADDR_NOTINUSE) assign IADDR_REG = 32'b0;
if (IADDR_OPTION == IADDR_EXTERNAL) assign IADDR_REG = 32'b0;
if (IADDR_OPTION == IADDR_SLOT0 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 0], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT1 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 1], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT2 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 2], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT3 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 3], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT4 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 4], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT5 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 5], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT6 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 6], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT7 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 7], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT8 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 8], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT9 ) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[ 9], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT10) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[10], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT11) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[11], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT12) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[12], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT13) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[13], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT14) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[14], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
if (IADDR_OPTION == IADDR_SLOT15) coreapb3_iaddr_reg #(SYNC_RESET, APB_DWIDTH, MADDR_BITS) iaddr_reg (PCLK, PRESETN, PENABLE, iPSELS[15], PADDR, PWRITE, PWDATA, IA_PRDATA, IADDR_REG);
end
endgenerate
generate
begin
if (IADDR_OPTION == IADDR_NOTINUSE)
begin
assign infill_upr = PADDR;
assign infill = 32'b0;
end
else if (IADDR_OPTION == IADDR_EXTERNAL)
begin
assign infill_upr = IADDR;
assign infill = IADDR;
end
else
begin
assign infill_upr = IADDR_REG;
assign infill = IADDR_REG;
end
end
endgenerate
generate if (MADDR_BITS == 12)
begin
always @(*)
case (UPR_NIBBLE_POSN)
2: PADDRS = {infill_upr[31:12], PADDR[11:0]};
3: PADDRS = {infill_upr[31:16], PADDR[11:8], infill[11:8], PADDR[7:0]};
4: PADDRS = {infill_upr[31:20], PADDR[11:8], infill[15:8], PADDR[7:0]};
5: PADDRS = {infill_upr[31:24], PADDR[11:8], infill[19:8], PADDR[7:0]};
6: PADDRS = {infill_upr[31:28], PADDR[11:8], infill[23:8], PADDR[7:0]};
7: PADDRS = { PADDR[11:8], infill[27:8], PADDR[7:0]};
8: PADDRS = { infill[31:8], PADDR[7:0]};
endcase
end
endgenerate
generate if (MADDR_BITS == 16)
begin
always @(*)
case (UPR_NIBBLE_POSN)
2: PADDRS = {infill_upr[31:16], PADDR[15:0]};
3: PADDRS = {infill_upr[31:16], PADDR[15:0]};
4: PADDRS = {infill_upr[31:20], PADDR[15:12], infill[15:12], PADDR[11:0]};
5: PADDRS = {infill_upr[31:24], PADDR[15:12], infill[19:12], PADDR[11:0]};
6: PADDRS = {infill_upr[31:28], PADDR[15:12], infill[23:12], PADDR[11:0]};
7: PADDRS = { PADDR[15:12], infill[27:12], PADDR[11:0]};
8: PADDRS = { infill[31:12], PADDR[11:0]};
endcase
end
endgenerate
generate if (MADDR_BITS == 20)
begin
always @(*)
case (UPR_NIBBLE_POSN)
2: PADDRS = {infill_upr[31:20], PADDR[19:0]};
3: PADDRS = {infill_upr[31:20], PADDR[19:0]};
4: PADDRS = {infill_upr[31:20], PADDR[19:0]};
5: PADDRS = {infill_upr[31:24], PADDR[19:16], infill[19:16], PADDR[15:0]};
6: PADDRS = {infill_upr[31:28], PADDR[19:16], infill[23:16], PADDR[15:0]};
7: PADDRS = { PADDR[19:16], infill[27:16], PADDR[15:0]};
8: PADDRS = { infill[31:16], PADDR[15:0]};
endcase
end
endgenerate
generate if (MADDR_BITS == 24)
begin
always @(*)
case (UPR_NIBBLE_POSN)
2: PADDRS = {infill_upr[31:24], PADDR[23:0]};
3: PADDRS = {infill_upr[31:24], PADDR[23:0]};
4: PADDRS = {infill_upr[31:24], PADDR[23:0]};
5: PADDRS = {infill_upr[31:24], PADDR[23:0]};
6: PADDRS = {infill_upr[31:28], PADDR[23:20], infill[23:20], PADDR[19:0]};
7: PADDRS = { PADDR[23:20], infill[27:20], PADDR[19:0]};
8: PADDRS = { infill[31:20], PADDR[19:0]};
endcase
end
endgenerate
generate if (MADDR_BITS == 28)
begin
always @(*)
case (UPR_NIBBLE_POSN)
2: PADDRS = {infill_upr[31:28], PADDR[27:0]};
3: PADDRS = {infill_upr[31:28], PADDR[27:0]};
4: PADDRS = {infill_upr[31:28], PADDR[27:0]};
5: PADDRS = {infill_upr[31:28], PADDR[27:0]};
6: PADDRS = {infill_upr[31:28], PADDR[27:0]};
7: PADDRS = { PADDR[27:24], infill[27:24], PADDR[23:0]};
8: PADDRS = { infill[31:24], PADDR[23:0]};
endcase
end
endgenerate
generate if (MADDR_BITS == 32)
begin
always @(*)
PADDRS = PADDR[31:0];
end
endgenerate
endmodule

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// ********************************************************************/
// Microsemi Corporation Proprietary and Confidential
// Copyright 2011 Microsemi Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: Implements indirect address registers for CoreAPB3
//
//
// SVN Revision Information:
// SVN $Revision: 24054 $
// SVN $Date: 2014-12-08 16:13:40 +0530 (Mon, 08 Dec 2014) $
//
//
// Notes:
// 1. best viewed with tabstops set to "4" (tabs used throughout file)
//
// *********************************************************************/
module coreapb3_iaddr_reg (
PCLK,
PRESETN,
PENABLE,
PSEL,
PADDR,
PWRITE,
PWDATA,
PRDATA,
IADDR_REG
);
parameter SYNC_RESET = 0;
parameter [5:0] APB_DWIDTH = 32;
parameter [5:0] MADDR_BITS = 32;
input PCLK;
input PRESETN;
input PENABLE;
input PSEL;
input [31:0] PADDR;
input PWRITE;
input [31:0] PWDATA;
output [31:0] PRDATA;
output [31:0] IADDR_REG;
reg [31:0] PRDATA;
reg [31:0] IADDR_REG;
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : PRESETN;
assign sresetn = (SYNC_RESET==1) ? PRESETN : 1'b1;
always @(posedge PCLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
IADDR_REG <= 32'b0;
end
else
begin
if (PSEL && PENABLE && PWRITE)
begin
if (APB_DWIDTH == 32)
begin
if (PADDR[MADDR_BITS-4-1:0] == {MADDR_BITS-4{1'b0}})
begin
IADDR_REG <= PWDATA;
end
end
if (APB_DWIDTH == 16)
begin
if (PADDR[MADDR_BITS-4-1:4] == {MADDR_BITS-4-4{1'b0}})
begin
case (PADDR[3:0])
4'b0000: IADDR_REG[15: 0] <= PWDATA[15:0];
4'b0100: IADDR_REG[31:16] <= PWDATA[15:0];
4'b1000: IADDR_REG <= IADDR_REG;
4'b1100: IADDR_REG <= IADDR_REG;
endcase
end
end
if (APB_DWIDTH == 8)
begin
if (PADDR[MADDR_BITS-4-1:4] == {MADDR_BITS-4-4{1'b0}})
begin
case (PADDR[3:0])
4'b0000: IADDR_REG[ 7: 0] <= PWDATA[7:0];
4'b0100: IADDR_REG[15: 8] <= PWDATA[7:0];
4'b1000: IADDR_REG[23:16] <= PWDATA[7:0];
4'b1100: IADDR_REG[31:24] <= PWDATA[7:0];
endcase
end
end
end
end
end
always @(*)
begin
PRDATA = 32'b0;
if (APB_DWIDTH == 32)
begin
if (PADDR[MADDR_BITS-4-1:0] == {MADDR_BITS-4{1'b0}})
begin
PRDATA = IADDR_REG;
end
end
if (APB_DWIDTH == 16)
begin
if (PADDR[MADDR_BITS-4-1:4] == {MADDR_BITS-4-4{1'b0}})
begin
case (PADDR[3:0])
4'b0000: PRDATA[15:0] = IADDR_REG[15: 0];
4'b0100: PRDATA[15:0] = IADDR_REG[31:16];
4'b1000: PRDATA = 32'b0;
4'b1100: PRDATA = 32'b0;
endcase
end
end
if (APB_DWIDTH == 8)
begin
if (PADDR[MADDR_BITS-4-1:4] == {MADDR_BITS-4-4{1'b0}})
begin
case (PADDR[3:0])
4'b0000: PRDATA[7:0] = IADDR_REG[ 7: 0];
4'b0100: PRDATA[7:0] = IADDR_REG[15: 8];
4'b1000: PRDATA[7:0] = IADDR_REG[23:16];
4'b1100: PRDATA[7:0] = IADDR_REG[31:24];
endcase
end
end
end
endmodule

171
component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v Normal file
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// ********************************************************************/
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: COREAPB3_MUXPTOB3 - Central mux - signals from peripherals to
// bridge. Stand-alone module to allow ease of removal if an
// alternative interconnection scheme is to be used.
//
// Revision Information:
// Date Description
// ---- -----------------------------------------
// 05Feb10 Production Release Version 3.0
//
// SVN Revision Information:
// SVN $Revision: 16159 $
// SVN $Date: 2012-01-14 01:45:19 +0530 (Sat, 14 Jan 2012) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4" (tabs used throughout file)
//
// *********************************************************************/
`timescale 1ns/1ps
module COREAPB3_MUXPTOB3 (
input [16:0] PSELS,
input [31:0] PRDATAS0,
input [31:0] PRDATAS1,
input [31:0] PRDATAS2,
input [31:0] PRDATAS3,
input [31:0] PRDATAS4,
input [31:0] PRDATAS5,
input [31:0] PRDATAS6,
input [31:0] PRDATAS7,
input [31:0] PRDATAS8,
input [31:0] PRDATAS9,
input [31:0] PRDATAS10,
input [31:0] PRDATAS11,
input [31:0] PRDATAS12,
input [31:0] PRDATAS13,
input [31:0] PRDATAS14,
input [31:0] PRDATAS15,
input [31:0] PRDATAS16,
input [16:0] PREADYS,
input [16:0] PSLVERRS,
output wire PREADY,
output wire PSLVERR,
output wire [31:0] PRDATA
);
localparam [4:0]PSEL_SL0 = 5'b00000;
localparam [4:0]PSEL_SL1 = 5'b00001;
localparam [4:0]PSEL_SL2 = 5'b00010;
localparam [4:0]PSEL_SL3 = 5'b00011;
localparam [4:0]PSEL_SL4 = 5'b00100;
localparam [4:0]PSEL_SL5 = 5'b00101;
localparam [4:0]PSEL_SL6 = 5'b00110;
localparam [4:0]PSEL_SL7 = 5'b00111;
localparam [4:0]PSEL_SL8 = 5'b01000;
localparam [4:0]PSEL_SL9 = 5'b01001;
localparam [4:0]PSEL_SL10 = 5'b01010;
localparam [4:0]PSEL_SL11 = 5'b01011;
localparam [4:0]PSEL_SL12 = 5'b01100;
localparam [4:0]PSEL_SL13 = 5'b01101;
localparam [4:0]PSEL_SL14 = 5'b01110;
localparam [4:0]PSEL_SL15 = 5'b01111;
localparam [4:0]PSEL_SL16 = 5'b10000;
reg iPREADY;
reg iPSLVERR;
reg [31:0] iPRDATA;
wire [4:0] PSELSBUS;
wire [31:0] lo32;
assign lo32 = 32'b0;
assign PSELSBUS[4] = PSELS[16];
assign PSELSBUS[3] = PSELS[15] | PSELS[14] | PSELS[13] | PSELS[12] |
PSELS[11] | PSELS[10] | PSELS[9] | PSELS[8];
assign PSELSBUS[2] = PSELS[15] | PSELS[14] | PSELS[13] | PSELS[12] |
PSELS[7] | PSELS[6] | PSELS[5] | PSELS[4];
assign PSELSBUS[1] = PSELS[15] | PSELS[14] | PSELS[11] | PSELS[10] |
PSELS[7] | PSELS[6] | PSELS[3] | PSELS[2];
assign PSELSBUS[0] = PSELS[15] | PSELS[13] | PSELS[11] | PSELS[9] |
PSELS[7] | PSELS[5] | PSELS[3] | PSELS[1];
always @ (*)
begin
case (PSELSBUS)
PSEL_SL0 :
if (PSELS[0])
iPRDATA[31:0] = PRDATAS0[31:0];
else
iPRDATA[31:0] = lo32[31:0];
PSEL_SL1 : iPRDATA[31:0] = PRDATAS1[31:0];
PSEL_SL2 : iPRDATA[31:0] = PRDATAS2[31:0];
PSEL_SL3 : iPRDATA[31:0] = PRDATAS3[31:0];
PSEL_SL4 : iPRDATA[31:0] = PRDATAS4[31:0];
PSEL_SL5 : iPRDATA[31:0] = PRDATAS5[31:0];
PSEL_SL6 : iPRDATA[31:0] = PRDATAS6[31:0];
PSEL_SL7 : iPRDATA[31:0] = PRDATAS7[31:0];
PSEL_SL8 : iPRDATA[31:0] = PRDATAS8[31:0];
PSEL_SL9 : iPRDATA[31:0] = PRDATAS9[31:0];
PSEL_SL10 : iPRDATA[31:0] = PRDATAS10[31:0];
PSEL_SL11 : iPRDATA[31:0] = PRDATAS11[31:0];
PSEL_SL12 : iPRDATA[31:0] = PRDATAS12[31:0];
PSEL_SL13 : iPRDATA[31:0] = PRDATAS13[31:0];
PSEL_SL14 : iPRDATA[31:0] = PRDATAS14[31:0];
PSEL_SL15 : iPRDATA[31:0] = PRDATAS15[31:0];
PSEL_SL16 : iPRDATA[31:0] = PRDATAS16[31:0];
default : iPRDATA[31:0] = lo32[31:0];
endcase
end
always @ (*)
begin
case (PSELSBUS)
PSEL_SL0 :
if (PSELS[0])
iPREADY = PREADYS[0];
else
iPREADY = 1'b1;
PSEL_SL1 : iPREADY = PREADYS[1];
PSEL_SL2 : iPREADY = PREADYS[2];
PSEL_SL3 : iPREADY = PREADYS[3];
PSEL_SL4 : iPREADY = PREADYS[4];
PSEL_SL5 : iPREADY = PREADYS[5];
PSEL_SL6 : iPREADY = PREADYS[6];
PSEL_SL7 : iPREADY = PREADYS[7];
PSEL_SL8 : iPREADY = PREADYS[8];
PSEL_SL9 : iPREADY = PREADYS[9];
PSEL_SL10 : iPREADY = PREADYS[10];
PSEL_SL11 : iPREADY = PREADYS[11];
PSEL_SL12 : iPREADY = PREADYS[12];
PSEL_SL13 : iPREADY = PREADYS[13];
PSEL_SL14 : iPREADY = PREADYS[14];
PSEL_SL15 : iPREADY = PREADYS[15];
PSEL_SL16 : iPREADY = PREADYS[16];
default : iPREADY = 1'b1;
endcase
end
always @ (*)
begin
case (PSELSBUS)
PSEL_SL0 :
if (PSELS[0])
iPSLVERR = PSLVERRS[0];
else
iPSLVERR = 1'b0;
PSEL_SL1 : iPSLVERR = PSLVERRS[1];
PSEL_SL2 : iPSLVERR = PSLVERRS[2];
PSEL_SL3 : iPSLVERR = PSLVERRS[3];
PSEL_SL4 : iPSLVERR = PSLVERRS[4];
PSEL_SL5 : iPSLVERR = PSLVERRS[5];
PSEL_SL6 : iPSLVERR = PSLVERRS[6];
PSEL_SL7 : iPSLVERR = PSLVERRS[7];
PSEL_SL8 : iPSLVERR = PSLVERRS[8];
PSEL_SL9 : iPSLVERR = PSLVERRS[9];
PSEL_SL10 : iPSLVERR = PSLVERRS[10];
PSEL_SL11 : iPSLVERR = PSLVERRS[11];
PSEL_SL12 : iPSLVERR = PSLVERRS[12];
PSEL_SL13 : iPSLVERR = PSLVERRS[13];
PSEL_SL14 : iPSLVERR = PSLVERRS[14];
PSEL_SL15 : iPSLVERR = PSLVERRS[15];
PSEL_SL16 : iPSLVERR = PSLVERRS[16];
default : iPSLVERR = 1'b0;
endcase
end
assign PREADY = iPREADY;
assign PSLVERR = iPSLVERR;
assign PRDATA = iPRDATA[31:0];
endmodule

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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2010 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: User Testbench for CoreAPB3
//
// Revision Information:
// Date Description
// 05Feb10 Production Release Version 3.0
//
// SVN Revision Information:
// SVN $Revision: 23124 $
// SVN $Date: 2014-07-17 20:01:27 +0530 (Thu, 17 Jul 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4"
// 2. Most of the behavior is driven from the BFM script for the APB
// master. Consult the Actel AMBA BFM documentation for more information.
//
// History: 1/28/10 - TFB created
//
// *********************************************************************
`timescale 1ns/1ps
module testbench ();
// location of this can be overridden at compile time (+incdir switch)
`include "../../../../coreparameters.v"
//`include "coreparameters.v"
//parameter RANGESIZE = 268435456;
//parameter IADDR_ENABLE = 0;
//-----------------------------------------------------------------------------
// top-level parameters
//-----------------------------------------------------------------------------
// vector files for driving the APB master BFM
// NOTE: location of the following files can be overridden at run time
parameter APB_MASTER_VECTFILE = "coreapb3_usertb_master.vec";
// APB Master System Clock cycle (in ns)
parameter APB_MASTER_CLK_CYCLE = 30;
// propagation delay in ns
parameter TPD = 3;
// BFM slave constants
//localparam SLAVE_AWIDTH = 8;
localparam SLAVE_AWIDTH = 8;
localparam SLAVE_DEPTH = (2**SLAVE_AWIDTH) ;
// System signals
reg SYSRSTN_apb;
reg SYSCLK_apb;
// APB master bfm signals
wire PCLK;
wire PRESETN;
wire [31:0] PADDR_apb_bfm_wide;
//wire [23:0] PADDR;
wire [31:0] PADDR;
wire [15:0] PSEL_apb_bfm_wide;
wire PSEL;
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA_apb_bfm_wide;
//wire [APB_DWIDTH-1:0] PWDATA;
wire [31:0] PWDATA;
// input to bfm
wire [31:0] PRDATA_apb_bfm_wide;
//wire [APB_DWIDTH-1:0] PRDATA;
wire [31:0] PRDATA;
wire PREADY;
wire PSLVERR;
// input to APB bfm
//wire [31:0] GP_IN_apb_bfm=32'b0;
//wire [31:0] GP_OUT_apb_bfm;
wire FINISHED_apb_bfm;
wire FAILED_apb_bfm;
// misc. signals
wire [255:0] GND256=256'b0;
wire [31:0] GND32=32'b0;
wire GND1=1'b0;
reg stopsim=0;
//wire [23:0] PADDRS;
wire [31:0] PADDRS;
//wire [(((1-IADDR_ENABLE)*24)+((IADDR_ENABLE)*32))-1:0] PADDRS0;
wire PWRITES;
wire PENABLES;
//wire [APB_DWIDTH-1:0] PWDATAS;
wire [31:0] PWDATAS;
wire PSELS0;
wire PSELS1;
wire PSELS2;
wire PSELS3;
wire PSELS4;
wire PSELS5;
wire PSELS6;
wire PSELS7;
wire PSELS8;
wire PSELS9;
wire PSELS10;
wire PSELS11;
wire PSELS12;
wire PSELS13;
wire PSELS14;
wire PSELS15;
wire PSELS16;
/*
wire [APB_DWIDTH-1:0] PRDATAS0;
wire [APB_DWIDTH-1:0] PRDATAS1;
wire [APB_DWIDTH-1:0] PRDATAS2;
wire [APB_DWIDTH-1:0] PRDATAS3;
wire [APB_DWIDTH-1:0] PRDATAS4;
wire [APB_DWIDTH-1:0] PRDATAS5;
wire [APB_DWIDTH-1:0] PRDATAS6;
wire [APB_DWIDTH-1:0] PRDATAS7;
wire [APB_DWIDTH-1:0] PRDATAS8;
wire [APB_DWIDTH-1:0] PRDATAS9;
wire [APB_DWIDTH-1:0] PRDATAS10;
wire [APB_DWIDTH-1:0] PRDATAS11;
wire [APB_DWIDTH-1:0] PRDATAS12;
wire [APB_DWIDTH-1:0] PRDATAS13;
wire [APB_DWIDTH-1:0] PRDATAS14;
wire [APB_DWIDTH-1:0] PRDATAS15;
*/
wire [31:0] PRDATAS0;
wire [31:0] PRDATAS1;
wire [31:0] PRDATAS2;
wire [31:0] PRDATAS3;
wire [31:0] PRDATAS4;
wire [31:0] PRDATAS5;
wire [31:0] PRDATAS6;
wire [31:0] PRDATAS7;
wire [31:0] PRDATAS8;
wire [31:0] PRDATAS9;
wire [31:0] PRDATAS10;
wire [31:0] PRDATAS11;
wire [31:0] PRDATAS12;
wire [31:0] PRDATAS13;
wire [31:0] PRDATAS14;
wire [31:0] PRDATAS15;
wire [31:0] PRDATAS16;
wire PREADYS0;
wire PREADYS1;
wire PREADYS2;
wire PREADYS3;
wire PREADYS4;
wire PREADYS5;
wire PREADYS6;
wire PREADYS7;
wire PREADYS8;
wire PREADYS9;
wire PREADYS10;
wire PREADYS11;
wire PREADYS12;
wire PREADYS13;
wire PREADYS14;
wire PREADYS15;
wire PREADYS16;
wire PSLVERRS0;
wire PSLVERRS1;
wire PSLVERRS2;
wire PSLVERRS3;
wire PSLVERRS4;
wire PSLVERRS5;
wire PSLVERRS6;
wire PSLVERRS7;
wire PSLVERRS8;
wire PSLVERRS9;
wire PSLVERRS10;
wire PSLVERRS11;
wire PSLVERRS12;
wire PSLVERRS13;
wire PSLVERRS14;
wire PSLVERRS15;
wire PSLVERRS16;
/*
wire [31:0] PWDATAS_apb_slave;
wire [31:0] PRDATAS0_apb_slave;
wire [31:0] PRDATAS1_apb_slave;
wire [31:0] PRDATAS2_apb_slave;
wire [31:0] PRDATAS3_apb_slave;
wire [31:0] PRDATAS4_apb_slave;
wire [31:0] PRDATAS5_apb_slave;
wire [31:0] PRDATAS6_apb_slave;
wire [31:0] PRDATAS7_apb_slave;
wire [31:0] PRDATAS8_apb_slave;
wire [31:0] PRDATAS9_apb_slave;
wire [31:0] PRDATAS10_apb_slave;
wire [31:0] PRDATAS11_apb_slave;
wire [31:0] PRDATAS12_apb_slave;
wire [31:0] PRDATAS13_apb_slave;
wire [31:0] PRDATAS14_apb_slave;
wire [31:0] PRDATAS15_apb_slave;
*/
reg s0_write;
reg s1_write;
reg s2_write;
reg s3_write;
reg s4_write;
reg s5_write;
reg s6_write;
reg s7_write;
reg s8_write;
reg s9_write;
reg s10_write;
reg s11_write;
reg s12_write;
reg s13_write;
reg s14_write;
reg s15_write;
reg s16_write;
// BFM GPIO
wire [31:0] GP_OUT;
wire [31:0] GP_IN;
// instantiate DUT(s)
CoreAPB3 #(
.APB_DWIDTH(APB_DWIDTH),
.IADDR_OPTION(IADDR_OPTION),
.APBSLOT0ENABLE(APBSLOT0ENABLE),
.APBSLOT1ENABLE(APBSLOT1ENABLE),
.APBSLOT2ENABLE(APBSLOT2ENABLE),
.APBSLOT3ENABLE(APBSLOT3ENABLE),
.APBSLOT4ENABLE(APBSLOT4ENABLE),
.APBSLOT5ENABLE(APBSLOT5ENABLE),
.APBSLOT6ENABLE(APBSLOT6ENABLE),
.APBSLOT7ENABLE(APBSLOT7ENABLE),
.APBSLOT8ENABLE(APBSLOT8ENABLE),
.APBSLOT9ENABLE(APBSLOT9ENABLE),
.APBSLOT10ENABLE(APBSLOT10ENABLE),
.APBSLOT11ENABLE(APBSLOT11ENABLE),
.APBSLOT12ENABLE(APBSLOT12ENABLE),
.APBSLOT13ENABLE(APBSLOT13ENABLE),
.APBSLOT14ENABLE(APBSLOT14ENABLE),
.APBSLOT15ENABLE(APBSLOT15ENABLE),
.MADDR_BITS(MADDR_BITS),
.UPR_NIBBLE_POSN(UPR_NIBBLE_POSN),
.SC_0 (SC_0 ),
.SC_1 (SC_1 ),
.SC_2 (SC_2 ),
.SC_3 (SC_3 ),
.SC_4 (SC_4 ),
.SC_5 (SC_5 ),
.SC_6 (SC_6 ),
.SC_7 (SC_7 ),
.SC_8 (SC_8 ),
.SC_9 (SC_9 ),
.SC_10 (SC_10),
.SC_11 (SC_11),
.SC_12 (SC_12),
.SC_13 (SC_13),
.SC_14 (SC_14),
.SC_15 (SC_15),
.FAMILY (FAMILY)
) u_coreapb3 (
.IADDR(32'b0),
.PRESETN(PRESETN),
.PCLK(PCLK),
.PADDR(PADDR),
.PWRITE(PWRITE),
.PENABLE(PENABLE),
.PSEL(PSEL),
.PWDATA(PWDATA),
.PRDATA(PRDATA),
.PREADY(PREADY),
.PSLVERR(PSLVERR),
.PADDRS(PADDRS),
.PWRITES(PWRITES),
.PENABLES(PENABLES),
.PWDATAS(PWDATAS),
.PSELS0(PSELS0),
.PSELS1(PSELS1),
.PSELS2(PSELS2),
.PSELS3(PSELS3),
.PSELS4(PSELS4),
.PSELS5(PSELS5),
.PSELS6(PSELS6),
.PSELS7(PSELS7),
.PSELS8(PSELS8),
.PSELS9(PSELS9),
.PSELS10(PSELS10),
.PSELS11(PSELS11),
.PSELS12(PSELS12),
.PSELS13(PSELS13),
.PSELS14(PSELS14),
.PSELS15(PSELS15),
.PSELS16(PSELS16),
.PRDATAS0(PRDATAS0),
.PRDATAS1(PRDATAS1),
.PRDATAS2(PRDATAS2),
.PRDATAS3(PRDATAS3),
.PRDATAS4(PRDATAS4),
.PRDATAS5(PRDATAS5),
.PRDATAS6(PRDATAS6),
.PRDATAS7(PRDATAS7),
.PRDATAS8(PRDATAS8),
.PRDATAS9(PRDATAS9),
.PRDATAS10(PRDATAS10),
.PRDATAS11(PRDATAS11),
.PRDATAS12(PRDATAS12),
.PRDATAS13(PRDATAS13),
.PRDATAS14(PRDATAS14),
.PRDATAS15(PRDATAS15),
.PRDATAS16(PRDATAS16),
.PREADYS0(PREADYS0),
.PREADYS1(PREADYS1),
.PREADYS2(PREADYS2),
.PREADYS3(PREADYS3),
.PREADYS4(PREADYS4),
.PREADYS5(PREADYS5),
.PREADYS6(PREADYS6),
.PREADYS7(PREADYS7),
.PREADYS8(PREADYS8),
.PREADYS9(PREADYS9),
.PREADYS10(PREADYS10),
.PREADYS11(PREADYS11),
.PREADYS12(PREADYS12),
.PREADYS13(PREADYS13),
.PREADYS14(PREADYS14),
.PREADYS15(PREADYS15),
.PREADYS16(PREADYS16),
.PSLVERRS0(PSLVERRS0),
.PSLVERRS1(PSLVERRS1),
.PSLVERRS2(PSLVERRS2),
.PSLVERRS3(PSLVERRS3),
.PSLVERRS4(PSLVERRS4),
.PSLVERRS5(PSLVERRS5),
.PSLVERRS6(PSLVERRS6),
.PSLVERRS7(PSLVERRS7),
.PSLVERRS8(PSLVERRS8),
.PSLVERRS9(PSLVERRS9),
.PSLVERRS10(PSLVERRS10),
.PSLVERRS11(PSLVERRS11),
.PSLVERRS12(PSLVERRS12),
.PSLVERRS13(PSLVERRS13),
.PSLVERRS14(PSLVERRS14),
.PSLVERRS15(PSLVERRS15),
.PSLVERRS16(PSLVERRS16)
);
//assign PRDATA_apb_bfm_wide = {{32-APB_DWIDTH{1'b0}},PRDATA};
assign PRDATA_apb_bfm_wide = PRDATA;
// BFM monitors various signals
assign GP_IN = {
15'b0, // 31:17
s16_write, // 16
s15_write, // 15
s14_write, // 14
s13_write, // 13
s12_write, // 12
s11_write, // 11
s10_write, // 10
s9_write, // 9
s8_write, // 8
s7_write, // 7
s6_write, // 6
s5_write, // 5
s4_write, // 4
s3_write, // 3
s2_write, // 2
s1_write, // 1
s0_write // 0
};
// instantiate APB Master BFM to drive APB mirrored master port
COREAPB3_BFM_APB #(
.VECTFILE(APB_MASTER_VECTFILE),
.TPD(TPD),
// passing testbench parameters to BFM ARGVALUE* parameters
.ARGVALUE0 (APB_DWIDTH),
.ARGVALUE1 (IADDR_OPTION),
.ARGVALUE2 (APBSLOT0ENABLE),
.ARGVALUE3 (APBSLOT1ENABLE),
.ARGVALUE4 (APBSLOT2ENABLE),
.ARGVALUE5 (APBSLOT3ENABLE),
.ARGVALUE6 (APBSLOT4ENABLE),
.ARGVALUE7 (APBSLOT5ENABLE),
.ARGVALUE8 (APBSLOT6ENABLE),
.ARGVALUE9 (APBSLOT7ENABLE),
.ARGVALUE10 (APBSLOT8ENABLE),
.ARGVALUE11 (APBSLOT9ENABLE),
.ARGVALUE12 (APBSLOT10ENABLE),
.ARGVALUE13 (APBSLOT11ENABLE),
.ARGVALUE14 (APBSLOT12ENABLE),
.ARGVALUE15 (APBSLOT13ENABLE),
.ARGVALUE16 (APBSLOT14ENABLE),
.ARGVALUE17 (APBSLOT15ENABLE),
.ARGVALUE18 (MADDR_BITS),
.ARGVALUE19 (UPR_NIBBLE_POSN),
.ARGVALUE20 (SC_0),
.ARGVALUE21 (SC_1),
.ARGVALUE22 (SC_2),
.ARGVALUE23 (SC_3),
.ARGVALUE24 (SC_4),
.ARGVALUE25 (SC_5),
.ARGVALUE26 (SC_6),
.ARGVALUE27 (SC_7),
.ARGVALUE28 (SC_8),
.ARGVALUE29 (SC_9),
.ARGVALUE30 (SC_10),
.ARGVALUE31 (SC_11),
.ARGVALUE32 (SC_12),
.ARGVALUE33 (SC_13),
.ARGVALUE34 (SC_14),
.ARGVALUE35 (SC_15)
) u_apb_master (
.SYSCLK(SYSCLK_apb),
.SYSRSTN(SYSRSTN_apb),
.PCLK(PCLK),
.PRESETN(PRESETN),
.PADDR(PADDR_apb_bfm_wide),
.PSEL(PSEL_apb_bfm_wide),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA_apb_bfm_wide),
.PRDATA(PRDATA_apb_bfm_wide),
.PREADY(PREADY),
.PSLVERR(PSLVERR),
.INTERRUPT(GND256),
.GP_OUT(GP_OUT),
.GP_IN(GP_IN),
.EXT_WR(),
.EXT_RD(),
.EXT_ADDR(),
.EXT_DATA(),
.EXT_WAIT(GND1),
.FINISHED(FINISHED_apb_bfm),
.FAILED(FAILED_apb_bfm)
);
//assign PADDR = PADDR_apb_bfm_wide[23:0];
assign PADDR = PADDR_apb_bfm_wide[31:0];
//assign PSEL = PSEL_apb_bfm_wide[0];
assign PSEL = PSEL_apb_bfm_wide[ 0] ||
PSEL_apb_bfm_wide[ 1] ||
PSEL_apb_bfm_wide[ 2] ||
PSEL_apb_bfm_wide[ 3] ||
PSEL_apb_bfm_wide[ 4] ||
PSEL_apb_bfm_wide[ 5] ||
PSEL_apb_bfm_wide[ 6] ||
PSEL_apb_bfm_wide[ 7] ||
PSEL_apb_bfm_wide[ 8] ||
PSEL_apb_bfm_wide[ 9] ||
PSEL_apb_bfm_wide[10] ||
PSEL_apb_bfm_wide[11] ||
PSEL_apb_bfm_wide[12] ||
PSEL_apb_bfm_wide[13] ||
PSEL_apb_bfm_wide[14] ||
PSEL_apb_bfm_wide[15] ;
//assign PWDATA = PWDATA_apb_bfm_wide[APB_DWIDTH-1:0];
assign PWDATA = PWDATA_apb_bfm_wide;
// BFM slave 0
COREAPB3_BFM_APBSLAVE#(
//.AWIDTH(((1-IADDR_ENABLE)*SLAVE_AWIDTH)+((IADDR_ENABLE)*28)),
//.DEPTH(((1-IADDR_ENABLE)*SLAVE_DEPTH)+((IADDR_ENABLE)*(2**28))),
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave0 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS0),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
//.PADDR(PADDRS0[(((1-IADDR_ENABLE)*SLAVE_AWIDTH)+((IADDR_ENABLE)*28)-1):0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS0),
.PREADY(PREADYS0),
.PSLVERR(PSLVERRS0)
);
// BFM slave 1
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave1 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS1),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS1),
.PREADY(PREADYS1),
.PSLVERR(PSLVERRS1)
);
// BFM slave 2
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave2 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS2),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS2),
.PREADY(PREADYS2),
.PSLVERR(PSLVERRS2)
);
// BFM slave 3
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave3 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS3),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS3),
.PREADY(PREADYS3),
.PSLVERR(PSLVERRS3)
);
// BFM slave 4
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave4 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS4),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS4),
.PREADY(PREADYS4),
.PSLVERR(PSLVERRS4)
);
// BFM slave 5
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave5 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS5),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS5),
.PREADY(PREADYS5),
.PSLVERR(PSLVERRS5)
);
// BFM slave 6
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave6 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS6),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS6),
.PREADY(PREADYS6),
.PSLVERR(PSLVERRS6)
);
// BFM slave 7
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave7 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS7),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS7),
.PREADY(PREADYS7),
.PSLVERR(PSLVERRS7)
);
// BFM slave 8
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave8 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS8),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS8),
.PREADY(PREADYS8),
.PSLVERR(PSLVERRS8)
);
// BFM slave 9
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave9 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS9),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS9),
.PREADY(PREADYS9),
.PSLVERR(PSLVERRS9)
);
// BFM slave 10
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave10 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS10),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS10),
.PREADY(PREADYS10),
.PSLVERR(PSLVERRS10)
);
// BFM slave 11
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave11 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS11),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS11),
.PREADY(PREADYS11),
.PSLVERR(PSLVERRS11)
);
// BFM slave 12
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave12 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS12),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS12),
.PREADY(PREADYS12),
.PSLVERR(PSLVERRS12)
);
// BFM slave 13
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave13 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS13),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS13),
.PREADY(PREADYS13),
.PSLVERR(PSLVERRS13)
);
// BFM slave 14
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave14 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS14),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS14),
.PREADY(PREADYS14),
.PSLVERR(PSLVERRS14)
);
// BFM slave 15
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave15 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS15),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS15),
.PREADY(PREADYS15),
.PSLVERR(PSLVERRS15)
);
// BFM slave 16 (combined region)
COREAPB3_BFM_APBSLAVE #(
.AWIDTH(SLAVE_AWIDTH),
.DEPTH(SLAVE_DEPTH),
.DWIDTH(32),
.TPD(TPD)
) u_slave16 (
.PCLK(PCLK),
.PRESETN(PRESETN),
.PENABLE(PENABLES),
.PWRITE(PWRITES),
.PSEL(PSELS16),
.PADDR(PADDRS[SLAVE_AWIDTH-1:0]),
.PWDATA(PWDATAS),
.PRDATA(PRDATAS16),
.PREADY(PREADYS16),
.PSLVERR(PSLVERRS16)
);
/*
// adjust busses to widths
assign PWDATAS_apb_slave = {{32-APB_DWIDTH{1'b0}},PWDATAS[APB_DWIDTH-1:0]};
assign PRDATAS0 = PRDATAS0_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS1 = PRDATAS1_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS2 = PRDATAS2_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS3 = PRDATAS3_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS4 = PRDATAS4_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS5 = PRDATAS5_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS6 = PRDATAS6_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS7 = PRDATAS7_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS8 = PRDATAS8_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS9 = PRDATAS9_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS10 = PRDATAS10_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS11 = PRDATAS11_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS12 = PRDATAS12_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS13 = PRDATAS13_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS14 = PRDATAS14_apb_slave[APB_DWIDTH-1:0];
assign PRDATAS15 = PRDATAS15_apb_slave[APB_DWIDTH-1:0];
*/
//---------------------------------------------------------------------
// Detect writes to individual slots
//---------------------------------------------------------------------
always @(posedge PCLK or negedge PRESETN)
begin
if (!PRESETN)
begin
s0_write <= 1'b0;
s1_write <= 1'b0;
s2_write <= 1'b0;
s3_write <= 1'b0;
s4_write <= 1'b0;
s5_write <= 1'b0;
s6_write <= 1'b0;
s7_write <= 1'b0;
s8_write <= 1'b0;
s9_write <= 1'b0;
s10_write <= 1'b0;
s11_write <= 1'b0;
s12_write <= 1'b0;
s13_write <= 1'b0;
s14_write <= 1'b0;
s15_write <= 1'b0;
s16_write <= 1'b0;
end
else
begin
// Set write indication bits
if (PSELS0 && PWRITES) s0_write <= 1'b1; // && PENABLES
if (PSELS1 && PWRITES) s1_write <= 1'b1; // && PENABLES
if (PSELS2 && PWRITES) s2_write <= 1'b1; // && PENABLES
if (PSELS3 && PWRITES) s3_write <= 1'b1; // && PENABLES
if (PSELS4 && PWRITES) s4_write <= 1'b1; // && PENABLES
if (PSELS5 && PWRITES) s5_write <= 1'b1; // && PENABLES
if (PSELS6 && PWRITES) s6_write <= 1'b1; // && PENABLES
if (PSELS7 && PWRITES) s7_write <= 1'b1; // && PENABLES
if (PSELS8 && PWRITES) s8_write <= 1'b1; // && PENABLES
if (PSELS9 && PWRITES) s9_write <= 1'b1; // && PENABLES
if (PSELS10 && PWRITES) s10_write <= 1'b1; // && PENABLES
if (PSELS11 && PWRITES) s11_write <= 1'b1; // && PENABLES
if (PSELS12 && PWRITES) s12_write <= 1'b1; // && PENABLES
if (PSELS13 && PWRITES) s13_write <= 1'b1; // && PENABLES
if (PSELS14 && PWRITES) s14_write <= 1'b1; // && PENABLES
if (PSELS15 && PWRITES) s15_write <= 1'b1; // && PENABLES
if (PSELS16 && PWRITES) s16_write <= 1'b1; // && PENABLES
// Clear write indication bits
if (GP_OUT[0]) s0_write <= 1'b0;
if (GP_OUT[1]) s1_write <= 1'b0;
if (GP_OUT[2]) s2_write <= 1'b0;
if (GP_OUT[3]) s3_write <= 1'b0;
if (GP_OUT[4]) s4_write <= 1'b0;
if (GP_OUT[5]) s5_write <= 1'b0;
if (GP_OUT[6]) s6_write <= 1'b0;
if (GP_OUT[7]) s7_write <= 1'b0;
if (GP_OUT[8]) s8_write <= 1'b0;
if (GP_OUT[9]) s9_write <= 1'b0;
if (GP_OUT[10]) s10_write <= 1'b0;
if (GP_OUT[11]) s11_write <= 1'b0;
if (GP_OUT[12]) s12_write <= 1'b0;
if (GP_OUT[13]) s13_write <= 1'b0;
if (GP_OUT[14]) s14_write <= 1'b0;
if (GP_OUT[15]) s15_write <= 1'b0;
if (GP_OUT[16]) s16_write <= 1'b0;
end
end
// System Clocks
initial SYSCLK_apb = 1'b0;
always #(APB_MASTER_CLK_CYCLE/2) SYSCLK_apb = ~SYSCLK_apb;
// Main simulation
initial
begin: main_sim
SYSRSTN_apb = 0;
@ (posedge SYSCLK_apb); #TPD;
SYSRSTN_apb = 1;
// wait until BFM is finished
while (!(FINISHED_apb_bfm===1'b1))
begin
@ (posedge SYSCLK_apb); #TPD;
end
stopsim=1;
#1;
$stop;
end
endmodule // testbench

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CoreUARTapb</name><vendor>Actel</vendor><library>DirectCore</library><version>5.7.100</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"/><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="0"><name>mti\scripts\bfmtovec.exe</name><userFileType>unknown</userFileType></file><file fileid="1"><name>mti\scripts\bfmtovec.lin</name><userFileType>unknown</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"/></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_CCC</name><vendor>Actel</vendor><library>SgCore</library><version>2.2.220</version><fileSets/><hwModel><views><view><name>HDL</name></view></views></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_CLK_DIV</name><vendor>Actel</vendor><library>SgCore</library><version>1.0.103</version><fileSets/><hwModel><views/></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_INIT_MONITOR</name><vendor>Actel</vendor><library>SgCore</library><version>2.0.308</version><fileSets/><hwModel><views><view><name>HDL</name></view></views></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_IOD</name><vendor>Actel</vendor><library>SgCore</library><version>1.0.218</version><fileSets/><hwModel><views/></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_LANECTRL</name><vendor>Actel</vendor><library>SgCore</library><version>2.0.102</version><fileSets><fileSet fileSetId="HDL_FILESET"/></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_TPSRAM</name><vendor>Actel</vendor><library>SgCore</library><version>1.1.108</version><fileSets/><hwModel><views/></hwModel></Component>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MIV_RV32</name><vendor>Microsemi</vendor><library>MiV</library><version>3.1.200</version><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>pkg\miv_rv32_hart_cfg_pkg.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>pkg\miv_rv32_pkg.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>pkg\miv_rv32_subsys_pkg.v</name><fileType>verilogSource</fileType></file><file fileid="3"><name>subsys_merged\miv_rv32_subsys_merged.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>hart_merged\miv_rv32_hart_merged.v</name><fileType>verilogSource</fileType></file><file fileid="5"><name>memory\miv_rv32_ram_singleport_lp.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>memory\miv_rv32_ram_singleport_lp_ecc.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:14 2026
// Parameters for MIV_RV32
//--------------------------------------------------------------------
parameter AHB_END_ADDR_0 = 'hffff;
parameter AHB_END_ADDR_1 = 'h8fff;
parameter AHB_INITIATOR_TYPE = 0;
parameter AHB_START_ADDR_0 = 'h0;
parameter AHB_START_ADDR_1 = 'h8000;
parameter AHB_TARGET_MIRROR = 0;
parameter APB_END_ADDR_0 = 'hffff;
parameter APB_END_ADDR_1 = 'h6fff;
parameter APB_INITIATOR_TYPE = 1;
parameter APB_START_ADDR_0 = 'h0;
parameter APB_START_ADDR_1 = 'h6000;
parameter APB_TARGET_MIRROR = 0;
parameter AXI_END_ADDR_0 = 'hffff;
parameter AXI_END_ADDR_1 = 'h6fff;
parameter AXI_INITIATOR_TYPE = 0;
parameter AXI_START_ADDR_0 = 'h0;
parameter AXI_START_ADDR_1 = 'h6000;
parameter AXI_TARGET_MIRROR = 0;
parameter BOOTROM_DEST_ADDR_LOWER = 'h0;
parameter BOOTROM_DEST_ADDR_UPPER = 'h4000;
parameter BOOTROM_PRESENT = 0;
parameter BOOTROM_SRC_END_ADDR_LOWER = 'h3fff;
parameter BOOTROM_SRC_END_ADDR_UPPER = 'h8000;
parameter BOOTROM_SRC_START_ADDR_LOWER = 'h0;
parameter BOOTROM_SRC_START_ADDR_UPPER = 'h8000;
parameter C_EXT = 1;
parameter DEBUGGER = 1;
parameter ECC_ENABLE = 0;
parameter F_EXT = 0;
parameter FAMILY = 26;
parameter FWD_REGS = 0;
parameter GEN_MUL_TYPE = 0;
parameter GPR_REGS = 0;
parameter I_REGS = 0;
parameter I_TRACE = 0;
parameter ICACHE_EN = 0;
parameter INTERNAL_MTIME = 1;
parameter INTERNAL_MTIME_IRQ = 1;
parameter M_EXT = 1;
parameter MI_I_MEM = 0;
parameter MIV_HART_ID = 'h0;
parameter MTIME_PRESCALER = 100;
parameter NO_MACC_BLK = 0;
parameter NUM_EXT_IRQS = 0;
parameter RECONFIG_BOOTROM = 0;
parameter RESET_VECTOR_ADDR_0 = 'h0;
parameter RESET_VECTOR_ADDR_1 = 'h8000;
parameter TAS_END_ADDR_0 = 'h3fff;
parameter TAS_END_ADDR_1 = 'h4000;
parameter TAS_START_ADDR_0 = 'h0;
parameter TAS_START_ADDR_1 = 'h4000;
parameter TCM_END_ADDR_0 = 'h8fff;
parameter TCM_END_ADDR_1 = 'h8000;
parameter TCM_PRESENT = 1;
parameter TCM_REGS = 0;
parameter TCM_START_ADDR_0 = 'h0;
parameter TCM_START_ADDR_1 = 'h8000;
parameter TCM_TAS_PRESENT = 0;
parameter VECTORED_INTERRUPTS = 0;

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// Copyright (c) 2023, Microchip Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// APACHE LICENSE
// Copyright (c) 2023, Microchip Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// v1.1 HW trigger local params uncommented
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// File: core_pkg.sv
//
// Purpose: core configuration package
//
// Author:
//
// Version: 1.1
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
package miv_rv32_hart_cfg_pkg;
//****************************************************************************
// Core Configuration
//****************************************************************************
// localparam logic[31:0] l_core_mtvec_offset = 32'h34;
localparam logic l_core_cfg_archid_reg = 1'b0;
localparam logic l_core_cfg_extension_state = 1'b0;
localparam logic l_core_cfg_fpu = 1'b0;
localparam logic l_core_cfg_hartid_reg = 1'b0;
localparam logic l_core_cfg_hw_dp_fpu = 1'b0;
localparam logic l_core_cfg_hw_sp_fpu = 1'b0;
localparam logic l_core_cfg_impid_reg = 1'b0;
localparam logic l_core_cfg_num_harts = 1'b0;
localparam logic l_core_cfg_supervisor_mode = 1'b0;
localparam logic l_core_cfg_user_mode = 1'b0;
localparam logic l_core_cfg_vendorid_reg = 32'h29;
// localparam logic l_core_cfg_static_mtvec_base = 1'b0;
// localparam logic[31:0] l_core_static_mtvec_base = 32'h6000_0000;
// localparam logic l_core_cfg_static_mtvec_mode = 1'b0;
// localparam logic[1:0] l_core_static_mtvec_mode = 2'b00;
localparam l_core_cfg_num_pmp = 0;
localparam l_core_cfg_cycle_count_width = 0;
// localparam l_core_cfg_time_count_width = 0;
localparam l_core_cfg_instret_count_width = 0;
localparam l_core_cfg_num_hpm_counters = 0;
localparam l_core_cfg_hpm_count_width = 0;
localparam l_core_cfg_hpm_event_sel_width = 0;
localparam logic l_core_cfg_hw_atomics = 1'b0;
// localparam logic l_core_cfg_hw_compressed = 1'b1;
localparam logic l_core_cfg_hw_economy = 1'b0;
localparam logic l_core_cfg_hw_float = 1'b1;
localparam logic l_core_cfg_hw_integer = 1'b1;
// localparam logic l_core_cfg_hw_multiply_divide = 1'b1;
localparam logic l_core_cfg_hw_multiply = 1'b1;
// localparam logic l_core_cfg_hw_macc_multiplier = 1'b1;
localparam logic l_core_cfg_hw_divide = 1'b1;
localparam logic l_core_cfg_mscratch = 1'b1;
localparam logic l_core_cfg_user_mode_traps = 1'b0;
localparam logic l_cfg_core_trigger_both = 1'b0;
//localparam logic l_core_cfg_hw_debug = 1'b1;
//localparam l_core_cfg_num_triggers = 2;
//localparam l_core_cfg_trigger_bus_width = (l_core_cfg_num_triggers > 0) ? l_core_cfg_num_triggers : 1;
localparam l_core_cfg_trigger_select_width = 1;
localparam logic l_core_cfg_debug_reg_ctrl_pipeline = 1'b1;
localparam logic l_core_cfg_irq_ext_capture = 1'b1;
localparam logic l_core_cfg_irq_sw_capture = 1'b1;
// localparam logic l_core_cfg_lsu_fwd = 1'b0;
// localparam logic l_core_cfg_csr_fwd = 1'b1;
// localparam logic l_core_cfg_exu_fwd = 1'b1;
localparam logic l_core_cfg_gpr_rd_ex = 1'b1;
localparam logic l_core_cfg_spec_load = 1'b0;
localparam logic l_core_cfg_formal_dbg_if = 1'b0;
// localparam logic l_core_cfg_gpr_type = 0; // 0 = RAM, 1 = Fabric
// localparam logic[31:0] l_core_reset_vector = 32'h6000_0000;
localparam logic[4:0] l_core_mcause_code_reset_state = 5'h0;
localparam logic l_core_mcause_interrupt_reset_state = 1'b0;
localparam logic[31:0] l_core_marchid = 32'h0000_0000; // OS ID's allocated by RISCV Foundation
localparam logic[31:0] l_core_mimpid = 32'hE501_0302; // Core E501, Ver 3.1.200
localparam logic[31:0] l_core_vendorid = 32'h0000_0029; // Microchip
// localparam l_core_num_sys_ext_irqs = 0; // max 8
//localparam logic l_core_cfg_gpr_ecc_uncorrectable_irq = 1'b0;
//localparam logic l_core_cfg_gpr_ecc_correctable_irq = 1'b0;
localparam logic l_core_cfg_instret_count_irq = 1'b0;
localparam logic l_core_cfg_cycle_count_irq = 1'b0;
localparam logic l_core_cfg_hpm_count_irq = 1'b0;
localparam logic l_core_cfg_i_bus_error_excpt = 1'b1;
localparam logic l_core_cfg_i_parity_error_excpt = 1'b1;
localparam logic l_core_cfg_d_bus_error_excpt = 1'b1;
localparam logic l_core_cfg_d_parity_error_excpt = 1'b1;
// l_core_pulp_divsqrt = 0 enables T-head-based DivSqrt unit. Supported only for FP32-only instances of Fpnew
localparam logic l_core_pulp_divsqrt = 1'b0;
localparam MEM_SECURITY_REGIONS = 1;
localparam LOG2_MEM_SECURITY_REGIONS = 1;
localparam MEM_REGIONS = 1;
localparam LOG2_MEM_REGIONS = 1;
endpackage
`default_nettype wire

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// Copyright (c) 2023, Microchip Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// APACHE LICENSE
// Copyright (c) 2023, Microchip Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
//
// File: miv_rv32_subsys_pkg.sv
//
// Purpose: subsys shared package
//
// Author:
//
// Version: 1.0
//
////////////////////////////////////////////////////////////////////////////////
`default_nettype none
package miv_rv32_subsys_pkg;
//------------------
// Global definitions
//------------------
localparam l_subsys_cfg_cpu_addr_width = 32;
localparam L_XLEN = 32;
localparam l_subsys_cfg_udma_present = 0; // always = 0, uDMA is not implemented in MIV_RV32
localparam l_subsys_cfg_udma_ctrl_addr_width = 32; //always = 32, uDMA is not implemented in MIV_RV32
localparam l_subsys_cfg_subsys_cfg_addr_width = 12;
localparam l_subsys_cfg_tcm0_addr_width = 32;
localparam l_subsys_cfg_tcm0_udma_present = 0;
localparam l_subsys_cfg_tcm0_cpu_i_present = 1;
localparam l_subsys_cfg_tcm0_cpu_d_present = 1;
localparam l_subsys_cfg_tcm0_use_ram_parity_bits = 0;
localparam l_subsys_cfg_tcm1_present = 0;
localparam l_subsys_cfg_tcm1_addr_width = 32;
localparam l_subsys_cfg_tcm1_udma_present = 0;
localparam l_subsys_cfg_tcm1_tas_present = 0;
localparam l_subsys_cfg_tcm1_cpu_i_present = 1;
localparam l_subsys_cfg_tcm1_cpu_d_present = 1;
localparam l_subsys_cfg_tcm1_use_ram_parity_bits = 0;
localparam l_subsys_cfg_use_bus_parity = 1;
localparam l_subsys_cfg_tcm_ram_sb_in_width = 4;
localparam l_subsys_cfg_tcm_ram_sb_out_width = 4;
localparam l_subsys_icache_burst_size = 8;
localparam l_subsys_icache_ram_depth = 256; // Use when icache ram is configured - valid values are 16, 32, 64, 128, 256 and 512
localparam l_subsys_icache_reg_depth = 32; // Use when icache registers is configured - valid values are 16, 32, 64, 128, 256 and 512
localparam logic l_cfg_fence_all_src = 1'b0;
localparam logic l_subsys_cfg_raw_hzd_en = 1'b1;
localparam logic l_subsys_cfg_war_hzd_en = 1'b1;
localparam logic [3:0] l_subsys_cfg_ar_cache = 4'b0011; // Normal Non-cacheable Bufferable
localparam logic [3:0] l_subsys_cfg_aw_cache = 4'b0011; // Normal Non-cacheable Bufferable
localparam logic [1:0] l_subsys_axi_rd_cfg_min_size = 2'b10;
localparam logic [1:0] l_subsys_axi_wr_cfg_min_size = 2'b10;
localparam logic [31:0] l_mtimecmp_addr_base = 32'h0200_4000;
localparam logic [31:0] l_mtime_prescaler_addr = 32'h0200_5000;
localparam logic [31:0] l_mtime_addr_base = 32'h0200_BFF8;
localparam logic l_cfg_hard_tcm0_en = 1'b1; // when = 1'b1 instantiates PF Low Power RAM for TCM which can be initialized by the System Controller
// when = 1'b0 uses inferred RAM for TCM which cannot be initialized by the System Controller
// workaround for SAR#114807.
// Note that ECC enabled TCM cannot be initialized by the System Controller.
localparam logic l_cfg_ecc_err_inj_en = 1'b0; // when = 1'b1 ecc error injection registers for TCM, GPR and ICache are enabled.
// when = 1'b0 ecc error injection registers for TCM, GPR and ICache are disabled.
localparam logic l_subsys_gpr_ded_reset_en = 1'b1; // when = 1'b1 GPR DED Reset Enabled
// when = 1'b0 GPR DED Reset Disabled
// Functions
//-----------------------
//***************************************************************************
// Constant function for Ceiling Log Base 2: ceiling(log2(n))
// Unlike $clog2(1) = 0, this function returns func_clog2(1) = 1
//***************************************************************************
function integer func_clog2 (input integer value);
integer val;
begin
val = (value == 1) ? value : value - 1;
for (func_clog2 = 0; val > 0; func_clog2 = func_clog2 + 1) begin
val = val >> 1;
end
end
endfunction
localparam ABSTRACT_ERR_BUSY = 1'b1;
localparam [1:0] ABSTRACT_ERR_CMD = 2'b10;
localparam [2:0] ABSTRACT_ERR_EXCEPTION = 3'b011;
localparam [2:0] ABSTRACT_ERR_NOHALT = 3'b100;
localparam ADDR_WIDTH = 32;
localparam DATA_WIDTH = 32;
localparam IR_REG_WIDTH = 5;
localparam DR_REG_WIDTH = 32;
localparam DMI_REG_WIDTH = 41;
localparam ACTIVE_HIGH_RESET = 0;
// Debug Registers Addresses
localparam [6:0] ABS_DATA_0_ADDR = 7'h04; //
localparam [6:0] ABS_DATA_1_ADDR = 7'h05; //
localparam [6:0] ABS_DATA_2_ADDR = 7'h06; //
localparam [6:0] ABS_DATA_3_ADDR = 7'h07; //
localparam [6:0] ABS_DATA_4_ADDR = 7'h08; //
localparam [6:0] ABS_DATA_5_ADDR = 7'h09; //
localparam [6:0] ABS_DATA_6_ADDR = 7'h0a; //
localparam [6:0] ABS_DATA_7_ADDR = 7'h0b; //
localparam [6:0] ABS_DATA_8_ADDR = 7'h0c; //
localparam [6:0] ABS_DATA_9_ADDR = 7'h0d; //
localparam [6:0] ABS_DATA_10_ADDR = 7'h0e; //
localparam [6:0] ABS_DATA_11_ADDR = 7'h0f; //
localparam [6:0] DMCONTROL_ADDR = 7'h10; //
localparam [6:0] DMSTATUS_ADDR = 7'h11; //
localparam [6:0] HART_INFO_ADDR = 7'h12; //
localparam [6:0] HALT_SUM_0_ADDR = 7'h40;
localparam [6:0] HALT_SUM_1_ADDR = 7'h13; //
localparam [6:0] HART_ARRAY_WINDOW_SEL_ADDR = 7'h14; // Hart Array Window Select.
localparam [6:0] HART_ARRAY_WINDOW_ADDR = 7'h15; // HArt Array Window.
localparam [6:0] ABST_CONTROL_AND_STATUS_ADDR = 7'h16; // Abstract Control and Status.
localparam [6:0] ABST_COMMAND_ADDR = 7'h17; // Abstract Command.
localparam [6:0] ABST_COMMAND_AUTOEXEC_ADDR = 7'h18; // Abstract Command Autoexec.
localparam [6:0] CONF_STR_PTR_0_ADDR = 7'h19; // Config String Pointer Address 0.
localparam [6:0] CONF_STR_PTR_1_ADDR = 7'h1a; // Config String Pointer Address 1.
localparam [6:0] CONF_STR_PTR_2_ADDR = 7'h1b; // Config String Pointer Address 2.
localparam [6:0] CONF_STR_PTR_3_ADDR = 7'h1c; // Config String Pointer Address 3.
localparam [6:0] PROG_BUFF_0_ADDR = 7'h20; // Program Buffer 0.
localparam [6:0] PROG_BUFF_1_ADDR = 7'h21; // Program Buffer 1.
localparam [6:0] PROG_BUFF_2_ADDR = 7'h22; // Program Buffer 2.
localparam [6:0] PROG_BUFF_3_ADDR = 7'h23; // Program Buffer 3.
localparam [6:0] PROG_BUFF_4_ADDR = 7'h24; // Program Buffer 4.
localparam [6:0] PROG_BUFF_5_ADDR = 7'h25; // Program Buffer 5.
localparam [6:0] PROG_BUFF_6_ADDR = 7'h26; // Program Buffer 6.
localparam [6:0] PROG_BUFF_7_ADDR = 7'h27; // Program Buffer 7.
localparam [6:0] PROG_BUFF_8_ADDR = 7'h28; // Program Buffer 8.
localparam [6:0] PROG_BUFF_9_ADDR = 7'h29; // Program Buffer 9.
localparam [6:0] PROG_BUFF_10_ADDR = 7'h2a; // Program Buffer 10.
localparam [6:0] PROG_BUFF_11_ADDR = 7'h2b; // Program Buffer 11.
localparam [6:0] PROG_BUFF_12_ADDR = 7'h2c; // Program Buffer 12.
localparam [6:0] PROG_BUFF_13_ADDR = 7'h2d; // Program Buffer 13.
localparam [6:0] PROG_BUFF_14_ADDR = 7'h2e; // Program Buffer 14.
localparam [6:0] PROG_BUFF_15_ADDR = 7'h2f; // Program Buffer 15.
localparam [6:0] AUTH_DATA_ADDR = 7'h30; // Authentication Data.
localparam [6:0] SBA_CONTROL_AND_STATUS_ADDR = 7'h38; // System Bus Access Control and Status.
localparam [6:0] SYS_BUS_ADDR_0_ADDR = 7'h39; // System Bus Address 31:0.
localparam [6:0] SYS_BUS_ADDR_1_ADDR = 7'h3a; // System Bus Address 63:32.
localparam [6:0] SYS_BUS_ADDR_2_ADDR = 7'h3b; // System Bus Address 95:64.
localparam [6:0] SYS_BUS_DATA_0_ADDR = 7'h3c; // System Bus Data 31:0.
localparam [6:0] SYS_BUS_DATA_1_ADDR = 7'h3d; // System Bus Data 63:32.
localparam [6:0] SYS_BUS_DATA_2_ADDR = 7'h3e; // System Bus Data 96:64.
localparam [6:0] SYS_BUS_DATA_3_ADDR = 7'h3f; // System Bus Data 127:96. 8 bit
// Machine Information Registers (read-only)
localparam [11:0] CSR_ADDR_MVENDORID = 12'hF11;
localparam [11:0] CSR_ADDR_MARCHID = 12'hF12;
localparam [11:0] CSR_ADDR_MIMPID = 12'hF13;
localparam [11:0] CSR_ADDR_MHARTID = 12'hF14;
localparam [11:0] CSR_ADDR_MISA = 12'h301;
localparam [11:0] DBGCSR_ADDR_DPC = 12'h7b0;
// ABSTRACTCS
localparam ABSTRACTCS_RESERVEDD = 1'b0;
localparam [4:0] ABSTRACTCS_PROGBUFSIZE = 5'b0;
localparam ABSTRACTCS_RESERVEDC = 1'b0;
localparam ABSTRACTCS_RESERVEDB = 1'b0;
localparam ABSTRACTCS_RESERVEDA = 1'b0;
localparam [3:0] ABSTRACTCS_DATACOUNT = 4'b0001;
// DMCONTROL
localparam DMCONTROL_HARTRESET = 1'b0;
localparam DMCONTROL_RESERVEDB = 1'b0;
localparam DMCONTROL_HASEL = 1'b0;
localparam [9:0] DMCONTROL_HARTSELLO = 10'b0;
localparam [9:0] DMCONTROL_HARTSELHI = 10'b0;
localparam [3:0] DMCONTROL_RESERVEDA = 4'b0;
// DMSTATUS
localparam [8:0] DMSTATUS_RESERVEDC = 9'b0;
localparam DMSTATUS_IMPEBREAK = 1'b0;
localparam [1:0] DMSTATUS_RESERVEDB = 2'b0;
localparam DMSTATUS_ALLUNAVAIL = 1'b0;
localparam DMSTATUS_ANYUNAVAIL = 1'b0;
localparam DMSTATUS_ALLANYUNAVAIL = 1'b0;
localparam DMSTATUS_ALLANYNONEXIST = 1'b0;
localparam DMSTATUS_AUTHENTICATED = 1'b1;
localparam DMSTATUS_AUTHBUSY = 1'b0;
localparam DMSTATUS_HASRESETHALTREQ = 1'b0;//disabled
localparam DMSTATUS_CONFSTRPTRVALID = 1'b0;
localparam [3:0] DMSTATUS_VERSION = 4'b0010;
// SBA
localparam [2:0] SBCS_VER = 3'b1; // post 2018 spec implemented
localparam [6:0] SBCS_SIZE = 7'h20; //tied to 32
localparam [4:0] SBCS_ACCESSES = 5'h7; // 32/16/8 bit bus accesses supported
localparam [3:0] TIMEOUT_VAL = 4'h8; // 8 bit base counter used, increments prescale counter on overflow.
// Timeout occurs when prescale counter reaches or exceeds TIMOUT_VAL
// DMI
localparam DBG_DMI_OP_WIDTH = 2;
localparam DBG_DMI_DATA_WIDTH = 32;
localparam DBG_DMI_ADDR_WIDTH = 7;
localparam DMI_REQ_DATA_WIDTH = 41; //DBG_DMI_ADDR_WIDTH + DBG_DMI_DATA_WIDTH + DBG_DMI_OP_WIDTH;
localparam DMI_RESP_DATA_WIDTH = 34; //DBG_DMI_DATA_WIDTH + DBG_DMI_OP_WIDTH;
localparam DBG_CDC_FIFO_DEPTH = 2;
// DTMS
// DTMCS
localparam [13:0] DTMCS_RESERVEDB = 14'b0;
localparam DTMCS_RESERVEDA = 1'b0;
localparam [2:0] DTMCS_IDLE = 3'b0; // 0 xtra clocks if busy
localparam [5:0] DTMCS_ABITS = 6'b000111; // 7 bit address
localparam [3:0] DTMCS_VERSION = 4'b0001; // v0.13
// JTAG TAP
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
// JTAG State Machine
localparam [3:0] TEST_LOGIC_RESET = 4'h0;
localparam [3:0] RUN_TEST_IDLE = 4'h1;
localparam [3:0] SELECT_DR = 4'h2;
localparam [3:0] CAPTURE_DR = 4'h3;
localparam [3:0] SHIFT_DR = 4'h4;
localparam [3:0] EXIT1_DR = 4'h5;
localparam [3:0] PAUSE_DR = 4'h6;
localparam [3:0] EXIT2_DR = 4'h7;
localparam [3:0] UPDATE_DR = 4'h8;
localparam [3:0] SELECT_IR = 4'h9;
localparam [3:0] CAPTURE_IR = 4'hA;
localparam [3:0] SHIFT_IR = 4'hB;
localparam [3:0] EXIT1_IR = 4'hC;
localparam [3:0] PAUSE_IR = 4'hD;
localparam [3:0] EXIT2_IR = 4'hE;
localparam [3:0] UPDATE_IR = 4'hF;
//RISCV DTM Registers (see RISC-V Debug Specification)
// All others are treated as 'BYPASS'.
localparam [4:0] REG_BYPASS = 5'b11111;
localparam [4:0] REG_IDCODE = 5'b00001;
localparam [4:0] REG_DMI_ACCESS = 5'b10001;
localparam [4:0] REG_DTMCS = 5'b10000;
// TAP ID code
localparam [31:0] ID_CODE = 32'h4E50105F; // Ver[31:28] 0x3 (MIV_RV32 v3.1.100), Part No.[27:12] E501, ManufID[11:1] 0x02F (Actel), Hardwired[0] = 1'b1
// SBA
localparam [2:0] BYTE_ACCESS = 3'b000;
localparam [2:0] HWORD_ACCESS = 3'b001;
localparam [2:0] WORD_ACCESS = 3'b010;
localparam [2:0] DWORD_ACCESS = 3'b011;
localparam [2:0] QWORD_ACCESS = 3'b100;
//3 (64-bit) and 4 (128-bit) unsupported.
endpackage
`default_nettype wire

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./COREFIFO_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./COREFIFO_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./COREFIFO_C0_0/COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./COREFIFO_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="DirectCore" name="COREFIFO" vendor="Actel" version="3.1.101"/><configuration><configurableElement referenceId="AE_STATIC_EN" value="false"/><configurableElement referenceId="AEVAL" value="4"/><configurableElement referenceId="AF_STATIC_EN" value="false"/><configurableElement referenceId="AFVAL" value="1020"/><configurableElement referenceId="CTRL_TYPE" value="2"/><configurableElement referenceId="DIE_SIZE" value="15"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="ESTOP" value="true"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="FSTOP" value="true"/><configurableElement referenceId="FWFT" value="true"/><configurableElement referenceId="NUM_STAGES" value="2"/><configurableElement referenceId="OVERFLOW_EN" value="false"/><configurableElement referenceId="PIPE" value="1"/><configurableElement referenceId="PREFETCH" value="false"/><configurableElement referenceId="RAM_OPT" value="0"/><configurableElement referenceId="RDCNT_EN" value="false"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_POLARITY" value="0"/><configurableElement referenceId="READ_DVALID" value="false"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SYNC" value="1"/><configurableElement referenceId="SYNC_RESET" value="0"/><configurableElement referenceId="testbench" value="User"/><configurableElement referenceId="UNDERFLOW_EN" value="false"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_POLARITY" value="0"/><configurableElement referenceId="WRCNT_EN" value="false"/><configurableElement referenceId="WRITE_ACK" value="false"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RESET_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FULL</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>EMPTY</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Q</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 18:21:52 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of COREFIFO_C0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component COREFIFO_C0
create_and_configure_core -core_vlnv {Actel:DirectCore:COREFIFO:3.1.101} -component_name {COREFIFO_C0} -params {\
"AE_STATIC_EN:false" \
"AEVAL:4" \
"AF_STATIC_EN:false" \
"AFVAL:1020" \
"CTRL_TYPE:2" \
"DIE_SIZE:15" \
"ECC:0" \
"ESTOP:true" \
"FSTOP:true" \
"FWFT:true" \
"NUM_STAGES:2" \
"OVERFLOW_EN:false" \
"PIPE:1" \
"PREFETCH:false" \
"RAM_OPT:0" \
"RDCNT_EN:false" \
"RDEPTH:1024" \
"RE_POLARITY:0" \
"READ_DVALID:false" \
"RWIDTH:32" \
"SYNC:1" \
"SYNC_RESET:0" \
"UNDERFLOW_EN:false" \
"WDEPTH:1024" \
"WE_POLARITY:0" \
"WRCNT_EN:false" \
"WRITE_ACK:false" \
"WWIDTH:32" }
# Exporting Component Description of COREFIFO_C0 to TCL done
*/
// COREFIFO_C0
module COREFIFO_C0(
// Inputs
CLK,
DATA,
RE,
RESET_N,
WE,
// Outputs
EMPTY,
FULL,
Q
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input CLK;
input [31:0] DATA;
input RE;
input RESET_N;
input WE;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output EMPTY;
output FULL;
output [31:0] Q;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire CLK;
wire [31:0] DATA;
wire EMPTY_net_0;
wire FULL_net_0;
wire [31:0] Q_net_0;
wire RE;
wire RESET_N;
wire WE;
wire FULL_net_1;
wire EMPTY_net_1;
wire [31:0] Q_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [31:0] MEMRD_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign MEMRD_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign FULL_net_1 = FULL_net_0;
assign FULL = FULL_net_1;
assign EMPTY_net_1 = EMPTY_net_0;
assign EMPTY = EMPTY_net_1;
assign Q_net_1 = Q_net_0;
assign Q[31:0] = Q_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------COREFIFO_C0_COREFIFO_C0_0_COREFIFO - Actel:DirectCore:COREFIFO:3.1.101
COREFIFO_C0_COREFIFO_C0_0_COREFIFO #(
.AE_STATIC_EN ( 0 ),
.AEVAL ( 4 ),
.AF_STATIC_EN ( 0 ),
.AFVAL ( 1020 ),
.CTRL_TYPE ( 2 ),
.DIE_SIZE ( 15 ),
.ECC ( 0 ),
.ESTOP ( 1 ),
.FAMILY ( 26 ),
.FSTOP ( 1 ),
.FWFT ( 1 ),
.NUM_STAGES ( 2 ),
.OVERFLOW_EN ( 0 ),
.PIPE ( 1 ),
.PREFETCH ( 0 ),
.RAM_OPT ( 0 ),
.RDCNT_EN ( 0 ),
.RDEPTH ( 1024 ),
.RE_POLARITY ( 0 ),
.READ_DVALID ( 0 ),
.RWIDTH ( 32 ),
.SYNC ( 1 ),
.SYNC_RESET ( 0 ),
.UNDERFLOW_EN ( 0 ),
.WDEPTH ( 1024 ),
.WE_POLARITY ( 0 ),
.WRCNT_EN ( 0 ),
.WRITE_ACK ( 0 ),
.WWIDTH ( 32 ) )
COREFIFO_C0_0(
// Inputs
.CLK ( CLK ),
.WCLOCK ( GND_net ), // tied to 1'b0 from definition
.RCLOCK ( GND_net ), // tied to 1'b0 from definition
.RESET_N ( RESET_N ),
.WRESET_N ( GND_net ), // tied to 1'b0 from definition
.RRESET_N ( GND_net ), // tied to 1'b0 from definition
.WE ( WE ),
.RE ( RE ),
.DATA ( DATA ),
.MEMRD ( MEMRD_const_net_0 ), // tied to 32'h00000000 from definition
// Outputs
.FULL ( FULL_net_0 ),
.EMPTY ( EMPTY_net_0 ),
.AFULL ( ),
.AEMPTY ( ),
.OVERFLOW ( ),
.UNDERFLOW ( ),
.WACK ( ),
.DVLD ( ),
.MEMWE ( ),
.MEMRE ( ),
.SB_CORRECT ( ),
.DB_DETECT ( ),
.Q ( Q_net_0 ),
.WRCNT ( ),
.RDCNT ( ),
.MEMWADDR ( ),
.MEMRADDR ( ),
.MEMWD ( )
);
endmodule

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0_COREFIFO_C0_0_COREFIFO</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\core\COREFIFO.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="3"><name>rtl\vlog\core\corefifo_sync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\core\corefifo_sync_scntr.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="5"><name>rtl\vlog\core\corefifo_async.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vlog\core\corefifo_nstagessync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vlog\core\corefifo_graytobinconv.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="8"><name>rtl\vlog\core\corefifo_fwft.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="9"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vlog\test\user\top_define.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="11"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v</name><fileType>verilogSource</fileType></file><file fileid="12"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v</name><fileType>verilogSource</fileType></file><file fileid="13"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v</name><fileType>verilogSource</fileType></file><file fileid="14"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v</name><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\test\user\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime> -all</SimulationTime><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="16"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v</name><fileType>verilogSource</fileType></file><file fileid="17"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v</name><fileType>verilogSource</fileType></file><file fileid="18"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="19"><name>mti\scripts\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="20"><name>mti\scripts\runall.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel></Component>

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set_component COREFIFO_C0_COREFIFO_C0_0_COREFIFO
set_false_path -to [ get_cells { genblk*.U_corefifo_async/*/shift_reg* } ]

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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Wed Apr 15 18:21:52 2026
// Parameters for COREFIFO
//--------------------------------------------------------------------
parameter AE_STATIC_EN = 0;
parameter AEVAL = 4;
parameter AF_STATIC_EN = 0;
parameter AFVAL = 1020;
parameter CTRL_TYPE = 2;
parameter DIE_SIZE = 15;
parameter ECC = 0;
parameter ESTOP = 1;
parameter FAMILY = 26;
parameter FSTOP = 1;
parameter FWFT = 1;
parameter NUM_STAGES = 2;
parameter OVERFLOW_EN = 0;
parameter PIPE = 1;
parameter PREFETCH = 0;
parameter RAM_OPT = 0;
parameter RDCNT_EN = 0;
parameter RDEPTH = 1024;
parameter RE_POLARITY = 0;
parameter READ_DVALID = 0;
parameter RWIDTH = 32;
parameter SYNC = 1;
parameter SYNC_RESET = 0;
parameter testbench = "User";
parameter UNDERFLOW_EN = 0;
parameter WDEPTH = 1024;
parameter WE_POLARITY = 0;
parameter WRCNT_EN = 0;
parameter WRITE_ACK = 0;
parameter WWIDTH = 32;

2
component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/runall.do Normal file
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run 700000ns
radix h

82
component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/uut_fifo/RESET_N
add wave -noupdate /testbench/uut_fifo/WCLOCK
add wave -noupdate /testbench/uut_fifo/WE
add wave -noupdate /testbench/uut_fifo/DATA
add wave -noupdate /testbench/uut_fifo/FULL
add wave -noupdate /testbench/uut_fifo/AFULL
add wave -noupdate /testbench/uut_fifo/WACK
add wave -noupdate /testbench/uut_fifo/OVERFLOW
add wave -noupdate /testbench/uut_fifo/RCLOCK
add wave -noupdate /testbench/uut_fifo/RE
add wave -noupdate /testbench/uut_fifo/Q
add wave -noupdate /testbench/uut_fifo/DVLD
add wave -noupdate /testbench/uut_fifo/EMPTY
add wave -noupdate /testbench/uut_fifo/AEMPTY
add wave -noupdate /testbench/uut_fifo/RDCNT
add wave -noupdate /testbench/uut_fifo/UNDERFLOW
add wave -noupdate /testbench/uut_fifo/MEMWE
add wave -noupdate /testbench/uut_fifo/MEMWD
add wave -noupdate /testbench/uut_fifo/MEMWADDR
add wave -noupdate /testbench/uut_fifo/MEMRE
add wave -noupdate /testbench/uut_fifo/MEMRD
add wave -noupdate /testbench/uut_fifo/MEMRADDR
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/wclk
add wave -noupdate /testbench/we
add wave -noupdate /testbench/wdata
add wave -noupdate /testbench/full
add wave -noupdate /testbench/afull
add wave -noupdate /testbench/overflow
add wave -noupdate /testbench/wrcount
add wave -noupdate /testbench/rclk
add wave -noupdate /testbench/re
add wave -noupdate /testbench/rdata
add wave -noupdate /testbench/empty
add wave -noupdate /testbench/aempty
add wave -noupdate /testbench/dvld
add wave -noupdate /testbench/rdcount
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/err_cnt
add wave -noupdate /testbench/ext_waddr
add wave -noupdate /testbench/ext_raddr
add wave -noupdate /testbench/ext_data
add wave -noupdate /testbench/ext_rd
add wave -noupdate /testbench/ext_we
add wave -noupdate /testbench/ext_re
add wave -noupdate /testbench/int_waddr
add wave -noupdate /testbench/int_raddr
add wave -noupdate /testbench/int_data
add wave -noupdate /testbench/int_rd
add wave -noupdate /testbench/int_we
add wave -noupdate /testbench/int_re
add wave -noupdate /testbench/monitor/wack_r
add wave -noupdate /testbench/monitor/tb_wcnt
add wave -noupdate /testbench/monitor/tb_wack
add wave -noupdate /testbench/monitor/tb_underflow
add wave -noupdate /testbench/monitor/tb_rcnt
add wave -noupdate /testbench/monitor/tb_overflow
add wave -noupdate /testbench/monitor/tb_empty
add wave -noupdate /testbench/monitor/tb_dvld
add wave -noupdate /testbench/monitor/tb_full
add wave -noupdate /testbench/monitor/tb_afull
add wave -noupdate /testbench/monitor/tb_aempty
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {32473187607 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 524
configure wave -valuecolwidth 60
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
WaveRestoreZoom {30291784830 fs} {35134349071 fs}

1479
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v Normal file
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File diff suppressed because it is too large Load Diff

44
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.gen Normal file
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DESIGN:COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
FAM:PolarFire
DEVICE:300
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
CLKS:1
PTYPE:1
BATCH:T
MGNTIMER:F
MGNCMPL:F
GEN_BEHV_MODULE:F
WWIDTH:32
RWIDTH:32
WDEPTH:1024
RDEPTH:1024
WE_POLARITY:1
RE_POLARITY:1
RCLK_EDGE:RISE
WCLK_EDGE:RISE
CLK_EDGE:RISE
INIT_RAM:F
LPM_HINT:0
ECC:0
PMODE2:0
BUSY_FLAG:0
BYTEENABLES:0
DATA_IN_PN:W_DATA
DATA_OUT_PN:R_DATA
WADDRESS_PN:W_ADDR
RADDRESS_PN:R_ADDR
WE_PN:W_EN
RE_PN:R_EN
WCLOCK_PN:W_CLK
RCLOCK_PN:R_CLK
CLOCK_PN:CLK
SII_LOCK:0
SD_EXPORT_HIDDEN_PORTS:false
CASCADE:0
A_DOUT_EN_POLARITY:2
A_DOUT_EN_PN:R_DATA_EN
A_DOUT_SRST_POLARITY:2
A_DOUT_SRST_PN:R_DATA_SRST_N
RESET_POLARITY:2
RESET_PN:R_DATA_ARST_N

80
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.log Normal file
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****************
Macro Parameters
****************
Name : COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
Family : PolarFire
Output Format : VERILOG
Type : RAM
Write Block Enable Polarity : Active High
Read Block Enable Polarity : Active High
A_DOUT Enable Polarity : None
B_DOUT Enable Polarity : None
A_DOUT Sync-reset Polarity : None
B_DOUT Sync-reset Polarity : None
A_DOUT Async-reset Polarity : None
B_DOUT Async-reset Polarity : None
Reset Polarity : None
Read Clock Edge : Rising
Write Clock Edge : Rising
A_REN Polarity : None
B_REN Polarity : None
Write Depth : 1024
Write Width : 32
Read Depth : 1024
Read Width : 32
Portname DataIn : W_DATA
Portname DataOut : R_DATA
Portname WClock : W_CLK
Portname RClock : R_CLK
Portname WAddress : W_ADDR
Portname RAddress : R_ADDR
Portname Single Clock : CLK
Portname Single Async-reset : R_DATA_ARST_N
Portname DataAIn :
Portname DataBIn :
Portname DataAOut :
Portname DataBOut :
Portname AddressA :
Portname AddressB :
Portname CLKA :
Portname CLKB :
Portname RWA :
Portname RWB :
Portname BLKA :
Portname BLKB :
Portname A_DOUT_EN : R_DATA_EN
Portname B_DOUT_EN :
Portname A_DOUT_SRST_N : R_DATA_SRST_N
Portname B_DOUT_SRST_N :
Portname A_DOUT_ARST_N :
Portname B_DOUT_ARST_N :
Portname Write Enable : W_EN
Portname Read Enable : R_EN
Portname A_WBYTE_EN :
Portname B_WBYTE_EN :
Portname A_REN :
Portname B_REN :
LPM_HINT : 0
Device : 300
RAM Type : Two Port
Optimized for : Speed
Initialize RAM : False
Clocks : Single Read/Write Clock
Byte Enables : No
Read Pipeline A : No
Read Pipeline B : No
Write Mode A : Hold Data
Write Mode B : Hold Data
ECC Type : Disabled
Lock access : Off
ACCESS_BUSY : Disabled
Cascade Configuration:
Write Port configuration : 1024x20
Read Port configuration : 1024x20
Number of blocks depth wise: 1
Number of blocks width wise: 2
Wrote Verilog netlist to E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v.

86
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top(
W_DATA,
R_DATA,
W_ADDR,
R_ADDR,
W_EN,
R_EN,
CLK
);
input [31:0] W_DATA;
output [31:0] R_DATA;
input [9:0] W_ADDR;
input [9:0] R_ADDR;
input W_EN;
input R_EN;
input CLK;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
wire GND_power_net1;
wire VCC_power_net1;
assign GND = GND_power_net1;
assign VCC = VCC_power_net1;
assign ADLIB_VCC = VCC_power_net1;
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 (.A_DOUT({nc0,
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 (.A_DOUT({nc24,
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
GND GND_power_inst1 (.Y(GND_power_net1));
VCC VCC_power_inst1 (.Y(VCC_power_net1));
endmodule

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