13 lines
633 B
XML
13 lines
633 B
XML
<?xml version="1.0" encoding="ISO-8859-1" ?>
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<?xml-stylesheet type="text/xsl" href="drcss.xsl"?>
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<drcreport>
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<header>top</header>
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<drc>
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<status>E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/data/drcreport\warn.png</status>
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<StatusMessage>Warning</StatusMessage>
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<message> bus interface data width mismatch</message>
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<detail> There is a data width mismatch between CoreAPB3_0_0:APBmslave1:PWDATAS[0-31] and CoreUARTapb_0:APB_bif:PWDATA[0-7] which may result in a loss of data.</detail>
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<crossprobe>liberoaction://cross_probe/smartdesign/top/pins/CoreAPB3_0_0:APBmslave1</crossprobe>
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</drc>
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</drcreport>
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