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Ethernet-IP-Core/tooldata/ethernet_tpsram_test.msg

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Design Entry;SmartDesign Check||(null)||SmartDesign 'top' design rules check succeeded, but with warnings||(null);(null)||(null);(null)
Design Entry;SmartDesign Check||(null)||Warning: There is a data width mismatch between CoreAPB3_0_0:APBmslave1:PWDATAS[0-31] and CoreUARTapb_0:APB_bif:PWDATA[0-7] which may result in a loss of data.||(null);(null)|| bus interface data width mismatch;liberoaction://cross_probe/smartdesign/top/pins/CoreAPB3_0_0:APBmslave1
HelpInfo,E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\html,fpgahelp.qhc,synerrmsg.mp,E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin\assistant
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(48);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/48||syn_comps.v(21);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/21
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(50);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/50||syn_comps.v(61);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/61
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(52);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/52||syn_comps.v(88);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/88
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(54);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/54||syn_comps.v(118);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/118
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(56);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/56||syn_comps.v(168);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/168
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(58);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/58||syn_comps.v(213);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/213
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(60);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/60||syn_comps.v(232);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/232
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(62);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/62||syn_comps.v(281);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/281
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(64);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/64||syn_comps.v(335);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/335
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(66);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/66||syn_comps.v(657);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/657
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(68);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/68||syn_comps.v(761);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/761
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(70);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/70||syn_comps.v(795);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/795
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(72);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/72||syn_comps.v(1059);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1059
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(74);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/74||syn_comps.v(1369);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1369
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(76);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/76||syn_comps.v(1396);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1396
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(78);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/78||syn_comps.v(1441);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1441
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(80);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/80||syn_comps.v(1474);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1474
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(82);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/82||syn_comps.v(1492);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1492
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(84);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/84||syn_comps.v(1518);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1518
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(86);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/86||syn_comps.v(1559);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1559
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(88);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/88||syn_comps.v(1581);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1581
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(90);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/90||syn_comps.v(1599);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1599
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(92);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/92||syn_comps.v(1616);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1616
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(94);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/94||syn_comps.v(1635);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1635
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(96);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/96||syn_comps.v(1652);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1652
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(98);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/98||syn_comps.v(1681);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1681
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(100);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/100||syn_comps.v(1712);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1712
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(102);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/102||syn_comps.v(1802);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/1802
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(104);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/104||syn_comps.v(2026);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2026
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(106);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/106||syn_comps.v(2187);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2187
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(108);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/108||syn_comps.v(2203);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2203
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(110);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/110||syn_comps.v(2219);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2219
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(112);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/112||syn_comps.v(2235);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2235
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(114);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/114||syn_comps.v(2267);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2267
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(116);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/116||syn_comps.v(2648);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/2648
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(118);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/118||syn_comps.v(3661);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3661
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(120);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/120||syn_comps.v(3732);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3732
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(122);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/122||syn_comps.v(3861);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3861
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(124);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/124||syn_comps.v(3879);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3879
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(126);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/126||syn_comps.v(3896);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3896
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(128);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/128||syn_comps.v(3911);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3911
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(130);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/130||syn_comps.v(3926);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3926
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(132);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/132||syn_comps.v(3953);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/3953
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(134);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/134||syn_comps.v(4067);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4067
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(136);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/136||syn_comps.v(4098);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4098
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(138);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/138||syn_comps.v(4144);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4144
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(140);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/140||syn_comps.v(4255);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4255
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(142);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/142||syn_comps.v(4439);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4439
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(144);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/144||syn_comps.v(4480);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4480
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(146);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/146||syn_comps.v(4506);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4506
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(148);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/148||syn_comps.v(4523);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4523
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(150);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/150||syn_comps.v(4600);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/4600
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(152);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/152||syn_comps.v(5364);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/5364
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(154);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/154||syn_comps.v(6174);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/6174
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(156);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/156||syn_comps.v(6283);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/6283
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(158);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/158||syn_comps.v(6321);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/6321
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(160);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/160||syn_comps.v(6394);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/6394
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(162);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/162||syn_comps.v(7283);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/7283
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(164);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/164||syn_comps.v(8340);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/8340
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(166);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/166||syn_comps.v(9299);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/9299
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(168);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/168||syn_comps.v(10035);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10035
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(170);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/170||syn_comps.v(10750);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10750
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(172);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/172||syn_comps.v(10784);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10784
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(174);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/174||syn_comps.v(10820);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10820
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(176);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/176||syn_comps.v(10867);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10867
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(178);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/178||syn_comps.v(10901);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/10901
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(180);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/180||syn_comps.v(11767);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/11767
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(182);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/182||syn_comps.v(12810);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/12810
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(184);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/184||syn_comps.v(12822);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/12822
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(186);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/186||syn_comps.v(12831);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/12831
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(188);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/188||syn_comps.v(12843);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/12843
Implementation;Synthesis||CG100||@W:User defined pragma syn_black_box detected||top.srr(190);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/190||syn_comps.v(12856);liberoaction://cross_probe/hdl/file/'<project>\component\syn_comps.v'/linenumber/12856
Implementation;Synthesis||CG1337||@W:Net resetn_rx_s is not declared.||top.srr(211);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/211||spi_chanctrl.v(805);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/805
Implementation;Synthesis||CG1337||@W:Net ooOI1 is not declared.||top.srr(223);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/223||CoreTSE.v(430844);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/430844
Implementation;Synthesis||CG1337||@W:Net ioOI1 is not declared.||top.srr(224);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/224||CoreTSE.v(430859);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/430859
Implementation;Synthesis||CG1337||@W:Net oI0i0 is not declared.||top.srr(225);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/225||CoreTSE.v(476678);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/476678
Implementation;Synthesis||CG1337||@W:Net Ol0i0 is not declared.||top.srr(226);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/226||CoreTSE.v(476693);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/476693
Implementation;Synthesis||CG1337||@W:Net l0iIo is not declared.||top.srr(227);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/227||CoreTSE.v(548082);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548082
Implementation;Synthesis||CG1337||@W:Net o0iIo is not declared.||top.srr(228);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/228||CoreTSE.v(548102);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548102
Implementation;Synthesis||CG1337||@W:Net i0iIo is not declared.||top.srr(229);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/229||CoreTSE.v(548122);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548122
Implementation;Synthesis||CG1337||@W:Net O1iIo is not declared.||top.srr(230);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/230||CoreTSE.v(548142);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548142
Implementation;Synthesis||CG1337||@W:Net I1iIo is not declared.||top.srr(231);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/231||CoreTSE.v(548162);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548162
Implementation;Synthesis||CG1337||@W:Net l1iIo is not declared.||top.srr(232);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/232||CoreTSE.v(548182);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v'/linenumber/548182
Implementation;Synthesis||CS138||@W:Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine.||top.srr(264);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/264||miv_rv32_hart_merged.v(26989);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/26989
Implementation;Synthesis||CS138||@W:Macro definition for RAM_BIST_VIEW not found. Cannot undefine.||top.srr(265);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/265||miv_rv32_hart_merged.v(26990);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/26990
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive dc_script_begin. Verify the correct directive name.||top.srr(278);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/278||miv_rv32_hart_merged.v(29121);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/29121
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive dc_script_end. Verify the correct directive name.||top.srr(279);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/279||miv_rv32_hart_merged.v(29124);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/29124
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(280);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/280||miv_rv32_hart_merged.v(33910);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/33910
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(281);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/281||miv_rv32_hart_merged.v(34706);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/34706
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(282);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/282||miv_rv32_hart_merged.v(35086);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/35086
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(283);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/283||miv_rv32_hart_merged.v(35316);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/35316
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(284);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/284||miv_rv32_hart_merged.v(35536);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/35536
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(285);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/285||miv_rv32_hart_merged.v(35932);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/35932
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(286);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/286||miv_rv32_hart_merged.v(36264);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/36264
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(287);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/287||miv_rv32_hart_merged.v(36476);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/36476
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(288);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/288||miv_rv32_hart_merged.v(36692);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/36692
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(289);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/289||miv_rv32_hart_merged.v(37011);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/37011
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(290);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/290||miv_rv32_hart_merged.v(37227);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/37227
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(291);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/291||miv_rv32_hart_merged.v(37457);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/37457
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(292);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/292||miv_rv32_hart_merged.v(37837);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/37837
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(293);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/293||miv_rv32_hart_merged.v(38116);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/38116
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(294);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/294||miv_rv32_hart_merged.v(38316);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/38316
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(295);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/295||miv_rv32_hart_merged.v(38581);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/38581
Implementation;Synthesis||CG104||@W:Unsized number in concatenation is 32 bits||top.srr(296);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/296||miv_rv32_hart_merged.v(39241);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/39241
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(297);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/297||miv_rv32_hart_merged.v(39806);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/39806
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(306);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/306||miv_rv32_hart_merged.v(42208);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/42208
Implementation;Synthesis||CS141||@W:Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.||top.srr(307);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/307||miv_rv32_hart_merged.v(42549);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/42549
Implementation;Synthesis||CG775||@N: Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB||top.srr(358);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/358||coreapb3.v(31);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/31
Implementation;Synthesis||CG775||@N: Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB||top.srr(359);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/359||corejtagdebug.v(22);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/22
Implementation;Synthesis||CG775||@N: Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB||top.srr(360);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/360||corespi.v(27);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v'/linenumber/27
Implementation;Synthesis||CG360||@W:Removing wire IA_PRDATA, as there is no assignment to it.||top.srr(453);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/453||coreapb3.v(244);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/244
Implementation;Synthesis||CG360||@W:Removing wire neg_reset, as there is no assignment to it.||top.srr(532);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/532||corefifo_sync_scntr.v(173);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/173
Implementation;Synthesis||CL169||@W:Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.||top.srr(534);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/534||corefifo_sync_scntr.v(485);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/485
Implementation;Synthesis||CL169||@W:Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.||top.srr(535);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/535||corefifo_sync_scntr.v(463);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/463
Implementation;Synthesis||CL169||@W:Pruning unused register full_reg. Make sure that there are no unused intermediate registers.||top.srr(536);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/536||corefifo_sync_scntr.v(463);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/463
Implementation;Synthesis||CL169||@W:Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers.||top.srr(537);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/537||corefifo_sync_scntr.v(463);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/463
Implementation;Synthesis||CL169||@W:Pruning unused register sc_w[10:0]. Make sure that there are no unused intermediate registers.||top.srr(538);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/538||corefifo_sync_scntr.v(371);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/371
Implementation;Synthesis||CL169||@W:Pruning unused register we_f_i. Make sure that there are no unused intermediate registers.||top.srr(539);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/539||corefifo_sync_scntr.v(331);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/331
Implementation;Synthesis||CL207||@W:All reachable assignments to genblk8.wack_r assign 0, register removed by optimization.||top.srr(540);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/540||corefifo_sync_scntr.v(579);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/579
Implementation;Synthesis||CL207||@W:All reachable assignments to genblk8.overflow_r assign 0, register removed by optimization.||top.srr(541);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/541||corefifo_sync_scntr.v(579);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/579
Implementation;Synthesis||CL207||@W:All reachable assignments to underflow_r assign 0, register removed by optimization.||top.srr(542);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/542||corefifo_sync_scntr.v(485);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/485
Implementation;Synthesis||CL207||@W:All reachable assignments to dvld_r assign 0, register removed by optimization.||top.srr(543);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/543||corefifo_sync_scntr.v(485);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/485
Implementation;Synthesis||CL207||@W:All reachable assignments to rdcnt[10:0] assign 0, register removed by optimization.||top.srr(544);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/544||corefifo_sync_scntr.v(275);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/275
Implementation;Synthesis||CL207||@W:All reachable assignments to wrcnt[10:0] assign 0, register removed by optimization.||top.srr(545);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/545||corefifo_sync_scntr.v(248);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/248
Implementation;Synthesis||CG133||@W:Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.||top.srr(564);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/564||corefifo_fwft.v(119);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/119
Implementation;Synthesis||CG360||@W:Removing wire aresetn, as there is no assignment to it.||top.srr(565);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/565||corefifo_fwft.v(125);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/125
Implementation;Synthesis||CG360||@W:Removing wire empty1, as there is no assignment to it.||top.srr(566);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/566||corefifo_fwft.v(132);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/132
Implementation;Synthesis||CG360||@W:Removing wire reset_wclk, as there is no assignment to it.||top.srr(567);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/567||corefifo_fwft.v(140);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/140
Implementation;Synthesis||CG360||@W:Removing wire reset_rclk, as there is no assignment to it.||top.srr(568);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/568||corefifo_fwft.v(141);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/141
Implementation;Synthesis||CL169||@W:Pruning unused register we_p_r. Make sure that there are no unused intermediate registers.||top.srr(570);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/570||corefifo_fwft.v(358);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/358
Implementation;Synthesis||CL169||@W:Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers.||top.srr(571);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/571||corefifo_fwft.v(244);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/244
Implementation;Synthesis||CL169||@W:Pruning unused register re_p_d. Make sure that there are no unused intermediate registers.||top.srr(572);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/572||corefifo_fwft.v(233);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/233
Implementation;Synthesis||CL169||@W:Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers.||top.srr(573);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/573||corefifo_fwft.v(214);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/214
Implementation;Synthesis||CL169||@W:Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers.||top.srr(574);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/574||corefifo_fwft.v(214);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/214
Implementation;Synthesis||CL318||@W:*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(601);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/601||COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(46);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/46
Implementation;Synthesis||CL318||@W:*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(602);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/602||COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(47);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/47
Implementation;Synthesis||CL318||@W:*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(603);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/603||COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(48);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/48
Implementation;Synthesis||CL318||@W:*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(604);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/604||COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/49
Implementation;Synthesis||CG360||@W:Removing wire pf_MEMRADDR, as there is no assignment to it.||top.srr(606);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/606||COREFIFO.v(211);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/211
Implementation;Synthesis||CG360||@W:Removing wire pf_Q, as there is no assignment to it.||top.srr(607);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/607||COREFIFO.v(217);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/217
Implementation;Synthesis||CG184||@W:Removing wire DVLD_async, as it has the load but no drivers.||top.srr(608);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/608||COREFIFO.v(236);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/236
Implementation;Synthesis||CG184||@W:Removing wire DVLD_sync, as it has the load but no drivers.||top.srr(609);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/609||COREFIFO.v(238);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/238
Implementation;Synthesis||CG360||@W:Removing wire pf_dvld, as there is no assignment to it.||top.srr(610);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/610||COREFIFO.v(241);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/241
Implementation;Synthesis||CG133||@W:Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.||top.srr(611);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/611||COREFIFO.v(250);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/250
Implementation;Synthesis||CG133||@W:Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.||top.srr(612);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/612||COREFIFO.v(264);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/264
Implementation;Synthesis||CG360||@W:Removing wire reset_rclk, as there is no assignment to it.||top.srr(613);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/613||COREFIFO.v(283);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/283
Implementation;Synthesis||CG360||@W:Removing wire reset_wclk, as there is no assignment to it.||top.srr(614);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/614||COREFIFO.v(284);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/284
Implementation;Synthesis||CG360||@W:Removing wire reset_sync_r, as there is no assignment to it.||top.srr(615);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/615||COREFIFO.v(285);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/285
Implementation;Synthesis||CG360||@W:Removing wire reset_sync_w, as there is no assignment to it.||top.srr(616);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/616||COREFIFO.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/286
Implementation;Synthesis||CL169||@W:Pruning unused register RDATA_ext_r1[31:0]. Make sure that there are no unused intermediate registers.||top.srr(618);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/618||COREFIFO.v(1175);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1175
Implementation;Synthesis||CL169||@W:Pruning unused register RDATA_ext_r[31:0]. Make sure that there are no unused intermediate registers.||top.srr(619);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/619||COREFIFO.v(1165);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1165
Implementation;Synthesis||CL169||@W:Pruning unused register REN_d2. Make sure that there are no unused intermediate registers.||top.srr(620);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/620||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register REN_d3. Make sure that there are no unused intermediate registers.||top.srr(621);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/621||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register RE_d2. Make sure that there are no unused intermediate registers.||top.srr(622);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/622||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register RE_d3. Make sure that there are no unused intermediate registers.||top.srr(623);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/623||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers.||top.srr(624);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/624||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers.||top.srr(625);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/625||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers.||top.srr(626);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/626||COREFIFO.v(1100);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1100
Implementation;Synthesis||CL169||@W:Pruning unused register RDATA_r2[31:0]. Make sure that there are no unused intermediate registers.||top.srr(627);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/627||COREFIFO.v(1088);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1088
Implementation;Synthesis||CL169||@W:Pruning unused register RDATA_r1[31:0]. Make sure that there are no unused intermediate registers.||top.srr(628);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/628||COREFIFO.v(1078);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1078
Implementation;Synthesis||CL169||@W:Pruning unused register RDATA_r_pre[31:0]. Make sure that there are no unused intermediate registers.||top.srr(629);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/629||COREFIFO.v(1068);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1068
Implementation;Synthesis||CL169||@W:Pruning unused register fwft_Q_r[31:0]. Make sure that there are no unused intermediate registers.||top.srr(630);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/630||COREFIFO.v(1058);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/1058
Implementation;Synthesis||CL169||@W:Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers.||top.srr(631);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/631||COREFIFO.v(503);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/503
Implementation;Synthesis||CL169||@W:Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers.||top.srr(632);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/632||COREFIFO.v(503);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/503
Implementation;Synthesis||CL169||@W:Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers.||top.srr(633);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/633||COREFIFO.v(503);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/503
Implementation;Synthesis||CL169||@W:Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers.||top.srr(634);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/634||COREFIFO.v(490);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/490
Implementation;Synthesis||CL169||@W:Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers.||top.srr(635);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/635||COREFIFO.v(490);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v'/linenumber/490
Implementation;Synthesis||CG360||@W:Removing wire UTRSTB, as there is no assignment to it.||top.srr(711);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/711||corejtagdebug.v(31);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/31
Implementation;Synthesis||CG360||@W:Removing wire UTMS, as there is no assignment to it.||top.srr(712);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/712||corejtagdebug.v(32);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/32
Implementation;Synthesis||CG360||@W:Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.||top.srr(713);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/713||corejtagdebug.v(169);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/169
Implementation;Synthesis||CG360||@W:Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it.||top.srr(714);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/714||corejtagdebug.v(176);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/176
Implementation;Synthesis||CG360||@W:Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it.||top.srr(715);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/715||corejtagdebug.v(183);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/183
Implementation;Synthesis||CG360||@W:Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it.||top.srr(716);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/716||corejtagdebug.v(190);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/190
Implementation;Synthesis||CG360||@W:Removing wire iURSTB_inv, as there is no assignment to it.||top.srr(717);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/717||corejtagdebug.v(241);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/241
Implementation;Synthesis||CL318||@W:*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(719);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/719||corejtagdebug.v(31);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/31
Implementation;Synthesis||CL318||@W:*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.||top.srr(720);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/720||corejtagdebug.v(32);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/32
Implementation;Synthesis||CL208||@W:All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization.||top.srr(732);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/732||spi_rf.v(134);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v'/linenumber/134
Implementation;Synthesis||CG1340||@W:Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible.||top.srr(779);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/779||spi_chanctrl.v(416);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/416
Implementation;Synthesis||CG133||@W:Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration.||top.srr(780);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/780||spi_chanctrl.v(195);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/195
Implementation;Synthesis||CG360||@W:Removing wire resetn_rx_p, as there is no assignment to it.||top.srr(781);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/781||spi_chanctrl.v(196);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/196
Implementation;Synthesis||CG360||@W:Removing wire resetn_rx_r, as there is no assignment to it.||top.srr(782);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/782||spi_chanctrl.v(200);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/200
Implementation;Synthesis||CG133||@W:Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration.||top.srr(783);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/783||spi_chanctrl.v(222);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/222
Implementation;Synthesis||CL169||@W:Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers.||top.srr(785);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/785||spi_chanctrl.v(1130);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/1130
Implementation;Synthesis||CL169||@W:Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers.||top.srr(786);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/786||spi_chanctrl.v(823);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/823
Implementation;Synthesis||CL169||@W:Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers.||top.srr(787);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/787||spi_chanctrl.v(719);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/719
Implementation;Synthesis||CL169||@W:Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers.||top.srr(788);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/788||spi_chanctrl.v(416);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/416
Implementation;Synthesis||CL169||@W:Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers.||top.srr(789);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/789||spi_chanctrl.v(416);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/416
Implementation;Synthesis||CL177||@W:Sharing sequential element cfg_enable_P1 and merging msrx_async_reset_ok. Add a syn_preserve attribute to the element to prevent sharing.||top.srr(790);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/790||spi_chanctrl.v(343);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/343
Implementation;Synthesis||CG781||@W:Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(948);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/948||CORETSE_0.v(270);liberoaction://cross_probe/hdl/file/'<project>\component\work\CORETSE_0\CORETSE_0.v'/linenumber/270
Implementation;Synthesis||CG1340||@W:Index into variable tx_byte could be out of range ; a simulation mismatch is possible.||top.srr(970);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/970||Tx_async.v(268);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v'/linenumber/268
Implementation;Synthesis||CG1340||@W:Index into variable tx_byte could be out of range ; a simulation mismatch is possible.||top.srr(971);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/971||Tx_async.v(268);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v'/linenumber/268
Implementation;Synthesis||CL169||@W:Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.||top.srr(974);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/974||Tx_async.v(119);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v'/linenumber/119
Implementation;Synthesis||CL177||@W:Sharing sequential element clear_framing_error_en and merging clear_parity_en. Add a syn_preserve attribute to the element to prevent sharing.||top.srr(988);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/988||Rx_async.v(501);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/501
Implementation;Synthesis||CG133||@W:Object data_ready is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1000);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1000||CoreUART.v(136);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/136
Implementation;Synthesis||CL169||@W:Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers.||top.srr(1002);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1002||CoreUART.v(376);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/376
Implementation;Synthesis||CL169||@W:Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers.||top.srr(1003);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1003||CoreUART.v(341);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/341
Implementation;Synthesis||CL169||@W:Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers.||top.srr(1004);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1004||CoreUART.v(341);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/341
Implementation;Synthesis||CL169||@W:Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers.||top.srr(1005);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1005||CoreUART.v(326);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/326
Implementation;Synthesis||CL169||@W:Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers.||top.srr(1006);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1006||CoreUART.v(293);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/293
Implementation;Synthesis||CL169||@W:Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers.||top.srr(1007);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1007||CoreUART.v(278);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/278
Implementation;Synthesis||CL169||@W:Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers.||top.srr(1008);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1008||CoreUART.v(278);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/278
Implementation;Synthesis||CL169||@W:Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers.||top.srr(1009);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1009||CoreUART.v(263);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/263
Implementation;Synthesis||CL169||@W:Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers.||top.srr(1010);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1010||CoreUART.v(263);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/263
Implementation;Synthesis||CL169||@W:Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers.||top.srr(1011);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1011||CoreUART.v(159);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v'/linenumber/159
Implementation;Synthesis||CG133||@W:Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1030);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1030||CoreUARTapb.v(158);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v'/linenumber/158
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1047);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1047||miv_rv32_hart_merged.v(18721);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18721
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1049);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1049||miv_rv32_hart_merged.v(18721);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18721
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1051);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1051||miv_rv32_hart_merged.v(18721);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18721
Implementation;Synthesis||CG133||@W:Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1075);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1075||miv_rv32_hart_merged.v(19009);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19009
Implementation;Synthesis||CG133||@W:Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1076);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1076||miv_rv32_hart_merged.v(19017);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19017
Implementation;Synthesis||CG133||@W:Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1077);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1077||miv_rv32_hart_merged.v(19020);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19020
Implementation;Synthesis||CG133||@W:Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1078);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1078||miv_rv32_hart_merged.v(19021);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19021
Implementation;Synthesis||CG133||@W:Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1079);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1079||miv_rv32_hart_merged.v(19022);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19022
Implementation;Synthesis||CG133||@W:Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1080);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1080||miv_rv32_hart_merged.v(19023);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19023
Implementation;Synthesis||CG133||@W:Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1081);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1081||miv_rv32_hart_merged.v(19024);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19024
Implementation;Synthesis||CG133||@W:Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1082);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1082||miv_rv32_hart_merged.v(19025);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19025
Implementation;Synthesis||CG133||@W:Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1083);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1083||miv_rv32_hart_merged.v(19026);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19026
Implementation;Synthesis||CG133||@W:Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1084);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1084||miv_rv32_hart_merged.v(19027);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19027
Implementation;Synthesis||CG1340||@W:Index into variable mul_mp could be out of range ; a simulation mismatch is possible.||top.srr(1114);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1114||miv_rv32_hart_merged.v(10740);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/10740
Implementation;Synthesis||CG1340||@W:Index into variable mul_mp could be out of range ; a simulation mismatch is possible.||top.srr(1115);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1115||miv_rv32_hart_merged.v(10740);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/10740
Implementation;Synthesis||CG133||@W:Object fpu_frm_i is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1116);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1116||miv_rv32_hart_merged.v(10766);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/10766
Implementation;Synthesis||CG133||@W:Object op_i is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1117);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1117||miv_rv32_hart_merged.v(10767);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/10767
Implementation;Synthesis||CG133||@W:Object status_o.NV is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1118);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1118||miv_rv32_pkg.v(843);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v'/linenumber/843
Implementation;Synthesis||CG133||@W:Object status_o.DZ is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1119);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1119||miv_rv32_pkg.v(844);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v'/linenumber/844
Implementation;Synthesis||CG133||@W:Object status_o.OF is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1120);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1120||miv_rv32_pkg.v(845);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v'/linenumber/845
Implementation;Synthesis||CG133||@W:Object status_o.UF is declared but not assigned. Either assign a value or remove the declaration.||top.srr(1121);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1121||miv_rv32_pkg.v(846);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v'/linenumber/846
Implementation;Synthesis||CL168||@W:Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1245);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1245||miv_rv32_hart_merged.v(4310);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/4310
Implementation;Synthesis||CL134||@N: Found RAM mem_xf, depth=32, width=32||top.srr(1300);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1300||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||CL134||@N: Found RAM mem_xf, depth=32, width=32||top.srr(1301);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1301||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||CL134||@N: Found RAM mem_xf, depth=32, width=32||top.srr(1302);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1302||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||CL169||@W:Pruning unused register sreset. Make sure that there are no unused intermediate registers.||top.srr(1307);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1307||miv_rv32_hart_merged.v(10390);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/10390
Implementation;Synthesis||CL189||@N: Register bit gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5] is always 0.||top.srr(1308);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1308||miv_rv32_hart_merged.v(9191);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9191
Implementation;Synthesis||CL260||@W:Pruning register bit 5 of gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(1309);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1309||miv_rv32_hart_merged.v(9191);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9191
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1355);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1355||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1357);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1357||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1367);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1367||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1369);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1369||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1386);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1386||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CG532||@W:Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur||top.srr(1388);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1388||miv_rv32_subsys_merged.v(10042);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10042
Implementation;Synthesis||CL169||@W:Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.||top.srr(1534);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1534||miv_rv32_subsys_merged.v(15811);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15811
Implementation;Synthesis||CL134||@N: Found RAM fifo_memory, depth=2, width=41||top.srr(1535);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1535||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(1536);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1536||miv_rv32_subsys_merged.v(15791);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15791
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(1537);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1537||miv_rv32_subsys_merged.v(15785);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15785
Implementation;Synthesis||CL169||@W:Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.||top.srr(1545);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1545||miv_rv32_subsys_merged.v(15811);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15811
Implementation;Synthesis||CL134||@N: Found RAM fifo_memory, depth=2, width=34||top.srr(1546);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1546||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(1547);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1547||miv_rv32_subsys_merged.v(15791);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15791
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(1548);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1548||miv_rv32_subsys_merged.v(15785);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15785
Implementation;Synthesis||CL265||@W:Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.||top.srr(1553);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1553||miv_rv32_subsys_merged.v(14337);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14337
Implementation;Synthesis||CL271||@W:Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||top.srr(1554);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1554||miv_rv32_subsys_merged.v(14337);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14337
Implementation;Synthesis||CL169||@W:Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.||top.srr(1555);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1555||miv_rv32_subsys_merged.v(14337);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14337
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1772);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1772||miv_rv32_ram_singleport_lp.v(25538);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25538
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R20C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1773);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1773||miv_rv32_ram_singleport_lp.v(25498);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25498
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1774);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1774||miv_rv32_ram_singleport_lp.v(25465);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25465
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1775);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1775||miv_rv32_ram_singleport_lp.v(25376);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25376
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1776);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1776||miv_rv32_ram_singleport_lp.v(25295);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25295
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1777);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1777||miv_rv32_ram_singleport_lp.v(25265);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25265
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R24C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1778);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1778||miv_rv32_ram_singleport_lp.v(25182);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25182
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1779);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1779||miv_rv32_ram_singleport_lp.v(25159);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25159
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[6] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1780);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1780||miv_rv32_ram_singleport_lp.v(25104);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25104
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1781);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1781||miv_rv32_ram_singleport_lp.v(25049);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/25049
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1782);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1782||miv_rv32_ram_singleport_lp.v(24993);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24993
Implementation;Synthesis||CL168||@W:Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1783);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1783||miv_rv32_ram_singleport_lp.v(24990);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24990
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1784);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1784||miv_rv32_ram_singleport_lp.v(24953);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24953
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1785);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1785||miv_rv32_ram_singleport_lp.v(24901);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24901
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1786);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1786||miv_rv32_ram_singleport_lp.v(24863);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24863
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1787);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1787||miv_rv32_ram_singleport_lp.v(24853);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24853
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1788);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1788||miv_rv32_ram_singleport_lp.v(24804);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24804
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1789);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1789||miv_rv32_ram_singleport_lp.v(24764);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24764
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1790);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1790||miv_rv32_ram_singleport_lp.v(24686);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24686
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1791);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1791||miv_rv32_ram_singleport_lp.v(24667);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24667
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1792);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1792||miv_rv32_ram_singleport_lp.v(24622);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24622
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R31C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1793);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1793||miv_rv32_ram_singleport_lp.v(24548);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24548
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1794);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1794||miv_rv32_ram_singleport_lp.v(24502);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24502
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1795);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1795||miv_rv32_ram_singleport_lp.v(24492);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24492
Implementation;Synthesis||CL168||@W:Removing instance CFG3_22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1796);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1796||miv_rv32_ram_singleport_lp.v(24490);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24490
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1797);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1797||miv_rv32_ram_singleport_lp.v(24451);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24451
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1798);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1798||miv_rv32_ram_singleport_lp.v(24412);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24412
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1799);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1799||miv_rv32_ram_singleport_lp.v(24308);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24308
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1800);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1800||miv_rv32_ram_singleport_lp.v(24268);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24268
Implementation;Synthesis||CL168||@W:Removing instance CFG3_11 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1801);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1801||miv_rv32_ram_singleport_lp.v(24254);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24254
Implementation;Synthesis||CL168||@W:Removing instance CFG3_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1802);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1802||miv_rv32_ram_singleport_lp.v(24231);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24231
Implementation;Synthesis||CL168||@W:Removing instance CFG3_21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1803);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1803||miv_rv32_ram_singleport_lp.v(24202);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24202
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R25C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1804);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1804||miv_rv32_ram_singleport_lp.v(24148);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24148
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1805);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1805||miv_rv32_ram_singleport_lp.v(24142);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24142
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R28C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1806);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1806||miv_rv32_ram_singleport_lp.v(24105);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24105
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1807);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1807||miv_rv32_ram_singleport_lp.v(24033);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24033
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1808);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1808||miv_rv32_ram_singleport_lp.v(24029);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/24029
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1809);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1809||miv_rv32_ram_singleport_lp.v(23903);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23903
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1810);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1810||miv_rv32_ram_singleport_lp.v(23864);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23864
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1811);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1811||miv_rv32_ram_singleport_lp.v(23805);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23805
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[7] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1812);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1812||miv_rv32_ram_singleport_lp.v(23799);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23799
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1813);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1813||miv_rv32_ram_singleport_lp.v(23753);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23753
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1814);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1814||miv_rv32_ram_singleport_lp.v(23685);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23685
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[5] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1815);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1815||miv_rv32_ram_singleport_lp.v(23662);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23662
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1816);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1816||miv_rv32_ram_singleport_lp.v(23601);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23601
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1817);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1817||miv_rv32_ram_singleport_lp.v(23540);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23540
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1818);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1818||miv_rv32_ram_singleport_lp.v(23490);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23490
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1819);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1819||miv_rv32_ram_singleport_lp.v(23440);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23440
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1820);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1820||miv_rv32_ram_singleport_lp.v(23401);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23401
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1821);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1821||miv_rv32_ram_singleport_lp.v(23338);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23338
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1822);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1822||miv_rv32_ram_singleport_lp.v(23292);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23292
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R26C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1823);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1823||miv_rv32_ram_singleport_lp.v(23222);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23222
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1824);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1824||miv_rv32_ram_singleport_lp.v(23130);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23130
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1825);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1825||miv_rv32_ram_singleport_lp.v(23092);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23092
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1826);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1826||miv_rv32_ram_singleport_lp.v(23071);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23071
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1827);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1827||miv_rv32_ram_singleport_lp.v(23012);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/23012
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1828);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1828||miv_rv32_ram_singleport_lp.v(22972);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22972
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1829);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1829||miv_rv32_ram_singleport_lp.v(22882);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22882
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1830);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1830||miv_rv32_ram_singleport_lp.v(22821);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22821
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1831);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1831||miv_rv32_ram_singleport_lp.v(22779);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22779
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1832);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1832||miv_rv32_ram_singleport_lp.v(22733);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22733
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R27C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1833);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1833||miv_rv32_ram_singleport_lp.v(22687);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22687
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1834);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1834||miv_rv32_ram_singleport_lp.v(22671);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22671
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1835);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1835||miv_rv32_ram_singleport_lp.v(22665);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22665
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1836);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1836||miv_rv32_ram_singleport_lp.v(22600);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22600
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1837);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1837||miv_rv32_ram_singleport_lp.v(22556);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22556
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1838);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1838||miv_rv32_ram_singleport_lp.v(22510);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22510
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1839);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1839||miv_rv32_ram_singleport_lp.v(22433);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22433
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1840);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1840||miv_rv32_ram_singleport_lp.v(22330);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22330
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1841);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1841||miv_rv32_ram_singleport_lp.v(22260);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22260
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1842);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1842||miv_rv32_ram_singleport_lp.v(22193);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22193
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1843);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1843||miv_rv32_ram_singleport_lp.v(22147);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22147
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R29C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1844);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1844||miv_rv32_ram_singleport_lp.v(22094);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/22094
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1845);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1845||miv_rv32_ram_singleport_lp.v(21997);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21997
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1846);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1846||miv_rv32_ram_singleport_lp.v(21988);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21988
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1847);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1847||miv_rv32_ram_singleport_lp.v(21943);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21943
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R30C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1848);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1848||miv_rv32_ram_singleport_lp.v(21894);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21894
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1849);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1849||miv_rv32_ram_singleport_lp.v(21848);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21848
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1850);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1850||miv_rv32_ram_singleport_lp.v(21845);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21845
Implementation;Synthesis||CL168||@W:Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1851);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1851||miv_rv32_ram_singleport_lp.v(21838);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21838
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1852);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1852||miv_rv32_ram_singleport_lp.v(21814);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21814
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1853);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1853||miv_rv32_ram_singleport_lp.v(21791);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21791
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1854);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1854||miv_rv32_ram_singleport_lp.v(21713);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21713
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1855);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1855||miv_rv32_ram_singleport_lp.v(21667);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21667
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1856);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1856||miv_rv32_ram_singleport_lp.v(21589);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21589
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1857);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1857||miv_rv32_ram_singleport_lp.v(21586);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21586
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1858);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1858||miv_rv32_ram_singleport_lp.v(21578);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21578
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1859);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1859||miv_rv32_ram_singleport_lp.v(21562);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21562
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1860);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1860||miv_rv32_ram_singleport_lp.v(21440);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21440
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1861);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1861||miv_rv32_ram_singleport_lp.v(21385);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21385
Implementation;Synthesis||CL168||@W:Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1862);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1862||miv_rv32_ram_singleport_lp.v(21341);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21341
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R18C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1863);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1863||miv_rv32_ram_singleport_lp.v(21304);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21304
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1864);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1864||miv_rv32_ram_singleport_lp.v(21236);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21236
Implementation;Synthesis||CL168||@W:Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1865);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1865||miv_rv32_ram_singleport_lp.v(21193);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21193
Implementation;Synthesis||CL168||@W:Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.||top.srr(1866);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1866||miv_rv32_ram_singleport_lp.v(21098);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v'/linenumber/21098
Implementation;Synthesis||CL169||@W:Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers.||top.srr(1871);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1871||miv_rv32_subsys_merged.v(10961);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10961
Implementation;Synthesis||CL169||@W:Pruning unused register tcm_tas_access_disable_reg. Make sure that there are no unused intermediate registers.||top.srr(1872);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1872||miv_rv32_subsys_merged.v(10961);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10961
Implementation;Synthesis||CL265||@W:Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal.||top.srr(1873);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1873||miv_rv32_subsys_merged.v(11237);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/11237
Implementation;Synthesis||CL271||@W:Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||top.srr(1874);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1874||miv_rv32_subsys_merged.v(11056);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/11056
Implementation;Synthesis||CS263||@W:Port-width mismatch for port cpu_i_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.||top.srr(1876);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1876||miv_rv32_subsys_merged.v(1481);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/1481
Implementation;Synthesis||CS263||@W:Port-width mismatch for port cpu_d_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.||top.srr(1877);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1877||miv_rv32_subsys_merged.v(1494);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/1494
Implementation;Synthesis||CS263||@W:Port-width mismatch for port udma_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.||top.srr(1878);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1878||miv_rv32_subsys_merged.v(1509);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/1509
Implementation;Synthesis||CS263||@W:Port-width mismatch for port tcm_tas_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.||top.srr(1879);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/1879||miv_rv32_subsys_merged.v(1526);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/1526
Implementation;Synthesis||CG360||@W:Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it.||top.srr(2025);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2025||miv_rv32.v(343);liberoaction://cross_probe/hdl/file/'<project>\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v'/linenumber/343
Implementation;Synthesis||CS263||@W:Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port.||top.srr(2028);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2028||MIV_RV32_C0.v(305);liberoaction://cross_probe/hdl/file/'<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.v'/linenumber/305
Implementation;Synthesis||CG781||@W:Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2063);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2063||PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v'/linenumber/70
Implementation;Synthesis||CG781||@W:Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2064);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2064||PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v'/linenumber/70
Implementation;Synthesis||CG781||@W:Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2067);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2067||PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v(64);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v'/linenumber/64
Implementation;Synthesis||CG781||@W:Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2070);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2070||PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v(67);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v'/linenumber/67
Implementation;Synthesis||CG781||@W:Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2073);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2073||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/49
Implementation;Synthesis||CG781||@W:Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2074);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2074||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/49
Implementation;Synthesis||CG781||@W:Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2075);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2075||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/49
Implementation;Synthesis||CG781||@W:Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2076);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2076||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/50
Implementation;Synthesis||CG781||@W:Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2077);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2077||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/50
Implementation;Synthesis||CG781||@W:Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2078);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2078||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/50
Implementation;Synthesis||CG781||@W:Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2079);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2079||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/50
Implementation;Synthesis||CG781||@W:Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2080);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2080||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/50
Implementation;Synthesis||CG781||@W:Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2081);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2081||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/51
Implementation;Synthesis||CG781||@W:Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2082);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2082||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/51
Implementation;Synthesis||CG781||@W:Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2083);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2083||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/51
Implementation;Synthesis||CG781||@W:Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2084);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2084||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/51
Implementation;Synthesis||CG781||@W:Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2085);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2085||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/52
Implementation;Synthesis||CG781||@W:Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2086);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2086||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/52
Implementation;Synthesis||CG781||@W:Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2087);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2087||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/52
Implementation;Synthesis||CG781||@W:Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2088);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2088||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/54
Implementation;Synthesis||CG781||@W:Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2089);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2089||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/54
Implementation;Synthesis||CG781||@W:Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2090);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2090||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(59);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/59
Implementation;Synthesis||CG781||@W:Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2091);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2091||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/94
Implementation;Synthesis||CG781||@W:Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. ||top.srr(2092);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2092||PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v'/linenumber/94
Implementation;Synthesis||CG360||@W:Removing wire pause_sync_0_i, as there is no assignment to it.||top.srr(2100);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2100||PF_LANECTRL_PAUSE_SYNC.v(21);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/21
Implementation;Synthesis||CG168||@W:Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type ||top.srr(2111);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2111||PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v(47);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v'/linenumber/47
Implementation;Synthesis||CG360||@W:Removing wire pause_sync_0_i, as there is no assignment to it.||top.srr(2125);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2125||PF_LANECTRL_PAUSE_SYNC.v(21);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/21
Implementation;Synthesis||CL246||@W:Input port bits 9 to 7 of rx_data[9:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2143);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2143||SSDetect.v(24);liberoaction://cross_probe/hdl/file/'<project>\hdl\SSDetect.v'/linenumber/24
Implementation;Synthesis||CL159||@N: Input CLK is unused.||top.srr(2154);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2154||PF_LANECTRL_PAUSE_SYNC.v(15);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/15
Implementation;Synthesis||CL159||@N: Input RESET is unused.||top.srr(2155);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2155||PF_LANECTRL_PAUSE_SYNC.v(15);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/15
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register state.||top.srr(2158);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2158||CoreDelayCode_TIP.v(59);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v'/linenumber/59
Implementation;Synthesis||CL159||@N: Input DLL_LOCK is unused.||top.srr(2177);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2177||PF_IOD_CDR_C0.v(70);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v'/linenumber/70
Implementation;Synthesis||CL159||@N: Input PLL_LOCK is unused.||top.srr(2178);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2178||PF_IOD_CDR_C0.v(77);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v'/linenumber/77
Implementation;Synthesis||CL159||@N: Input CLK is unused.||top.srr(2185);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2185||PF_LANECTRL_PAUSE_SYNC.v(15);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/15
Implementation;Synthesis||CL159||@N: Input RESET is unused.||top.srr(2186);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2186||PF_LANECTRL_PAUSE_SYNC.v(15);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v'/linenumber/15
Implementation;Synthesis||CL159||@N: Input FAB_CLK is unused.||top.srr(2197);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2197||PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(31);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v'/linenumber/31
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register tune_st.||top.srr(2204);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2204||corecdr4_cntl_tip.v(117);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v'/linenumber/117
Implementation;Synthesis||CL159||@N: Input mtime_count_in is unused.||top.srr(2231);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2231||miv_rv32_subsys_merged.v(13005);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/13005
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register cpu_d_wr_rd_state.||top.srr(2246);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2246||miv_rv32_subsys_merged.v(11056);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/11056
Implementation;Synthesis||CL279||@W:Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||top.srr(2252);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2252||miv_rv32_subsys_merged.v(11056);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/11056
Implementation;Synthesis||CL246||@W:Input port bits 1 to 0 of cpu_i_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2253);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2253||miv_rv32_subsys_merged.v(10831);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10831
Implementation;Synthesis||CL246||@W:Input port bits 1 to 0 of cpu_d_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2254);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2254||miv_rv32_subsys_merged.v(10844);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10844
Implementation;Synthesis||CL159||@N: Input subsys_parity_en is unused.||top.srr(2256);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2256||miv_rv32_subsys_merged.v(10821);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10821
Implementation;Synthesis||CL159||@N: Input cpu_i_req_rd_byte_en is unused.||top.srr(2257);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2257||miv_rv32_subsys_merged.v(10830);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10830
Implementation;Synthesis||CL159||@N: Input cpu_i_req_addr_p is unused.||top.srr(2258);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2258||miv_rv32_subsys_merged.v(10832);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10832
Implementation;Synthesis||CL159||@N: Input cpu_i_resp_ready is unused.||top.srr(2259);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2259||miv_rv32_subsys_merged.v(10834);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10834
Implementation;Synthesis||CL159||@N: Input cpu_d_req_rd_byte_en is unused.||top.srr(2260);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2260||miv_rv32_subsys_merged.v(10840);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10840
Implementation;Synthesis||CL159||@N: Input cpu_d_req_read is unused.||top.srr(2261);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2261||miv_rv32_subsys_merged.v(10842);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10842
Implementation;Synthesis||CL159||@N: Input cpu_d_req_write is unused.||top.srr(2262);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2262||miv_rv32_subsys_merged.v(10843);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10843
Implementation;Synthesis||CL159||@N: Input cpu_d_req_addr_p is unused.||top.srr(2263);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2263||miv_rv32_subsys_merged.v(10845);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10845
Implementation;Synthesis||CL159||@N: Input cpu_d_req_wr_data_p is unused.||top.srr(2264);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2264||miv_rv32_subsys_merged.v(10847);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10847
Implementation;Synthesis||CL159||@N: Input cpu_d_resp_ready is unused.||top.srr(2265);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2265||miv_rv32_subsys_merged.v(10849);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10849
Implementation;Synthesis||CL159||@N: Input udma_req_valid is unused.||top.srr(2266);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2266||miv_rv32_subsys_merged.v(10855);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10855
Implementation;Synthesis||CL159||@N: Input udma_req_rd_byte_en is unused.||top.srr(2267);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2267||miv_rv32_subsys_merged.v(10857);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10857
Implementation;Synthesis||CL159||@N: Input udma_req_wr_byte_en is unused.||top.srr(2268);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2268||miv_rv32_subsys_merged.v(10858);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10858
Implementation;Synthesis||CL159||@N: Input udma_req_read is unused.||top.srr(2269);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2269||miv_rv32_subsys_merged.v(10859);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10859
Implementation;Synthesis||CL159||@N: Input udma_req_write is unused.||top.srr(2270);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2270||miv_rv32_subsys_merged.v(10860);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10860
Implementation;Synthesis||CL159||@N: Input udma_req_addr is unused.||top.srr(2271);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2271||miv_rv32_subsys_merged.v(10861);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10861
Implementation;Synthesis||CL159||@N: Input udma_req_addr_p is unused.||top.srr(2272);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2272||miv_rv32_subsys_merged.v(10862);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10862
Implementation;Synthesis||CL159||@N: Input udma_req_len is unused.||top.srr(2273);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2273||miv_rv32_subsys_merged.v(10863);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10863
Implementation;Synthesis||CL159||@N: Input udma_req_wr_data is unused.||top.srr(2274);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2274||miv_rv32_subsys_merged.v(10864);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10864
Implementation;Synthesis||CL159||@N: Input udma_req_wr_data_p is unused.||top.srr(2275);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2275||miv_rv32_subsys_merged.v(10865);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10865
Implementation;Synthesis||CL159||@N: Input udma_resp_ready is unused.||top.srr(2276);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2276||miv_rv32_subsys_merged.v(10867);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10867
Implementation;Synthesis||CL159||@N: Input tcm_dma_access_disable is unused.||top.srr(2277);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2277||miv_rv32_subsys_merged.v(10874);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10874
Implementation;Synthesis||CL159||@N: Input tcm_tas_access_disable is unused.||top.srr(2278);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2278||miv_rv32_subsys_merged.v(10875);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10875
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_valid is unused.||top.srr(2279);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2279||miv_rv32_subsys_merged.v(10876);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10876
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_rd_byte_en is unused.||top.srr(2280);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2280||miv_rv32_subsys_merged.v(10878);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10878
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_wr_byte_en is unused.||top.srr(2281);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2281||miv_rv32_subsys_merged.v(10879);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10879
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_addr is unused.||top.srr(2282);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2282||miv_rv32_subsys_merged.v(10880);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10880
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_addr_p is unused.||top.srr(2283);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2283||miv_rv32_subsys_merged.v(10881);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10881
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_wr_data is unused.||top.srr(2284);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2284||miv_rv32_subsys_merged.v(10882);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10882
Implementation;Synthesis||CL159||@N: Input tcm_tas_req_wr_data_p is unused.||top.srr(2285);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2285||miv_rv32_subsys_merged.v(10883);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10883
Implementation;Synthesis||CL159||@N: Input tcm_tas_resp_ready is unused.||top.srr(2286);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2286||miv_rv32_subsys_merged.v(10885);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10885
Implementation;Synthesis||CL159||@N: Input tcm_ram_sb_in is unused.||top.srr(2287);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2287||miv_rv32_subsys_merged.v(10890);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10890
Implementation;Synthesis||CL159||@N: Input tcm_ecc_error_injection is unused.||top.srr(2288);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2288||miv_rv32_subsys_merged.v(10891);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10891
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register hipri_req_ptr.||top.srr(2293);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2293||miv_rv32_subsys_merged.v(10391);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10391
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register gen_apb_byte_shim.apb_st.||top.srr(2305);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2305||miv_rv32_subsys_merged.v(6231);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6231
Implementation;Synthesis||CL159||@N: Input subsys_parity_en is unused.||top.srr(2314);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2314||miv_rv32_subsys_merged.v(6063);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6063
Implementation;Synthesis||CL159||@N: Input cpu_i_req_rd_byte_en is unused.||top.srr(2315);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2315||miv_rv32_subsys_merged.v(6070);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6070
Implementation;Synthesis||CL159||@N: Input cpu_i_req_addr_p is unused.||top.srr(2316);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2316||miv_rv32_subsys_merged.v(6072);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6072
Implementation;Synthesis||CL159||@N: Input cpu_i_resp_ready is unused.||top.srr(2317);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2317||miv_rv32_subsys_merged.v(6074);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6074
Implementation;Synthesis||CL159||@N: Input cpu_d_req_rd_byte_en is unused.||top.srr(2318);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2318||miv_rv32_subsys_merged.v(6080);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6080
Implementation;Synthesis||CL159||@N: Input cpu_d_req_addr_p is unused.||top.srr(2319);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2319||miv_rv32_subsys_merged.v(6083);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6083
Implementation;Synthesis||CL159||@N: Input cpu_d_resp_ready is unused.||top.srr(2320);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2320||miv_rv32_subsys_merged.v(6087);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6087
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register hipri_req_ptr.||top.srr(2325);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2325||miv_rv32_subsys_merged.v(10391);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10391
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register debug_state.||top.srr(2335);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2335||miv_rv32_subsys_merged.v(14736);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14736
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register command_reg_state.||top.srr(2344);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2344||miv_rv32_subsys_merged.v(14337);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14337
Implementation;Synthesis||CL159||@N: Input dmi_resp_ready is unused.||top.srr(2345);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2345||miv_rv32_subsys_merged.v(13800);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/13800
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register sba_state.||top.srr(2348);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2348||miv_rv32_subsys_merged.v(15192);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15192
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat.||top.srr(2361);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2361||miv_rv32_subsys_merged.v(16135);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16135
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState.||top.srr(2368);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2368||miv_rv32_subsys_merged.v(16013);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16013
Implementation;Synthesis||CL159||@N: Input dtm_req_ready is unused.||top.srr(2387);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2387||miv_rv32_subsys_merged.v(15942);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15942
Implementation;Synthesis||CL159||@N: Input m_timer_irq is unused.||top.srr(2391);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2391||miv_rv32_subsys_merged.v(191);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/191
Implementation;Synthesis||CL159||@N: Input tcm1_cpu_access_disable is unused.||top.srr(2392);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2392||miv_rv32_subsys_merged.v(227);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/227
Implementation;Synthesis||CL159||@N: Input tcm1_dma_access_disable is unused.||top.srr(2393);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2393||miv_rv32_subsys_merged.v(228);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/228
Implementation;Synthesis||CL159||@N: Input tcm1_tas_access_disable is unused.||top.srr(2394);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2394||miv_rv32_subsys_merged.v(229);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/229
Implementation;Synthesis||CL159||@N: Input tcm_tas_paddr is unused.||top.srr(2395);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2395||miv_rv32_subsys_merged.v(230);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/230
Implementation;Synthesis||CL159||@N: Input tcm_tas_paddr_p is unused.||top.srr(2396);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2396||miv_rv32_subsys_merged.v(231);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/231
Implementation;Synthesis||CL159||@N: Input tcm_tas_pprot is unused.||top.srr(2397);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2397||miv_rv32_subsys_merged.v(232);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/232
Implementation;Synthesis||CL159||@N: Input tcm_tas_psel is unused.||top.srr(2398);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2398||miv_rv32_subsys_merged.v(233);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/233
Implementation;Synthesis||CL159||@N: Input tcm_tas_penable is unused.||top.srr(2399);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2399||miv_rv32_subsys_merged.v(234);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/234
Implementation;Synthesis||CL159||@N: Input tcm_tas_pwrite is unused.||top.srr(2400);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2400||miv_rv32_subsys_merged.v(235);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/235
Implementation;Synthesis||CL159||@N: Input tcm_tas_pwdata is unused.||top.srr(2401);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2401||miv_rv32_subsys_merged.v(236);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/236
Implementation;Synthesis||CL159||@N: Input tcm_tas_pwdata_p is unused.||top.srr(2402);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2402||miv_rv32_subsys_merged.v(237);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/237
Implementation;Synthesis||CL159||@N: Input tcm1_ram_sb_in is unused.||top.srr(2403);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2403||miv_rv32_subsys_merged.v(248);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/248
Implementation;Synthesis||CL159||@N: Input axi_aclk_en is unused.||top.srr(2404);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2404||miv_rv32_subsys_merged.v(252);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/252
Implementation;Synthesis||CL159||@N: Input axi_arready is unused.||top.srr(2405);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2405||miv_rv32_subsys_merged.v(261);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/261
Implementation;Synthesis||CL159||@N: Input axi_rresp is unused.||top.srr(2406);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2406||miv_rv32_subsys_merged.v(264);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/264
Implementation;Synthesis||CL159||@N: Input axi_rdata is unused.||top.srr(2407);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2407||miv_rv32_subsys_merged.v(265);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/265
Implementation;Synthesis||CL159||@N: Input axi_rlast is unused.||top.srr(2408);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2408||miv_rv32_subsys_merged.v(266);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/266
Implementation;Synthesis||CL159||@N: Input axi_rid is unused.||top.srr(2409);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2409||miv_rv32_subsys_merged.v(267);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/267
Implementation;Synthesis||CL159||@N: Input axi_rvalid is unused.||top.srr(2410);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2410||miv_rv32_subsys_merged.v(269);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/269
Implementation;Synthesis||CL159||@N: Input axi_r_data_p is unused.||top.srr(2411);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2411||miv_rv32_subsys_merged.v(270);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/270
Implementation;Synthesis||CL159||@N: Input axi_awready is unused.||top.srr(2412);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2412||miv_rv32_subsys_merged.v(280);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/280
Implementation;Synthesis||CL159||@N: Input axi_wready is unused.||top.srr(2413);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2413||miv_rv32_subsys_merged.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/286
Implementation;Synthesis||CL159||@N: Input axi_bresp is unused.||top.srr(2414);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2414||miv_rv32_subsys_merged.v(289);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/289
Implementation;Synthesis||CL159||@N: Input axi_bid is unused.||top.srr(2415);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2415||miv_rv32_subsys_merged.v(290);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/290
Implementation;Synthesis||CL159||@N: Input axi_bvalid is unused.||top.srr(2416);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2416||miv_rv32_subsys_merged.v(292);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/292
Implementation;Synthesis||CL159||@N: Input ahb_hrdata is unused.||top.srr(2417);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2417||miv_rv32_subsys_merged.v(305);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/305
Implementation;Synthesis||CL159||@N: Input ahb_hrdata_p is unused.||top.srr(2418);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2418||miv_rv32_subsys_merged.v(306);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/306
Implementation;Synthesis||CL159||@N: Input ahb_hready is unused.||top.srr(2419);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2419||miv_rv32_subsys_merged.v(307);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/307
Implementation;Synthesis||CL159||@N: Input ahb_hresp is unused.||top.srr(2420);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2420||miv_rv32_subsys_merged.v(308);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/308
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_apb_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2423);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2423||miv_rv32_subsys_merged.v(2494);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2494
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_apb_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2424);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2424||miv_rv32_subsys_merged.v(2495);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2495
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_subsys_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2425);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2425||miv_rv32_subsys_merged.v(2500);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2500
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_subsys_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2426);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2426||miv_rv32_subsys_merged.v(2501);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2501
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2427);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2427||miv_rv32_subsys_merged.v(2502);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2502
Implementation;Synthesis||CL246||@W:Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2428);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2428||miv_rv32_subsys_merged.v(2503);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2503
Implementation;Synthesis||CL159||@N: Input cfg_axi_start_addr is unused.||top.srr(2429);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2429||miv_rv32_subsys_merged.v(2492);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2492
Implementation;Synthesis||CL159||@N: Input cfg_axi_end_addr is unused.||top.srr(2430);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2430||miv_rv32_subsys_merged.v(2493);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2493
Implementation;Synthesis||CL159||@N: Input cfg_ahb_start_addr is unused.||top.srr(2431);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2431||miv_rv32_subsys_merged.v(2496);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2496
Implementation;Synthesis||CL159||@N: Input cfg_ahb_end_addr is unused.||top.srr(2432);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2432||miv_rv32_subsys_merged.v(2497);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2497
Implementation;Synthesis||CL159||@N: Input cfg_udma_ctrl_start_addr is unused.||top.srr(2433);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2433||miv_rv32_subsys_merged.v(2498);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2498
Implementation;Synthesis||CL159||@N: Input cfg_udma_ctrl_end_addr is unused.||top.srr(2434);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2434||miv_rv32_subsys_merged.v(2499);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2499
Implementation;Synthesis||CL159||@N: Input cfg_tcm1_start_addr is unused.||top.srr(2435);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2435||miv_rv32_subsys_merged.v(2504);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2504
Implementation;Synthesis||CL159||@N: Input cfg_tcm1_end_addr is unused.||top.srr(2436);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2436||miv_rv32_subsys_merged.v(2505);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2505
Implementation;Synthesis||CL159||@N: Input apb_trx_os_d_rd is unused.||top.srr(2437);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2437||miv_rv32_subsys_merged.v(2575);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2575
Implementation;Synthesis||CL159||@N: Input apb_trx_os_d_wr is unused.||top.srr(2438);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2438||miv_rv32_subsys_merged.v(2576);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2576
Implementation;Synthesis||CL159||@N: Input tcm0_trx_os_d_rd is unused.||top.srr(2439);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2439||miv_rv32_subsys_merged.v(2604);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2604
Implementation;Synthesis||CL159||@N: Input tcm0_trx_os_d_wr is unused.||top.srr(2440);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2440||miv_rv32_subsys_merged.v(2605);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2605
Implementation;Synthesis||CL159||@N: Input tcm1_i_req_ready is unused.||top.srr(2441);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2441||miv_rv32_subsys_merged.v(2611);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2611
Implementation;Synthesis||CL159||@N: Input tcm1_d_req_ready is unused.||top.srr(2442);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2442||miv_rv32_subsys_merged.v(2621);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2621
Implementation;Synthesis||CL159||@N: Input tcm1_trx_os_d_rd is unused.||top.srr(2443);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2443||miv_rv32_subsys_merged.v(2635);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2635
Implementation;Synthesis||CL159||@N: Input tcm1_trx_os_d_wr is unused.||top.srr(2444);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2444||miv_rv32_subsys_merged.v(2636);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2636
Implementation;Synthesis||CL159||@N: Input axi_i_req_ready is unused.||top.srr(2445);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2445||miv_rv32_subsys_merged.v(2642);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2642
Implementation;Synthesis||CL159||@N: Input axi_i_resp_last is unused.||top.srr(2446);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2446||miv_rv32_subsys_merged.v(2647);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2647
Implementation;Synthesis||CL159||@N: Input axi_d_req_ready is unused.||top.srr(2447);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2447||miv_rv32_subsys_merged.v(2653);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2653
Implementation;Synthesis||CL159||@N: Input axi_trx_os_d_rd is unused.||top.srr(2448);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2448||miv_rv32_subsys_merged.v(2668);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/2668
Implementation;Synthesis||CL246||@W:Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2453);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2453||miv_rv32_subsys_merged.v(4490);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/4490
Implementation;Synthesis||CL246||@W:Input port bits 31 to 3 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2454);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2454||miv_rv32_subsys_merged.v(4495);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/4495
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_data, depth=2, width=7||top.srr(2457);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2457||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_data, depth=2, width=11||top.srr(2462);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2462||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_data, depth=2, width=6||top.srr(2465);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2465||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||CL247||@W:Input port bit 5 of waddr0[5:0] is unused||top.srr(2470);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2470||miv_rv32_hart_merged.v(6360);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6360
Implementation;Synthesis||CL247||@W:Input port bit 1 of excpt_trigger[1:0] is unused||top.srr(2484);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2484||miv_rv32_hart_merged.v(1854);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/1854
Implementation;Synthesis||CL246||@W:Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2504);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2504||miv_rv32_hart_merged.v(6887);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6887
Implementation;Synthesis||CL246||@W:Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2505);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2505||miv_rv32_hart_merged.v(6887);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6887
Implementation;Synthesis||CL246||@W:Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2506);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2506||miv_rv32_hart_merged.v(6887);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6887
Implementation;Synthesis||CL246||@W:Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2507);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2507||miv_rv32_hart_merged.v(6887);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6887
Implementation;Synthesis||CL246||@W:Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2508);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2508||miv_rv32_hart_merged.v(6887);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6887
Implementation;Synthesis||CL246||@W:Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2509);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2509||miv_rv32_hart_merged.v(6896);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6896
Implementation;Synthesis||CL279||@W:Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.||top.srr(2516);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2516||miv_rv32_hart_merged.v(11446);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/11446
Implementation;Synthesis||CL260||@W:Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(2523);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2523||miv_rv32_hart_merged.v(19324);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19324
Implementation;Synthesis||CL260||@W:Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(2524);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2524||miv_rv32_hart_merged.v(19324);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19324
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(2525);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2525||miv_rv32_hart_merged.v(19324);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19324
Implementation;Synthesis||CL260||@W:Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(2526);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2526||miv_rv32_hart_merged.v(19324);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19324
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16||top.srr(2531);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2531||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32||top.srr(2532);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2532||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2||top.srr(2533);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2533||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||CL134||@N: Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2||top.srr(2534);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2534||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register state.||top.srr(2539);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2539||fifo_to_tpsram_bridge.v(45);liberoaction://cross_probe/hdl/file/'<project>\hdl\fifo_to_tpsram_bridge.v'/linenumber/45
Implementation;Synthesis||CL246||@W:Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2548);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2548||CoreUARTapb.v(104);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v'/linenumber/104
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register rx_state.||top.srr(2554);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2554||Rx_async.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/286
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register xmit_state.||top.srr(2563);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2563||Tx_async.v(119);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v'/linenumber/119
Implementation;Synthesis||CL246||@W:Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2747);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2747||spi.v(70);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v'/linenumber/70
Implementation;Synthesis||CL260||@W:Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.||top.srr(2750);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2750||spi_chanctrl.v(823);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/823
Implementation;Synthesis||CL201||@N: Trying to extract state machine for register mtx_state.||top.srr(2751);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2751||spi_chanctrl.v(416);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/416
Implementation;Synthesis||CL134||@N: Found RAM fifo_mem_q, depth=32, width=1||top.srr(2764);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2764||spi_fifo.v(101);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/101
Implementation;Synthesis||CL134||@N: Found RAM fifo_mem_q, depth=32, width=16||top.srr(2765);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2765||spi_fifo.v(101);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/101
Implementation;Synthesis||CL246||@W:Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2770);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2770||spi_rf.v(42);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v'/linenumber/42
Implementation;Synthesis||CL246||@W:Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.||top.srr(2807);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2807||coreapb3.v(75);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/75
Implementation;Synthesis||CL135||@N: Found sequential shift dff with address depth of 16 words and data bit width of 1.||top.srr(2814);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2814||corereset_pf.v(58);liberoaction://cross_probe/hdl/file/'<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v'/linenumber/58
Implementation;Synthesis||FX1183||@W:User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. ||top.srr(2950);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2950||corereset_pf.v(58);liberoaction://cross_probe/hdl/file/'<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v'/linenumber/58
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture. ||top.srr(2951);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2951||miv_rv32_hart_merged.v(18726);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18726
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture. ||top.srr(2952);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2952||miv_rv32_hart_merged.v(18726);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18726
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture. ||top.srr(2953);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2953||miv_rv32_hart_merged.v(18726);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18726
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2954);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2954||miv_rv32_hart_merged.v(11493);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/11493
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2955);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2955||miv_rv32_hart_merged.v(11473);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/11473
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2956);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2956||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2957);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2957||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2958);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2958||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2959);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2959||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2960);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2960||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2961);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2961||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2962);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2962||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(2963);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2963||miv_rv32_subsys_merged.v(14495);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14495
Implementation;Synthesis||BN132||@W:Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(2964);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2964||miv_rv32_subsys_merged.v(14495);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/14495
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture. ||top.srr(2965);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2965||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture. ||top.srr(2966);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2966||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture. ||top.srr(2967);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2967||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture. ||top.srr(2968);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2968||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX1171||@N: Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. ||top.srr(2969);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2969||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture. ||top.srr(2970);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2970||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX1172||@W:User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture. ||top.srr(2971);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2971||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||MO111||@N: Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(2978);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2978||corefifo_c0_corefifo_c0_0_ram_wrapper.v(48);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/48
Implementation;Synthesis||MO111||@N: Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(2979);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2979||corefifo_c0_corefifo_c0_0_ram_wrapper.v(46);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/46
Implementation;Synthesis||MO111||@N: Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(2980);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2980||corefifo_c0_corefifo_c0_0_ram_wrapper.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/49
Implementation;Synthesis||MO111||@N: Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(2981);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2981||corefifo_c0_corefifo_c0_0_ram_wrapper.v(47);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/47
Implementation;Synthesis||MO111||@N: Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2982);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2982||corejtagdebug.v(169);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/169
Implementation;Synthesis||MO111||@N: Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2983);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2983||corejtagdebug.v(176);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/176
Implementation;Synthesis||MO111||@N: Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2984);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2984||corejtagdebug.v(183);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/183
Implementation;Synthesis||MO111||@N: Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2985);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2985||corejtagdebug.v(190);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/190
Implementation;Synthesis||MO111||@N: Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2986);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2986||corejtagdebug.v(32);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/32
Implementation;Synthesis||MO111||@N: Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.||top.srr(2987);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2987||corejtagdebug.v(31);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v'/linenumber/31
Implementation;Synthesis||BN115||@N: Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.||top.srr(2994);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2994||miv_rv32_hart_merged.v(7090);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/7090
Implementation;Synthesis||BN115||@N: Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.||top.srr(2995);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2995||miv_rv32_hart_merged.v(7090);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/7090
Implementation;Synthesis||BN115||@N: Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.||top.srr(2996);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2996||miv_rv32_hart_merged.v(7016);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/7016
Implementation;Synthesis||BN115||@N: Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.||top.srr(2997);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2997||miv_rv32_hart_merged.v(2565);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/2565
Implementation;Synthesis||BN115||@N: Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.||top.srr(2998);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2998||miv_rv32_subsys_merged.v(4653);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/4653
Implementation;Synthesis||BN115||@N: Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.||top.srr(2999);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/2999||miv_rv32_subsys_merged.v(4904);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/4904
Implementation;Synthesis||BN115||@N: Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.||top.srr(3000);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3000||miv_rv32_subsys_merged.v(4923);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/4923
Implementation;Synthesis||BN115||@N: Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances.||top.srr(3001);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3001||pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v(107);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v'/linenumber/107
Implementation;Synthesis||BN115||@N: Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances.||top.srr(3002);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3002||pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v(93);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v'/linenumber/93
Implementation;Synthesis||BN362||@N: Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3003);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3003||spi_fifo.v(111);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/111
Implementation;Synthesis||BN362||@N: Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3004);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3004||spi_fifo.v(111);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/111
Implementation;Synthesis||BN362||@N: Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3005);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3005||spi_fifo.v(111);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/111
Implementation;Synthesis||BN362||@N: Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3006);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3006||spi_fifo.v(111);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/111
Implementation;Synthesis||BN362||@N: Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.||top.srr(3007);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3007||rx_async.v(501);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/501
Implementation;Synthesis||BN362||@N: Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3008);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3008||rx_async.v(501);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/501
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.||top.srr(3009);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3009||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN115||@N: Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.||top.srr(3010);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3010||miv_rv32_hart_merged.v(2594);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/2594
Implementation;Synthesis||BN362||@N: Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3011);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3011||miv_rv32_subsys_merged.v(10461);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10461
Implementation;Synthesis||BN362||@N: Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.||top.srr(3012);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3012||corefifo_sync_scntr.v(579);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/579
Implementation;Synthesis||BN362||@N: Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3013);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3013||miv_rv32_hart_merged.v(6376);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6376
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.||top.srr(3014);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3014||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN362||@N: Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.||top.srr(3015);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3015||miv_rv32_subsys_merged.v(6361);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6361
Implementation;Synthesis||BN362||@N: Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3016);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3016||miv_rv32_hart_merged.v(6097);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6097
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.||top.srr(3017);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3017||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.||top.srr(3018);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3018||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.||top.srr(3019);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3019||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||BN362||@N: Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.||top.srr(3020);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3020||miv_rv32_hart_merged.v(6097);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6097
Implementation;Synthesis||BN362||@N: Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.||top.srr(3021);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3021||corefifo_sync_scntr.v(438);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/438
Implementation;Synthesis||BN362||@N: Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3022);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3022||miv_rv32_subsys_merged.v(16308);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16308
Implementation;Synthesis||BN362||@N: Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.||top.srr(3023);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3023||miv_rv32_hart_merged.v(9775);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9775
Implementation;Synthesis||BN362||@N: Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3024);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3024||spi_chanctrl.v(630);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/630
Implementation;Synthesis||BN362||@N: Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.||top.srr(3025);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3025||spi_chanctrl.v(416);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/416
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.||top.srr(3026);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3026||miv_rv32_hart_merged.v(9245);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9245
Implementation;Synthesis||FX1184||@N: Applying syn_allowed_resources blockrams=952 on top level netlist top ||top.srr(3027);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3027||null;null
Implementation;Synthesis||MT530||@W:Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance. ||top.srr(3092);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3092||pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v(48);liberoaction://cross_probe/hdl/file/'<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v'/linenumber/48
Implementation;Synthesis||MT530||@W:Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance. ||top.srr(3093);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3093||corejtagdebug_uj_jtag.v(215);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v'/linenumber/215
Implementation;Synthesis||FX1143||@N: Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.||top.srr(3095);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3095||null;null
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.||top.srr(3170);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3170||rx_async.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/286
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.||top.srr(3175);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3175||fifo_to_tpsram_bridge.v(45);liberoaction://cross_probe/hdl/file/'<project>\hdl\fifo_to_tpsram_bridge.v'/linenumber/45
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.||top.srr(3200);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3200||miv_rv32_subsys_merged.v(16135);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16135
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.||top.srr(3207);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3207||miv_rv32_subsys_merged.v(15192);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15192
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.||top.srr(3249);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3249||corecdr4_cntl_tip.v(117);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v'/linenumber/117
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.||top.srr(3256);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3256||coredelaycode_tip.v(59);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v'/linenumber/59
Implementation;Synthesis||MF511||@W:Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .||top.srr(3260);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3260||null;null
Implementation;Synthesis||MO111||@N: Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(3315);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3315||corefifo_c0_corefifo_c0_0_ram_wrapper.v(49);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/49
Implementation;Synthesis||MO111||@N: Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(3316);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3316||corefifo_c0_corefifo_c0_0_ram_wrapper.v(48);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/48
Implementation;Synthesis||MO111||@N: Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(3317);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3317||corefifo_c0_corefifo_c0_0_ram_wrapper.v(47);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/47
Implementation;Synthesis||MO111||@N: Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.||top.srr(3318);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3318||corefifo_c0_corefifo_c0_0_ram_wrapper.v(46);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v'/linenumber/46
Implementation;Synthesis||BN362||@N: Removing sequential instance genblk17\.u_corefifo_fwft.reg_valid_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3319);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3319||corefifo_fwft.v(347);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/347
Implementation;Synthesis||BN362||@N: Removing sequential instance genblk17\.u_corefifo_fwft.empty_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.||top.srr(3320);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3320||corefifo_fwft.v(347);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v'/linenumber/347
Implementation;Synthesis||BZ173||@N: ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) mapped in logic.||top.srr(3321);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3321||spi_chanctrl.v(645);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/645
Implementation;Synthesis||MO106||@N: Found ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) with 10 words by 2 bits.||top.srr(3322);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3322||spi_chanctrl.v(645);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/645
Implementation;Synthesis||BZ173||@N: ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic.||top.srr(3323);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3323||miv_rv32_hart_merged.v(19089);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19089
Implementation;Synthesis||MO106||@N: Found ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 3 bits.||top.srr(3324);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3324||miv_rv32_hart_merged.v(19089);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/19089
Implementation;Synthesis||BZ173||@N: ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.||top.srr(3325);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3325||coreapb3.v(267);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/267
Implementation;Synthesis||BZ173||@N: ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.||top.srr(3326);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3326||coreapb3.v(267);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/267
Implementation;Synthesis||MO106||@N: Found ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) with 3 words by 3 bits.||top.srr(3327);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3327||coreapb3.v(267);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v'/linenumber/267
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.||top.srr(3328);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3328||miv_rv32_subsys_merged.v(6231);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/6231
Implementation;Synthesis||MO231||@N: Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memraddr_r[9:0] ||top.srr(3332);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3332||corefifo_sync_scntr.v(636);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/636
Implementation;Synthesis||MO231||@N: Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memwaddr_r[9:0] ||top.srr(3333);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3333||corefifo_sync_scntr.v(620);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/620
Implementation;Synthesis||FX107||@W:RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.||top.srr(3334);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3334||spi_fifo.v(101);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/101
Implementation;Synthesis||FX107||@W:RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.||top.srr(3335);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3335||spi_fifo.v(101);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v'/linenumber/101
Implementation;Synthesis||MO231||@N: Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance stxs_bitcnt[4:0] ||top.srr(3344);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3344||spi_chanctrl.v(823);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/823
Implementation;Synthesis||MO231||@N: Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance spi_clk_count[7:0] ||top.srr(3345);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3345||spi_chanctrl.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/286
Implementation;Synthesis||MF179||@N: Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog))||top.srr(3353);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3353||null;null
Implementation;Synthesis||MO231||@N: Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0] ||top.srr(3394);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3394||clock_gen.v(283);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v'/linenumber/283
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.||top.srr(3409);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3409||rx_async.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/286
Implementation;Synthesis||BN132||@W:Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3410);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3410||rx_async.v(261);liberoaction://cross_probe/hdl/file/'<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v'/linenumber/261
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.||top.srr(3415);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3415||fifo_to_tpsram_bridge.v(45);liberoaction://cross_probe/hdl/file/'<project>\hdl\fifo_to_tpsram_bridge.v'/linenumber/45
Implementation;Synthesis||MO231||@N: Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[9:0] ||top.srr(3416);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3416||fifo_to_tpsram_bridge.v(31);liberoaction://cross_probe/hdl/file/'<project>\hdl\fifo_to_tpsram_bridge.v'/linenumber/31
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[25] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3417);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3417||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3418);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3418||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3419);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3419||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3420);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3420||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3421);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3421||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3422);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3422||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3423);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3423||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3424);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3424||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3425);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3425||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3426);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3426||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3427);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3427||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3428);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3428||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3429);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3429||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3430);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3430||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3431);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3431||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3432);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3432||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3433);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3433||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3434);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3434||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3435);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3435||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3436);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3436||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3437);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3437||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3438);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3438||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3439);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3439||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3440);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3440||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3441);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3441||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3442);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3442||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3443);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3443||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3444);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3444||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3445);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3445||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3446);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3446||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||FX107||@W:RAM u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.||top.srr(3447);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3447||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX702||@N: Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)).||top.srr(3448);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3448||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX702||@N: Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0]||top.srr(3449);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3449||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits.||top.srr(3450);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3450||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].||top.srr(3451);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3451||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].||top.srr(3452);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3452||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].||top.srr(3453);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3453||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].||top.srr(3454);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3454||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].||top.srr(3455);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3455||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].||top.srr(3456);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3456||null;null
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[6:0] is 2 words by 7 bits.||top.srr(3457);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3457||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].||top.srr(3458);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3458||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].||top.srr(3459);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3459||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].||top.srr(3460);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3460||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[3].||top.srr(3461);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3461||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[4].||top.srr(3462);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3462||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[5].||top.srr(3463);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3463||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[6].||top.srr(3464);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3464||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].||top.srr(3465);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3465||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].||top.srr(3466);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3466||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].||top.srr(3467);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3467||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[3].||top.srr(3468);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3468||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[4].||top.srr(3469);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3469||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[5].||top.srr(3470);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3470||null;null
Implementation;Synthesis||FX493||@N: Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[6].||top.srr(3471);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3471||null;null
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] is 2 words by 34 bits.||top.srr(3472);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3472||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] is 2 words by 41 bits.||top.srr(3473);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3473||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3474);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3474||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3475);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3475||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3476);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3476||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3477);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3477||miv_rv32_subsys_merged.v(10047);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10047
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[0] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.||top.srr(3478);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3478||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN362||@N: Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[16] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.||top.srr(3479);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3479||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3480);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3480||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3481);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3481||miv_rv32_subsys_merged.v(15839);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15839
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] is 4 words by 1 bits.||top.srr(3482);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3482||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[0] is 4 words by 1 bits.||top.srr(3483);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3483||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] is 4 words by 32 bits.||top.srr(3484);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3484||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||MF135||@N: RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] is 4 words by 16 bits.||top.srr(3485);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3485||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3486);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3486||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3487);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3487||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3488);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3488||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3489);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3489||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3490);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3490||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3491);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3491||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3492);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3492||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3493);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3493||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3494);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3494||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3495);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3495||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3496);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3496||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3497);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3497||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3498);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3498||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3499);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3499||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3500);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3500||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3501);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3501||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3502);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3502||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3503);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3503||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3504);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3504||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3505);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3505||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3506);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3506||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3507);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3507||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3508);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3508||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3509);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3509||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3510);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3510||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3511);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3511||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3512);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3512||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3513);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3513||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3514);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3514||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3515);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3515||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3516);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3516||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3517);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3517||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3518);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3518||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3519);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3519||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3520);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3520||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3521);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3521||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3522);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3522||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3523);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3523||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3524);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3524||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3525);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3525||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3526);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3526||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3527);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3527||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3528);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3528||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3529);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3529||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3530);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3530||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3531);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3531||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3532);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3532||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3533);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3533||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3534);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3534||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3535);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3535||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3536);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3536||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3537);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3537||miv_rv32_hart_merged.v(18735);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/18735
Implementation;Synthesis||BN362||@N: Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.||top.srr(3538);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3538||miv_rv32_hart_merged.v(9798);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9798
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3539);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3539||miv_rv32_hart_merged.v(9414);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9414
Implementation;Synthesis||MO231||@N: Found counter in view:work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog) instance mul_div_cnt[5:0] ||top.srr(3540);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3540||miv_rv32_hart_merged.v(11446);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/11446
Implementation;Synthesis||MF179||@N: Found 32 by 32 bit equality operator ('==') un152_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog))||top.srr(3541);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3541||miv_rv32_hart_merged.v(11165);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/11165
Implementation;Synthesis||FX107||@W:RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.||top.srr(3543);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3543||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||FX107||@W:RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.||top.srr(3545);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3545||miv_rv32_hart_merged.v(6370);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/6370
Implementation;Synthesis||MF179||@N: Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))||top.srr(3546);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3546||miv_rv32_hart_merged.v(4547);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/4547
Implementation;Synthesis||MF179||@N: Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))||top.srr(3547);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3547||miv_rv32_hart_merged.v(4547);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/4547
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.||top.srr(3572);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3572||miv_rv32_subsys_merged.v(16135);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16135
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.||top.srr(3587);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3587||miv_rv32_subsys_merged.v(15192);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15192
Implementation;Synthesis||MO231||@N: Found counter in view:work.miv_rv32_debug_sba(verilog) instance counter[7:0] ||top.srr(3588);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3588||miv_rv32_subsys_merged.v(15548);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/15548
Implementation;Synthesis||MO231||@N: Found counter in view:work.miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820(verilog) instance mtime_count_out[63:0] ||top.srr(3616);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3616||miv_rv32_subsys_merged.v(13076);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/13076
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.||top.srr(3623);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3623||corecdr4_cntl_tip.v(117);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v'/linenumber/117
Implementation;Synthesis||MO225||@N: There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.||top.srr(3630);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3630||coredelaycode_tip.v(59);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v'/linenumber/59
Implementation;Synthesis||MO231||@N: Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0] ||top.srr(3631);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3631||coredelaycode_tip.v(59);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v'/linenumber/59
Implementation;Synthesis||BN362||@N: Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances.||top.srr(3635);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3635||miv_rv32_hart_merged.v(8721);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/8721
Implementation;Synthesis||BN362||@N: Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3644);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3644||miv_rv32_hart_merged.v(9395);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9395
Implementation;Synthesis||BN362||@N: Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3645);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3645||miv_rv32_hart_merged.v(9775);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/9775
Implementation;Synthesis||BN362||@N: Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3646);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3646||miv_rv32_subsys_merged.v(10391);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10391
Implementation;Synthesis||BN362||@N: Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3647);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3647||miv_rv32_subsys_merged.v(10391);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/10391
Implementation;Synthesis||BN362||@N: Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3648);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3648||corefifo_sync_scntr.v(463);liberoaction://cross_probe/hdl/file/'<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v'/linenumber/463
Implementation;Synthesis||BN132||@W:Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.||top.srr(3652);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3652||miv_rv32_hart_merged.v(5705);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v'/linenumber/5705
Implementation;Synthesis||BN362||@N: Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3662);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3662||miv_rv32_subsys_merged.v(16013);liberoaction://cross_probe/hdl/file/'<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v'/linenumber/16013
Implementation;Synthesis||BN362||@N: Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.||top.srr(3663);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3663||spi_chanctrl.v(286);liberoaction://cross_probe/hdl/file/'<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v'/linenumber/286
Implementation;Synthesis||FP130||@N: Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4035 ||top.srr(3688);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3688||null;null
Implementation;Synthesis||FP130||@N: Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4036 ||top.srr(3689);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3689||null;null
Implementation;Synthesis||FP130||@N: Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4037 ||top.srr(3690);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3690||null;null
Implementation;Synthesis||FP130||@N: Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4038 ||top.srr(3691);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3691||null;null
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3724);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3724||synthesis.fdc(47);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/47
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3725);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3725||synthesis.fdc(48);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/48
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3726);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3726||synthesis.fdc(49);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/49
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3727);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3727||synthesis.fdc(50);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/50
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3728);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3728||synthesis.fdc(51);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/51
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3729);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3729||synthesis.fdc(52);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/52
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3730);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3730||synthesis.fdc(53);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/53
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3731);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3731||synthesis.fdc(54);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/54
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3732);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3732||null;null
Implementation;Synthesis||BW150||@W:Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated||top.srr(3733);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3733||null;null
Implementation;Synthesis||BW156||@W:Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.||top.srr(3734);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3734||null;null
Implementation;Synthesis||MT615||@N: Found clock REF_CLK_0 with period 20.00ns ||top.srr(3745);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3745||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns ||top.srr(3746);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3746||null;null
Implementation;Synthesis||MT615||@N: Found clock REFCLK_P with period 8.00ns ||top.srr(3747);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3747||null;null
Implementation;Synthesis||MT615||@N: Found clock TCK with period 100.00ns ||top.srr(3748);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3748||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns ||top.srr(3749);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3749||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns ||top.srr(3750);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3750||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns ||top.srr(3751);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3751||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns ||top.srr(3752);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3752||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns ||top.srr(3753);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3753||null;null
Implementation;Synthesis||MT615||@N: Found clock PHY_MDC_CLOCK with period 350.00ns ||top.srr(3754);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3754||null;null
Implementation;Synthesis||MT615||@N: Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns ||top.srr(3755);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3755||null;null
Implementation;Synthesis||MT420||@W:Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK.||top.srr(3756);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3756||null;null
Implementation;Synthesis||MT420||@W:Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK_0.||top.srr(3757);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/3757||null;null
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6339);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6339||synthesis.fdc(25);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/25
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6340);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6340||synthesis.fdc(26);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/26
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6341);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6341||synthesis.fdc(27);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/27
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6342);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6342||synthesis.fdc(32);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/32
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6343);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6343||synthesis.fdc(33);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/33
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6344);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6344||synthesis.fdc(34);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/34
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6345);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6345||synthesis.fdc(35);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/35
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6346);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6346||synthesis.fdc(36);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/36
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6347);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6347||synthesis.fdc(37);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/37
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6348);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6348||synthesis.fdc(38);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/38
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6349);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6349||synthesis.fdc(39);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/39
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6350);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6350||synthesis.fdc(40);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/40
Implementation;Synthesis||MT447||@W:Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6351);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6351||synthesis.fdc(41);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/41
Implementation;Synthesis||MT447||@W:Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6352);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6352||synthesis.fdc(42);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/42
Implementation;Synthesis||MT447||@W:Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design ||top.srr(6353);liberoaction://cross_probe/hdl/file/'<project>\synthesis\top.srr'/linenumber/6353||synthesis.fdc(45);liberoaction://cross_probe/hdl/file/'<project>\designer\top\synthesis.fdc'/linenumber/45
Implementation;Place and Route;RootName:top
Implementation;Place and Route||(null)||Please refer to the log file for details about 9 Info(s)||top_layout_log.log;liberoaction://open_report/file/top_layout_log.log||(null);(null)
Implementation;Generate Bitstream;RootName:top
Implementation;Generate Bitstream||(null)||Please refer to the log file for details about 2 Info(s)||top_generateBitstream.log;liberoaction://open_report/file/top_generateBitstream.log||(null);(null)
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