102 lines
6.7 KiB
Tcl
102 lines
6.7 KiB
Tcl
# Written by Synplify Pro version map202309act, Build 395R. Synopsys Run ID: sid1776273489
|
|
# Top Level Design Parameters
|
|
|
|
# Clocks
|
|
create_clock -period 8.000 -waveform {0.000 4.000} -name {REFCLK_P} [get_ports {REFCLK_P}]
|
|
create_clock -period 20.000 -waveform {0.000 10.000} -name {REF_CLK_0} [get_ports {REF_CLK_0}]
|
|
create_clock -period 100.000 -waveform {0.000 50.000} -name {TCK} [get_ports {TCK}]
|
|
create_clock -period 8.000 -waveform {0.000 3.200} -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} [get_pins {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R}]
|
|
create_clock -period 10.000 -waveform {0.000 5.000} -name {PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop} [get_pins {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CDR_CLK}]
|
|
create_clock -period 10.000 -waveform {0.000 5.000} -name {COREJTAGDEBUG_Z5|iUDRCK_inferred_clock} [get_pins {COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst/UDRCK}]
|
|
|
|
# Virtual Clocks
|
|
|
|
# Generated Clocks
|
|
create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by {8} -divide_by {5} -source [get_pins {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/REF_CLK_0}] [get_pins {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0}]
|
|
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by {5} -source [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0}] [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0}]
|
|
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by {5} -source [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0}] [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1}]
|
|
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by {5} -source [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0}] [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2}]
|
|
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by {5} -source [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0}] [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3}]
|
|
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A}] [get_pins {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV}]
|
|
create_generated_clock -name {PHY_MDC_CLOCK} -divide_by {28} -source [get_pins {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0}] [get_pins {PHY_MDC_obuf/PAD}]
|
|
|
|
# Paths Between Clocks
|
|
|
|
# Multicycle Constraints
|
|
|
|
# Point-to-point Delay Constraints
|
|
|
|
# False Path Constraints
|
|
set_false_path -to [get_cells {PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[4] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[3] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[2] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[1] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[0] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[6] PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[5]}]
|
|
set_false_path -to [get_cells {PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag[1]}]
|
|
set_false_path -to [get_cells {PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag[1]}]
|
|
set_false_path -to [get_cells {PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag[1]}]
|
|
set_false_path -from [get_cells {PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane}]
|
|
set_false_path -to [get_cells {PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync[1]}]
|
|
set_false_path -to [get_cells {PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync[1]}]
|
|
|
|
# Output Load Constraints
|
|
|
|
# Driving Cell Constraints
|
|
|
|
# Input Delay Constraints
|
|
set_input_delay {0} -min -add_delay -clock [get_clocks {REF_CLK_0}] [get_ports {RESET_N}]
|
|
set_input_delay {20} -max -add_delay -clock [get_clocks {REF_CLK_0}] [get_ports {RESET_N}]
|
|
set_input_delay {0} -min -add_delay -clock [get_clocks {PHY_MDC_CLOCK}] [get_ports {PHY_MDIO}]
|
|
set_input_delay {20} -max -add_delay -clock [get_clocks {PHY_MDC_CLOCK}] [get_ports {PHY_MDIO}]
|
|
|
|
# Output Delay Constraints
|
|
set_output_delay {10} -max -clock [get_clocks {PHY_MDC_CLOCK}] [get_ports {PHY_MDIO}]
|
|
set_output_delay {-10} -min -clock [get_clocks {PHY_MDC_CLOCK}] [get_ports {PHY_MDIO}]
|
|
|
|
# Wire Loads
|
|
|
|
# Other Constraints
|
|
|
|
# syn_hier Attributes
|
|
|
|
# set_case Attributes
|
|
|
|
# Clock Delay Constraints
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0}] -group [get_clocks {TCK}]
|
|
set_clock_groups -asynchronous -group [get_clocks {PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop}]
|
|
set_clock_groups -asynchronous -group [get_clocks {COREJTAGDEBUG_Z5|iUDRCK_inferred_clock}]
|
|
|
|
# syn_mode Attributes
|
|
|
|
# Cells
|
|
|
|
# Port DRC Rules
|
|
|
|
# Input Transition Constraints
|
|
|
|
# Unused constraints (intentionally commented out)
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]
|
|
# set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
|
|
# set_false_path -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]
|
|
# set_false_path -to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]
|
|
|
|
|
|
# Non-forward-annotatable constraints (intentionally commented out)
|
|
|
|
# Block Path constraints
|
|
|