85 lines
14 KiB
Plaintext
85 lines
14 KiB
Plaintext
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Copyright (C) 1994-2023 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: V-2023.09M-5
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Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
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OS: Windows 10 or later
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Hostname: SOFTWARE-PC
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Implementation : synthesis
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# Written on Wed Apr 15 22:47:57 2026
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##### FILES SYNTAX CHECKED ##############################################
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Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc"
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#Run constraint checker to find more issues with constraints.
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#########################################################################
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No issues found in constraint syntax.
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Clock Summary
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*************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------
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0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
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1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
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2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
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0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT0_GRP 3
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2 .. PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 8.000 generated (from REFCLK_P) Y_DIV_GRP 1410
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT1_GRP 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT2_GRP 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT3_GRP 1
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0 - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 8.000 declared SGMII_CDR_0_0_CLK_OUT_GRP 1323
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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0 - TCK 10.0 MHz 100.000 declared JTAG_Async_2 0
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0 - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0_3 184
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0 - PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz 10.000 inferred Inferred_clkgroup_0_1 2
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====================================================================================================================================================================
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Clock Load Summary
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******************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
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PHY_MDC_CLOCK 0 - - - -
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REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 3 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0(PLL) PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3.A(HS_IO_CLK)
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PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 1410 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV(ICB_CLKDIV) PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1:0].C - -
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7.A(HS_IO_CLK)
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.REF_CLK(DLL)
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15.A(HS_IO_CLK)
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PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 1323 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R(LANECTRL) SSDetect_0.rx_start[1:0].C - PF_IOD_CDR_C0_0.RCLKINT_0.A(RCLKINT)
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System 0 - - - -
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TCK 0 TCK(port) - - -
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COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 184 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst.UDRCK(UJTAG) MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.genblk1\.rst_synch_reg[1:0].C - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.un1_jtag_tck.I[0](inv)
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PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK(LANECTRL) PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.CDR_CLK - -
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===========================================================================================================================================================================================================================================================================================================================================================================================================================
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