206 lines
16 KiB
Plaintext
206 lines
16 KiB
Plaintext
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Copyright (C) 1994-2023 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: V-2023.09M-5
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Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
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OS: Windows 10 or later
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Hostname: SOFTWARE-PC
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Implementation : synthesis
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# Written on Wed Apr 15 22:48:07 2026
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##### DESIGN INFO #######################################################
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Top View: "top"
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Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc"
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##### SUMMARY ############################################################
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Found 15 issues in 15 out of 47 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
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System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | No paths | 10.000 | No paths
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REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
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PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 | 8.000 | 3.200 | 4.800
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PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
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PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | No paths | No paths
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp | No paths | No paths | No paths
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp | No paths | Diff grp | No paths
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PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
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PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | Diff grp | No paths
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PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths
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PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 | No paths | No paths | No paths
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COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 | No paths | No paths | No paths
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COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | Diff grp
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COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | 10.000 | 5.000 | 5.000
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=========================================================================================================================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Unconstrained Start/End Points
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******************************
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p:LINK_OK
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p:PHY_RST
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p:RD_BC_ERROR
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p:REFCLK_N
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p:REF_CLK_SEL
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p:RX
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p:RX_N
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p:RX_P
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p:R_DATA[0]
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p:R_DATA[1]
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p:R_DATA[2]
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p:R_DATA[3]
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p:R_DATA[4]
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p:R_DATA[5]
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p:R_DATA[6]
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p:R_DATA[7]
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p:R_DATA[8]
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p:R_DATA[9]
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p:R_DATA[10]
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p:R_DATA[11]
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p:R_DATA[12]
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p:R_DATA[13]
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p:R_DATA[14]
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p:R_DATA[15]
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p:R_DATA[16]
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p:R_DATA[17]
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p:R_DATA[18]
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p:R_DATA[19]
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p:R_DATA[20]
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p:R_DATA[21]
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p:R_DATA[22]
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p:R_DATA[23]
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p:R_DATA[24]
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p:R_DATA[25]
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p:R_DATA[26]
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p:R_DATA[27]
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p:R_DATA[28]
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p:R_DATA[29]
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p:R_DATA[30]
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p:R_DATA[31]
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p:SPISCLKO
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p:SPISDI
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p:SPISDO
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p:SPISS
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p:TDI
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p:TDO
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p:TMS
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p:TRSTB
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p:TX
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p:TX_N
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p:TX_P
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p:coma_mode
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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set_false_path -to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]
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@W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
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Constraints with matching wildcard expressions
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**********************************************
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set_false_path -from [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":46:0:46:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]" applies to objects:
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PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane
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PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane6_0_i4
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PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane_4
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set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|expression "[get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }]" applies to objects:
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[0]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[4]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[5]
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PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE
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set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":28:0:28:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]" applies to objects:
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[0]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[1]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[2]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[3]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[4]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[5]
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6]
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set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":30:0:30:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]" applies to objects:
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1]
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set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":31:0:31:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]" applies to objects:
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1]
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set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":29:0:29:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]" applies to objects:
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PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1]
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set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":44:0:44:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]" applies to objects:
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PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1]
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set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]
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@N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":43:0:43:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]" applies to objects:
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PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1]
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Library Report
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**************
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# End of Constraint Checker Report
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