1 line
897 B
XML
1 line
897 B
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="T"/></reports><subproject libero="T"/><hdltype>Verilog</hdltype><componentInstances/><component name="COREJTAGDEBUG_C0::work"/><component name="Core_reset_pf::work"/><component name="CoreAPB3_0::work"/><component name="CORESPI_0::work"/><component name="CORETSE_0::work"/><component name="CoreUARTapb_0::work"/><component name="MIV_RV32_C0::work"/><component name="PF_CCC_0::work"/><component name="pf_init_monitor_0::work"/><component name="PF_IOD_CDR_C0::work"/><component name="PF_IOD_CDR_CCC_C0::work"/><component name="top::work"/><device die="PA5M300TS" family="PolarFire" package="fcg1152"/><component name="COREFIFO_C0::work"/><component name="PF_TPSRAM_C0::work"/><SmartGen version="8.0"/></workspace> |