242 lines
6.9 KiB
Plaintext
242 lines
6.9 KiB
Plaintext
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memmap master 0x10000000
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memmap slave 0x11000000
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constant R_control 0x00
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constant R_intclear 0x04
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constant R_rxdata 0x08
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constant R_txdata 0x0C
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constant R_intmask 0x10
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constant R_intraw 0x10
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constant R_control2 0x18
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constant R_command 0x1C
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constant R_stat 0x20
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constant R_ssel 0x24
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constant R_txdatal 0x28
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constant R_CLK_DIV 0x2C
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# R_control bits
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constant B_enable 0x00000001
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constant B_master 0x00000002
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constant B_slave 0x00000000
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constant B_intenrxovr 0x00000004
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constant B_intentx 0x00000008
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constant B_intentxov 0x00000010
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constant B_intenrxov 0x00000020
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constant B_intenurun 0x00000040
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constant B_oenoff 0x00000080
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# R_control2 bits
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constant B_intencmd 0x00000010
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constant B_intentssend 0x00000020
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constant B_intendatarx 0x00000040
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# R_command bits (write-only)
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constant B_rxfiforst 0x00000001
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constant B_txfiforst 0x00000002
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# R_intclear/raw/mask bits
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constant B_txint 0x00000001
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constant B_rxovint 0x00000004
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constant B_txurint 0x00000008
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constant B_cmdint 0x00000010
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constant B_ssendint 0x00000020
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constant B_datarxint 0x00000040
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# R_status
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constant B_firstframe 0x00000001
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constant B_done 0x00000002
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constant B_rxempty 0x00000004
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constant B_txfull 0x00000008
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constant B_rxoverflow 0x00000010
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constant B_txunderrun 0x00000020
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constant B_ssel 0x00000040
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constant B_active 0x00000080
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procedure main
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print "CoreSPI User testbench"
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debug 0
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#setup 7 1 # execute $stop at end
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timeout 10000
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print "********************************************************************"
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print "Test1: Read Initial Register values"
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print "********************************************************************"
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call read_reg
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print "********************************************************************"
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print "Test2: Master -> Slave : 4 Byte transfer"
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print "********************************************************************"
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call test_slave_rx
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wait 100
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print "********************************************************************"
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print "Test3: Check Master TX_DONE & slave DATA_RX interrupt operation"
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print "********************************************************************"
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call test_interrupt_operation
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print "********************************************************************"
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print "Test4: Read Register values after the transfer"
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print "********************************************************************"
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call read_reg
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print "********************************************************************"
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print "CoreSPI user testbench completed"
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print "********************************************************************"
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return
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procedure read_reg
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int i x
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## Read contents of APB register block
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print "CoreSPI master registers"
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loop i 0x00 0x2C 4
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readstore b master i x
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print "Read from %08x: %08x" i x
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endloop
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print "CoreSPI slave registers"
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loop i 0x00 0x2C 4
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readstore b slave i x
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print "Read from %08x: %08x" i x
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endloop
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return
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procedure test_slave_rx
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int i x
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## 4 Byte transfer to test master->slave transfer
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print "Enable the slave"
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write w slave R_control (B_slave | B_enable)
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print "Set slave up with TX data"
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loop i 0x5 0x8 1
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write w slave R_txdata i
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print "Slave TX byte : %08x" i
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endloop
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print "Configure master to Tx to slave 0"
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write w master R_ssel 1
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write w master R_control (B_master | B_enable)
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print "Set master up with TX data"
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loop i 0x01 0x03 1
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write w master R_txdata i
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print "Master TX byte : %08x" i
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endloop
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print "Write last byte(0x04) to the tx_datal register to terminate the transfer"
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write w master R_txdatal 0x04
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#write b master R_CLK_DIV 0x04
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#print "********************************************************************************"
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#print "Dynamically configuring the clock division factor of master generated SPI clock"
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#print "********************************************************************************"
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## Wait for the transfer to complete
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wait 1500
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print "************************************"
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print "Check contents of slave RX FIFO"
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print "************************************"
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loop i 0x01 0x04 1
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readstore w slave R_rxdata x
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print "Read %08x" x
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compare x i
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endloop
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print "************************************"
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print "Check contents of master RX FIFO"
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print "************************************"
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loop i 0x5 0x8 1
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readstore w master R_rxdata x
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print "Read %08x" x
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compare x i
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endloop
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return
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procedure test_interrupt_operation
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int i x
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print "Set slave up with TX data"
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loop i 0x0A 0x0D 1
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write w slave R_txdata i
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print "Slave TX byte : %08x" i
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endloop
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## Enable slave DATA_RX interrupt
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print "Clear any pending DATA_TX raw interrupts before enabling the DATA_RX interrupt"
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write b slave R_intclear 0x40
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wait 100
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print "Enable slave DATA_RX interrupt"
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write b slave R_control2 B_intendatarx
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## Enable master TX_DONE interrupt
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print "Clear any pending TX_DONE raw interrupts before enabling the TX_DONE interrupt"
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write b master R_intclear 0x01
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wait 100
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print "Enable master TX_DONE interrupt"
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write w master R_control (B_master | B_enable | B_intentx)
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## Load master with tx data
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print "Set master up with TX data"
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loop i 0x04 0x06 1
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write w master R_txdata i
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print "Master TX byte : %08x" i
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endloop
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print "Write last byte(0x07) to the tx_datal register to terminate the transfer"
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write w master R_txdatal 0x07
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wait 1500
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print "************************************"
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print "Check master SPIINT interrupt asserted"
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print "************************************"
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## Check master interrupt
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iotstbit 0 1
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readstore b master R_intmask x
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print "Masked Interrupt Register read as: %08x" x
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print "Clear master TX_DONE interrupt & check SPIINT de-asserts"
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## Clear interrupt
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write b master R_intclear 0x01
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wait 100
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## Check clear
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iotstbit 0 0
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print "************************************"
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print "Check slave SPIINT interrupt asserted"
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print "************************************"
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## Check slave interrupt
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iotstbit 1 1
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readstore b slave R_intmask x
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print "Masked Interrupt Register read as: %08x" x
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print "************************************"
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print "Check contents of slave RX FIFO"
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print "************************************"
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## Check slave
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loop i 0x04 0x07
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readstore w slave R_rxdata x
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print "Read %08x" x
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compare x i
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endloop
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print "Wait until data is removed from the RX_FIFO"
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wait 20
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print "Clear slave DATA_RX interrupt and check SPIINT de-asserts"
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write b slave R_intclear 0x40
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wait 100
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## Check clear
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iotstbit 1 0
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print "************************************"
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print "Check contents of master RX FIFO"
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print "************************************"
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loop i 0xA 0xD 1
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readstore w master R_rxdata x
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print "Read %08x" x
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compare x i
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endloop
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return
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