469 lines
13 KiB
Plaintext
469 lines
13 KiB
Plaintext
// ********************************************************************
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// Actel Corporation Proprietary and Confidential
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// Copyright 2009 Actel Corporation All rights reserved
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//
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// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
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// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
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// IN ADVANCE IN WRITING
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//
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// Description: User testbench include file for CoreAI - contains
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// various constants procedures etc used by main BFM script
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//
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// Revision Information:
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// Date Description
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// 19Jan09 Production Release Version 3 0
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//
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// SVN Revision Information:
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// SVN $Revision: $
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// SVN $Date: $
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//
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// Resolved SARs
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// SAR Date Who Description
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//
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// Notes:
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// 1 best viewed with tabstops set to "4"
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//
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// History:
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//
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// *********************************************************************
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// PSEL[0] HSEL[0] used to access the AHB-to-APB bridge in the BFM_APB mod
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// (for UART Transmitter)
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memmap BASE1 0x10000000
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// PSEL[1] HSEL[1] used to access the AHB-to-APB bridge in the BFM_APB mod
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// (for UART Receiver)
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memmap BASE2 0x11000000
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// variables to store passed parameter values
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int FAMILY
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int TX_FIFO
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int RX_FIFO
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int FIXEDMODE
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int BAUD_VALUE
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int PRG_BIT8
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int PRG_PARITY
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int RX_LEGACY_MODE
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int USE_SOFT_FIFO
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// derived parameters
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int FIFO_DEPTH
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int TIMEOUT_VAL
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int BYTE_WAIT_TIME
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int BYTE_WAIT_256
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int BYTE_WAIT_16
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int BYTE_WAIT_8
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// data variables
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int rdata[256]
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// other variables
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int PRINT_VARS
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int BITVAR
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int data
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// temp vars
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int i j k l w x y z tc rc
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int cmp
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// CoreGPIO internal addresses
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constant TXDATA 0x00
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constant RXDATA 0x04
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constant CTRL1 0x08
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constant CTRL2 0x0C
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constant STA 0x10
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constant CRTL3 0x14
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//BFM GPIN bit defs
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constant RXRDY1 0
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constant TXRDY1 1
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constant PARITY_ERR1 2
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constant OVERFLOW1 3
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constant RXRDY2 4
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constant TXRDY2 5
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constant PARITY_ERR2 6
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constant OVERFLOW2 7
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//---------------------------------------------------------------------------
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// procedures
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// initialize local variables from the ARGVALUE* BFM parameters passed
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// down from the testbench HDL
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//---------------------------------------------------------------------------
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procedure init_parameter_vars
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set FAMILY $ARGVALUE0
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set TX_FIFO $ARGVALUE1
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set RX_FIFO $ARGVALUE2
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set FIXEDMODE $ARGVALUE3
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set BAUD_VALUE $ARGVALUE4
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set PRG_BIT8 $ARGVALUE5
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set PRG_PARITY $ARGVALUE6
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set RX_LEGACY_MODE $ARGVALUE7
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set USE_SOFT_FIFO $ARGVALUE8
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// derived parameters
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 255
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endif
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// check for SX or RTSX or RTAXS
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// and set FIFO depth accordingly
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// (these 3 have soft FIFOs)
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set cmp FAMILY == 8
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if cmp
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set FIFO_DEPTH 15
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endif
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set cmp FAMILY == 9
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if cmp
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set FIFO_DEPTH 15
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endif
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// set cmp FAMILY == 12
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// if cmp
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// set FIFO_DEPTH 15
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// endif
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//check for SmartFusion2 or Igloo2 or RTG4
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//and set FIFO depth accordingly
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set cmp FAMILY == 19
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if cmp
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 127
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endif
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endif
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set cmp FAMILY == 24
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if cmp
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 127
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endif
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endif
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set cmp FAMILY == 25
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if cmp
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 127
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endif
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endif
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//check for PolarFire
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//and set FIFO depth accordingly
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set cmp FAMILY == 26
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if cmp
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 255
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endif
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endif
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//check for ProASICplus
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//and set FIFO depth accordingly
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set cmp FAMILY == 14
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if cmp
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if USE_SOFT_FIFO
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set FIFO_DEPTH 15
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else
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set FIFO_DEPTH 254
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endif
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endif
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set BYTE_WAIT_TIME BAUD_VALUE * 250
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set BYTE_WAIT_256 BYTE_WAIT_TIME * 256
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set BYTE_WAIT_16 BYTE_WAIT_TIME * 16
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set BYTE_WAIT_8 BYTE_WAIT_TIME * 8
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set TIMEOUT_VAL BYTE_WAIT_256 + 1
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timeout TIMEOUT_VAL
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set PRINT_VARS 1
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if PRINT_VARS
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header " Begin printing variables from APB Master BFM Script ..."
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print "FAMILY:%0d" FAMILY
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print "TX_FIFO:%0d" TX_FIFO
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print "RX_FIFO:%0d" RX_FIFO
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print "FIXEDMODE:%0d" FIXEDMODE
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print "BAUD_VALUE:%0d" BAUD_VALUE
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print "PRG_BIT8:%0d" PRG_BIT8
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print "PRG_PARITY:%0d" PRG_PARITY
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print "RX_LEGACY_MODE:%0d" RX_LEGACY_MODE
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print "FIFO_DEPTH:%0d" FIFO_DEPTH
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header " Done printing variables from APB Master BFM Script."
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header " "
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endif
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return
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//---------------------------------------------------------------------------
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// get bit number (bnum) from given wval integer
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//---------------------------------------------------------------------------
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procedure get_bit wval bnum
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int d01
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set d01 wval >> bnum
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// set global BITVAR variable
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set BITVAR d01 & 0x1
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return
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//---------------------------------------------------------------------------
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// print line of underscores
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//---------------------------------------------------------------------------
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procedure pr_underscores
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print "____________________________________________________________________"
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print " "
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return
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//---------------------------------------------------------------------------
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// test procedures
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//---------------------------------------------------------------------------
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procedure set_config dn pe p bv bn
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int dut_num // 1 = RX(DUT2), 0 = TX(DUT1)
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int par_en // 1 = enabled, 0 = disabled
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int par // 1 = odd, 0 = even
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int baud_val // 13-bit baud-value (split into 2 config registers)
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int bit_num // 1 = 8 bits, 0 = 7 bits
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// temp vars
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int baud1
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int baud2
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int ctrl2_val
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set dut_num dn
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set par_en pe
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set par p
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set baud_val bv
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set bit_num bn
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print "Configuring UART:%0d with par_en:%0d parity:%0d baud_val:%0d bit_num:%0d" dut_num par_en par baud_val bit_num
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// Set config regsiter data
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set baud1 baud_val << 8 >> 8 // CONFIG REG 1
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set baud2 baud_val >> 8 // CONFIG REG 2
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set par par << 2
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set par_en par_en << 1
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set baud2 baud2 << 3
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set ctrl2_val par
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set ctrl2_val ctrl2_val | par_en
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set ctrl2_val ctrl2_val | baud2
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set ctrl2_val ctrl2_val | bit_num
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// set base address based on DUT selected
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if dut_num == 1
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// write control registers
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//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
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write b BASE2 CTRL1 baud1
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write b BASE2 CTRL2 ctrl2_val
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else
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// write control registers
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//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
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write b BASE1 CTRL1 baud1
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write b BASE1 CTRL2 ctrl2_val
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endif
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return
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procedure data_stream
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call pr_underscores
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print "Testing Continuous Data Stream UART1 to UART2"
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set rc 0
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loop tc 0 FIFO_DEPTH 1
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//print "Sending byte %0d" tc
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iowaitbit TXRDY1 1 // wait until TXRDY
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set data tc & 0x7F // mask byte
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//print "Got TXRDY %0d times" tc
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write b BASE1 TXDATA data // transmit a byte
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ifnot TX_FIFO
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iowaitbit TXRDY1 0 // wait until TXRDY deasserted
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endif
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ifnot RX_FIFO // must read immediately
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iowaitbit RXRDY2 1 // wait until RXRDY
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//print "Receiving byte %0d" tc
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readstore b BASE2 RXDATA rdata[rc] // read received byte
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set rc rc + 1
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endif
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endloop
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if RX_FIFO // test out FIFO operation
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wait BYTE_WAIT_16 // wait for data to be received
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loop rc 0 FIFO_DEPTH 1
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iowaitbit RXRDY2 1 // wait until RXRDY
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readstore b BASE2 RXDATA rdata[rc] // read received byte
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endloop
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endif
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// check data
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loop i 0 FIFO_DEPTH 1
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set j i & 0x7F
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if rdata[i] != j
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call pr_underscores
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print "TEST FAILED"
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print "Expected %0d, got %0d" i rdata[i]
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setfail
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endif
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endloop
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print "Continuous data stream successfull"
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call pr_underscores
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return
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procedure framing_err_test
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call pr_underscores
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print "Performing framing error test by setting input to DUT2 low"
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// set the input to UART2 RX line low
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// (no stop bit)
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iowrite 0x01
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wait BYTE_WAIT_16
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ifnot RX_FIFO
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// back to normal:
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iowrite 0x00
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wait BYTE_WAIT_16
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readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
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read b BASE2 RXDATA // doing a read should clear this
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readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
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else
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readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
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iowrite 0x00
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// transmit a byte to clear the framing error
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iowaitbit TXRDY1 1 // wait until TXRDY
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write b BASE1 TXDATA 0xAA
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wait BYTE_WAIT_16
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readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
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//loop i 0 FIFO_DEPTH 1 // probably caused an overflow,
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readstore b BASE2 STA x // read status
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set x x & 0x02
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set cmp x == 2
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while cmp
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iowaitbit RXRDY2 1 // wait until RXRDY
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read b BASE2 RXDATA // need to clear
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iowaitbit RXRDY2 0 // wait until RXRDY clear
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wait 4
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readstore b BASE2 STA x // read status
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set x x & 0x02
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set cmp x == 2
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endwhile
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endif
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wait 10
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print "Framing error test completed"
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call pr_underscores
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return
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procedure overflow_test
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call pr_underscores
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print "Overflow test"
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if RX_FIFO
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loop tc 0 FIFO_DEPTH 1
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iowaitbit TXRDY1 1 // wait until TXRDY
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set data tc & 0x7F // mask byte
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write b BASE1 TXDATA data // transmit a byte
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ifnot TX_FIFO
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iowaitbit TXRDY1 0 // wait until TXRDY deasserted
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endif
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endloop
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iowaitbit TXRDY1 1 // wait until TXRDY
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wait BYTE_WAIT_256
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iotstbit OVERFLOW2 0 // check that overflow not set
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write b BASE1 TXDATA 0xab // transmit a byte (0xab)
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wait BYTE_WAIT_256 // worst case: 3 blocks (BAUD_VAL=1)
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wait BYTE_WAIT_256
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wait BYTE_WAIT_256
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iotstbit OVERFLOW2 1 // check that overflow set
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// read RX data
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loop rc 0 FIFO_DEPTH 1
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if rc == 1
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iotstbit OVERFLOW2 0 // check
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endif
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iowaitbit RXRDY2 1 // wait until RXRDY
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readstore b BASE2 RXDATA rdata[rc] // read received byte
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endloop
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// check data
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loop i 0 FIFO_DEPTH 1
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set j i & 0x7F
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if rdata[i] != j
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call pr_underscores
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print "TEST FAILED"
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print "Expected %0d, got %0d" i rdata[i]
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setfail
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endif
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endloop
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endif
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call pr_underscores
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return
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procedure parity_err_test
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call pr_underscores
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print "Performing Parity Error Test"
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call set_config 0 1 0 1 1
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call set_config 1 1 1 1 1
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// -- transmit a byte --
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iotstbit PARITY_ERR2 0 // check that parity error is 0
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iowaitbit txrdy1 1 // wait until txrdy
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write b base1 txdata 0xab // transmit a byte (0xab)
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iowaitbit PARITY_ERR2 1 // check that parity error asserted
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if RX_FIFO
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iowaitbit PARITY_ERR2 0 // check that parity error deasserted
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call set_config 0 1 1 1 1 // match parity
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iowaitbit txrdy1 1 // wait until txrdy
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write b base1 txdata 0xac // transmit a new byte (0xab)
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iowaitbit RXRDY2 1 // read byte
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iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
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readstore b BASE2 RXDATA x // store
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if x != 0xac
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call pr_underscores
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print "TEST FAILED"
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print "Expected 0xac, got %0h" x
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setfail
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endif
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else
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// NO RX_FIFO
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// clear parity error
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read b BASE2 RXDATA // read should clear
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wait 4
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iotstbit PARITY_ERR2 0 // the parity error
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call set_config 0 1 1 1 1 // match parity
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iowaitbit txrdy1 1 // wait until txrdy
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write b base1 txdata 0xac // transmit a new byte (0xab)
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iowaitbit RXRDY2 1 // read byte
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iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
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readstore b BASE2 RXDATA x // store
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if x != 0xac
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call pr_underscores
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print "TEST FAILED"
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print "Expected 0xac, got %0h" x
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setfail
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endif
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endif
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print "Parity Error Test Complete"
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call pr_underscores
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return
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