79 lines
2.2 KiB
Verilog
79 lines
2.2 KiB
Verilog
module fifo_to_tpsram_bridge #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 10 // 1024 depth
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)(
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input wire clk,
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input wire reset_n,
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// CoreFIFO Interface (FWFT Mode)
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input wire [DATA_WIDTH-1:0] fifo_data_out,
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input wire fifo_empty,
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output reg fifo_rd_en,
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// TPSRAM Port A Interface (Write Port)
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output reg [ADDR_WIDTH-1:0] ram_w_addr,
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output reg [DATA_WIDTH-1:0] ram_w_data,
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output reg ram_w_en,
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// Control/Status
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input wire transfer_enable,
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output reg buffer_full
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);
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// State Encoding
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localparam IDLE = 2'b00,
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WRITE = 2'b01,
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FULL = 2'b10;
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reg [1:0] state, next_state;
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// Address Counter Logic
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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ram_w_addr <= 0;
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buffer_full <= 0;
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end else if (ram_w_en) begin
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if (ram_w_addr == {ADDR_WIDTH{1'b1}}) begin
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buffer_full <= 1; // Memory is topped off
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end else begin
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ram_w_addr <= ram_w_addr + 1;
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end
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end
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end
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// FSM State Transitions
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) state <= IDLE;
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else state <= next_state;
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end
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// Next State Logic
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always @(*) begin
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next_state = state;
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case (state)
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IDLE: begin
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// Start writing if FIFO has data and RAM isn't full
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if (!fifo_empty && transfer_enable && !buffer_full)
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next_state = WRITE;
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end
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WRITE: begin
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if (fifo_empty || buffer_full)
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next_state = IDLE;
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end
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default: next_state = IDLE;
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endcase
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end
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// Output Logic
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always @(*) begin
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fifo_rd_en = 0;
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ram_w_en = 0;
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ram_w_data = fifo_data_out;
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if (state == WRITE && !fifo_empty && !buffer_full) begin
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fifo_rd_en = 1;
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ram_w_en = 1;
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end
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end
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endmodule |