49 lines
1.2 KiB
Verilog
49 lines
1.2 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////////////////////////
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// Company: <Name>
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//
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// File: SSDetect.v
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// File history:
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// <Revision number>: <Date>: <Comments>
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// <Revision number>: <Date>: <Comments>
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// <Revision number>: <Date>: <Comments>
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//
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// Description:
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//
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// <Description here>
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//
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// Targeted device: <Family::PolarFire> <Die::MPF300TS> <Package::FCG1152>
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// Author: <Name>
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//
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///////////////////////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module SSDetect( rst_b, rck, rx_data, stream_start );
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input rst_b;
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input rck;
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input [9:0] rx_data; // from RX_P
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output stream_start;
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function is_match (input [6:0] x, input [6:0] y);
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begin
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is_match = (x == y) | (x == ~y);
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end
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endfunction
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reg [1:0] rx_start;
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assign stream_start = rx_start[0]; // CDR starts after RX data detects two consecutive non-static words
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always @(posedge rck or negedge rst_b) begin // SAR 101393, use negedge clock
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if (!rst_b) begin
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rx_start <= 2'd0;
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end
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else if (!rx_start[0]) begin // two consecutive non-static words
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rx_start <= is_match(rx_data[6:0], 0) ? 2'd0 : {1'b1, rx_start[1]};
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end
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end
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endmodule
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