Files
Ethernet-IP-Core/designer/top/top_RAM_definition.txt

11 lines
7.9 KiB
Plaintext

logical_instance_name-COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe Physical_names-[COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1/INST_RAM1K20_IP@@COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-32 Port_B_Depth-1024 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_6/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_5/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_7/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_4/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-4096 Port_A_Width-36 Port_B_Depth-4096 Port_B_Width-36 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-2048 Port_A_Width-40 Port_B_Depth-2048 Port_B_Width-40 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0 Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0/INST_RAM1K20_IP@@] Cascade_type-Depth Port_A_Depth-9216 Port_A_Width-32 Port_B_Depth-9216 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-2 Port_A_Width-6 Port_B_Depth-2 Port_B_Width-6 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
logical_instance_name-PF_TPSRAM_C0_0/PF_TPSRAM_C0_0 Physical_names-[PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-32 Port_B_Depth-1024 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0