23108 lines
3.5 MiB
23108 lines
3.5 MiB
# Microchip Physical design constraints file
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# Version: 2025.1 2025.1.0.14
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# Design Name: top
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# Input Netlist Format: EDIF
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# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1
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# Date generated: Wed Apr 15 23:05:02 2026
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#
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# I/O constraints
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#
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set_io -port_name LINK_OK -DIRECTION OUTPUT -pin_name D25 -fixed false
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set_io -port_name PHY_MDC -DIRECTION OUTPUT -pin_name Y12 -fixed false
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set_io -port_name PHY_MDIO -DIRECTION INOUT -pin_name Y13 -fixed false
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set_io -port_name PHY_RST -DIRECTION OUTPUT -pin_name U11 -fixed false
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set_io -port_name RD_BC_ERROR -DIRECTION OUTPUT -pin_name F22 -fixed false
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set_io -port_name REFCLK_N -DIRECTION INPUT -pin_name U5 -fixed false
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set_io -port_name REFCLK_P -DIRECTION INPUT -pin_name U4 -fixed false
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set_io -port_name REF_CLK_0 -DIRECTION INPUT -pin_name E25 -fixed false
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set_io -port_name REF_CLK_SEL -DIRECTION OUTPUT -pin_name AA10 -fixed false
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set_io -port_name RESET_N -DIRECTION INPUT -pin_name K22 -fixed false
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set_io -port_name RX -DIRECTION INPUT -pin_name H18 -fixed false
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set_io -port_name RX_N -DIRECTION INPUT -pin_name U1 -fixed false
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set_io -port_name RX_P -DIRECTION INPUT -pin_name U2 -fixed false
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set_io -port_name R_DATA\[0\] -DIRECTION OUTPUT -pin_name AF9 -fixed false
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set_io -port_name R_DATA\[1\] -DIRECTION OUTPUT -pin_name AE6 -fixed false
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set_io -port_name R_DATA\[2\] -DIRECTION OUTPUT -pin_name AL2 -fixed false
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set_io -port_name R_DATA\[3\] -DIRECTION OUTPUT -pin_name AK1 -fixed false
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set_io -port_name R_DATA\[4\] -DIRECTION OUTPUT -pin_name AD6 -fixed false
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set_io -port_name R_DATA\[5\] -DIRECTION OUTPUT -pin_name AD8 -fixed false
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set_io -port_name R_DATA\[6\] -DIRECTION OUTPUT -pin_name AJ1 -fixed false
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set_io -port_name R_DATA\[7\] -DIRECTION OUTPUT -pin_name AH4 -fixed false
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set_io -port_name R_DATA\[8\] -DIRECTION OUTPUT -pin_name AK3 -fixed false
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set_io -port_name R_DATA\[9\] -DIRECTION OUTPUT -pin_name AD9 -fixed false
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set_io -port_name R_DATA\[10\] -DIRECTION OUTPUT -pin_name AH2 -fixed false
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set_io -port_name R_DATA\[11\] -DIRECTION OUTPUT -pin_name AG7 -fixed false
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set_io -port_name R_DATA\[12\] -DIRECTION OUTPUT -pin_name AG9 -fixed false
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set_io -port_name R_DATA\[13\] -DIRECTION OUTPUT -pin_name AG6 -fixed false
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set_io -port_name R_DATA\[14\] -DIRECTION OUTPUT -pin_name AK2 -fixed false
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set_io -port_name R_DATA\[15\] -DIRECTION OUTPUT -pin_name AJ4 -fixed false
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set_io -port_name R_DATA\[16\] -DIRECTION OUTPUT -pin_name AF7 -fixed false
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set_io -port_name R_DATA\[17\] -DIRECTION OUTPUT -pin_name AD13 -fixed false
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set_io -port_name R_DATA\[18\] -DIRECTION OUTPUT -pin_name AG10 -fixed false
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set_io -port_name R_DATA\[19\] -DIRECTION OUTPUT -pin_name AE8 -fixed false
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set_io -port_name R_DATA\[20\] -DIRECTION OUTPUT -pin_name AE10 -fixed false
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set_io -port_name R_DATA\[21\] -DIRECTION OUTPUT -pin_name AD11 -fixed false
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set_io -port_name R_DATA\[22\] -DIRECTION OUTPUT -pin_name AF13 -fixed false
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set_io -port_name R_DATA\[23\] -DIRECTION OUTPUT -pin_name AE7 -fixed false
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set_io -port_name R_DATA\[24\] -DIRECTION OUTPUT -pin_name AE11 -fixed false
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set_io -port_name R_DATA\[25\] -DIRECTION OUTPUT -pin_name AF10 -fixed false
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set_io -port_name R_DATA\[26\] -DIRECTION OUTPUT -pin_name AF12 -fixed false
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set_io -port_name R_DATA\[27\] -DIRECTION OUTPUT -pin_name AD10 -fixed false
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set_io -port_name R_DATA\[28\] -DIRECTION OUTPUT -pin_name AF8 -fixed false
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set_io -port_name R_DATA\[29\] -DIRECTION OUTPUT -pin_name AE13 -fixed false
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set_io -port_name R_DATA\[30\] -DIRECTION OUTPUT -pin_name AE12 -fixed false
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set_io -port_name R_DATA\[31\] -DIRECTION OUTPUT -pin_name AD14 -fixed false
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set_io -port_name SPISCLKO -DIRECTION OUTPUT -pin_name K21 -fixed false
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set_io -port_name SPISDI -DIRECTION INPUT -pin_name L20 -fixed false
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set_io -port_name SPISDO -DIRECTION OUTPUT -pin_name K20 -fixed false
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set_io -port_name SPISS -DIRECTION OUTPUT -pin_name J20 -fixed false
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set_io -port_name TX -DIRECTION OUTPUT -pin_name G17 -fixed false
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set_io -port_name TX_N -DIRECTION OUTPUT -pin_name V2 -fixed false
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set_io -port_name TX_P -DIRECTION OUTPUT -pin_name V1 -fixed false
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set_io -port_name coma_mode -DIRECTION OUTPUT -pin_name U12 -fixed false
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#
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# Core cell constraints
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#
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[1\] -fixed false -x 613 -y 117
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[4\] -fixed false -x 638 -y 118
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[10\] -fixed false -x 529 -y 172
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IO1Oo_0\[0\] -fixed false -x 104 -y 159
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set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_4 -fixed false -x 422 -y 3
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m7 -fixed false -x 794 -y 171
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_2_RNI7PU6D -fixed false -x 833 -y 147
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[7\] -fixed false -x 674 -y 183
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1151 -fixed false -x 598 -y 144
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lI0i1_0_0 -fixed false -x 227 -y 186
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[9\] -fixed false -x 806 -y 157
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[0\] -fixed false -x 420 -y 159
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[5\] -fixed false -x 68 -y 186
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_119 -fixed false -x 634 -y 171
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z\[1\] -fixed false -x 340 -y 199
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iiiI1 -fixed false -x 419 -y 192
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[1\] -fixed false -x 731 -y 120
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[12\] -fixed false -x 897 -y 147
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0\[1\] -fixed false -x 731 -y 150
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[2\] -fixed false -x 313 -y 196
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[8\] -fixed false -x 733 -y 141
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[15\] -fixed false -x 897 -y 187
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[6\] -fixed false -x 249 -y 187
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[5\] -fixed false -x 372 -y 198
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_0_sqmuxa_0 -fixed false -x 202 -y 216
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[7\] -fixed false -x 915 -y 156
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[2\] -fixed false -x 395 -y 198
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[5\] -fixed false -x 344 -y 151
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[20\] -fixed false -x 83 -y 229
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_15 -fixed false -x 714 -y 147
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_1_0 -fixed false -x 95 -y 198
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[2\] -fixed false -x 188 -y 202
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[23\] -fixed false -x 557 -y 165
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIio1_RNO -fixed false -x 59 -y 207
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set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[0\] -fixed false -x 385 -y 235
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_470 -fixed false -x 748 -y 198
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2\[8\] -fixed false -x 131 -y 216
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[38\] -fixed false -x 917 -y 177
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_820 -fixed false -x 715 -y 186
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1111 -fixed false -x 74 -y 208
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[16\] -fixed false -x 461 -y 174
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNIKCAA3\[15\] -fixed false -x 574 -y 117
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[6\] -fixed false -x 565 -y 139
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioo11_1 -fixed false -x 395 -y 171
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[21\] -fixed false -x 777 -y 150
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex\[0\] -fixed false -x 733 -y 133
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[26\] -fixed false -x 677 -y 123
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set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt\[2\] -fixed false -x 560 -y 151
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[5\] -fixed false -x 601 -y 118
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1166 -fixed false -x 592 -y 183
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iii11 -fixed false -x 353 -y 196
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[30\] -fixed false -x 420 -y 168
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_data_gen_buff_loop\[0\].buff_data_0_0_RNO_0 -fixed false -x 827 -y 138
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_a0 -fixed false -x 805 -y 135
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg\[0\] -fixed false -x 701 -y 181
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 390 -y 169
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set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO\[3\] -fixed false -x 535 -y 144
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_301 -fixed false -x 669 -y 198
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[2\] -fixed false -x 210 -y 214
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[5\] -fixed false -x 409 -y 213
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_306 -fixed false -x 670 -y 171
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_m3\[0\] -fixed false -x 671 -y 138
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[18\] -fixed false -x 969 -y 168
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set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[13\] -fixed false -x 387 -y 193
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_a0_1 -fixed false -x 823 -y 135
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_2\[4\] -fixed false -x 842 -y 120
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[10\] -fixed false -x 947 -y 144
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[3\] -fixed false -x 773 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[6\] -fixed false -x 60 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIJ5GUI\[8\] -fixed false -x 872 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01 -fixed false -x 214 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb7_i_o3 -fixed false -x 728 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[6\] -fixed false -x 156 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOiOo_0_a2_0 -fixed false -x 235 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[3\] -fixed false -x 228 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[15\] -fixed false -x 814 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[2\] -fixed false -x 685 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[9\] -fixed false -x 813 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIRD2R7\[14\] -fixed false -x 59 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[0\] -fixed false -x 36 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_0_sqmuxa_0_a3_1 -fixed false -x 201 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_52\[11\] -fixed false -x 317 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[21\] -fixed false -x 434 -y 151
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2\[0\] -fixed false -x 486 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[8\] -fixed false -x 238 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_518 -fixed false -x 732 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[0\] -fixed false -x 162 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel -fixed false -x 695 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0 -fixed false -x 28 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[12\] -fixed false -x 699 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1 -fixed false -x 294 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[26\] -fixed false -x 450 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911 -fixed false -x 688 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1247 -fixed false -x 658 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_10_m\[1\] -fixed false -x 853 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_4_0\[0\] -fixed false -x 782 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[36\] -fixed false -x 624 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_0_0\[7\] -fixed false -x 742 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_rxfifo_5 -fixed false -x 518 -y 153
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[2\] -fixed false -x 52 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_3_sqmuxa -fixed false -x 542 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957 -fixed false -x 672 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[34\] -fixed false -x 484 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001 -fixed false -x 93 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[1\] -fixed false -x 329 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_642 -fixed false -x 706 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_0_RNI0SQ9T1_0 -fixed false -x 866 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[18\] -fixed false -x 643 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[6\] -fixed false -x 63 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[8\] -fixed false -x 154 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_547 -fixed false -x 671 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[6\] -fixed false -x 105 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[8\] -fixed false -x 37 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[12\] -fixed false -x 34 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_rd_req_cmb_1 -fixed false -x 766 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[21\] -fixed false -x 923 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[6\] -fixed false -x 430 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex -fixed false -x 765 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1__RNILHUN8\[1\] -fixed false -x 642 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[9\] -fixed false -x 212 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[39\] -fixed false -x 237 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[1\] -fixed false -x 356 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_RNO_0 -fixed false -x 47 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_13_iv_i\[1\] -fixed false -x 519 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo_6 -fixed false -x 305 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[3\] -fixed false -x 450 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[3\] -fixed false -x 501 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[5\] -fixed false -x 338 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[20\] -fixed false -x 689 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[7\] -fixed false -x 331 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[4\] -fixed false -x 402 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0\[31\] -fixed false -x 677 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/IilI1 -fixed false -x 263 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[27\] -fixed false -x 795 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[0\] -fixed false -x 253 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Oio01 -fixed false -x 129 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1_0_1\[1\] -fixed false -x 131 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/OloIo -fixed false -x 388 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_trap_ret_ex_2 -fixed false -x 733 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[8\] -fixed false -x 143 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout_RNICA8SET -fixed false -x 814 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/un1_iOI01_1_i_0 -fixed false -x 221 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[25\] -fixed false -x 464 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o0I01_5_1.CO1 -fixed false -x 194 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_24 -fixed false -x 742 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01_2 -fixed false -x 213 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[4\] -fixed false -x 418 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[13\] -fixed false -x 383 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[10\] -fixed false -x 231 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2\[1\] -fixed false -x 283 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[8\] -fixed false -x 464 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_3 -fixed false -x 119 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[39\] -fixed false -x 625 -y 120
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2\[3\] -fixed false -x 381 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[9\] -fixed false -x 383 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[17\] -fixed false -x 37 -y 178
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/PRDDATA\[4\] -fixed false -x 491 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_3 -fixed false -x 685 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[10\] -fixed false -x 321 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[2\] -fixed false -x 426 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[13\] -fixed false -x 128 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[1\] -fixed false -x 911 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[16\] -fixed false -x 275 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_4_RNI4IU79 -fixed false -x 387 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[30\] -fixed false -x 419 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[4\] -fixed false -x 419 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I1ll1 -fixed false -x 453 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[17\] -fixed false -x 419 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[26\] -fixed false -x 693 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[2\] -fixed false -x 536 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[15\] -fixed false -x 346 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oili1 -fixed false -x 201 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[2\] -fixed false -x 288 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0 -fixed false -x 810 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI78M4E\[9\] -fixed false -x 452 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[29\] -fixed false -x 688 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[12\] -fixed false -x 357 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[10\] -fixed false -x 394 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[7\] -fixed false -x 297 -y 169
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[7\] -fixed false -x 82 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0Oo_1 -fixed false -x 277 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1\[0\] -fixed false -x 192 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_RNO\[0\] -fixed false -x 723 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[32\] -fixed false -x 549 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_32 -fixed false -x 694 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_9_RNISJVIA -fixed false -x 856 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_i_0\[3\] -fixed false -x 490 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[7\] -fixed false -x 310 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[5\] -fixed false -x 255 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[8\] -fixed false -x 477 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[18\] -fixed false -x 155 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[2\] -fixed false -x 404 -y 202
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto7 -fixed false -x 83 -y 219
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_o2\[0\] -fixed false -x 488 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[25\] -fixed false -x 404 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[6\] -fixed false -x 897 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[13\] -fixed false -x 838 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[18\] -fixed false -x 409 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz_1\[0\] -fixed false -x 658 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[2\] -fixed false -x 109 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[29\] -fixed false -x 683 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_4 -fixed false -x 174 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo_2 -fixed false -x 125 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_resumeack -fixed false -x 750 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo\[7\] -fixed false -x 300 -y 153
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[4\] -fixed false -x 54 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[20\] -fixed false -x 895 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[17\] -fixed false -x 763 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[23\] -fixed false -x 839 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI6AA84\[20\] -fixed false -x 909 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[1\] -fixed false -x 423 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[57\] -fixed false -x 945 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[24\] -fixed false -x 379 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m12_0 -fixed false -x 263 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[25\] -fixed false -x 414 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[2\] -fixed false -x 359 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[11\] -fixed false -x 425 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[24\] -fixed false -x 445 -y 217
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sellto7_2_0 -fixed false -x 82 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un24_oIiOo_1.CO3 -fixed false -x 347 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[27\] -fixed false -x 763 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1139 -fixed false -x 709 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[30\] -fixed false -x 661 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[3\] -fixed false -x 243 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa_RNIPGUPA5 -fixed false -x 776 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[9\] -fixed false -x 141 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[1\] -fixed false -x 71 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_12_0\[0\] -fixed false -x 756 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[3\] -fixed false -x 790 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[56\] -fixed false -x 575 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un179_I1Oi1 -fixed false -x 71 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_RNI1GLK5 -fixed false -x 527 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_RNIPQTN7 -fixed false -x 658 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_393 -fixed false -x 610 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[5\] -fixed false -x 302 -y 169
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv\[5\] -fixed false -x 501 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIARI09 -fixed false -x 776 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[8\] -fixed false -x 467 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[33\] -fixed false -x 474 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo_5 -fixed false -x 339 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l1oo1 -fixed false -x 65 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[5\] -fixed false -x 202 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[18\] -fixed false -x 842 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1li1_0_a2 -fixed false -x 203 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_0\[3\] -fixed false -x 119 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNIUIOI11 -fixed false -x 830 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[3\] -fixed false -x 765 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_5 -fixed false -x 83 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_0\[3\] -fixed false -x 324 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[0\] -fixed false -x 506 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_665 -fixed false -x 681 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3_RNI09IF31 -fixed false -x 718 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_lOoi1_1 -fixed false -x 215 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[23\].BUFD_BLK -fixed false -x 551 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI7PFUI\[2\] -fixed false -x 875 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4\[1\] -fixed false -x 96 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[5\] -fixed false -x 259 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/wtrst_1 -fixed false -x 327 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_926 -fixed false -x 748 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[14\] -fixed false -x 100 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[9\] -fixed false -x 426 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[12\] -fixed false -x 860 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIFP0P9\[8\] -fixed false -x 92 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[11\] -fixed false -x 472 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[8\] -fixed false -x 392 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[6\] -fixed false -x 423 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[15\] -fixed false -x 179 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[7\] -fixed false -x 418 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type_1\[1\] -fixed false -x 811 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[23\] -fixed false -x 457 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[8\] -fixed false -x 44 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[7\] -fixed false -x 71 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_a4_0_2\[2\] -fixed false -x 36 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un131_I1Oi1_1 -fixed false -x 71 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[2\] -fixed false -x 439 -y 148
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[9\] -fixed false -x 383 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[15\] -fixed false -x 819 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_instr_is_lsu_op_retr_RNIFR945 -fixed false -x 801 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[9\] -fixed false -x 379 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[20\] -fixed false -x 959 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[28\] -fixed false -x 466 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1185 -fixed false -x 718 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[21\] -fixed false -x 656 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[8\] -fixed false -x 923 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo\[2\] -fixed false -x 16 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[5\] -fixed false -x 110 -y 208
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA28 -fixed false -x 479 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[1\] -fixed false -x 93 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[10\] -fixed false -x 728 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_rd_op_ex -fixed false -x 758 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[4\] -fixed false -x 369 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[32\] -fixed false -x 421 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_update_dout_1_0 -fixed false -x 388 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_0 -fixed false -x 614 -y 147
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[18\].BUFD_BLK -fixed false -x 515 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[5\] -fixed false -x 495 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[8\] -fixed false -x 117 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[22\] -fixed false -x 804 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[9\] -fixed false -x 382 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01\[1\] -fixed false -x 193 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[6\] -fixed false -x 366 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[4\] -fixed false -x 457 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv_RNO\[11\] -fixed false -x 636 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OI1I1 -fixed false -x 400 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/IilI1 -fixed false -x 288 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[4\] -fixed false -x 368 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[25\] -fixed false -x 593 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI586GO\[10\] -fixed false -x 882 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[3\] -fixed false -x 250 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_680 -fixed false -x 653 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[24\] -fixed false -x 74 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[2\] -fixed false -x 431 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[21\] -fixed false -x 453 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[9\] -fixed false -x 604 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[7\] -fixed false -x 450 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01 -fixed false -x 484 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2125_0_0 -fixed false -x 671 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[15\] -fixed false -x 471 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[19\] -fixed false -x 861 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m3 -fixed false -x 490 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1282 -fixed false -x 730 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[1\] -fixed false -x 402 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_4_0\[15\] -fixed false -x 136 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[8\] -fixed false -x 95 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[27\] -fixed false -x 863 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig_0_RNI9OMIT1 -fixed false -x 803 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_488 -fixed false -x 634 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[12\] -fixed false -x 947 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/empty_out_RNO -fixed false -x 537 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2_3\[1\] -fixed false -x 632 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/illegal_instr_retr -fixed false -x 743 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[14\] -fixed false -x 218 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[7\] -fixed false -x 404 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_5\[13\] -fixed false -x 693 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25\[8\] -fixed false -x 297 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[21\] -fixed false -x 373 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[9\] -fixed false -x 223 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[0\] -fixed false -x 29 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0\[0\] -fixed false -x 124 -y 198
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i -fixed false -x 23 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[22\] -fixed false -x 874 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_2\[25\] -fixed false -x 737 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[12\] -fixed false -x 351 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_e_2 -fixed false -x 655 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[29\] -fixed false -x 923 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_0\[3\] -fixed false -x 753 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiO1 -fixed false -x 108 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[9\] -fixed false -x 511 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1170 -fixed false -x 670 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[6\] -fixed false -x 919 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0\[15\] -fixed false -x 324 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m37 -fixed false -x 34 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_0\[11\] -fixed false -x 843 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[11\] -fixed false -x 781 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[13\] -fixed false -x 323 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[24\] -fixed false -x 449 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m74_0_a3 -fixed false -x 35 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[13\] -fixed false -x 368 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[13\] -fixed false -x 747 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[3\] -fixed false -x 720 -y 132
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write_8.m5_2_0 -fixed false -x 465 -y 147
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[25\] -fixed false -x 415 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_m2 -fixed false -x 634 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_8\[5\] -fixed false -x 296 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[6\] -fixed false -x 66 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[0\] -fixed false -x 298 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[11\] -fixed false -x 408 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[0\] -fixed false -x 268 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.m4_1_0 -fixed false -x 83 -y 198
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[0\] -fixed false -x 442 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_0 -fixed false -x 116 -y 171
|
|
set_location -inst_name coma_mode_obuf_RNO -fixed false -x 89 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_39_0_a2 -fixed false -x 632 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[25\] -fixed false -x 120 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1\[0\] -fixed false -x 105 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liOOo -fixed false -x 53 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[2\] -fixed false -x 203 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[0\].BUFD_BLK -fixed false -x 489 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[57\] -fixed false -x 834 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_27\[3\] -fixed false -x 496 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[3\] -fixed false -x 233 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2\[2\] -fixed false -x 227 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[15\] -fixed false -x 886 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2\[10\] -fixed false -x 695 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[17\] -fixed false -x 374 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[7\] -fixed false -x 702 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_7 -fixed false -x 730 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[11\] -fixed false -x 935 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[7\] -fixed false -x 803 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iolOo\[0\] -fixed false -x 132 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_0_0 -fixed false -x 100 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19_1_RNI09BIB -fixed false -x 653 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNICGA84\[26\] -fixed false -x 947 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[3\] -fixed false -x 248 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q\[2\] -fixed false -x 567 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[17\] -fixed false -x 664 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[9\] -fixed false -x 176 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mvendorid_sw_rd_sel_3 -fixed false -x 702 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m14 -fixed false -x 789 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[8\] -fixed false -x 204 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m10 -fixed false -x 127 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[7\] -fixed false -x 34 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[25\] -fixed false -x 392 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_453 -fixed false -x 793 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un60_OIoO1 -fixed false -x 81 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftIR_ne_0 -fixed false -x 557 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_9 -fixed false -x 22 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1\[0\] -fixed false -x 88 -y 196
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2\[1\] -fixed false -x 381 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[12\] -fixed false -x 477 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4951_3 -fixed false -x 656 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto10 -fixed false -x 143 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[7\] -fixed false -x 308 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[27\] -fixed false -x 910 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[23\] -fixed false -x 598 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[7\] -fixed false -x 165 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[12\] -fixed false -x 457 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[10\] -fixed false -x 947 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s\[6\] -fixed false -x 517 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_update_dout_0 -fixed false -x 386 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_611 -fixed false -x 669 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[7\] -fixed false -x 280 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[5\] -fixed false -x 443 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[20\] -fixed false -x 755 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[3\] -fixed false -x 549 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_495 -fixed false -x 604 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[4\] -fixed false -x 401 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2_0_tz_0\[1\] -fixed false -x 21 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[28\] -fixed false -x 684 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlOo1_0 -fixed false -x 306 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[28\] -fixed false -x 841 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_675 -fixed false -x 694 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m10_1 -fixed false -x 774 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2 -fixed false -x 701 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oooo1_0 -fixed false -x 71 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[31\] -fixed false -x 630 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[14\] -fixed false -x 856 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_2_0 -fixed false -x 790 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_0_4\[0\] -fixed false -x 140 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[19\] -fixed false -x 342 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[18\] -fixed false -x 381 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[1\] -fixed false -x 185 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv_0\[7\] -fixed false -x 755 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[1\] -fixed false -x 890 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[22\] -fixed false -x 450 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1022 -fixed false -x 657 -y 171
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full6_6 -fixed false -x 407 -y 255
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_3 -fixed false -x 85 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv\[1\] -fixed false -x 725 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1\[1\] -fixed false -x 129 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIBE6GO\[13\] -fixed false -x 897 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_826 -fixed false -x 718 -y 198
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/state_RNO\[0\] -fixed false -x 403 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/un1_iOI01_1_i_0 -fixed false -x 341 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[11\] -fixed false -x 47 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val_RNI7LT92\[0\] -fixed false -x 568 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a2_0\[2\] -fixed false -x 688 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1077 -fixed false -x 693 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[6\] -fixed false -x 525 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[36\] -fixed false -x 913 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO_1 -fixed false -x 797 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un71_I1Oi1_2 -fixed false -x 59 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[8\] -fixed false -x 935 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un7_Iiii1 -fixed false -x 130 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0\[0\] -fixed false -x 655 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[27\] -fixed false -x 814 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM\[1\] -fixed false -x 206 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[14\] -fixed false -x 119 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOOOo_2 -fixed false -x 141 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_1 -fixed false -x 773 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNISUR5C\[23\] -fixed false -x 683 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[27\] -fixed false -x 683 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[45\] -fixed false -x 564 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[1\] -fixed false -x 302 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1\[4\] -fixed false -x 140 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[6\] -fixed false -x 631 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex\[0\] -fixed false -x 750 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[30\] -fixed false -x 243 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[12\] -fixed false -x 794 -y 121
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10_0 -fixed false -x 515 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[4\] -fixed false -x 923 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[0\] -fixed false -x 572 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_buff_resp_head_compressed -fixed false -x 635 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1 -fixed false -x 816 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_217 -fixed false -x 616 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[2\] -fixed false -x 445 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[2\] -fixed false -x 121 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[20\] -fixed false -x 654 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[3\] -fixed false -x 423 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[22\] -fixed false -x 144 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m_a0_3_1_0\[0\] -fixed false -x 840 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[6\] -fixed false -x 688 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[13\] -fixed false -x 26 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[8\] -fixed false -x 782 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oloo1_RNO -fixed false -x 106 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_0_RNIVV66JP -fixed false -x 824 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_4_RNII9Q102\[3\] -fixed false -x 37 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[7\] -fixed false -x 755 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/un1_iOI01_1_i_0 -fixed false -x 202 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_225 -fixed false -x 739 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[22\] -fixed false -x 170 -y 178
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[13\] -fixed false -x 562 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[23\] -fixed false -x 216 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m212 -fixed false -x 263 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oliO1 -fixed false -x 198 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[30\] -fixed false -x 462 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[22\] -fixed false -x 119 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[0\] -fixed false -x 510 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_1 -fixed false -x 171 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_4 -fixed false -x 406 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[8\] -fixed false -x 302 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[1\] -fixed false -x 530 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.debug_mode6 -fixed false -x 786 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_10 -fixed false -x 769 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq\[0\].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val\[0\] -fixed false -x 779 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[5\] -fixed false -x 432 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_0_0\[4\] -fixed false -x 351 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[6\] -fixed false -x 53 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_2 -fixed false -x 533 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_3 -fixed false -x 815 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[24\] -fixed false -x 873 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_ptr_0\[0\] -fixed false -x 788 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_38 -fixed false -x 694 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_str_ex -fixed false -x 765 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_o2_2 -fixed false -x 192 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un128_OOOI1_cZ\[21\] -fixed false -x 452 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[0\] -fixed false -x 548 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[9\] -fixed false -x 62 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[2\] -fixed false -x 686 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[14\] -fixed false -x 384 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_2 -fixed false -x 227 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[4\] -fixed false -x 275 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[1\] -fixed false -x 453 -y 208
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO\[4\] -fixed false -x 518 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3_0 -fixed false -x 765 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[8\] -fixed false -x 782 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[14\] -fixed false -x 141 -y 208
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[6\] -fixed false -x 488 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOli1_9 -fixed false -x 179 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[16\].BUFD_BLK -fixed false -x 533 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1\[4\] -fixed false -x 336 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[22\] -fixed false -x 864 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1 -fixed false -x 74 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01\[3\] -fixed false -x 209 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m268 -fixed false -x 262 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[6\] -fixed false -x 430 -y 196
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[3\] -fixed false -x 44 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[27\] -fixed false -x 846 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.IloIo -fixed false -x 388 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O01i1_i_a3 -fixed false -x 203 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[1\] -fixed false -x 256 -y 178
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err15 -fixed false -x 464 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[43\] -fixed false -x 232 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_894 -fixed false -x 660 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[29\] -fixed false -x 93 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[9\] -fixed false -x 300 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[5\] -fixed false -x 615 -y 154
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_2 -fixed false -x 441 -y 3
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[1\] -fixed false -x 377 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[6\] -fixed false -x 430 -y 214
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_6 -fixed false -x 440 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_812 -fixed false -x 766 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[20\] -fixed false -x 58 -y 235
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_2 -fixed false -x 44 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19 -fixed false -x 93 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[56\] -fixed false -x 545 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb\[0\] -fixed false -x 595 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[22\] -fixed false -x 818 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr4 -fixed false -x 783 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[8\] -fixed false -x 61 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_759 -fixed false -x 646 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lO1o1 -fixed false -x 59 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[6\] -fixed false -x 136 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[8\] -fixed false -x 183 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[8\] -fixed false -x 343 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[13\] -fixed false -x 24 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[12\] -fixed false -x 530 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[0\] -fixed false -x 246 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_m2_2\[1\] -fixed false -x 121 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2_0\[0\] -fixed false -x 647 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[61\] -fixed false -x 935 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[4\] -fixed false -x 361 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[24\] -fixed false -x 142 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIoo1_RNO -fixed false -x 104 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_a0_1\[3\] -fixed false -x 752 -y 129
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3\[1\] -fixed false -x 103 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1 -fixed false -x 107 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[8\] -fixed false -x 311 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_resume_req -fixed false -x 797 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1 -fixed false -x 798 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[8\] -fixed false -x 922 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_263 -fixed false -x 729 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1\[0\] -fixed false -x 470 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_160 -fixed false -x 609 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIVQKV4\[8\] -fixed false -x 95 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[22\] -fixed false -x 865 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_20 -fixed false -x 874 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[14\] -fixed false -x 412 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel\[2\] -fixed false -x 540 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/cause_excpt_code_excpt\[1\] -fixed false -x 742 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[10\] -fixed false -x 499 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_RNI1MMDF -fixed false -x 685 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[20\] -fixed false -x 471 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/un1_iOI01_1_i_0 -fixed false -x 261 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I0I01 -fixed false -x 361 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_2_i -fixed false -x 784 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[10\] -fixed false -x 431 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_2_RNIT56KL1 -fixed false -x 169 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[4\] -fixed false -x 121 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[17\] -fixed false -x 274 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[8\] -fixed false -x 74 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[3\] -fixed false -x 370 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIT3VA9 -fixed false -x 43 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr\[0\] -fixed false -x 786 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[28\] -fixed false -x 734 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_8 -fixed false -x 449 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m14 -fixed false -x 262 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[5\] -fixed false -x 272 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_5\[0\] -fixed false -x 107 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2 -fixed false -x 663 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m26 -fixed false -x 59 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[6\] -fixed false -x 831 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[3\] -fixed false -x 178 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0\[7\] -fixed false -x 135 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOo11 -fixed false -x 152 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/un1_iOI01_1_i_0 -fixed false -x 224 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[15\] -fixed false -x 382 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1 -fixed false -x 385 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_3_1 -fixed false -x 647 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_998 -fixed false -x 609 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[29\] -fixed false -x 604 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39\[3\] -fixed false -x 280 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[4\] -fixed false -x 338 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[0\] -fixed false -x 234 -y 217
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[5\] -fixed false -x 38 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[6\] -fixed false -x 266 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lI1I1\[0\] -fixed false -x 377 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJDVQ8\[30\] -fixed false -x 621 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[0\] -fixed false -x 394 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI1Oo\[0\] -fixed false -x 145 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[4\] -fixed false -x 275 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z\[3\] -fixed false -x 292 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4917_3 -fixed false -x 649 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_10_0_o2 -fixed false -x 194 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[19\] -fixed false -x 670 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[31\] -fixed false -x 236 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[34\] -fixed false -x 911 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[8\] -fixed false -x 328 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[4\] -fixed false -x 103 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_37 -fixed false -x 671 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[4\] -fixed false -x 278 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[19\] -fixed false -x 838 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[4\] -fixed false -x 610 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loOOo -fixed false -x 56 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_3 -fixed false -x 202 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[20\] -fixed false -x 946 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[1\] -fixed false -x 151 -y 171
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/iPSELS\[1\] -fixed false -x 478 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[5\] -fixed false -x 634 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[15\] -fixed false -x 711 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O0iI1 -fixed false -x 479 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4\[6\] -fixed false -x 122 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[5\] -fixed false -x 896 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[14\] -fixed false -x 923 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[1\] -fixed false -x 139 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[24\] -fixed false -x 708 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[6\] -fixed false -x 169 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[2\] -fixed false -x 37 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[0\] -fixed false -x 427 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[9\] -fixed false -x 467 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8\[11\] -fixed false -x 266 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10\[11\] -fixed false -x 268 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/extract_os_i_loop_l1.un12_req_os_i_src\[0\] -fixed false -x 762 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[16\] -fixed false -x 419 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIQF7VA\[10\] -fixed false -x 670 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[0\] -fixed false -x 175 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtm_resp_ready -fixed false -x 618 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[7\] -fixed false -x 362 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[6\] -fixed false -x 102 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[15\] -fixed false -x 923 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[15\] -fixed false -x 923 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0IIo -fixed false -x 265 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_791 -fixed false -x 694 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[10\] -fixed false -x 437 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[26\] -fixed false -x 863 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[22\] -fixed false -x 863 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[33\] -fixed false -x 678 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[14\] -fixed false -x 470 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[1\] -fixed false -x 498 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[0\] -fixed false -x 599 -y 118
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count\[3\] -fixed false -x 483 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[29\] -fixed false -x 829 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[1\] -fixed false -x 331 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.fifo_reset -fixed false -x 596 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[7\] -fixed false -x 674 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO -fixed false -x 805 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[13\] -fixed false -x 498 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_2_1 -fixed false -x 126 -y 192
|
|
set_location -inst_name SSDetect_0/rx_start\[1\] -fixed false -x 18 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO -fixed false -x 841 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_459 -fixed false -x 669 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[10\] -fixed false -x 84 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[28\] -fixed false -x 959 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[24\] -fixed false -x 540 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[26\] -fixed false -x 836 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg\[1\] -fixed false -x 741 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_697 -fixed false -x 766 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[1\] -fixed false -x 911 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u\[3\] -fixed false -x 907 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[9\] -fixed false -x 747 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_796 -fixed false -x 663 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/un1_iOI01_1_i_0 -fixed false -x 403 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[6\] -fixed false -x 111 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex\[1\] -fixed false -x 747 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftBP_ne_0_3 -fixed false -x 559 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[16\] -fixed false -x 699 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_512 -fixed false -x 668 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[51\] -fixed false -x 153 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[14\] -fixed false -x 135 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr\[1\] -fixed false -x 822 -y 148
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples\[1\] -fixed false -x 469 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5\[1\] -fixed false -x 229 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12 -fixed false -x 650 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_951 -fixed false -x 772 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[16\] -fixed false -x 310 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiOo1_2 -fixed false -x 300 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].un1_lsu_flush -fixed false -x 822 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[36\] -fixed false -x 916 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[16\] -fixed false -x 651 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m7 -fixed false -x 863 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_1_0 -fixed false -x 791 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO\[1\] -fixed false -x 77 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[12\] -fixed false -x 663 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[6\] -fixed false -x 354 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[4\] -fixed false -x 650 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[25\] -fixed false -x 681 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1i11_2 -fixed false -x 308 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[5\] -fixed false -x 725 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z\[3\] -fixed false -x 349 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[6\] -fixed false -x 431 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[6\] -fixed false -x 169 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush_RNO\[1\] -fixed false -x 787 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[29\] -fixed false -x 959 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_o17_2 -fixed false -x 639 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[5\] -fixed false -x 646 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[6\] -fixed false -x 322 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[31\] -fixed false -x 879 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_4 -fixed false -x 736 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[7\] -fixed false -x 833 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1OOo -fixed false -x 19 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/wr_en_data_or -fixed false -x 722 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un139_i11Io -fixed false -x 417 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[8\] -fixed false -x 887 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[21\] -fixed false -x 550 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[34\] -fixed false -x 647 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[11\] -fixed false -x 934 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1_RNIGL6FD13 -fixed false -x 785 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[2\] -fixed false -x 371 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01\[1\] -fixed false -x 211 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un19_ioIO1_0 -fixed false -x 154 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1179 -fixed false -x 703 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un6_I1ii1_0_a2 -fixed false -x 139 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[20\] -fixed false -x 426 -y 195
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[5\] -fixed false -x 485 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[16\] -fixed false -x 395 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[6\] -fixed false -x 346 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[17\] -fixed false -x 381 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_7\[0\] -fixed false -x 262 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIIo\[0\] -fixed false -x 123 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2_RNO\[22\] -fixed false -x 895 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_364 -fixed false -x 670 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_RNI1SM77\[1\] -fixed false -x 15 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[15\] -fixed false -x 725 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[16\] -fixed false -x 533 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[0\] -fixed false -x 334 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto3 -fixed false -x 139 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_273 -fixed false -x 777 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRHRQ8\[16\] -fixed false -x 650 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[17\] -fixed false -x 893 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[26\] -fixed false -x 737 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[13\] -fixed false -x 530 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O11l1 -fixed false -x 394 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_337 -fixed false -x 622 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[29\] -fixed false -x 635 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_170 -fixed false -x 682 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[18\] -fixed false -x 590 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[1\] -fixed false -x 114 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[25\] -fixed false -x 871 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1 -fixed false -x 106 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[6\] -fixed false -x 91 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[14\] -fixed false -x 959 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_1_140_a2 -fixed false -x 429 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1255 -fixed false -x 681 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1196 -fixed false -x 688 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo_RNO\[1\] -fixed false -x 131 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i_a2_1 -fixed false -x 595 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[15\] -fixed false -x 28 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[22\] -fixed false -x 740 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_116 -fixed false -x 687 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/force_debug_nop_de -fixed false -x 712 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_888 -fixed false -x 621 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1116 -fixed false -x 670 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[7\] -fixed false -x 303 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m5 -fixed false -x 130 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[12\] -fixed false -x 575 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1io1 -fixed false -x 83 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[7\] -fixed false -x 170 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[6\] -fixed false -x 185 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z\[1\] -fixed false -x 254 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[11\] -fixed false -x 92 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1 -fixed false -x 202 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_1 -fixed false -x 635 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_9 -fixed false -x 391 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[21\] -fixed false -x 910 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/iII01 -fixed false -x 226 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0_1_0\[0\] -fixed false -x 297 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O0lI1 -fixed false -x 384 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_ready_reg_RNO -fixed false -x 759 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m183 -fixed false -x 263 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_28_u\[31\] -fixed false -x 934 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5\[5\] -fixed false -x 150 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_15\[9\] -fixed false -x 311 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[13\] -fixed false -x 154 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO_0 -fixed false -x 863 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[23\] -fixed false -x 911 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[9\] -fixed false -x 802 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff -fixed false -x 727 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_7 -fixed false -x 754 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[13\] -fixed false -x 83 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4\[0\] -fixed false -x 519 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Olio1 -fixed false -x 83 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/gen_bit_reset.state_val\[0\] -fixed false -x 730 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_5 -fixed false -x 658 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[8\] -fixed false -x 408 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_a4\[2\] -fixed false -x 40 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[8\] -fixed false -x 696 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr\[3\] -fixed false -x 768 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oioOo -fixed false -x 99 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[23\] -fixed false -x 916 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[11\] -fixed false -x 768 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_50 -fixed false -x 645 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un75_I1Oi1_0 -fixed false -x 40 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[3\] -fixed false -x 267 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0 -fixed false -x 820 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_5 -fixed false -x 164 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[33\] -fixed false -x 679 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/o01l1 -fixed false -x 386 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI93FGI\[2\] -fixed false -x 449 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_1\[1\] -fixed false -x 623 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[49\] -fixed false -x 930 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[11\] -fixed false -x 704 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[40\] -fixed false -x 522 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[11\] -fixed false -x 558 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[15\] -fixed false -x 971 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[33\] -fixed false -x 626 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1 -fixed false -x 135 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[22\] -fixed false -x 822 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[17\] -fixed false -x 383 -y 187
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[15\] -fixed false -x 391 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[6\] -fixed false -x 257 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[17\] -fixed false -x 729 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[13\] -fixed false -x 916 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9\[4\] -fixed false -x 171 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ll1o1 -fixed false -x 78 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[2\] -fixed false -x 65 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/genblk1.rst_synch_reg\[1\] -fixed false -x 664 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[8\] -fixed false -x 140 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[8\] -fixed false -x 407 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_RNO\[1\] -fixed false -x 667 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[10\] -fixed false -x 853 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[12\] -fixed false -x 527 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[23\] -fixed false -x 838 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[31\] -fixed false -x 753 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[11\] -fixed false -x 298 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_7 -fixed false -x 35 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[7\] -fixed false -x 166 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[19\] -fixed false -x 679 -y 123
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0_1 -fixed false -x 1742 -y 5
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite -fixed false -x 588 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[12\] -fixed false -x 153 -y 181
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_1_sqmuxa_2 -fixed false -x 42 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[6\] -fixed false -x 399 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[3\] -fixed false -x 79 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[14\] -fixed false -x 346 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[0\] -fixed false -x 66 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.lloIo -fixed false -x 472 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[5\] -fixed false -x 181 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[27\] -fixed false -x 946 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[16\] -fixed false -x 816 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_43\[10\] -fixed false -x 239 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 367 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[4\] -fixed false -x 735 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[9\] -fixed false -x 411 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[22\] -fixed false -x 409 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[15\] -fixed false -x 959 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[10\] -fixed false -x 457 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI0O9V9_0\[7\] -fixed false -x 105 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[12\] -fixed false -x 880 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[4\] -fixed false -x 431 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM\[1\] -fixed false -x 72 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[25\] -fixed false -x 756 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[15\] -fixed false -x 74 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_4 -fixed false -x 765 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write8 -fixed false -x 463 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[8\] -fixed false -x 193 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[11\] -fixed false -x 347 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[15\] -fixed false -x 711 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_lliOo_1.CO1_1 -fixed false -x 339 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[2\] -fixed false -x 494 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[4\] -fixed false -x 69 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[15\] -fixed false -x 598 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[5\] -fixed false -x 381 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[30\] -fixed false -x 800 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO -fixed false -x 778 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40_cZ\[8\] -fixed false -x 382 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[1\] -fixed false -x 401 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[15\] -fixed false -x 848 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[2\] -fixed false -x 620 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[9\] -fixed false -x 175 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[15\] -fixed false -x 877 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m3 -fixed false -x 850 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_11_RNO -fixed false -x 364 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[28\] -fixed false -x 737 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd -fixed false -x 725 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[3\] -fixed false -x 392 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[6\] -fixed false -x 830 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un37_lolIo -fixed false -x 23 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2\[1\] -fixed false -x 618 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_299 -fixed false -x 740 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_281 -fixed false -x 610 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_441 -fixed false -x 597 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[57\] -fixed false -x 547 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[12\] -fixed false -x 156 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un3_IOIOo -fixed false -x 38 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_742 -fixed false -x 777 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[11\] -fixed false -x 214 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[24\] -fixed false -x 445 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[14\] -fixed false -x 241 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_execute/gen_bit_reset.state_val_RNO\[0\] -fixed false -x 807 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[15\] -fixed false -x 685 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOoOo_0 -fixed false -x 175 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[14\] -fixed false -x 126 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_1_3 -fixed false -x 186 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/olli1 -fixed false -x 188 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[20\] -fixed false -x 428 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv\[3\] -fixed false -x 30 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[23\] -fixed false -x 836 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[24\] -fixed false -x 852 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[11\] -fixed false -x 94 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[0\] -fixed false -x 278 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[3\] -fixed false -x 116 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_lIii1lto3 -fixed false -x 134 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[10\] -fixed false -x 134 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txready_at_ssel -fixed false -x 507 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_374 -fixed false -x 686 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[9\] -fixed false -x 429 -y 217
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3_1\[1\] -fixed false -x 81 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[13\] -fixed false -x 473 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[22\] -fixed false -x 911 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[6\] -fixed false -x 370 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[3\] -fixed false -x 878 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un83_I1Oi1_1 -fixed false -x 33 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[19\] -fixed false -x 712 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[12\] -fixed false -x 459 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[27\] -fixed false -x 680 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_1_sqmuxa -fixed false -x 486 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_183 -fixed false -x 669 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_o1oOo_0 -fixed false -x 130 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2 -fixed false -x 165 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[2\] -fixed false -x 65 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/loIO1\[8\] -fixed false -x 97 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[27\] -fixed false -x 849 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[8\] -fixed false -x 38 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIBTFUI\[4\] -fixed false -x 876 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[11\] -fixed false -x 368 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[25\] -fixed false -x 862 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[5\] -fixed false -x 68 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state137 -fixed false -x 515 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[10\] -fixed false -x 707 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_29\[2\] -fixed false -x 293 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[9\] -fixed false -x 44 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/l1lIo.m5 -fixed false -x 119 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[0\] -fixed false -x 322 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[14\] -fixed false -x 781 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2_2_1 -fixed false -x 119 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_48 -fixed false -x 836 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[5\] -fixed false -x 792 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[6\] -fixed false -x 62 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[13\] -fixed false -x 363 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m11_0 -fixed false -x 118 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1146 -fixed false -x 789 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOil1 -fixed false -x 408 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[17\] -fixed false -x 749 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO -fixed false -x 879 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[16\] -fixed false -x 753 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[35\] -fixed false -x 314 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIi11 -fixed false -x 359 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[25\] -fixed false -x 931 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IOio1 -fixed false -x 76 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[25\] -fixed false -x 610 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un128_OOOI1_cZ\[22\] -fixed false -x 455 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[9\] -fixed false -x 335 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[21\] -fixed false -x 791 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[16\] -fixed false -x 348 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[0\] -fixed false -x 424 -y 198
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[30\].BUFD_BLK -fixed false -x 489 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1039 -fixed false -x 646 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m21_1 -fixed false -x 59 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[30\] -fixed false -x 935 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[13\] -fixed false -x 355 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[4\] -fixed false -x 507 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[6\] -fixed false -x 102 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_hword_high_only_u_i_m2_1_0 -fixed false -x 875 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[4\] -fixed false -x 819 -y 190
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc2 -fixed false -x 119 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[6\] -fixed false -x 738 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[16\] -fixed false -x 84 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_1\[16\] -fixed false -x 947 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i\[0\] -fixed false -x 106 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[0\] -fixed false -x 562 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_10 -fixed false -x 620 -y 186
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[1\] -fixed false -x 42 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i\[1\] -fixed false -x 59 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un59_ool01 -fixed false -x 187 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[25\] -fixed false -x 656 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_o2\[5\] -fixed false -x 746 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[18\] -fixed false -x 463 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un18_lsu_op_str_ex_2 -fixed false -x 764 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_390 -fixed false -x 652 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[7\] -fixed false -x 178 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[12\] -fixed false -x 394 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[27\] -fixed false -x 849 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_307 -fixed false -x 645 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[1\] -fixed false -x 147 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[12\] -fixed false -x 696 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_5 -fixed false -x 190 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[6\] -fixed false -x 403 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[0\] -fixed false -x 49 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[2\] -fixed false -x 206 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[2\] -fixed false -x 507 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[16\] -fixed false -x 806 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[10\] -fixed false -x 239 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1287 -fixed false -x 788 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[21\] -fixed false -x 664 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[25\] -fixed false -x 754 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OOIOo_RNIKB7HO -fixed false -x 45 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[28\] -fixed false -x 863 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_1 -fixed false -x 304 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[1\] -fixed false -x 306 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oiil1 -fixed false -x 524 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3_1\[5\] -fixed false -x 108 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_626 -fixed false -x 766 -y 186
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2\[1\] -fixed false -x 480 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliO1 -fixed false -x 174 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[16\] -fixed false -x 532 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel -fixed false -x 719 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0_a2_1_0 -fixed false -x 105 -y 210
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo -fixed false -x 524 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[11\] -fixed false -x 475 -y 201
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns\[5\] -fixed false -x 446 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[7\] -fixed false -x 472 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[29\] -fixed false -x 935 -y 132
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_4 -fixed false -x 539 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[7\] -fixed false -x 444 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un179_I1Oi1_1 -fixed false -x 70 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3\[5\] -fixed false -x 538 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[14\] -fixed false -x 313 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846 -fixed false -x 611 -y 147
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_6_RNO -fixed false -x 48 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[3\] -fixed false -x 406 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u\[8\] -fixed false -x 959 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_d_1_sqmuxa_2 -fixed false -x 502 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[18\] -fixed false -x 472 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.haltreq_debug_enter_pending6 -fixed false -x 776 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_34 -fixed false -x 670 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m271 -fixed false -x 261 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4\[15\] -fixed false -x 132 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[8\] -fixed false -x 145 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[14\] -fixed false -x 144 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Io1l1 -fixed false -x 412 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0\[4\] -fixed false -x 118 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[9\] -fixed false -x 373 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[7\] -fixed false -x 95 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[18\] -fixed false -x 421 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr\[5\] -fixed false -x 837 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4\[2\] -fixed false -x 634 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[4\] -fixed false -x 102 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_2\[0\] -fixed false -x 105 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_trx_os_d_wr_6_i_i_a2 -fixed false -x 622 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[8\] -fixed false -x 350 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1iO1 -fixed false -x 217 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[11\] -fixed false -x 407 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[13\] -fixed false -x 287 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[6\] -fixed false -x 364 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[10\] -fixed false -x 249 -y 184
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[11\] -fixed false -x 389 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[4\] -fixed false -x 416 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_0 -fixed false -x 839 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/tdo_0 -fixed false -x 558 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_910 -fixed false -x 604 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_129 -fixed false -x 771 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[2\] -fixed false -x 228 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[27\] -fixed false -x 383 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[17\] -fixed false -x 741 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.CO1 -fixed false -x 36 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.N_20_i -fixed false -x 71 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[0\] -fixed false -x 182 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex\[0\] -fixed false -x 719 -y 142
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/state\[0\] -fixed false -x 403 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_axb_31_1 -fixed false -x 912 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_195 -fixed false -x 706 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO\[3\] -fixed false -x 548 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[22\] -fixed false -x 804 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[31\] -fixed false -x 683 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[11\] -fixed false -x 706 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[30\] -fixed false -x 615 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[7\] -fixed false -x 252 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[5\] -fixed false -x 374 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[2\] -fixed false -x 99 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1 -fixed false -x 44 -y 180
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_7 -fixed false -x 6 -y 164
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0\[6\] -fixed false -x 346 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[5\] -fixed false -x 236 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_m_0\[4\] -fixed false -x 671 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[20\] -fixed false -x 558 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[20\] -fixed false -x 472 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[12\] -fixed false -x 759 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[0\] -fixed false -x 726 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[4\] -fixed false -x 230 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[0\] -fixed false -x 418 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111_2 -fixed false -x 390 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_45\[5\] -fixed false -x 492 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[7\] -fixed false -x 754 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[2\] -fixed false -x 911 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[27\] -fixed false -x 338 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[7\] -fixed false -x 493 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[11\] -fixed false -x 387 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[13\] -fixed false -x 647 -y 123
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[31\] -fixed false -x 408 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[2\] -fixed false -x 682 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[0\] -fixed false -x 131 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[11\] -fixed false -x 539 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_414 -fixed false -x 706 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[13\] -fixed false -x 849 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIGMUT5 -fixed false -x 258 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[10\] -fixed false -x 371 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[2\] -fixed false -x 462 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[3\] -fixed false -x 607 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[6\] -fixed false -x 763 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[9\] -fixed false -x 362 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[27\] -fixed false -x 383 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[11\] -fixed false -x 236 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_0_sqmuxa -fixed false -x 695 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[38\] -fixed false -x 151 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[1\] -fixed false -x 128 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_a2_0 -fixed false -x 95 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[28\] -fixed false -x 815 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_O1Ii1_4 -fixed false -x 284 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op\[0\] -fixed false -x 813 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[15\] -fixed false -x 751 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7\[5\] -fixed false -x 203 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[31\] -fixed false -x 474 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[5\] -fixed false -x 639 -y 127
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples\[0\] -fixed false -x 471 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_I00Oo_4 -fixed false -x 247 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[6\] -fixed false -x 837 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[7\] -fixed false -x 118 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_682 -fixed false -x 634 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[0\] -fixed false -x 65 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[9\] -fixed false -x 549 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[18\] -fixed false -x 908 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[7\] -fixed false -x 760 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[13\] -fixed false -x 239 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[0\] -fixed false -x 59 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[29\] -fixed false -x 417 -y 237
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2\[2\] -fixed false -x 487 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[5\] -fixed false -x 231 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/I0lo1 -fixed false -x 324 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[15\] -fixed false -x 463 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_2 -fixed false -x 767 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_2_i -fixed false -x 529 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_587 -fixed false -x 728 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0_a2_0 -fixed false -x 203 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[8\] -fixed false -x 379 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_528 -fixed false -x 747 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2\[17\] -fixed false -x 118 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[15\] -fixed false -x 218 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[10\] -fixed false -x 442 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[21\] -fixed false -x 409 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[31\] -fixed false -x 451 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[17\].BUFD_BLK -fixed false -x 532 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_ptr\[0\] -fixed false -x 640 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[10\] -fixed false -x 516 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[13\] -fixed false -x 386 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m7 -fixed false -x 68 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[0\] -fixed false -x 788 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[11\] -fixed false -x 127 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[7\] -fixed false -x 498 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[19\] -fixed false -x 433 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_0_RNO_0 -fixed false -x 814 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en\[3\] -fixed false -x 749 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_3 -fixed false -x 644 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[6\] -fixed false -x 172 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_sn_m2 -fixed false -x 826 -y 135
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[8\] -fixed false -x 381 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[17\] -fixed false -x 805 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1_1_0 -fixed false -x 70 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[22\] -fixed false -x 675 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_1_0\[4\] -fixed false -x 14 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[4\] -fixed false -x 188 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[9\] -fixed false -x 165 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[6\] -fixed false -x 427 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_IoOOo_0 -fixed false -x 54 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[32\] -fixed false -x 125 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[17\] -fixed false -x 695 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[18\] -fixed false -x 832 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[3\] -fixed false -x 387 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO_1 -fixed false -x 836 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[10\] -fixed false -x 201 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[9\] -fixed false -x 390 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[29\] -fixed false -x 456 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_955 -fixed false -x 680 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[16\] -fixed false -x 748 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[8\] -fixed false -x 215 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_pktsel -fixed false -x 518 -y 148
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[4\] -fixed false -x 376 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[15\] -fixed false -x 669 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO -fixed false -x 271 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[13\] -fixed false -x 100 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[5\] -fixed false -x 215 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[8\] -fixed false -x 911 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[6\] -fixed false -x 299 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[28\] -fixed false -x 809 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[6\] -fixed false -x 249 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IOoo1_i_o2 -fixed false -x 103 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mstatus_sw_rd_sel_1 -fixed false -x 706 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_550 -fixed false -x 717 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[6\] -fixed false -x 129 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[3\] -fixed false -x 68 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[5\] -fixed false -x 859 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[25\] -fixed false -x 63 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[15\] -fixed false -x 528 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI69S5C\[28\] -fixed false -x 633 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[11\] -fixed false -x 503 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[21\] -fixed false -x 922 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[12\] -fixed false -x 517 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[21\] -fixed false -x 937 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m10 -fixed false -x 117 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[13\] -fixed false -x 544 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO\[2\] -fixed false -x 320 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iIIi1_2_tz -fixed false -x 179 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa_RNI98ALL -fixed false -x 733 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[7\] -fixed false -x 136 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel -fixed false -x 513 -y 148
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1 -fixed false -x 469 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[8\] -fixed false -x 64 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[16\] -fixed false -x 835 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[0\] -fixed false -x 337 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m44 -fixed false -x 35 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv\[0\] -fixed false -x 719 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[10\] -fixed false -x 550 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1_0 -fixed false -x 539 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2\[7\] -fixed false -x 263 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI06I0G1\[0\] -fixed false -x 32 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2\[3\] -fixed false -x 135 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[27\] -fixed false -x 654 -y 118
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14 -fixed false -x 491 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[9\] -fixed false -x 665 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[40\] -fixed false -x 260 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[2\] -fixed false -x 514 -y 148
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[6\] -fixed false -x 22 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[4\] -fixed false -x 101 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[13\] -fixed false -x 442 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m3 -fixed false -x 22 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[24\] -fixed false -x 877 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[17\] -fixed false -x 252 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[13\] -fixed false -x 100 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[11\] -fixed false -x 845 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0_o2\[15\] -fixed false -x 167 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[24\] -fixed false -x 816 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[26\] -fixed false -x 726 -y 124
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_dataerr -fixed false -x 502 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un7_i_0 -fixed false -x 481 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex\[1\] -fixed false -x 730 -y 142
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc4 -fixed false -x 62 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[7\] -fixed false -x 767 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[8\] -fixed false -x 334 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[20\] -fixed false -x 610 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[0\] -fixed false -x 343 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[2\] -fixed false -x 197 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[19\] -fixed false -x 652 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[5\] -fixed false -x 491 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[13\] -fixed false -x 147 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIEHT832 -fixed false -x 904 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[5\] -fixed false -x 307 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1_RNO -fixed false -x 188 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_branch_cond_1\[0\] -fixed false -x 724 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[12\] -fixed false -x 779 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[11\] -fixed false -x 697 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1\[3\] -fixed false -x 295 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff\[0\] -fixed false -x 705 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[4\] -fixed false -x 257 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[20\] -fixed false -x 408 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_dbreak_ex -fixed false -x 745 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[24\] -fixed false -x 423 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[10\] -fixed false -x 418 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_569 -fixed false -x 682 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Io0l1\[0\] -fixed false -x 448 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_olio1_2 -fixed false -x 71 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[3\] -fixed false -x 134 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[21\] -fixed false -x 850 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[12\] -fixed false -x 641 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o3_3 -fixed false -x 624 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[14\] -fixed false -x 82 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_0_sqmuxa_4 -fixed false -x 514 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2123 -fixed false -x 658 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en\[0\] -fixed false -x 789 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[1\] -fixed false -x 364 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[1\] -fixed false -x 403 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[10\] -fixed false -x 515 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[42\] -fixed false -x 561 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[16\] -fixed false -x 79 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[1\] -fixed false -x 457 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[15\] -fixed false -x 125 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[18\] -fixed false -x 656 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.step_debug_enter_pending6 -fixed false -x 770 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[14\] -fixed false -x 216 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[11\] -fixed false -x 659 -y 124
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[2\] -fixed false -x 15 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[8\] -fixed false -x 922 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_exce\[0\] -fixed false -x 772 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0\[5\] -fixed false -x 343 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1135 -fixed false -x 764 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[26\] -fixed false -x 947 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oOio1_0 -fixed false -x 58 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[4\] -fixed false -x 100 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0\[3\] -fixed false -x 716 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1 -fixed false -x 188 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOoI1 -fixed false -x 389 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[4\] -fixed false -x 84 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un55_Oo1Io -fixed false -x 407 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[8\] -fixed false -x 124 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[4\] -fixed false -x 77 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01\[8\] -fixed false -x 193 -y 210
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_9_u_2\[7\] -fixed false -x 483 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[6\] -fixed false -x 442 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2_4 -fixed false -x 400 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[1\] -fixed false -x 58 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m45 -fixed false -x 33 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[31\] -fixed false -x 617 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loI11_Z -fixed false -x 307 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[0\] -fixed false -x 251 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[5\] -fixed false -x 758 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_26\[4\] -fixed false -x 286 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1_0_1 -fixed false -x 166 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[12\] -fixed false -x 462 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/IilI1 -fixed false -x 322 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[5\] -fixed false -x 261 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[28\] -fixed false -x 13 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_RNO_0 -fixed false -x 799 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_x2 -fixed false -x 70 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0 -fixed false -x 477 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[1\] -fixed false -x 306 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[5\] -fixed false -x 192 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[14\] -fixed false -x 958 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[17\] -fixed false -x 515 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un368_lIlo1 -fixed false -x 170 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[7\] -fixed false -x 838 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[14\] -fixed false -x 858 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un117_I1Oi1 -fixed false -x 58 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/un1_iOI01_1_i_0 -fixed false -x 345 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[28\] -fixed false -x 495 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2119_1_RNO -fixed false -x 662 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[3\] -fixed false -x 64 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[14\] -fixed false -x 423 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1232 -fixed false -x 730 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0_1\[31\] -fixed false -x 851 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[30\] -fixed false -x 725 -y 118
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[9\] -fixed false -x 42 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_4 -fixed false -x 695 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[18\] -fixed false -x 693 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[18\] -fixed false -x 809 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[11\] -fixed false -x 45 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1220 -fixed false -x 610 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[2\] -fixed false -x 426 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOI11_0_a3_RNIFORSC -fixed false -x 143 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2\[10\] -fixed false -x 144 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[5\] -fixed false -x 575 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2 -fixed false -x 695 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[33\] -fixed false -x 500 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_335 -fixed false -x 619 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op\[2\] -fixed false -x 743 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[8\] -fixed false -x 354 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[7\] -fixed false -x 418 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[6\] -fixed false -x 71 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[10\] -fixed false -x 958 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[31\] -fixed false -x 758 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_datas2 -fixed false -x 722 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[7\] -fixed false -x 238 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[10\] -fixed false -x 383 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1 -fixed false -x 70 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[8\] -fixed false -x 799 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[7\] -fixed false -x 155 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0oo1 -fixed false -x 79 -y 202
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag -fixed false -x 28 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[15\] -fixed false -x 347 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_valid_u -fixed false -x 805 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oill1 -fixed false -x 451 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[21\] -fixed false -x 444 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2\[1\] -fixed false -x 646 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_765 -fixed false -x 646 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[22\] -fixed false -x 119 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[2\] -fixed false -x 762 -y 142
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2_2 -fixed false -x 489 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1 -fixed false -x 229 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[18\] -fixed false -x 248 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[12\] -fixed false -x 462 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0Ol1 -fixed false -x 430 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/oo1Io_0 -fixed false -x 418 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[0\] -fixed false -x 383 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO\[3\] -fixed false -x 273 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNILBHM8\[1\] -fixed false -x 791 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[14\] -fixed false -x 311 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_csr_complete_retr -fixed false -x 793 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[8\] -fixed false -x 718 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[11\] -fixed false -x 658 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[7\] -fixed false -x 507 -y 160
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_s1_0_a2 -fixed false -x 71 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold_RNO -fixed false -x 782 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_32\[31\] -fixed false -x 935 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[7\] -fixed false -x 212 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[14\] -fixed false -x 807 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[0\] -fixed false -x 617 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[31\] -fixed false -x 472 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[6\] -fixed false -x 249 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_str_amo_addr_misalign -fixed false -x 800 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[14\] -fixed false -x 324 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[1\] -fixed false -x 768 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[0\] -fixed false -x 710 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[0\] -fixed false -x 280 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un9_OOoo1_3_i_o2 -fixed false -x 107 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[8\] -fixed false -x 643 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[24\] -fixed false -x 424 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[29\] -fixed false -x 628 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_ifu_expipe_resp_next_vaddr -fixed false -x 749 -y 147
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/un1_D -fixed false -x 750 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_halted -fixed false -x 711 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[17\] -fixed false -x 141 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[16\] -fixed false -x 342 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[1\] -fixed false -x 514 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid_10_1 -fixed false -x 743 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24\[5\] -fixed false -x 295 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m53_1_0 -fixed false -x 34 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[30\] -fixed false -x 955 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[16\] -fixed false -x 95 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[8\] -fixed false -x 187 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_56\[11\] -fixed false -x 272 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0 -fixed false -x 272 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[5\] -fixed false -x 90 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[0\] -fixed false -x 893 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[1\] -fixed false -x 907 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[12\] -fixed false -x 427 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[32\] -fixed false -x 624 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1_RNI19HSQO -fixed false -x 826 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[6\] -fixed false -x 122 -y 184
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[4\] -fixed false -x 21 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[0\] -fixed false -x 196 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2\[9\] -fixed false -x 129 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m9x -fixed false -x 698 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u\[2\] -fixed false -x 957 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i_a2 -fixed false -x 752 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4\[1\] -fixed false -x 44 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel -fixed false -x 716 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01\[1\] -fixed false -x 52 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc5 -fixed false -x 66 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI117O2\[2\] -fixed false -x 220 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[5\] -fixed false -x 505 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[8\] -fixed false -x 782 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0_1_0\[0\] -fixed false -x 315 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/ssel_rx_q2 -fixed false -x 525 -y 145
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[26\].BUFD_BLK -fixed false -x 512 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_668 -fixed false -x 668 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[8\] -fixed false -x 370 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[19\] -fixed false -x 930 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_exception_os\[1\] -fixed false -x 799 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[7\] -fixed false -x 518 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oo0l1\[0\] -fixed false -x 462 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4\[3\] -fixed false -x 152 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_7 -fixed false -x 837 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_579 -fixed false -x 677 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[6\] -fixed false -x 430 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[52\] -fixed false -x 895 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_0 -fixed false -x 25 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_1 -fixed false -x 688 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[55\] -fixed false -x 954 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_0\[15\] -fixed false -x 715 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41_cZ\[5\] -fixed false -x 252 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[6\] -fixed false -x 721 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_0_tz\[0\] -fixed false -x 753 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1108 -fixed false -x 694 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[20\] -fixed false -x 714 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[12\] -fixed false -x 230 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[25\] -fixed false -x 934 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_621 -fixed false -x 706 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[16\] -fixed false -x 393 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[9\] -fixed false -x 283 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un23_ool01_1 -fixed false -x 46 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[47\] -fixed false -x 231 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[21\] -fixed false -x 846 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1123 -fixed false -x 633 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UTDI -fixed false -x 488 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[4\] -fixed false -x 802 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[10\] -fixed false -x 761 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[5\] -fixed false -x 366 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a3_1_2 -fixed false -x 181 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_24_RNIFK3D8 -fixed false -x 834 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[21\] -fixed false -x 771 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1052 -fixed false -x 755 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2\[4\] -fixed false -x 481 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[8\] -fixed false -x 213 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[7\] -fixed false -x 232 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0\[1\] -fixed false -x 565 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[6\] -fixed false -x 918 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/N_545_i -fixed false -x 123 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo56_RNILQ5CK -fixed false -x 63 -y 204
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_2 -fixed false -x 439 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[25\] -fixed false -x 682 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[13\] -fixed false -x 30 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[19\] -fixed false -x 653 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[19\] -fixed false -x 848 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[28\] -fixed false -x 756 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[4\] -fixed false -x 239 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m8 -fixed false -x 81 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[7\] -fixed false -x 872 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m3 -fixed false -x 792 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[28\] -fixed false -x 872 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo -fixed false -x 176 -y 160
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/UTDODriven\[0\] -fixed false -x 503 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[1\] -fixed false -x 73 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO_1 -fixed false -x 807 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[4\] -fixed false -x 174 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[9\] -fixed false -x 892 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1IIo -fixed false -x 266 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un9_o1oOo -fixed false -x 98 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[10\] -fixed false -x 351 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[5\] -fixed false -x 336 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush\[1\] -fixed false -x 782 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[10\] -fixed false -x 700 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[7\] -fixed false -x 78 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[8\] -fixed false -x 611 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[19\] -fixed false -x 772 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[10\] -fixed false -x 536 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1079 -fixed false -x 705 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[16\] -fixed false -x 334 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m6_2_1 -fixed false -x 611 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[13\] -fixed false -x 746 -y 175
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0_o3 -fixed false -x 70 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[31\] -fixed false -x 771 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1_RNO_0 -fixed false -x 795 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_227 -fixed false -x 812 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[19\] -fixed false -x 631 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[24\] -fixed false -x 410 -y 160
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns\[2\] -fixed false -x 426 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[11\] -fixed false -x 126 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ilo01 -fixed false -x 103 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/wr_en_data_or -fixed false -x 695 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[3\] -fixed false -x 376 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001\[0\] -fixed false -x 92 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.illi0 -fixed false -x 371 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[4\] -fixed false -x 434 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[30\] -fixed false -x 665 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[31\] -fixed false -x 835 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un203_I1Oi1_2 -fixed false -x 42 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_misalign_error_retr -fixed false -x 824 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO\[0\] -fixed false -x 275 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_63 -fixed false -x 668 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter\[0\] -fixed false -x 782 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[10\] -fixed false -x 765 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_33\[10\] -fixed false -x 287 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[16\] -fixed false -x 89 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[41\] -fixed false -x 144 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_O01l112 -fixed false -x 405 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001\[0\] -fixed false -x 81 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[12\] -fixed false -x 132 -y 199
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[6\].BUFD_BLK -fixed false -x 539 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[6\] -fixed false -x 815 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[20\] -fixed false -x 477 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_0_i_o3\[8\] -fixed false -x 129 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[5\] -fixed false -x 767 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[11\] -fixed false -x 220 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[8\] -fixed false -x 334 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_197 -fixed false -x 778 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[18\] -fixed false -x 436 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[3\] -fixed false -x 172 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[2\] -fixed false -x 398 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[5\] -fixed false -x 434 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[0\] -fixed false -x 863 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[25\] -fixed false -x 805 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto3 -fixed false -x 155 -y 177
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[4\] -fixed false -x 49 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[10\] -fixed false -x 918 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[14\] -fixed false -x 872 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/un1_iOI01_1_i_0 -fixed false -x 221 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[29\] -fixed false -x 20 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1\[1\] -fixed false -x 282 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[28\] -fixed false -x 349 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[9\] -fixed false -x 202 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[3\] -fixed false -x 250 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[10\] -fixed false -x 191 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/genblk1.rst_synch_reg\[1\] -fixed false -x 613 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[17\] -fixed false -x 691 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex -fixed false -x 767 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_318 -fixed false -x 706 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[12\] -fixed false -x 563 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_775 -fixed false -x 663 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[15\] -fixed false -x 76 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1061 -fixed false -x 658 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[52\] -fixed false -x 561 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[19\] -fixed false -x 750 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[27\] -fixed false -x 763 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4950_3 -fixed false -x 670 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[5\] -fixed false -x 97 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[2\] -fixed false -x 237 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[6\] -fixed false -x 374 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[22\] -fixed false -x 806 -y 184
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[6\] -fixed false -x 475 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io_RNO -fixed false -x 78 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[18\] -fixed false -x 851 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[4\] -fixed false -x 403 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_1 -fixed false -x 669 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_43\[9\] -fixed false -x 226 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[4\] -fixed false -x 45 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrx_async_reset_ok -fixed false -x 517 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_2 -fixed false -x 104 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_822 -fixed false -x 799 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[24\] -fixed false -x 451 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/mdc_Z -fixed false -x 296 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_20_RNI7CVC8 -fixed false -x 846 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_0 -fixed false -x 203 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_811 -fixed false -x 591 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_131 -fixed false -x 706 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[23\] -fixed false -x 268 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[19\] -fixed false -x 861 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_iOOl1_1_0 -fixed false -x 443 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_305 -fixed false -x 717 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI8LK9D_0 -fixed false -x 825 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[8\] -fixed false -x 713 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I11i1_0_a3 -fixed false -x 214 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[2\] -fixed false -x 802 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[31\] -fixed false -x 592 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[12\] -fixed false -x 703 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_794 -fixed false -x 646 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_3_1 -fixed false -x 639 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3_RNO\[0\] -fixed false -x 647 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1261 -fixed false -x 814 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[38\] -fixed false -x 155 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNIBN5VF\[14\] -fixed false -x 670 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[11\] -fixed false -x 103 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[7\] -fixed false -x 398 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo_6 -fixed false -x 343 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[5\] -fixed false -x 181 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2\[0\] -fixed false -x 770 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_678 -fixed false -x 609 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_332 -fixed false -x 777 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[4\] -fixed false -x 798 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[4\] -fixed false -x 105 -y 214
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m6 -fixed false -x 491 -y 96
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cdr_ready_reg_2\[0\] -fixed false -x 37 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1305 -fixed false -x 680 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO\[1\] -fixed false -x 593 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[5\] -fixed false -x 213 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m4_2 -fixed false -x 633 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_o2 -fixed false -x 681 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_o3_0 -fixed false -x 141 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[45\] -fixed false -x 122 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_a2_4 -fixed false -x 118 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_6 -fixed false -x 803 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[12\] -fixed false -x 288 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO -fixed false -x 899 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[17\].BUFD_BLK -fixed false -x 514 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[12\] -fixed false -x 947 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[29\] -fixed false -x 599 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[3\] -fixed false -x 371 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[2\] -fixed false -x 744 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[14\] -fixed false -x 803 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_1_0_2 -fixed false -x 685 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[1\] -fixed false -x 173 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[8\] -fixed false -x 428 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[1\] -fixed false -x 758 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[30\] -fixed false -x 789 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2\[11\] -fixed false -x 299 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO -fixed false -x 227 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNI99EPJ1 -fixed false -x 262 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iIio1_1 -fixed false -x 58 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[10\] -fixed false -x 445 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0 -fixed false -x 101 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1 -fixed false -x 775 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[5\] -fixed false -x 357 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_strobe -fixed false -x 524 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_5\[1\] -fixed false -x 142 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[4\] -fixed false -x 719 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[0\] -fixed false -x 255 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[2\] -fixed false -x 509 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_934 -fixed false -x 610 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3\[5\] -fixed false -x 130 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[5\] -fixed false -x 427 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[20\] -fixed false -x 835 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[38\] -fixed false -x 354 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto8 -fixed false -x 147 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1\[2\] -fixed false -x 127 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_760 -fixed false -x 657 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_343 -fixed false -x 679 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[9\] -fixed false -x 599 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2\[2\] -fixed false -x 126 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_1 -fixed false -x 721 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[9\] -fixed false -x 250 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[31\] -fixed false -x 406 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[2\] -fixed false -x 26 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0li1_0 -fixed false -x 190 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[17\] -fixed false -x 760 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[53\] -fixed false -x 968 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[7\] -fixed false -x 487 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[15\] -fixed false -x 226 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_5 -fixed false -x 105 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[0\] -fixed false -x 255 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1_RNO -fixed false -x 107 -y 201
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa_1 -fixed false -x 462 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[17\] -fixed false -x 911 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[7\] -fixed false -x 750 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4951 -fixed false -x 659 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo\[1\] -fixed false -x 272 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[29\] -fixed false -x 873 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_0_sqmuxa_1_i_0_o3_0_o3 -fixed false -x 778 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[2\] -fixed false -x 415 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1_cZ\[17\] -fixed false -x 254 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_44\[8\] -fixed false -x 923 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGTK9D_0 -fixed false -x 728 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[26\] -fixed false -x 359 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_2\[0\] -fixed false -x 780 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z\[1\] -fixed false -x 355 -y 154
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[31\] -fixed false -x 412 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[31\] -fixed false -x 880 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[3\] -fixed false -x 59 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[11\] -fixed false -x 771 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO -fixed false -x 816 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.llol1 -fixed false -x 351 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_c2_RNI72A3C -fixed false -x 311 -y 201
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0_o3_0 -fixed false -x 69 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0\[19\] -fixed false -x 161 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[3\] -fixed false -x 118 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[0\] -fixed false -x 16 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_952 -fixed false -x 776 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[46\] -fixed false -x 504 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_11_0 -fixed false -x 816 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[2\] -fixed false -x 58 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[9\] -fixed false -x 883 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1020 -fixed false -x 598 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[10\] -fixed false -x 375 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[25\] -fixed false -x 609 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[40\] -fixed false -x 523 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[12\] -fixed false -x 496 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[15\] -fixed false -x 81 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[2\] -fixed false -x 177 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[3\] -fixed false -x 88 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[10\] -fixed false -x 76 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[21\] -fixed false -x 814 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o0ii1 -fixed false -x 134 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/un1_iOI01_1_i -fixed false -x 410 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[9\] -fixed false -x 223 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[1\] -fixed false -x 321 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[2\] -fixed false -x 411 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/exu_csr_op_wr_data14 -fixed false -x 757 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[2\] -fixed false -x 213 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2_1 -fixed false -x 684 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_0_sqmuxa_0_a3 -fixed false -x 226 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_instr_decoded_3 -fixed false -x 681 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_0_0 -fixed false -x 82 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_2 -fixed false -x 707 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[13\] -fixed false -x 593 -y 142
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt\[2\] -fixed false -x 464 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[4\] -fixed false -x 310 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en\[2\] -fixed false -x 801 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5s2_0 -fixed false -x 823 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_2_0 -fixed false -x 646 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de -fixed false -x 786 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_clock -fixed false -x 447 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/un1_Ioli0_1_0 -fixed false -x 290 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_693 -fixed false -x 645 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[32\] -fixed false -x 343 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_91_u\[2\] -fixed false -x 956 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[24\] -fixed false -x 745 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[2\] -fixed false -x 528 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[2\] -fixed false -x 204 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_522 -fixed false -x 647 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO_1 -fixed false -x 661 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_4 -fixed false -x 634 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un18_i0Oo1 -fixed false -x 281 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[16\] -fixed false -x 39 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[14\] -fixed false -x 890 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO001_3 -fixed false -x 228 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0_1\[2\] -fixed false -x 622 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA\[0\] -fixed false -x 549 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone_2_sqmuxa -fixed false -x 533 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[30\] -fixed false -x 872 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[33\] -fixed false -x 552 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_oIIi1_5 -fixed false -x 165 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[4\] -fixed false -x 358 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[34\] -fixed false -x 639 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[11\] -fixed false -x 160 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[39\] -fixed false -x 314 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/looo1 -fixed false -x 57 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[8\] -fixed false -x 740 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[20\] -fixed false -x 465 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[25\] -fixed false -x 861 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[1\] -fixed false -x 884 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPHTQ8\[24\] -fixed false -x 661 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[15\] -fixed false -x 140 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_1\[2\] -fixed false -x 772 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[0\] -fixed false -x 499 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[24\] -fixed false -x 867 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1226 -fixed false -x 682 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[3\] -fixed false -x 854 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5\[0\] -fixed false -x 624 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1008 -fixed false -x 776 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[0\] -fixed false -x 138 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[12\] -fixed false -x 392 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0\[27\] -fixed false -x 141 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[4\] -fixed false -x 372 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[1\] -fixed false -x 181 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[0\] -fixed false -x 399 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[11\] -fixed false -x 667 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[37\] -fixed false -x 923 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[2\] -fixed false -x 185 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter -fixed false -x 783 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[1\] -fixed false -x 343 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0_1_0\[0\] -fixed false -x 201 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_OioOo_1 -fixed false -x 105 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[51\] -fixed false -x 971 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1269 -fixed false -x 693 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_RNO\[1\] -fixed false -x 504 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[9\] -fixed false -x 383 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[6\] -fixed false -x 575 -y 147
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_0_sqmuxa -fixed false -x 527 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1264 -fixed false -x 609 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI1B0P9\[1\] -fixed false -x 93 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[0\] -fixed false -x 408 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oI0i1_i_0_a2 -fixed false -x 178 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[16\] -fixed false -x 753 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_13 -fixed false -x 743 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[13\] -fixed false -x 556 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[17\] -fixed false -x 341 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[6\] -fixed false -x 305 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[10\] -fixed false -x 248 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[17\] -fixed false -x 443 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol1Oo\[0\] -fixed false -x 151 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01 -fixed false -x 45 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[16\] -fixed false -x 474 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[24\] -fixed false -x 731 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m3 -fixed false -x 129 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1o01_RNII47I8 -fixed false -x 95 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.awe0 -fixed false -x 624 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[4\] -fixed false -x 414 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl0112 -fixed false -x 202 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01\[0\] -fixed false -x 164 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR20_1 -fixed false -x 575 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[5\] -fixed false -x 400 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_34\[3\] -fixed false -x 275 -y 171
|
|
set_location -inst_name SSDetect_0/rx_start_2\[0\] -fixed false -x 13 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[6\] -fixed false -x 422 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[0\] -fixed false -x 262 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[17\] -fixed false -x 253 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1175 -fixed false -x 622 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 258 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[17\] -fixed false -x 465 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[13\] -fixed false -x 561 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[6\] -fixed false -x 634 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_6 -fixed false -x 670 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[18\] -fixed false -x 826 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0_tz_0 -fixed false -x 99 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_5 -fixed false -x 239 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_o2\[7\] -fixed false -x 244 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[2\] -fixed false -x 128 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q\[1\] -fixed false -x 492 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_14_122_a2 -fixed false -x 458 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[7\] -fixed false -x 818 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter_1 -fixed false -x 774 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_4_194_a2 -fixed false -x 439 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_126 -fixed false -x 646 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[11\] -fixed false -x 567 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[0\] -fixed false -x 119 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[2\] -fixed false -x 307 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_rd_op -fixed false -x 707 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[28\] -fixed false -x 947 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[27\] -fixed false -x 564 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[21\] -fixed false -x 640 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[7\] -fixed false -x 188 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[12\] -fixed false -x 946 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_2 -fixed false -x 229 -y 195
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m18 -fixed false -x 473 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[29\] -fixed false -x 175 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[20\] -fixed false -x 83 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[10\] -fixed false -x 646 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_a3_0_1 -fixed false -x 166 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_101 -fixed false -x 766 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[5\] -fixed false -x 848 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_770 -fixed false -x 634 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[9\] -fixed false -x 911 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[3\] -fixed false -x 573 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[1\] -fixed false -x 839 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[9\] -fixed false -x 820 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_445 -fixed false -x 716 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[6\] -fixed false -x 290 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[18\] -fixed false -x 113 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[5\] -fixed false -x 272 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_7 -fixed false -x 99 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[5\] -fixed false -x 385 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIiO1 -fixed false -x 140 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u\[2\] -fixed false -x 959 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_0_sqmuxa_2 -fixed false -x 771 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_O1iIo -fixed false -x 442 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[3\] -fixed false -x 441 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[4\] -fixed false -x 156 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[21\] -fixed false -x 921 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[1\] -fixed false -x 719 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[2\] -fixed false -x 538 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[8\] -fixed false -x 225 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3\[1\] -fixed false -x 69 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_534 -fixed false -x 633 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_302 -fixed false -x 633 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[20\] -fixed false -x 85 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1272 -fixed false -x 698 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNINIRFO3 -fixed false -x 795 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[16\] -fixed false -x 51 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[12\] -fixed false -x 140 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_1\[6\] -fixed false -x 635 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.awe0 -fixed false -x 639 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s2_0_a2 -fixed false -x 471 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[1\] -fixed false -x 415 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[30\] -fixed false -x 683 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[23\] -fixed false -x 429 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[25\] -fixed false -x 402 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_10 -fixed false -x 608 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[7\] -fixed false -x 344 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[4\] -fixed false -x 113 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[9\] -fixed false -x 97 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oIol1 -fixed false -x 376 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13\[3\] -fixed false -x 775 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[2\] -fixed false -x 275 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[2\] -fixed false -x 717 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[1\] -fixed false -x 420 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[21\] -fixed false -x 473 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0\[2\] -fixed false -x 96 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[4\] -fixed false -x 948 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[29\] -fixed false -x 842 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[0\] -fixed false -x 492 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_o3\[3\] -fixed false -x 717 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns\[0\] -fixed false -x 430 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_103_i -fixed false -x 169 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1\[38\] -fixed false -x 388 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[1\] -fixed false -x 131 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[17\] -fixed false -x 843 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1186 -fixed false -x 705 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_strobe -fixed false -x 521 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[8\] -fixed false -x 454 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNI6098E\[21\] -fixed false -x 659 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iOil1 -fixed false -x 418 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_904 -fixed false -x 753 -y 189
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_15\[0\] -fixed false -x 755 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[2\] -fixed false -x 57 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_1 -fixed false -x 88 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa_0 -fixed false -x 526 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_0 -fixed false -x 815 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[3\] -fixed false -x 354 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0\[0\] -fixed false -x 325 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[1\] -fixed false -x 381 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[4\] -fixed false -x 221 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIP7EQI\[5\] -fixed false -x 862 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[18\] -fixed false -x 867 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[23\] -fixed false -x 683 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_70 -fixed false -x 615 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Ilii1 -fixed false -x 154 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oIIOo -fixed false -x 41 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[20\] -fixed false -x 887 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[18\] -fixed false -x 92 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[2\] -fixed false -x 859 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[31\] -fixed false -x 739 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo -fixed false -x 118 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[7\] -fixed false -x 341 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m67_1_0 -fixed false -x 30 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[28\] -fixed false -x 688 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig -fixed false -x 780 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[14\] -fixed false -x 400 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[4\] -fixed false -x 287 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3_0_RNIGNE502 -fixed false -x 763 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[6\] -fixed false -x 368 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_3 -fixed false -x 81 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[10\] -fixed false -x 325 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_0\[1\] -fixed false -x 623 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/gen_bit_reset.state_val\[0\] -fixed false -x 722 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_481 -fixed false -x 763 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[4\] -fixed false -x 318 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[1\] -fixed false -x 729 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_782 -fixed false -x 693 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OiIO1_Z -fixed false -x 290 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[21\] -fixed false -x 475 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo263_0_0 -fixed false -x 58 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[2\] -fixed false -x 382 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[5\] -fixed false -x 654 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4\[3\] -fixed false -x 787 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_192 -fixed false -x 678 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[2\] -fixed false -x 51 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI1K99I -fixed false -x 745 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[41\] -fixed false -x 533 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/stop_strobe -fixed false -x 479 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[3\] -fixed false -x 914 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[10\] -fixed false -x 249 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[6\] -fixed false -x 238 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[4\] -fixed false -x 285 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[1\] -fixed false -x 527 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_3\[2\] -fixed false -x 254 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[12\] -fixed false -x 478 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0\[11\] -fixed false -x 842 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[17\] -fixed false -x 758 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[0\] -fixed false -x 317 -y 196
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m4_1_0 -fixed false -x 489 -y 96
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[7\] -fixed false -x 55 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0o11 -fixed false -x 354 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4927 -fixed false -x 617 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_9 -fixed false -x 691 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/un1_Ioli0_1_0 -fixed false -x 219 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[17\] -fixed false -x 910 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[4\] -fixed false -x 184 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1 -fixed false -x 57 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[3\] -fixed false -x 513 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[5\] -fixed false -x 64 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[0\] -fixed false -x 859 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1 -fixed false -x 133 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_1 -fixed false -x 676 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_844 -fixed false -x 693 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_591 -fixed false -x 574 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_8\[9\] -fixed false -x 316 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0_sx -fixed false -x 808 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_3 -fixed false -x 720 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[11\] -fixed false -x 431 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[14\] -fixed false -x 757 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un13_trap_val -fixed false -x 724 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[6\] -fixed false -x 209 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[16\] -fixed false -x 626 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un16_OOOI1\[3\] -fixed false -x 356 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[13\] -fixed false -x 357 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011_RNO_0 -fixed false -x 252 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[12\] -fixed false -x 418 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[11\] -fixed false -x 856 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[22\] -fixed false -x 858 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[11\] -fixed false -x 354 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[1\] -fixed false -x 506 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[9\] -fixed false -x 175 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata\[6\] -fixed false -x 493 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv\[4\] -fixed false -x 685 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0_1_0\[0\] -fixed false -x 216 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[31\] -fixed false -x 871 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[11\] -fixed false -x 875 -y 195
|
|
set_location -inst_name pf_init_monitor_0_0/pf_init_monitor_0_0/I_INIT -fixed false -x 508 -y 2
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[10\] -fixed false -x 693 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[8\] -fixed false -x 661 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[5\] -fixed false -x 453 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[13\] -fixed false -x 922 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_694 -fixed false -x 622 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_i1oOo -fixed false -x 128 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state\[1\]\[0\] -fixed false -x 782 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo\[0\] -fixed false -x 205 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[2\] -fixed false -x 208 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_0 -fixed false -x 71 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[8\] -fixed false -x 709 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_533 -fixed false -x 705 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO\[3\] -fixed false -x 567 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[4\] -fixed false -x 260 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[15\] -fixed false -x 289 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/cause_excpt_code_excpt_m6\[3\] -fixed false -x 736 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1\[4\] -fixed false -x 292 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[11\] -fixed false -x 110 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_fast\[0\] -fixed false -x 710 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[14\] -fixed false -x 313 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_0\[6\] -fixed false -x 112 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[14\] -fixed false -x 311 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_wr_rd_state_Z\[0\] -fixed false -x 800 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[7\] -fixed false -x 227 -y 190
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/un1_tx_parity_1_sqmuxa_0_a2 -fixed false -x 453 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[12\] -fixed false -x 563 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_15 -fixed false -x 832 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[37\] -fixed false -x 518 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOo11 -fixed false -x 154 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[11\] -fixed false -x 273 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mscratch_sw_wr_sel -fixed false -x 718 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1\[42\] -fixed false -x 134 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[29\] -fixed false -x 886 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0_a3_4\[3\] -fixed false -x 155 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[28\] -fixed false -x 871 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg\[3\] -fixed false -x 806 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmstatus_allany_havereset10_0_a3 -fixed false -x 801 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[16\] -fixed false -x 625 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_997 -fixed false -x 616 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex_RNIADL341\[1\] -fixed false -x 828 -y 138
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc3 -fixed false -x 483 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op\[0\] -fixed false -x 684 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1237 -fixed false -x 669 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[7\] -fixed false -x 431 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_359 -fixed false -x 628 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[58\] -fixed false -x 540 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7\[6\] -fixed false -x 206 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[20\] -fixed false -x 85 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb -fixed false -x 801 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO_0 -fixed false -x 827 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[14\] -fixed false -x 559 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[19\] -fixed false -x 602 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv -fixed false -x 826 -y 141
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[4\] -fixed false -x 505 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_948 -fixed false -x 644 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[11\] -fixed false -x 400 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Oooo1 -fixed false -x 64 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[3\] -fixed false -x 452 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[10\] -fixed false -x 201 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ooo11 -fixed false -x 394 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_shift_op_completing_ex_1_0 -fixed false -x 770 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2\[8\] -fixed false -x 154 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOOl1 -fixed false -x 435 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[41\] -fixed false -x 914 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[2\] -fixed false -x 914 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[4\] -fixed false -x 250 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01\[1\] -fixed false -x 174 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[11\] -fixed false -x 399 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[2\] -fixed false -x 309 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/io0l1\[0\] -fixed false -x 457 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[9\] -fixed false -x 406 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_2_1\[0\] -fixed false -x 43 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIo01_0 -fixed false -x 103 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[1\] -fixed false -x 167 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[4\] -fixed false -x 163 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[13\] -fixed false -x 379 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[22\] -fixed false -x 909 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[2\] -fixed false -x 746 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23\[5\] -fixed false -x 252 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_1\[13\] -fixed false -x 327 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[1\] -fixed false -x 296 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[26\] -fixed false -x 399 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[14\] -fixed false -x 554 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[21\] -fixed false -x 444 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[23\] -fixed false -x 704 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01\[2\] -fixed false -x 200 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/liOo1 -fixed false -x 280 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0\[3\] -fixed false -x 253 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[2\] -fixed false -x 388 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_addr_align\[0\]\[0\] -fixed false -x 820 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[26\] -fixed false -x 687 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m8_1_0 -fixed false -x 78 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[21\] -fixed false -x 734 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[33\] -fixed false -x 226 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_2 -fixed false -x 92 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[3\] -fixed false -x 846 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1_1 -fixed false -x 32 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[6\] -fixed false -x 87 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[25\] -fixed false -x 404 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[18\] -fixed false -x 72 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[5\] -fixed false -x 190 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_6\[15\] -fixed false -x 654 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol0l1\[0\] -fixed false -x 466 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i -fixed false -x 94 -y 222
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_RNO_0\[1\] -fixed false -x 33 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7CB84\[30\] -fixed false -x 950 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[3\] -fixed false -x 775 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un1_irq_stall_lsu_req -fixed false -x 759 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo52 -fixed false -x 44 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un23_trap_val -fixed false -x 728 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[5\] -fixed false -x 180 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_s -fixed false -x 786 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[9\] -fixed false -x 785 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[1\] -fixed false -x 687 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_741 -fixed false -x 813 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[31\] -fixed false -x 612 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3\[3\] -fixed false -x 139 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[0\] -fixed false -x 287 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[22\] -fixed false -x 750 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[3\] -fixed false -x 690 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_504 -fixed false -x 621 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[0\] -fixed false -x 120 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_8_x -fixed false -x 835 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[21\] -fixed false -x 792 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO1Oo -fixed false -x 104 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_5 -fixed false -x 670 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[0\] -fixed false -x 127 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[24\] -fixed false -x 696 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OI0Oo -fixed false -x 158 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_2 -fixed false -x 232 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_o2 -fixed false -x 201 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_758 -fixed false -x 667 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2\[15\] -fixed false -x 304 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[5\] -fixed false -x 946 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[7\] -fixed false -x 843 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un95_lliOo_1.CO2 -fixed false -x 355 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_536 -fixed false -x 656 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_647 -fixed false -x 704 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I0o01 -fixed false -x 65 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_746 -fixed false -x 681 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_2 -fixed false -x 266 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_920 -fixed false -x 729 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[30\] -fixed false -x 717 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_i_iv -fixed false -x 706 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO_0 -fixed false -x 898 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un46_mtvec_warl_wr_enlto3 -fixed false -x 838 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[5\] -fixed false -x 303 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[8\] -fixed false -x 505 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[12\] -fixed false -x 945 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[3\] -fixed false -x 294 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[8\] -fixed false -x 428 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_492 -fixed false -x 646 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[17\] -fixed false -x 95 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[2\] -fixed false -x 863 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[10\] -fixed false -x 553 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[25\] -fixed false -x 592 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_413 -fixed false -x 670 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1oOo_1 -fixed false -x 90 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2_3 -fixed false -x 164 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[15\] -fixed false -x 695 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IiIo1 -fixed false -x 256 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[15\] -fixed false -x 840 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m46_2_0 -fixed false -x 274 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[9\] -fixed false -x 527 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ollOo -fixed false -x 30 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_i_a2\[3\] -fixed false -x 421 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[4\] -fixed false -x 523 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[14\] -fixed false -x 433 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[17\] -fixed false -x 922 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[17\] -fixed false -x 141 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[7\] -fixed false -x 46 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3\[2\] -fixed false -x 108 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_7 -fixed false -x 683 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0\[3\] -fixed false -x 777 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[7\] -fixed false -x 204 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[0\] -fixed false -x 342 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_7 -fixed false -x 450 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[14\] -fixed false -x 105 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO_1 -fixed false -x 777 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[7\] -fixed false -x 525 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[3\] -fixed false -x 773 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIRDDPQ3\[0\] -fixed false -x 32 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_ptr\[0\] -fixed false -x 744 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[8\] -fixed false -x 200 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[13\] -fixed false -x 142 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[15\] -fixed false -x 534 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_3_RNIVSQ5B -fixed false -x 189 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_a2 -fixed false -x 101 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[9\] -fixed false -x 820 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_1\[6\] -fixed false -x 127 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[7\] -fixed false -x 422 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[5\] -fixed false -x 862 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[13\] -fixed false -x 716 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[2\] -fixed false -x 357 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc2 -fixed false -x 118 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un9_l1Oo1_4 -fixed false -x 292 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int21 -fixed false -x 765 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_424 -fixed false -x 658 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[3\] -fixed false -x 326 -y 166
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[0\] -fixed false -x 37 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1\[2\] -fixed false -x 808 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[26\] -fixed false -x 886 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[3\] -fixed false -x 647 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNI8HDTF -fixed false -x 730 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[8\] -fixed false -x 770 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_264 -fixed false -x 704 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc2 -fixed false -x 71 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[19\] -fixed false -x 435 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sellto7 -fixed false -x 81 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m6 -fixed false -x 60 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_1 -fixed false -x 610 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[19\] -fixed false -x 441 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[29\] -fixed false -x 791 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[25\] -fixed false -x 899 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[8\] -fixed false -x 248 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_9 -fixed false -x 99 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_OOii1_0 -fixed false -x 152 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4950_1 -fixed false -x 701 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_18 -fixed false -x 721 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo -fixed false -x 21 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un65_ool01 -fixed false -x 186 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o2_0 -fixed false -x 634 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[1\] -fixed false -x 502 -y 154
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt\[1\] -fixed false -x 15 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[5\] -fixed false -x 711 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[0\] -fixed false -x 190 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2119_2 -fixed false -x 642 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[24\] -fixed false -x 897 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_15\[22\] -fixed false -x 272 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m8 -fixed false -x 71 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[15\] -fixed false -x 602 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[6\] -fixed false -x 512 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_1_1 -fixed false -x 107 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_857 -fixed false -x 692 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioIi1 -fixed false -x 109 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_RNIBFQ4F\[0\] -fixed false -x 95 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[33\] -fixed false -x 501 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[7\] -fixed false -x 458 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1_sqmuxa_1\[0\] -fixed false -x 43 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[2\] -fixed false -x 660 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[14\] -fixed false -x 770 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[9\] -fixed false -x 358 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[19\] -fixed false -x 822 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[2\] -fixed false -x 362 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[1\] -fixed false -x 156 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[2\] -fixed false -x 227 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[4\] -fixed false -x 804 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pslverr_reg -fixed false -x 712 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z\[0\] -fixed false -x 318 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[1\] -fixed false -x 774 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_4 -fixed false -x 723 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[7\] -fixed false -x 400 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[2\] -fixed false -x 161 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/I0Il1 -fixed false -x 466 -y 199
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[5\] -fixed false -x 485 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_1_0 -fixed false -x 609 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_1 -fixed false -x 230 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_i_0\[2\] -fixed false -x 480 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m3 -fixed false -x 705 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oioi1 -fixed false -x 116 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[2\] -fixed false -x 432 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1_1 -fixed false -x 73 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_1_0 -fixed false -x 706 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[8\] -fixed false -x 696 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[3\] -fixed false -x 121 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_503 -fixed false -x 718 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[0\] -fixed false -x 819 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[17\] -fixed false -x 289 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un21_loOo1_i_o2 -fixed false -x 319 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[7\] -fixed false -x 502 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[14\] -fixed false -x 589 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l10Oo_0_a3_0 -fixed false -x 130 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_17\[22\] -fixed false -x 247 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[15\] -fixed false -x 363 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[15\] -fixed false -x 841 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m278 -fixed false -x 260 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0_2\[2\] -fixed false -x 722 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en_RNI05K6M8 -fixed false -x 779 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[19\] -fixed false -x 822 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[1\] -fixed false -x 131 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1 -fixed false -x 690 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[3\] -fixed false -x 876 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[8\] -fixed false -x 248 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[8\] -fixed false -x 381 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_reg_ex -fixed false -x 804 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[5\] -fixed false -x 173 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[0\] -fixed false -x 243 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[27\] -fixed false -x 923 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[1\] -fixed false -x 827 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[29\] -fixed false -x 956 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_0\[7\] -fixed false -x 262 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_2 -fixed false -x 794 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IlOo1 -fixed false -x 148 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1091 -fixed false -x 622 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[10\] -fixed false -x 182 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lOll1 -fixed false -x 449 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[7\] -fixed false -x 647 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[11\] -fixed false -x 421 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[16\] -fixed false -x 469 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[17\] -fixed false -x 54 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1011 -fixed false -x 802 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[9\] -fixed false -x 169 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[5\] -fixed false -x 545 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[4\] -fixed false -x 174 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[7\] -fixed false -x 136 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_o6_1\[1\] -fixed false -x 657 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[25\] -fixed false -x 881 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[25\] -fixed false -x 274 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo -fixed false -x 26 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO_0\[6\] -fixed false -x 111 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_391 -fixed false -x 718 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[26\] -fixed false -x 780 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_719 -fixed false -x 667 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_396 -fixed false -x 658 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[17\] -fixed false -x 528 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[8\] -fixed false -x 200 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m11 -fixed false -x 71 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5\[4\] -fixed false -x 144 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z\[1\] -fixed false -x 786 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I018 -fixed false -x 192 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mvendorid_sw_rd_sel_0 -fixed false -x 704 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[6\] -fixed false -x 827 -y 130
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5\[5\] -fixed false -x 482 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[7\] -fixed false -x 139 -y 169
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[12\] -fixed false -x 481 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_1 -fixed false -x 106 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel\[3\] -fixed false -x 542 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[5\] -fixed false -x 167 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[5\] -fixed false -x 115 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IoIO1 -fixed false -x 82 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[11\] -fixed false -x 126 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[28\] -fixed false -x 542 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[4\] -fixed false -x 83 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/un1_Ioli0_1_0 -fixed false -x 182 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_2 -fixed false -x 161 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[3\] -fixed false -x 790 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[2\] -fixed false -x 39 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24\[6\] -fixed false -x 274 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[8\] -fixed false -x 294 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_4 -fixed false -x 137 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[7\] -fixed false -x 498 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3\[2\] -fixed false -x 68 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1291 -fixed false -x 608 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_ss0_0 -fixed false -x 774 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[7\] -fixed false -x 427 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1_i_m2\[2\] -fixed false -x 876 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0iIo -fixed false -x 414 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[5\] -fixed false -x 110 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O0lI1 -fixed false -x 434 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q1 -fixed false -x 733 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int\[1\] -fixed false -x 795 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1211 -fixed false -x 703 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[45\] -fixed false -x 917 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[4\] -fixed false -x 778 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[26\] -fixed false -x 870 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[4\] -fixed false -x 938 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[1\] -fixed false -x 796 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[4\] -fixed false -x 798 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_49\[9\] -fixed false -x 910 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m2 -fixed false -x 128 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_RNIDBOQT_0 -fixed false -x 856 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[14\] -fixed false -x 896 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[1\] -fixed false -x 368 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[14\] -fixed false -x 501 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[3\] -fixed false -x 869 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[22\] -fixed false -x 432 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[7\] -fixed false -x 137 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[0\] -fixed false -x 180 -y 178
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv_RNO\[5\] -fixed false -x 495 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI9RFUI\[3\] -fixed false -x 865 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[24\] -fixed false -x 958 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_249 -fixed false -x 801 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_20 -fixed false -x 695 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[24\] -fixed false -x 589 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[1\] -fixed false -x 78 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2\[1\] -fixed false -x 635 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[44\] -fixed false -x 969 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[7\] -fixed false -x 294 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[24\] -fixed false -x 476 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[10\] -fixed false -x 766 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_274 -fixed false -x 621 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_alu_op_completing_ex_RNIDSVU6 -fixed false -x 777 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[12\] -fixed false -x 844 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[5\] -fixed false -x 899 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0\[2\] -fixed false -x 131 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0\[3\] -fixed false -x 526 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[26\] -fixed false -x 491 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state136 -fixed false -x 526 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[31\] -fixed false -x 747 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_subsys_cfg_0_o2 -fixed false -x 802 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/un1_Ioli0_1_0 -fixed false -x 314 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_959 -fixed false -x 669 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_2\[24\] -fixed false -x 739 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_9 -fixed false -x 46 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[16\] -fixed false -x 849 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[23\] -fixed false -x 440 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m26_1_0 -fixed false -x 82 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[14\] -fixed false -x 621 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[6\] -fixed false -x 363 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[19\] -fixed false -x 772 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_o2 -fixed false -x 723 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[1\] -fixed false -x 469 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_0 -fixed false -x 537 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_506 -fixed false -x 765 -y 192
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[0\] -fixed false -x 491 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[25\] -fixed false -x 830 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[1\] -fixed false -x 822 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[23\] -fixed false -x 655 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/valid_out -fixed false -x 750 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[15\] -fixed false -x 922 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[4\] -fixed false -x 544 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[9\] -fixed false -x 762 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0\[0\] -fixed false -x 289 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[16\] -fixed false -x 419 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[0\] -fixed false -x 385 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[3\] -fixed false -x 110 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[22\] -fixed false -x 829 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[11\] -fixed false -x 508 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[3\] -fixed false -x 624 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[7\] -fixed false -x 418 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[11\] -fixed false -x 794 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[51\] -fixed false -x 606 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIOMCV6\[4\] -fixed false -x 259 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO -fixed false -x 826 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO1o1_RNI5IQ17 -fixed false -x 12 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[2\] -fixed false -x 342 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[8\] -fixed false -x 780 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[1\] -fixed false -x 498 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[15\] -fixed false -x 735 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[0\] -fixed false -x 235 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[31\] -fixed false -x 516 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[27\] -fixed false -x 485 -y 187
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[1\] -fixed false -x 375 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1250 -fixed false -x 762 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[5\] -fixed false -x 464 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mstatus_rd_data\[7\] -fixed false -x 728 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2\[2\] -fixed false -x 771 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[5\] -fixed false -x 346 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IOoO1_RNIL90CO -fixed false -x 264 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m3_0_a2_0 -fixed false -x 767 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_0 -fixed false -x 622 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[4\] -fixed false -x 310 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[2\] -fixed false -x 516 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i_a2_0 -fixed false -x 589 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[7\] -fixed false -x 867 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_10_f0 -fixed false -x 772 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[7\] -fixed false -x 80 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_m9_i_0 -fixed false -x 57 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[8\] -fixed false -x 551 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_639 -fixed false -x 755 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[25\] -fixed false -x 909 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[29\] -fixed false -x 845 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[14\] -fixed false -x 121 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_0\[13\] -fixed false -x 851 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[3\] -fixed false -x 185 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5\[1\] -fixed false -x 734 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[15\] -fixed false -x 889 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2\[1\] -fixed false -x 692 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[1\] -fixed false -x 498 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr\[0\] -fixed false -x 781 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[16\] -fixed false -x 442 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[21\] -fixed false -x 441 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m24 -fixed false -x 59 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[10\] -fixed false -x 269 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[5\] -fixed false -x 67 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_419 -fixed false -x 645 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[18\] -fixed false -x 642 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[7\] -fixed false -x 572 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/i0iI1 -fixed false -x 232 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[8\] -fixed false -x 109 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[30\] -fixed false -x 613 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[1\] -fixed false -x 921 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[2\] -fixed false -x 730 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_1\[4\] -fixed false -x 260 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[30\] -fixed false -x 907 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[27\] -fixed false -x 812 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[7\] -fixed false -x 450 -y 211
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[20\] -fixed false -x 410 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[17\] -fixed false -x 934 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_911 -fixed false -x 716 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[6\] -fixed false -x 104 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_340 -fixed false -x 633 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4 -fixed false -x 526 -y 147
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[6\].BUFD_BLK -fixed false -x 487 -y 93
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/full_out -fixed false -x 539 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0_1\[0\] -fixed false -x 634 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lool1 -fixed false -x 388 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_31_RNO -fixed false -x 833 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[8\] -fixed false -x 191 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex\[0\] -fixed false -x 730 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[6\] -fixed false -x 208 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iooo1 -fixed false -x 69 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr\[0\] -fixed false -x 661 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[1\] -fixed false -x 46 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[47\] -fixed false -x 604 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[10\] -fixed false -x 231 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[18\] -fixed false -x 453 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[37\] -fixed false -x 921 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Io0o1 -fixed false -x 82 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[5\] -fixed false -x 899 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv\[10\] -fixed false -x 646 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[8\] -fixed false -x 366 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[16\] -fixed false -x 396 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[0\] -fixed false -x 514 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[29\] -fixed false -x 415 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[6\] -fixed false -x 335 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[30\] -fixed false -x 598 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[2\] -fixed false -x 215 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_6 -fixed false -x 183 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/olOl1 -fixed false -x 442 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO_1\[1\] -fixed false -x 557 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[14\] -fixed false -x 417 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[2\] -fixed false -x 705 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0 -fixed false -x 72 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[5\] -fixed false -x 201 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un2_exception_taken_RNIDRB35 -fixed false -x 798 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1041 -fixed false -x 714 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[21\] -fixed false -x 920 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr_1\[7\] -fixed false -x 690 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_3 -fixed false -x 810 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0\[0\] -fixed false -x 107 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[28\] -fixed false -x 921 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m30_1_0 -fixed false -x 35 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[13\] -fixed false -x 899 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_67 -fixed false -x 693 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1_2_0_0 -fixed false -x 135 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/OloIo -fixed false -x 252 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[16\] -fixed false -x 420 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[16\] -fixed false -x 445 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[11\] -fixed false -x 706 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2\[0\] -fixed false -x 47 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_2_1\[0\] -fixed false -x 637 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_0\[2\] -fixed false -x 751 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[3\] -fixed false -x 450 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_2\[2\] -fixed false -x 641 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs1_rd_hzd_4 -fixed false -x 792 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count\[0\] -fixed false -x 781 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[9\] -fixed false -x 874 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_1\[13\] -fixed false -x 120 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0\[2\] -fixed false -x 140 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[1\] -fixed false -x 436 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[9\] -fixed false -x 286 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[24\] -fixed false -x 860 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[6\] -fixed false -x 679 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[35\] -fixed false -x 496 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[14\] -fixed false -x 841 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[24\] -fixed false -x 426 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1299 -fixed false -x 694 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_1 -fixed false -x 798 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[9\] -fixed false -x 382 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[1\] -fixed false -x 415 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0\[30\] -fixed false -x 939 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[3\] -fixed false -x 699 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_1 -fixed false -x 241 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_4\[0\] -fixed false -x 816 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1219 -fixed false -x 644 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[2\] -fixed false -x 254 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_2 -fixed false -x 821 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[25\] -fixed false -x 660 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[28\] -fixed false -x 662 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[17\] -fixed false -x 849 -y 132
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[24\].BUFD_BLK -fixed false -x 509 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1294 -fixed false -x 789 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[10\] -fixed false -x 229 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1_RNIHBJH62 -fixed false -x 167 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_5 -fixed false -x 177 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[22\] -fixed false -x 412 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[7\] -fixed false -x 371 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[12\] -fixed false -x 863 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1153 -fixed false -x 692 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[31\] -fixed false -x 273 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_145 -fixed false -x 682 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1214 -fixed false -x 741 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[9\] -fixed false -x 538 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[6\] -fixed false -x 176 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1241 -fixed false -x 754 -y 183
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state138 -fixed false -x 527 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[31\] -fixed false -x 886 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[7\] -fixed false -x 687 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_456 -fixed false -x 703 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[0\] -fixed false -x 148 -y 217
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_5_c4 -fixed false -x 107 -y 216
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[4\] -fixed false -x 440 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[19\] -fixed false -x 698 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_4_tz_0_RNO\[0\] -fixed false -x 839 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv\[15\] -fixed false -x 715 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_53 -fixed false -x 766 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO_0 -fixed false -x 790 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[2\] -fixed false -x 130 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[7\] -fixed false -x 418 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[12\] -fixed false -x 239 -y 213
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[24\].BUFD_BLK -fixed false -x 488 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[53\] -fixed false -x 897 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[0\] -fixed false -x 266 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err5 -fixed false -x 461 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[14\] -fixed false -x 390 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRUPD -fixed false -x 515 -y 90
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[21\] -fixed false -x 59 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[15\] -fixed false -x 416 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_11_RNIN1HN71 -fixed false -x 707 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_1\[3\] -fixed false -x 737 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[8\] -fixed false -x 206 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2\[0\] -fixed false -x 678 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_1\[3\] -fixed false -x 263 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[28\] -fixed false -x 909 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1\[3\] -fixed false -x 810 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[16\] -fixed false -x 308 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[9\] -fixed false -x 872 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oIiOo_1.iOiOo_3 -fixed false -x 333 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[13\] -fixed false -x 269 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1277 -fixed false -x 741 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1\[33\] -fixed false -x 472 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[8\] -fixed false -x 204 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI3D0P9\[2\] -fixed false -x 70 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[1\] -fixed false -x 251 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[11\] -fixed false -x 431 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_0 -fixed false -x 694 -y 111
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[2\] -fixed false -x 399 -y 256
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[9\] -fixed false -x 426 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[11\] -fixed false -x 727 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[5\] -fixed false -x 40 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_3_tz -fixed false -x 683 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val_12_0\[0\] -fixed false -x 727 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iooo1 -fixed false -x 63 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_22 -fixed false -x 681 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[22\] -fixed false -x 764 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[17\] -fixed false -x 418 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[0\] -fixed false -x 774 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1\[7\] -fixed false -x 159 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOi11 -fixed false -x 356 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[9\] -fixed false -x 500 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[13\] -fixed false -x 851 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_29 -fixed false -x 713 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9\[9\] -fixed false -x 169 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[0\] -fixed false -x 44 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[3\] -fixed false -x 572 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[15\] -fixed false -x 664 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[50\] -fixed false -x 567 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[0\] -fixed false -x 483 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[7\] -fixed false -x 321 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0 -fixed false -x 733 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_81 -fixed false -x 730 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[44\] -fixed false -x 121 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[0\] -fixed false -x 461 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[7\] -fixed false -x 443 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ilio1 -fixed false -x 73 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIO11\[0\] -fixed false -x 30 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3\[14\] -fixed false -x 862 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[10\] -fixed false -x 227 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[15\] -fixed false -x 388 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg\[3\] -fixed false -x 737 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[18\] -fixed false -x 458 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[6\] -fixed false -x 107 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[16\] -fixed false -x 593 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[0\] -fixed false -x 352 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[9\] -fixed false -x 96 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[4\] -fixed false -x 43 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[6\] -fixed false -x 420 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15_0 -fixed false -x 611 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_iOIOo\[0\] -fixed false -x 46 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/iOol1 -fixed false -x 406 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[3\] -fixed false -x 189 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[29\] -fixed false -x 870 -y 138
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[6\] -fixed false -x 566 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[12\] -fixed false -x 663 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/un1_iOI01_1_i_0 -fixed false -x 194 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_328 -fixed false -x 657 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0\[6\] -fixed false -x 63 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[6\] -fixed false -x 173 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_3 -fixed false -x 248 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4928_2 -fixed false -x 621 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_26_RNI3M8GT -fixed false -x 38 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un34_loOo1\[6\] -fixed false -x 300 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[19\] -fixed false -x 899 -y 138
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[25\] -fixed false -x 411 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/IilI1_RNO -fixed false -x 463 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[10\] -fixed false -x 516 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[31\] -fixed false -x 934 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30\[0\] -fixed false -x 251 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[25\] -fixed false -x 898 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0\[5\] -fixed false -x 775 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[0\] -fixed false -x 127 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1_1107_0 -fixed false -x 106 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIP2CS7\[5\] -fixed false -x 891 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[1\] -fixed false -x 181 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[15\] -fixed false -x 891 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[5\] -fixed false -x 860 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[12\] -fixed false -x 397 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[13\] -fixed false -x 503 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[6\] -fixed false -x 826 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.SUM\[2\] -fixed false -x 875 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[1\] -fixed false -x 70 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex\[1\] -fixed false -x 752 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[25\] -fixed false -x 876 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/wfi_waiting_reg6 -fixed false -x 772 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[6\] -fixed false -x 959 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOo01 -fixed false -x 105 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[4\] -fixed false -x 102 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_821 -fixed false -x 681 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_168 -fixed false -x 762 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter\[3\] -fixed false -x 787 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIR4FO8 -fixed false -x 260 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[6\] -fixed false -x 115 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_609 -fixed false -x 753 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lii01_1 -fixed false -x 39 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[5\] -fixed false -x 258 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[23\] -fixed false -x 814 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_3 -fixed false -x 804 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[4\] -fixed false -x 720 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Ilol1 -fixed false -x 357 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[3\] -fixed false -x 360 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_4 -fixed false -x 163 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[19\] -fixed false -x 135 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIGLF2G\[15\] -fixed false -x 82 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m6 -fixed false -x 113 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1iIo -fixed false -x 436 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14\[14\] -fixed false -x 947 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[23\] -fixed false -x 908 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO1I1 -fixed false -x 526 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[13\] -fixed false -x 735 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[11\] -fixed false -x 450 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic1881 -fixed false -x 659 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m47_1_0 -fixed false -x 83 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[18\] -fixed false -x 933 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_Io0I1_2_0 -fixed false -x 386 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_RNO\[1\] -fixed false -x 181 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o1I018_1 -fixed false -x 215 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[11\] -fixed false -x 381 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[3\] -fixed false -x 925 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[14\] -fixed false -x 884 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[10\] -fixed false -x 759 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1161 -fixed false -x 618 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[4\] -fixed false -x 354 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[17\] -fixed false -x 438 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_383 -fixed false -x 716 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_2\[0\] -fixed false -x 800 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[20\] -fixed false -x 403 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001\[2\] -fixed false -x 91 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[17\] -fixed false -x 745 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[5\] -fixed false -x 90 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[2\] -fixed false -x 232 -y 178
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_RNO\[3\] -fixed false -x 452 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[9\] -fixed false -x 382 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[4\] -fixed false -x 214 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[10\] -fixed false -x 191 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1249 -fixed false -x 717 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[2\] -fixed false -x 255 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_3_0\[5\] -fixed false -x 293 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[7\] -fixed false -x 133 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[14\] -fixed false -x 57 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/un1_iOI01_1_i_0 -fixed false -x 246 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[22\] -fixed false -x 212 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un60_OIoO1_1 -fixed false -x 73 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_0_RNI8AH6O -fixed false -x 822 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[27\] -fixed false -x 672 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/III11 -fixed false -x 140 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_1_RNIMCNVO3 -fixed false -x 777 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[8\] -fixed false -x 907 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1244 -fixed false -x 729 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[4\] -fixed false -x 524 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[18\] -fixed false -x 94 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[56\] -fixed false -x 936 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z\[2\] -fixed false -x 542 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[5\] -fixed false -x 945 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Il0l1\[0\] -fixed false -x 464 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7\[7\] -fixed false -x 207 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[2\] -fixed false -x 237 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[7\] -fixed false -x 93 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[8\] -fixed false -x 446 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_13 -fixed false -x 622 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO_0 -fixed false -x 835 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[21\] -fixed false -x 814 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 486 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state_0_sqmuxa_i_RNI4B2FB -fixed false -x 713 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[2\] -fixed false -x 369 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[12\] -fixed false -x 209 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_65 -fixed false -x 715 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOIo1 -fixed false -x 309 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIII1 -fixed false -x 506 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[4\] -fixed false -x 389 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[1\] -fixed false -x 880 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[0\] -fixed false -x 175 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_1_0 -fixed false -x 24 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[10\] -fixed false -x 167 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a3_0_5 -fixed false -x 178 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIIVK9D_0 -fixed false -x 720 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.N_8_i -fixed false -x 48 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_39_0_o2_0 -fixed false -x 627 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[60\] -fixed false -x 949 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ll1i1_0_a2_0 -fixed false -x 200 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[7\] -fixed false -x 287 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[3\] -fixed false -x 281 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[10\] -fixed false -x 233 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_4_1_0 -fixed false -x 46 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olo01_RNO -fixed false -x 97 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[11\] -fixed false -x 232 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3_0_RNO_1 -fixed false -x 857 -y 147
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc3 -fixed false -x 67 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[34\] -fixed false -x 430 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_11 -fixed false -x 482 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag\[0\] -fixed false -x 69 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[29\] -fixed false -x 572 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1I11 -fixed false -x 185 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3\[0\] -fixed false -x 575 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[8\] -fixed false -x 754 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1050 -fixed false -x 787 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[27\] -fixed false -x 395 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_0\[1\] -fixed false -x 487 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg\[1\] -fixed false -x 574 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[7\] -fixed false -x 252 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_read_gpr_rs1_ex.gen_rs1_exu_stall.un7_gpr_rs1_stall_exu_NE_1 -fixed false -x 742 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[6\] -fixed false -x 268 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[5\] -fixed false -x 920 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3\[1\] -fixed false -x 300 -y 168
|
|
set_location -inst_name SSDetect_0/is_match_0.un3_is_match_4 -fixed false -x 17 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1\[5\] -fixed false -x 909 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[4\] -fixed false -x 840 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[24\] -fixed false -x 222 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Il1I1 -fixed false -x 405 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[1\] -fixed false -x 384 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[5\] -fixed false -x 163 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[2\] -fixed false -x 550 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i\[6\] -fixed false -x 610 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m4 -fixed false -x 640 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[13\] -fixed false -x 373 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat14 -fixed false -x 562 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[4\] -fixed false -x 461 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[10\] -fixed false -x 721 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO\[2\] -fixed false -x 570 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i11l1 -fixed false -x 407 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1o01 -fixed false -x 106 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO\[3\] -fixed false -x 591 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNI0NE1B\[18\] -fixed false -x 79 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_mtie/gen_bit_no_reset.state_val\[0\] -fixed false -x 759 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1004 -fixed false -x 603 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_3_0 -fixed false -x 699 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5\[0\] -fixed false -x 638 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q1_3 -fixed false -x 725 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m23_2_0 -fixed false -x 688 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI8B984\[13\] -fixed false -x 840 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01_1 -fixed false -x 75 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[3\] -fixed false -x 604 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO_0\[1\] -fixed false -x 552 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[11\] -fixed false -x 241 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val\[0\] -fixed false -x 727 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_5 -fixed false -x 717 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_16_iv\[34\] -fixed false -x 473 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[2\] -fixed false -x 229 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[18\] -fixed false -x 409 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[26\] -fixed false -x 813 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_19 -fixed false -x 675 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[27\] -fixed false -x 673 -y 124
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[10\] -fixed false -x 377 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[31\] -fixed false -x 843 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[0\] -fixed false -x 225 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_3 -fixed false -x 666 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1iO1 -fixed false -x 189 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[3\] -fixed false -x 537 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO_1 -fixed false -x 825 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo -fixed false -x 40 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[1\] -fixed false -x 815 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[4\] -fixed false -x 308 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[30\] -fixed false -x 444 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[19\] -fixed false -x 537 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[5\] -fixed false -x 199 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[2\] -fixed false -x 286 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[28\] -fixed false -x 341 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i\[8\] -fixed false -x 718 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[8\] -fixed false -x 311 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[61\] -fixed false -x 599 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[17\] -fixed false -x 140 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_7 -fixed false -x 764 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1256 -fixed false -x 596 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m0_i_a2_0_RNIAVO2NT\[0\] -fixed false -x 764 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[31\] -fixed false -x 622 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[0\] -fixed false -x 123 -y 190
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n\[0\] -fixed false -x 15 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[31\] -fixed false -x 678 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[27\] -fixed false -x 387 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[7\] -fixed false -x 756 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[35\] -fixed false -x 627 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[3\] -fixed false -x 247 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[5\] -fixed false -x 117 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000111 -fixed false -x 66 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_178 -fixed false -x 592 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_UDRUPD -fixed false -x 525 -y 96
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[9\].BUFD_BLK -fixed false -x 491 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[13\] -fixed false -x 328 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_valid_mux_RNIV59BU -fixed false -x 817 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[13\] -fixed false -x 758 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001\[0\] -fixed false -x 84 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[7\] -fixed false -x 341 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/IO001 -fixed false -x 215 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[4\] -fixed false -x 238 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[30\].BUFD_BLK -fixed false -x 550 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_1_sqmuxa_0_a2 -fixed false -x 456 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_0 -fixed false -x 172 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[1\] -fixed false -x 526 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/empty_out -fixed false -x 537 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2\[15\] -fixed false -x 718 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo -fixed false -x 16 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un15_OIoO1 -fixed false -x 26 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel\[1\] -fixed false -x 545 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[27\] -fixed false -x 863 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7\[4\] -fixed false -x 182 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[3\] -fixed false -x 327 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i\[29\] -fixed false -x 911 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[13\] -fixed false -x 120 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_strb\[1\] -fixed false -x 806 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[15\] -fixed false -x 469 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un3_irq_stall_lsu_req -fixed false -x 805 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un2_i0Il1 -fixed false -x 458 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[43\] -fixed false -x 562 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[6\] -fixed false -x 536 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[13\] -fixed false -x 58 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[9\] -fixed false -x 245 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[9\] -fixed false -x 137 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_1\[31\] -fixed false -x 754 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0i01_0_x2 -fixed false -x 98 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_86 -fixed false -x 676 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold_2_i_o2 -fixed false -x 871 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_i0iOo -fixed false -x 125 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[7\] -fixed false -x 396 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[12\] -fixed false -x 498 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO\[2\] -fixed false -x 274 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[18\] -fixed false -x 439 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1l11 -fixed false -x 253 -y 190
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst -fixed false -x 504 -y 2
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO -fixed false -x 868 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_0 -fixed false -x 720 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iio11 -fixed false -x 335 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_485 -fixed false -x 634 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_loOo1_0_o2_0 -fixed false -x 291 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[12\] -fixed false -x 650 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_empty -fixed false -x 728 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[8\] -fixed false -x 250 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_0_1 -fixed false -x 95 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10\[3\] -fixed false -x 542 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[0\] -fixed false -x 793 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_bcu_op_sel_ex_2 -fixed false -x 748 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[25\] -fixed false -x 120 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICTI09 -fixed false -x 772 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un29_il0Oo_0 -fixed false -x 231 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[19\] -fixed false -x 669 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_10 -fixed false -x 232 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[24\] -fixed false -x 423 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNO -fixed false -x 100 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[10\] -fixed false -x 887 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[29\] -fixed false -x 834 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[23\] -fixed false -x 836 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[13\] -fixed false -x 807 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un183_I1Oi1 -fixed false -x 69 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV_4 -fixed false -x 438 -y 3
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[1\] -fixed false -x 334 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1208 -fixed false -x 702 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[19\] -fixed false -x 451 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2\[5\] -fixed false -x 291 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[4\] -fixed false -x 501 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iooo1 -fixed false -x 61 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[11\] -fixed false -x 193 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO\[4\] -fixed false -x 256 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[2\] -fixed false -x 111 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[5\] -fixed false -x 701 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_1\[5\] -fixed false -x 536 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m15 -fixed false -x 609 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3_2\[0\] -fixed false -x 637 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[17\] -fixed false -x 831 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[0\] -fixed false -x 68 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[30\] -fixed false -x 702 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_1\[3\] -fixed false -x 313 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_16\[0\] -fixed false -x 823 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_5_RNIQDDH9 -fixed false -x 658 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[52\] -fixed false -x 878 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[20\] -fixed false -x 443 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[2\] -fixed false -x 653 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[13\] -fixed false -x 806 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[15\] -fixed false -x 589 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[3\] -fixed false -x 369 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un16_i00i1lto15 -fixed false -x 186 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[15\] -fixed false -x 595 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l1iIo -fixed false -x 432 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[2\] -fixed false -x 145 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_5 -fixed false -x 527 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ioll1 -fixed false -x 490 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[5\] -fixed false -x 246 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[19\] -fixed false -x 93 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1136 -fixed false -x 655 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_SWITCH_LANE9\[0\] -fixed false -x 22 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[10\] -fixed false -x 705 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIDCBP2_0\[1\] -fixed false -x 258 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3_0_0\[3\] -fixed false -x 782 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[28\] -fixed false -x 958 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0 -fixed false -x 489 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[18\] -fixed false -x 638 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_m11_0_N_7L12 -fixed false -x 799 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[5\] -fixed false -x 362 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_3 -fixed false -x 677 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[24\] -fixed false -x 807 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_915 -fixed false -x 714 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[24\] -fixed false -x 682 -y 132
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[26\] -fixed false -x 418 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_50\[11\] -fixed false -x 328 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_emi_req_os_at_flush\[0\] -fixed false -x 788 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[26\] -fixed false -x 772 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[9\] -fixed false -x 229 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_a2\[4\] -fixed false -x 662 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[3\] -fixed false -x 198 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_o9_0 -fixed false -x 511 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[26\] -fixed false -x 346 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[10\] -fixed false -x 543 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[8\] -fixed false -x 822 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_3 -fixed false -x 235 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[0\] -fixed false -x 27 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[16\] -fixed false -x 967 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[12\] -fixed false -x 719 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_3 -fixed false -x 93 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[20\] -fixed false -x 751 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_256 -fixed false -x 658 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[6\] -fixed false -x 355 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[0\] -fixed false -x 767 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2s2_0 -fixed false -x 776 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m\[1\] -fixed false -x 336 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[10\] -fixed false -x 804 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[7\] -fixed false -x 274 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_510 -fixed false -x 702 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/loil1 -fixed false -x 484 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[6\] -fixed false -x 83 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy_1_sqmuxa -fixed false -x 531 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ooIl1 -fixed false -x 455 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[21\] -fixed false -x 448 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[0\] -fixed false -x 256 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_a2_0 -fixed false -x 94 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[33\] -fixed false -x 467 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[18\] -fixed false -x 802 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[10\] -fixed false -x 463 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lOlo1 -fixed false -x 321 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_0 -fixed false -x 70 -y 201
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE_10\[10\] -fixed false -x 19 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os -fixed false -x 713 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[17\] -fixed false -x 309 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[44\] -fixed false -x 316 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[17\] -fixed false -x 429 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/OlI01 -fixed false -x 197 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a2\[1\] -fixed false -x 668 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[22\] -fixed false -x 874 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[17\] -fixed false -x 386 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z\[3\] -fixed false -x 336 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[30\] -fixed false -x 833 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[2\] -fixed false -x 765 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40_cZ\[5\] -fixed false -x 324 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[51\] -fixed false -x 899 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[7\] -fixed false -x 152 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[3\] -fixed false -x 887 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5\[1\] -fixed false -x 649 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oi1o1_0_m2_i\[0\] -fixed false -x 79 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[26\] -fixed false -x 874 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_7 -fixed false -x 745 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[12\] -fixed false -x 531 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[36\] -fixed false -x 125 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[28\] -fixed false -x 945 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[28\] -fixed false -x 681 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_147 -fixed false -x 679 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_51\[7\] -fixed false -x 515 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex\[2\] -fixed false -x 697 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_could_commit_0_RNIDEK1B -fixed false -x 802 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_450 -fixed false -x 776 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2\[13\] -fixed false -x 748 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[5\] -fixed false -x 245 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[6\] -fixed false -x 350 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_884 -fixed false -x 597 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_oI0i1_1 -fixed false -x 114 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1\[2\] -fixed false -x 291 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_22 -fixed false -x 620 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[1\] -fixed false -x 194 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1\[7\] -fixed false -x 153 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_8 -fixed false -x 865 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIPU8GO\[29\] -fixed false -x 907 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff -fixed false -x 721 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_1 -fixed false -x 684 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_14 -fixed false -x 390 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[16\] -fixed false -x 707 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2 -fixed false -x 756 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[25\] -fixed false -x 897 -y 132
|
|
set_location -inst_name SSDetect_0/is_match_3 -fixed false -x 18 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr\[2\] -fixed false -x 829 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[5\] -fixed false -x 349 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[2\] -fixed false -x 202 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[27\] -fixed false -x 765 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[3\] -fixed false -x 406 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO\[0\] -fixed false -x 521 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[17\] -fixed false -x 806 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en -fixed false -x 797 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_o2\[1\] -fixed false -x 826 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[24\] -fixed false -x 933 -y 147
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_14\[0\] -fixed false -x 754 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOiI1 -fixed false -x 345 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[13\] -fixed false -x 138 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[14\] -fixed false -x 777 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[5\] -fixed false -x 181 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIO11\[0\] -fixed false -x 30 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[1\] -fixed false -x 885 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[15\] -fixed false -x 44 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l15_i_0 -fixed false -x 406 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[2\] -fixed false -x 393 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1 -fixed false -x 298 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[0\] -fixed false -x 410 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[20\] -fixed false -x 957 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[32\] -fixed false -x 900 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[32\] -fixed false -x 541 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo\[8\] -fixed false -x 311 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[30\] -fixed false -x 840 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11\[1\] -fixed false -x 287 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[2\] -fixed false -x 151 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[30\] -fixed false -x 599 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[32\] -fixed false -x 629 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[29\] -fixed false -x 652 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[29\] -fixed false -x 675 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a2 -fixed false -x 158 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[18\] -fixed false -x 74 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[9\] -fixed false -x 547 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0\[15\] -fixed false -x 140 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[1\] -fixed false -x 147 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_holdsel_RNO -fixed false -x 513 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0\[1\] -fixed false -x 104 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_660 -fixed false -x 691 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_Oill1 -fixed false -x 412 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[7\] -fixed false -x 551 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[0\] -fixed false -x 45 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[4\] -fixed false -x 359 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1_RNO -fixed false -x 271 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un213_I1Oi1_2 -fixed false -x 37 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_744 -fixed false -x 621 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[17\] -fixed false -x 382 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[0\] -fixed false -x 315 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_1\[2\] -fixed false -x 626 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[6\] -fixed false -x 41 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[6\] -fixed false -x 452 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[7\] -fixed false -x 371 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_1_sqmuxa_1 -fixed false -x 822 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[7\] -fixed false -x 303 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_RNIPKND6\[5\] -fixed false -x 115 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_a2_2\[4\] -fixed false -x 723 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/next_buff_valid\[0\] -fixed false -x 760 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1\[0\] -fixed false -x 166 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[1\] -fixed false -x 783 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo\[2\] -fixed false -x 121 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[15\] -fixed false -x 460 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[31\] -fixed false -x 879 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[7\] -fixed false -x 342 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_468 -fixed false -x 667 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[10\] -fixed false -x 517 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[36\] -fixed false -x 555 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ\[13\] -fixed false -x 278 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0ii1_2 -fixed false -x 132 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_OIio1_1_0 -fixed false -x 57 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[7\] -fixed false -x 727 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[18\] -fixed false -x 848 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[9\] -fixed false -x 150 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO\[1\] -fixed false -x 564 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oiol1 -fixed false -x 338 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m21 -fixed false -x 52 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[4\] -fixed false -x 191 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_cfg_enable -fixed false -x 528 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[0\] -fixed false -x 304 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[3\] -fixed false -x 89 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[18\] -fixed false -x 848 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[5\] -fixed false -x 851 -y 124
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit\[1\] -fixed false -x 465 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOIOo -fixed false -x 47 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state136_1 -fixed false -x 526 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO_0 -fixed false -x 830 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_0\[5\] -fixed false -x 308 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_988 -fixed false -x 703 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[5\] -fixed false -x 792 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[43\] -fixed false -x 148 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[2\] -fixed false -x 309 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[9\] -fixed false -x 535 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_reset -fixed false -x 630 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo_RNO -fixed false -x 13 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m6 -fixed false -x 107 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[2\] -fixed false -x 279 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[11\] -fixed false -x 657 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0\[1\] -fixed false -x 101 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m4 -fixed false -x 69 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[7\] -fixed false -x 515 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1_RNO -fixed false -x 799 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO0Oo -fixed false -x 162 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[1\] -fixed false -x 130 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[15\] -fixed false -x 379 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I0io1_0 -fixed false -x 56 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_1\[4\] -fixed false -x 875 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_17_0_i -fixed false -x 70 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[1\] -fixed false -x 242 -y 184
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/re_set_RNO -fixed false -x 390 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[26\] -fixed false -x 874 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m\[0\] -fixed false -x 337 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[1\] -fixed false -x 204 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_1 -fixed false -x 280 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[9\] -fixed false -x 430 -y 211
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane_RNO -fixed false -x 19 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[13\] -fixed false -x 561 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_1\[1\] -fixed false -x 661 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25_1\[11\] -fixed false -x 340 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loIOo -fixed false -x 20 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[0\] -fixed false -x 319 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[13\] -fixed false -x 269 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24\[7\] -fixed false -x 262 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[4\] -fixed false -x 114 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[16\] -fixed false -x 464 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[11\] -fixed false -x 776 -y 136
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[4\] -fixed false -x 450 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[9\] -fixed false -x 45 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[2\] -fixed false -x 177 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[6\] -fixed false -x 846 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[28\] -fixed false -x 707 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iiOI1 -fixed false -x 522 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[31\] -fixed false -x 518 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1_RNO -fixed false -x 136 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[8\] -fixed false -x 718 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[47\] -fixed false -x 566 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_oiiI1_1_0 -fixed false -x 440 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_IlIi1_1_0 -fixed false -x 163 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_2\[6\] -fixed false -x 633 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11\[2\] -fixed false -x 104 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[13\] -fixed false -x 650 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[7\] -fixed false -x 511 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[0\] -fixed false -x 161 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[10\] -fixed false -x 710 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[2\] -fixed false -x 58 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[13\] -fixed false -x 933 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[13\] -fixed false -x 274 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_flush -fixed false -x 727 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_781 -fixed false -x 658 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[11\] -fixed false -x 238 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex\[0\] -fixed false -x 771 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_oOOl1 -fixed false -x 436 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[4\] -fixed false -x 210 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[6\] -fixed false -x 120 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO_1 -fixed false -x 682 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[6\] -fixed false -x 224 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[15\] -fixed false -x 42 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_0_o2_0\[3\] -fixed false -x 608 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[28\] -fixed false -x 590 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRJTQ8\[25\] -fixed false -x 662 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[0\] -fixed false -x 44 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[32\] -fixed false -x 461 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[29\] -fixed false -x 415 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_2 -fixed false -x 620 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_28\[10\] -fixed false -x 225 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[2\] -fixed false -x 44 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1 -fixed false -x 227 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_RNO -fixed false -x 267 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[10\] -fixed false -x 728 -y 124
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_2\[1\] -fixed false -x 524 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[6\] -fixed false -x 78 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_687 -fixed false -x 705 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_786 -fixed false -x 743 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m15_e -fixed false -x 58 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[18\] -fixed false -x 646 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[29\] -fixed false -x 917 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo_RNO -fixed false -x 266 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[4\] -fixed false -x 406 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[1\] -fixed false -x 431 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[25\] -fixed false -x 850 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[9\] -fixed false -x 348 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/IilI1 -fixed false -x 292 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[2\] -fixed false -x 971 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[7\] -fixed false -x 274 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[21\] -fixed false -x 888 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0_4 -fixed false -x 98 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[19\] -fixed false -x 456 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[13\] -fixed false -x 350 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[14\] -fixed false -x 776 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr\[1\] -fixed false -x 708 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo -fixed false -x 13 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[2\] -fixed false -x 127 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_rd_ptr\[0\] -fixed false -x 750 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[0\] -fixed false -x 346 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 -fixed false -x 370 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[29\] -fixed false -x 460 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O00o1_f0\[2\] -fixed false -x 80 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc6 -fixed false -x 105 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[13\] -fixed false -x 362 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex -fixed false -x 756 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_643 -fixed false -x 752 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[6\] -fixed false -x 444 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_1_1\[16\] -fixed false -x 967 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[22\] -fixed false -x 921 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[11\] -fixed false -x 273 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1 -fixed false -x 23 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_2_i_x2_0\[0\] -fixed false -x 789 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[0\] -fixed false -x 127 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[6\] -fixed false -x 497 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33\[1\] -fixed false -x 322 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[1\] -fixed false -x 405 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1 -fixed false -x 107 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid_3_2 -fixed false -x 785 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[31\] -fixed false -x 819 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[14\] -fixed false -x 216 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a3_4 -fixed false -x 177 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_134 -fixed false -x 765 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[16\] -fixed false -x 57 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0_RNIUBGA4F2 -fixed false -x 797 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_423 -fixed false -x 728 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[12\] -fixed false -x 402 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[19\] -fixed false -x 863 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[14\] -fixed false -x 774 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[0\] -fixed false -x 116 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1\[6\] -fixed false -x 831 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oIiOo_1.CO2 -fixed false -x 325 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/un1_Ioli0_1_0 -fixed false -x 388 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[8\] -fixed false -x 514 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_2\[28\] -fixed false -x 946 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2 -fixed false -x 825 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[8\] -fixed false -x 166 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i\[7\] -fixed false -x 711 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_1\[2\] -fixed false -x 687 -y 138
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0_DELAY -fixed false -x 7 -y 376
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[4\] -fixed false -x 713 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1IOo -fixed false -x 26 -y 165
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_3\[0\] -fixed false -x 754 -y 4
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[15\] -fixed false -x 393 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_21 -fixed false -x 699 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_oIIi1_0 -fixed false -x 178 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[0\] -fixed false -x 425 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[5\] -fixed false -x 406 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1\[3\] -fixed false -x 120 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_rd_en -fixed false -x 731 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_5 -fixed false -x 682 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un7_cpu_d_resp_valid_rd_0 -fixed false -x 803 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1_1\[2\] -fixed false -x 500 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_i_o2\[5\] -fixed false -x 124 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[21\] -fixed false -x 380 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_3\[2\] -fixed false -x 753 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[2\] -fixed false -x 284 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[13\] -fixed false -x 81 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_670 -fixed false -x 669 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[11\] -fixed false -x 408 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[9\] -fixed false -x 513 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[31\] -fixed false -x 627 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a2_1 -fixed false -x 355 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[25\] -fixed false -x 479 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_IOio1 -fixed false -x 55 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[13\] -fixed false -x 323 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/IilI1 -fixed false -x 215 -y 169
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_3\[2\] -fixed false -x 514 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[2\] -fixed false -x 768 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[3\] -fixed false -x 362 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[7\] -fixed false -x 712 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch\[0\] -fixed false -x 646 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m40_1_0 -fixed false -x 34 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[1\] -fixed false -x 221 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io\[0\] -fixed false -x 384 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_3 -fixed false -x 160 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[19\] -fixed false -x 601 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[16\] -fixed false -x 389 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[9\] -fixed false -x 512 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[7\] -fixed false -x 389 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[9\] -fixed false -x 93 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush\[0\] -fixed false -x 780 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_397 -fixed false -x 669 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_478 -fixed false -x 760 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[53\] -fixed false -x 574 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[2\] -fixed false -x 37 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_0_RNIQH3GK\[1\] -fixed false -x 716 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[16\] -fixed false -x 381 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO_0 -fixed false -x 871 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_14 -fixed false -x 847 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iIIl1\[0\] -fixed false -x 373 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0iO1 -fixed false -x 169 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_1 -fixed false -x 80 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_di_mux -fixed false -x 510 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_ac0_5 -fixed false -x 44 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[3\] -fixed false -x 508 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[12\] -fixed false -x 405 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[22\] -fixed false -x 450 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1300 -fixed false -x 704 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[21\] -fixed false -x 716 -y 118
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write29 -fixed false -x 460 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35\[6\] -fixed false -x 273 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_34\[2\] -fixed false -x 200 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo_3 -fixed false -x 276 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_11_0\[0\] -fixed false -x 868 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[33\] -fixed false -x 479 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[15\] -fixed false -x 352 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0\[2\] -fixed false -x 944 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OlOOo_0_a3_2 -fixed false -x 138 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un16_OilI1\[31\] -fixed false -x 237 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_retr_2 -fixed false -x 776 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_MTIME.un1_T_l_En_0_a2 -fixed false -x 503 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_68\[11\] -fixed false -x 224 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[29\] -fixed false -x 124 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[2\] -fixed false -x 163 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_1_0 -fixed false -x 644 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[2\] -fixed false -x 199 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_2\[0\] -fixed false -x 607 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_ready_reg_RNO -fixed false -x 780 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[5\] -fixed false -x 302 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[28\] -fixed false -x 486 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO_0 -fixed false -x 841 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_4_0 -fixed false -x 72 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m12 -fixed false -x 39 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[27\] -fixed false -x 940 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOiI1 -fixed false -x 373 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[2\] -fixed false -x 249 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[9\] -fixed false -x 406 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_8 -fixed false -x 421 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O0111 -fixed false -x 124 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[7\] -fixed false -x 791 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[1\] -fixed false -x 70 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13\[1\] -fixed false -x 769 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i10i1_RNO -fixed false -x 189 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/io001 -fixed false -x 52 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31_0 -fixed false -x 504 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c_RNI311RSS -fixed false -x 827 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[5\] -fixed false -x 338 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[9\] -fixed false -x 392 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[8\] -fixed false -x 444 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[26\] -fixed false -x 789 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[16\] -fixed false -x 761 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[19\] -fixed false -x 121 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1 -fixed false -x 182 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[0\] -fixed false -x 411 -y 187
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[3\] -fixed false -x 388 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[51\] -fixed false -x 971 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[30\] -fixed false -x 146 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[13\] -fixed false -x 134 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNICLOH11\[2\] -fixed false -x 103 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0\[1\] -fixed false -x 721 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[10\] -fixed false -x 117 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[0\] -fixed false -x 190 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[4\] -fixed false -x 356 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[10\] -fixed false -x 360 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[3\] -fixed false -x 523 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold\[2\] -fixed false -x 564 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_lsu_op_ex_pipe\[3\] -fixed false -x 763 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[28\] -fixed false -x 946 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[7\] -fixed false -x 903 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[7\] -fixed false -x 692 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m7 -fixed false -x 106 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_1\[9\] -fixed false -x 351 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[12\] -fixed false -x 946 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_1\[0\] -fixed false -x 294 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_6_0_a2_0\[1\] -fixed false -x 786 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI9SGBH\[0\] -fixed false -x 26 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_28 -fixed false -x 717 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l15 -fixed false -x 405 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[12\] -fixed false -x 945 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[5\] -fixed false -x 361 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[3\] -fixed false -x 79 -y 223
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ\[4\] -fixed false -x 499 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[10\] -fixed false -x 769 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel -fixed false -x 720 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2\[19\] -fixed false -x 120 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[17\] -fixed false -x 927 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[10\] -fixed false -x 238 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[6\] -fixed false -x 237 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z\[1\] -fixed false -x 543 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0_1_0\[0\] -fixed false -x 267 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[18\] -fixed false -x 642 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[5\] -fixed false -x 695 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[7\] -fixed false -x 839 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH9TQ8\[20\] -fixed false -x 670 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[3\] -fixed false -x 637 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_729 -fixed false -x 692 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[7\] -fixed false -x 573 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[1\] -fixed false -x 323 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[29\] -fixed false -x 940 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state135 -fixed false -x 515 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[6\] -fixed false -x 430 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_8 -fixed false -x 603 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_l_En_0_a2_RNIC89L7 -fixed false -x 507 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[0\] -fixed false -x 160 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_exception -fixed false -x 737 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[2\] -fixed false -x 391 -y 199
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNILICS8\[0\] -fixed false -x 2 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_655 -fixed false -x 700 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[4\] -fixed false -x 64 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[13\] -fixed false -x 92 -y 223
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[15\] -fixed false -x 226 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[3\] -fixed false -x 842 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex\[1\] -fixed false -x 775 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo -fixed false -x 276 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[0\] -fixed false -x 409 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[6\] -fixed false -x 447 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[28\] -fixed false -x 225 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[27\] -fixed false -x 910 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_289 -fixed false -x 742 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[9\] -fixed false -x 661 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[12\] -fixed false -x 357 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0\[5\] -fixed false -x 572 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[0\] -fixed false -x 343 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[13\] -fixed false -x 318 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1_2 -fixed false -x 294 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z\[1\] -fixed false -x 131 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0\[7\] -fixed false -x 107 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_142 -fixed false -x 669 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[12\] -fixed false -x 706 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[4\] -fixed false -x 435 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_RNO -fixed false -x 800 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel_7_f0 -fixed false -x 513 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_2 -fixed false -x 764 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[8\] -fixed false -x 768 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[7\] -fixed false -x 339 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[6\] -fixed false -x 268 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_61\[0\] -fixed false -x 966 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[16\] -fixed false -x 309 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a2\[2\] -fixed false -x 752 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[6\] -fixed false -x 440 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_6 -fixed false -x 232 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa -fixed false -x 504 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[0\] -fixed false -x 56 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[25\] -fixed false -x 852 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[7\] -fixed false -x 944 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m10 -fixed false -x 65 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oio11 -fixed false -x 334 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[5\] -fixed false -x 432 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO_2 -fixed false -x 761 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[24\] -fixed false -x 912 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.mdc_0 -fixed false -x 296 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1\[1\] -fixed false -x 85 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[9\] -fixed false -x 874 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3_0\[2\] -fixed false -x 118 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[2\] -fixed false -x 230 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[5\] -fixed false -x 808 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.IloIo -fixed false -x 491 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[20\] -fixed false -x 786 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1191 -fixed false -x 668 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1081 -fixed false -x 764 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_4\[0\] -fixed false -x 275 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[5\] -fixed false -x 943 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[0\] -fixed false -x 265 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_17 -fixed false -x 114 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[10\] -fixed false -x 794 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_541 -fixed false -x 644 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat13_RNI1RVGA -fixed false -x 574 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtm_resp_ready_RNO -fixed false -x 618 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a3\[0\] -fixed false -x 623 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1111 -fixed false -x 775 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_Oiol1 -fixed false -x 344 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_1\[9\] -fixed false -x 68 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[15\] -fixed false -x 819 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[2\] -fixed false -x 431 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[6\] -fixed false -x 393 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[10\] -fixed false -x 87 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[6\] -fixed false -x 518 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[4\] -fixed false -x 530 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_ld_addr_misalign_0 -fixed false -x 815 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lI0Oo_i_a2_0 -fixed false -x 120 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[19\] -fixed false -x 430 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[1\] -fixed false -x 40 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u\[9\] -fixed false -x 891 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[16\] -fixed false -x 799 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[15\] -fixed false -x 380 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m2 -fixed false -x 58 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oO0o1 -fixed false -x 95 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[20\] -fixed false -x 846 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_644 -fixed false -x 622 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[17\] -fixed false -x 691 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[16\] -fixed false -x 600 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01\[9\] -fixed false -x 175 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[34\] -fixed false -x 347 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[8\] -fixed false -x 211 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[0\] -fixed false -x 16 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_104 -fixed false -x 739 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[27\] -fixed false -x 701 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[10\] -fixed false -x 334 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_0_tz_RNIQSNOO\[20\] -fixed false -x 155 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[31\] -fixed false -x 427 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo\[6\] -fixed false -x 337 -y 150
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA27 -fixed false -x 490 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[21\] -fixed false -x 883 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1265 -fixed false -x 657 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_sn_m4 -fixed false -x 832 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked -fixed false -x 767 -y 151
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[12\] -fixed false -x 383 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0\[20\] -fixed false -x 137 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[20\] -fixed false -x 245 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n1 -fixed false -x 174 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10 -fixed false -x 39 -y 225
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_11_RNI7ATB8 -fixed false -x 831 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0\[1\] -fixed false -x 725 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv\[11\] -fixed false -x 724 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1176 -fixed false -x 764 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[5\] -fixed false -x 336 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_912 -fixed false -x 627 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1281 -fixed false -x 632 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loo11_1 -fixed false -x 387 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[22\] -fixed false -x 633 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[7\] -fixed false -x 197 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5\[3\] -fixed false -x 237 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[3\] -fixed false -x 543 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[22\] -fixed false -x 68 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[8\] -fixed false -x 853 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un52_Oi1O1\[20\] -fixed false -x 471 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1\[6\] -fixed false -x 304 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0\[1\] -fixed false -x 791 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[30\] -fixed false -x 849 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[16\] -fixed false -x 860 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[13\] -fixed false -x 945 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m246 -fixed false -x 275 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[2\] -fixed false -x 816 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[1\] -fixed false -x 273 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[22\] -fixed false -x 789 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_380 -fixed false -x 621 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0 -fixed false -x 677 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[22\] -fixed false -x 760 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un88_OilI1_0_a2_i -fixed false -x 357 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_RNO_0\[47\] -fixed false -x 906 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[8\] -fixed false -x 542 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[3\] -fixed false -x 380 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_737 -fixed false -x 645 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[3\] -fixed false -x 42 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_947 -fixed false -x 656 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1\[5\] -fixed false -x 129 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[3\] -fixed false -x 106 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[11\] -fixed false -x 232 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[12\] -fixed false -x 29 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_429 -fixed false -x 638 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[18\] -fixed false -x 535 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2_1\[3\] -fixed false -x 115 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[10\] -fixed false -x 240 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_2_0 -fixed false -x 822 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_0_2\[1\] -fixed false -x 633 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0\[0\] -fixed false -x 569 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[10\] -fixed false -x 294 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[12\] -fixed false -x 388 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii0o1 -fixed false -x 93 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_57 -fixed false -x 632 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[21\] -fixed false -x 210 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_0_sqmuxa_1 -fixed false -x 693 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_39 -fixed false -x 702 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0 -fixed false -x 88 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2 -fixed false -x 58 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[58\] -fixed false -x 541 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_921 -fixed false -x 705 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[11\] -fixed false -x 801 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[16\] -fixed false -x 117 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[21\] -fixed false -x 908 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/un1_iOI01_1_i -fixed false -x 322 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_RNO_0 -fixed false -x 833 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[4\] -fixed false -x 355 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_4 -fixed false -x 188 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[0\] -fixed false -x 99 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0 -fixed false -x 165 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[23\] -fixed false -x 458 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[6\] -fixed false -x 947 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1 -fixed false -x 464 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_7_RNIV8ASC -fixed false -x 107 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[28\] -fixed false -x 955 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_O1Ii1_1 -fixed false -x 177 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[4\] -fixed false -x 760 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4\[1\] -fixed false -x 708 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_868 -fixed false -x 680 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_cZ\[1\] -fixed false -x 810 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[7\] -fixed false -x 356 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_3 -fixed false -x 244 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_2_i_o2 -fixed false -x 736 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1 -fixed false -x 656 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[8\] -fixed false -x 755 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[5\] -fixed false -x 198 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_3_0 -fixed false -x 809 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[11\] -fixed false -x 331 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0\[15\] -fixed false -x 662 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_839 -fixed false -x 805 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[3\] -fixed false -x 28 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[13\] -fixed false -x 398 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m2\[1\] -fixed false -x 745 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[13\] -fixed false -x 564 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3_1\[16\] -fixed false -x 946 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[6\] -fixed false -x 169 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[7\] -fixed false -x 920 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[8\] -fixed false -x 822 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[2\] -fixed false -x 105 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_1\[0\] -fixed false -x 103 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[1\] -fixed false -x 43 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1\[7\] -fixed false -x 157 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[5\] -fixed false -x 400 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[7\] -fixed false -x 168 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[21\] -fixed false -x 932 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[2\] -fixed false -x 47 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo\[2\] -fixed false -x 102 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_8 -fixed false -x 676 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[15\] -fixed false -x 694 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111 -fixed false -x 395 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un29_ool01 -fixed false -x 52 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[9\] -fixed false -x 193 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[21\] -fixed false -x 462 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2 -fixed false -x 80 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[29\] -fixed false -x 741 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19 -fixed false -x 672 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[4\] -fixed false -x 390 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[22\] -fixed false -x 854 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[11\] -fixed false -x 370 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_185 -fixed false -x 693 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_a2_2\[28\] -fixed false -x 186 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[6\] -fixed false -x 840 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[4\] -fixed false -x 511 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[39\] -fixed false -x 526 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[26\] -fixed false -x 899 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[1\] -fixed false -x 828 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/un1_iOI01_1_i_0 -fixed false -x 317 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_RNIRNGTI\[0\] -fixed false -x 106 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[29\] -fixed false -x 634 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[6\] -fixed false -x 157 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un85_i11Io -fixed false -x 416 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[5\] -fixed false -x 864 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_u -fixed false -x 813 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[4\] -fixed false -x 732 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[11\] -fixed false -x 275 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[7\] -fixed false -x 245 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[29\] -fixed false -x 218 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111 -fixed false -x 126 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[11\] -fixed false -x 136 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_m6_0_a2_3 -fixed false -x 723 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO_0\[5\] -fixed false -x 118 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[4\] -fixed false -x 174 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[7\] -fixed false -x 142 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 376 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m57_1 -fixed false -x 69 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_442 -fixed false -x 656 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Io0I1 -fixed false -x 390 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[1\] -fixed false -x 381 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi019_0_a2 -fixed false -x 76 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[9\] -fixed false -x 71 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[27\] -fixed false -x 906 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[19\] -fixed false -x 631 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_o1Ii1_RNIM7MGF1\[0\] -fixed false -x 178 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[22\] -fixed false -x 472 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un9_l1Oo1_3 -fixed false -x 299 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loi01\[9\] -fixed false -x 45 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1_1086_0 -fixed false -x 97 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[22\] -fixed false -x 455 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_valid -fixed false -x 394 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state\[1\]\[1\] -fixed false -x 790 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[6\] -fixed false -x 200 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[25\] -fixed false -x 651 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[24\] -fixed false -x 546 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_a2_4\[28\] -fixed false -x 215 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII1118 -fixed false -x 128 -y 216
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[6\] -fixed false -x 501 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0\[31\] -fixed false -x 941 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOo11\[0\] -fixed false -x 120 -y 160
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i\[2\] -fixed false -x 527 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_13 -fixed false -x 633 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[12\] -fixed false -x 521 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1141 -fixed false -x 705 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo_RNI5SKTK -fixed false -x 242 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[12\] -fixed false -x 486 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0\[13\] -fixed false -x 166 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[5\] -fixed false -x 498 -y 151
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[1\] -fixed false -x 449 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[18\] -fixed false -x 462 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3\[7\] -fixed false -x 94 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[8\] -fixed false -x 697 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[2\] -fixed false -x 356 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[16\] -fixed false -x 431 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[30\] -fixed false -x 460 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[30\] -fixed false -x 957 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[20\] -fixed false -x 778 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[8\] -fixed false -x 696 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[3\] -fixed false -x 386 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[26\] -fixed false -x 471 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[12\] -fixed false -x 793 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[4\] -fixed false -x 496 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].un1_lIII110 -fixed false -x 477 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO_1 -fixed false -x 865 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0Ii1 -fixed false -x 175 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[26\] -fixed false -x 726 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo -fixed false -x 108 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[15\] -fixed false -x 358 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_42\[4\] -fixed false -x 492 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[3\] -fixed false -x 522 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[26\] -fixed false -x 885 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[0\] -fixed false -x 519 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_ex -fixed false -x 800 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[27\] -fixed false -x 422 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_14_RNIDG0C8 -fixed false -x 831 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[14\] -fixed false -x 433 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1289 -fixed false -x 621 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_o2\[4\] -fixed false -x 125 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_6\[2\] -fixed false -x 755 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[3\] -fixed false -x 813 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[24\] -fixed false -x 543 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[5\] -fixed false -x 272 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_261 -fixed false -x 705 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1284 -fixed false -x 692 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[9\] -fixed false -x 128 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOIi1 -fixed false -x 161 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[10\] -fixed false -x 429 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[9\] -fixed false -x 383 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int\[0\] -fixed false -x 773 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[12\] -fixed false -x 479 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[12\] -fixed false -x 354 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_73 -fixed false -x 763 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[2\] -fixed false -x 249 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[11\] -fixed false -x 137 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel_8 -fixed false -x 719 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un230_lIlo1 -fixed false -x 313 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[28\] -fixed false -x 478 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01\[2\] -fixed false -x 212 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[13\] -fixed false -x 713 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[5\] -fixed false -x 301 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0_1\[0\] -fixed false -x 920 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_2\[27\] -fixed false -x 720 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i1I11_2 -fixed false -x 300 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un91_ool01\[8\] -fixed false -x 190 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[31\] -fixed false -x 778 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[28\] -fixed false -x 458 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[11\] -fixed false -x 447 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOO11 -fixed false -x 42 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[2\] -fixed false -x 380 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[24\] -fixed false -x 837 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid -fixed false -x 774 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO_1 -fixed false -x 862 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_1\[0\] -fixed false -x 594 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_RNO\[2\] -fixed false -x 482 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIFK8GO\[24\] -fixed false -x 863 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[20\] -fixed false -x 882 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_3_RNO -fixed false -x 813 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_16_110_a2 -fixed false -x 461 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[16\] -fixed false -x 891 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[2\] -fixed false -x 763 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111\[2\] -fixed false -x 131 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[6\] -fixed false -x 86 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un8_lolIo -fixed false -x 21 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_RNO -fixed false -x 531 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[6\] -fixed false -x 781 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[9\] -fixed false -x 146 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_17 -fixed false -x 657 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[8\] -fixed false -x 822 -y 130
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/re_set -fixed false -x 389 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[14\] -fixed false -x 177 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[19\] -fixed false -x 259 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_163 -fixed false -x 718 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[0\] -fixed false -x 386 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo\[3\] -fixed false -x 148 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[16\] -fixed false -x 294 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[12\] -fixed false -x 143 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[33\] -fixed false -x 457 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[11\] -fixed false -x 40 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_2 -fixed false -x 392 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[3\] -fixed false -x 152 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[11\] -fixed false -x 127 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[20\] -fixed false -x 878 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[3\] -fixed false -x 193 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_878 -fixed false -x 643 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[17\] -fixed false -x 526 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_2_RNIBLOEA5 -fixed false -x 800 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_RNO\[47\] -fixed false -x 910 -y 186
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[6\] -fixed false -x 50 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[21\] -fixed false -x 656 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_835 -fixed false -x 679 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_7 -fixed false -x 42 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/IilI1 -fixed false -x 391 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[8\] -fixed false -x 429 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[35\] -fixed false -x 287 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[7\] -fixed false -x 837 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI1UT441 -fixed false -x 724 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNIS780A -fixed false -x 813 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[21\] -fixed false -x 791 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_253 -fixed false -x 615 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[11\] -fixed false -x 233 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_12_RNO -fixed false -x 374 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[6\] -fixed false -x 853 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_150 -fixed false -x 701 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[1\] -fixed false -x 516 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO_1 -fixed false -x 847 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[4\] -fixed false -x 731 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[9\] -fixed false -x 117 -y 187
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO\[3\] -fixed false -x 422 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[49\] -fixed false -x 929 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[6\] -fixed false -x 727 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[4\] -fixed false -x 709 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[4\] -fixed false -x 837 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[17\] -fixed false -x 322 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[15\] -fixed false -x 133 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[27\] -fixed false -x 907 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_707 -fixed false -x 595 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0_iv_1\[0\] -fixed false -x 717 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[24\] -fixed false -x 947 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[26\] -fixed false -x 391 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un141_I1Oi1_1 -fixed false -x 56 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[22\] -fixed false -x 920 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[21\] -fixed false -x 459 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[30\] -fixed false -x 471 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[2\] -fixed false -x 388 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[31\] -fixed false -x 477 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_1\[0\] -fixed false -x 119 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/fifo_valid_RNI8NFDI -fixed false -x 394 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_341 -fixed false -x 753 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[14\] -fixed false -x 125 -y 204
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv\[3\] -fixed false -x 502 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_346 -fixed false -x 666 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0\[22\] -fixed false -x 269 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_1_0 -fixed false -x 68 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_could_commit_0_RNIQPUS01 -fixed false -x 775 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_55 -fixed false -x 632 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[18\] -fixed false -x 970 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[4\] -fixed false -x 496 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[18\] -fixed false -x 826 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1\[21\] -fixed false -x 452 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5\[2\] -fixed false -x 633 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[24\] -fixed false -x 669 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[31\] -fixed false -x 778 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/IilI1_RNO -fixed false -x 182 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[23\] -fixed false -x 935 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24\[8\] -fixed false -x 293 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_0\[0\] -fixed false -x 58 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[9\] -fixed false -x 502 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_IlOI18_1 -fixed false -x 205 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ooOl1 -fixed false -x 437 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_O1Ii1_5 -fixed false -x 279 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[5\] -fixed false -x 305 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[6\] -fixed false -x 625 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIll1 -fixed false -x 523 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[8\] -fixed false -x 123 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[4\] -fixed false -x 458 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[5\] -fixed false -x 524 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[16\] -fixed false -x 300 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[5\] -fixed false -x 420 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34\[0\] -fixed false -x 286 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_809 -fixed false -x 668 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1 -fixed false -x 176 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_ft_1 -fixed false -x 369 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_a3_0_RNIPADTFT -fixed false -x 813 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[30\] -fixed false -x 884 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[19\] -fixed false -x 394 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[0\] -fixed false -x 523 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01\[2\] -fixed false -x 215 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[11\] -fixed false -x 489 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[26\] -fixed false -x 781 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[0\] -fixed false -x 57 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[7\] -fixed false -x 72 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_0 -fixed false -x 60 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[16\] -fixed false -x 378 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m6_0 -fixed false -x 113 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_OOio1_2 -fixed false -x 19 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[2\] -fixed false -x 167 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_319 -fixed false -x 620 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[11\] -fixed false -x 95 -y 190
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0 -fixed false -x 0 -y 377
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1023 -fixed false -x 668 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un26_sba_req_rd_byte_en_int_i_o3 -fixed false -x 737 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[21\] -fixed false -x 549 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[10\] -fixed false -x 313 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[22\] -fixed false -x 921 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un96_OOOI1\[2\] -fixed false -x 399 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[28\] -fixed false -x 413 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124_1 -fixed false -x 650 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[5\] -fixed false -x 199 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43\[0\] -fixed false -x 285 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_2 -fixed false -x 236 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[2\] -fixed false -x 51 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[17\] -fixed false -x 358 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI5VEGI\[0\] -fixed false -x 545 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[11\] -fixed false -x 766 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13\[3\] -fixed false -x 792 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[25\] -fixed false -x 140 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[18\] -fixed false -x 680 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un2_Oo001_2_1 -fixed false -x 87 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1\[0\] -fixed false -x 489 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[29\] -fixed false -x 428 -y 169
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[15\] -fixed false -x 392 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iloi1 -fixed false -x 275 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[22\] -fixed false -x 719 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_I1Oi1 -fixed false -x 40 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[13\] -fixed false -x 903 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[6\] -fixed false -x 80 -y 157
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNITHIN9 -fixed false -x 397 -y 234
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct -fixed false -x 558 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loII1_cZ -fixed false -x 295 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_271 -fixed false -x 621 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[24\] -fixed false -x 541 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[5\] -fixed false -x 401 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[29\] -fixed false -x 834 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_5 -fixed false -x 535 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[10\] -fixed false -x 141 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[11\] -fixed false -x 37 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNISSBTF\[5\] -fixed false -x 808 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_395 -fixed false -x 642 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[27\] -fixed false -x 625 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2\[2\] -fixed false -x 690 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[8\] -fixed false -x 496 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m49 -fixed false -x 33 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[8\] -fixed false -x 760 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m5 -fixed false -x 117 -y 198
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3 -fixed false -x 1153 -y 162
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[3\] -fixed false -x 773 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[6\] -fixed false -x 292 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_d\[0\]_0_sqmuxa -fixed false -x 558 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7A984\[12\] -fixed false -x 953 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_19 -fixed false -x 842 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[28\] -fixed false -x 907 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_6 -fixed false -x 112 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[15\] -fixed false -x 908 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[30\] -fixed false -x 477 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[6\] -fixed false -x 160 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto3_0 -fixed false -x 143 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_7 -fixed false -x 187 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_i\[0\] -fixed false -x 739 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[8\] -fixed false -x 413 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.IloIo -fixed false -x 366 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[2\] -fixed false -x 395 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[16\] -fixed false -x 606 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[24\] -fixed false -x 114 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3\[0\] -fixed false -x 143 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[21\] -fixed false -x 381 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_0\[2\] -fixed false -x 666 -y 144
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[5\] -fixed false -x 379 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[0\] -fixed false -x 464 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[24\] -fixed false -x 971 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_3 -fixed false -x 384 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[14\] -fixed false -x 253 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_173 -fixed false -x 800 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01\[2\] -fixed false -x 187 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[19\] -fixed false -x 931 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[12\] -fixed false -x 459 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[0\] -fixed false -x 87 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[0\] -fixed false -x 778 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_718 -fixed false -x 668 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[29\] -fixed false -x 410 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_0\[1\] -fixed false -x 784 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[3\] -fixed false -x 322 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_662 -fixed false -x 775 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_24 -fixed false -x 620 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[31\] -fixed false -x 340 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[9\] -fixed false -x 559 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[4\] -fixed false -x 285 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed\[2\] -fixed false -x 644 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[10\] -fixed false -x 619 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_567 -fixed false -x 763 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0\[1\] -fixed false -x 101 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[1\] -fixed false -x 114 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOi11_0 -fixed false -x 348 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNIP480A -fixed false -x 801 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[20\] -fixed false -x 848 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[2\] -fixed false -x 177 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un67_OOOI1\[2\] -fixed false -x 284 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[5\] -fixed false -x 190 -y 210
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[21\].BUFD_BLK -fixed false -x 508 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_354 -fixed false -x 668 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[31\] -fixed false -x 516 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_5_ac0_3 -fixed false -x 67 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[2\] -fixed false -x 758 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[22\] -fixed false -x 560 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state\[2\] -fixed false -x 786 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[2\] -fixed false -x 85 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[17\] -fixed false -x 862 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IOoOo -fixed false -x 229 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[17\] -fixed false -x 703 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_0 -fixed false -x 781 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[10\] -fixed false -x 252 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[31\] -fixed false -x 670 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[10\] -fixed false -x 405 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[0\] -fixed false -x 223 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo\[0\] -fixed false -x 292 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_RNIGM24V2 -fixed false -x 796 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_2 -fixed false -x 472 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places57 -fixed false -x 864 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[19\] -fixed false -x 464 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[3\] -fixed false -x 520 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5\[6\] -fixed false -x 488 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[4\] -fixed false -x 422 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[3\] -fixed false -x 285 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[7\] -fixed false -x 850 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[5\] -fixed false -x 246 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[4\] -fixed false -x 648 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_437 -fixed false -x 708 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0_1_0\[0\] -fixed false -x 244 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_5 -fixed false -x 728 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_c2 -fixed false -x 169 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[4\] -fixed false -x 644 -y 118
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_parity -fixed false -x 445 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0\[3\] -fixed false -x 43 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[4\] -fixed false -x 386 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[13\] -fixed false -x 921 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[4\] -fixed false -x 69 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0o11 -fixed false -x 359 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12\[0\] -fixed false -x 284 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[1\] -fixed false -x 431 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[11\] -fixed false -x 425 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m57 -fixed false -x 68 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[30\] -fixed false -x 873 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[25\] -fixed false -x 875 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff -fixed false -x 775 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OIoOo_1 -fixed false -x 164 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[0\] -fixed false -x 313 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[3\] -fixed false -x 124 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/IilI1 -fixed false -x 464 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[5\] -fixed false -x 453 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_complete_qual_0_1 -fixed false -x 641 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[12\] -fixed false -x 778 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_15 -fixed false -x 753 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122_1 -fixed false -x 661 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[3\] -fixed false -x 191 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo\[0\] -fixed false -x 386 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[2\] -fixed false -x 569 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_2_sqmuxa_i -fixed false -x 780 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv -fixed false -x 703 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKX1\[0\] -fixed false -x 729 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_9 -fixed false -x 746 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[14\] -fixed false -x 57 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[15\] -fixed false -x 605 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[12\] -fixed false -x 850 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1_cZ\[18\] -fixed false -x 433 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[23\] -fixed false -x 730 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[7\] -fixed false -x 518 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[1\] -fixed false -x 441 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[29\] -fixed false -x 675 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[11\] -fixed false -x 855 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_805 -fixed false -x 774 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3\[1\] -fixed false -x 508 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_1_sqmuxa_i_0_m2 -fixed false -x 620 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0\[0\] -fixed false -x 919 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[1\] -fixed false -x 873 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un10_mul_mp -fixed false -x 814 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[27\] -fixed false -x 464 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[26\] -fixed false -x 768 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[3\] -fixed false -x 289 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[6\] -fixed false -x 754 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[9\] -fixed false -x 724 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_817 -fixed false -x 620 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[2\] -fixed false -x 556 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[9\] -fixed false -x 366 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[5\] -fixed false -x 825 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv\[6\] -fixed false -x 753 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_a3\[27\] -fixed false -x 835 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[5\] -fixed false -x 700 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[8\] -fixed false -x 131 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x2\[2\] -fixed false -x 117 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[3\] -fixed false -x 351 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[27\] -fixed false -x 892 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35\[5\] -fixed false -x 272 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[3\] -fixed false -x 425 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[1\] -fixed false -x 425 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19_1_0 -fixed false -x 708 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_17_0_RNO -fixed false -x 826 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIFLM4C\[8\] -fixed false -x 666 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[4\] -fixed false -x 870 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[3\] -fixed false -x 123 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_925 -fixed false -x 652 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[7\] -fixed false -x 212 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[4\] -fixed false -x 457 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[2\] -fixed false -x 366 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[12\] -fixed false -x 112 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.l0li0 -fixed false -x 368 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[5\] -fixed false -x 166 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[2\] -fixed false -x 548 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.N_13_i -fixed false -x 62 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[43\] -fixed false -x 917 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26\[1\] -fixed false -x 273 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNICO6H04\[0\] -fixed false -x 620 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[12\] -fixed false -x 462 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[4\] -fixed false -x 267 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[5\] -fixed false -x 133 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_RNIP78KK -fixed false -x 569 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[32\] -fixed false -x 445 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[10\] -fixed false -x 914 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[7\] -fixed false -x 53 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[26\] -fixed false -x 825 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[35\] -fixed false -x 484 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5\[1\] -fixed false -x 622 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0 -fixed false -x 703 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_8_1 -fixed false -x 669 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[2\] -fixed false -x 324 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[7\] -fixed false -x 371 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[35\] -fixed false -x 235 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_520 -fixed false -x 728 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[9\] -fixed false -x 154 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[7\] -fixed false -x 436 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo\[0\] -fixed false -x 14 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO\[2\] -fixed false -x 104 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[19\] -fixed false -x 445 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[12\] -fixed false -x 289 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[17\] -fixed false -x 896 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loo11 -fixed false -x 385 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_187 -fixed false -x 655 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[28\] -fixed false -x 754 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[26\] -fixed false -x 748 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo\[2\] -fixed false -x 274 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[12\] -fixed false -x 347 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[9\] -fixed false -x 704 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[4\] -fixed false -x 355 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[4\] -fixed false -x 125 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_o2\[2\] -fixed false -x 200 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[22\] -fixed false -x 60 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/OloIo -fixed false -x 491 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[31\] -fixed false -x 293 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOii1 -fixed false -x 144 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[21\] -fixed false -x 875 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l1Ol1_1 -fixed false -x 384 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[2\] -fixed false -x 432 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[50\] -fixed false -x 925 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[11\] -fixed false -x 868 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[3\] -fixed false -x 107 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_sx_RNIL5B4O -fixed false -x 813 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[1\] -fixed false -x 211 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[6\] -fixed false -x 763 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[7\] -fixed false -x 122 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un5_ool01 -fixed false -x 203 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122 -fixed false -x 668 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto9 -fixed false -x 153 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOo01 -fixed false -x 122 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13\[0\] -fixed false -x 801 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[8\] -fixed false -x 970 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_672 -fixed false -x 682 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_sn_m4 -fixed false -x 803 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 470 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIAEA84\[24\] -fixed false -x 957 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[13\] -fixed false -x 58 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[11\] -fixed false -x 305 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto4_1 -fixed false -x 193 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[4\] -fixed false -x 349 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[3\] -fixed false -x 384 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_577 -fixed false -x 620 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[21\] -fixed false -x 459 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[5\] -fixed false -x 498 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[3\] -fixed false -x 734 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[52\] -fixed false -x 892 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOl11 -fixed false -x 299 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[6\] -fixed false -x 828 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[4\] -fixed false -x 76 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[7\] -fixed false -x 563 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[8\] -fixed false -x 497 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O1Ol1 -fixed false -x 436 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/un1_Ioli0_1_0 -fixed false -x 298 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[9\] -fixed false -x 174 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_8 -fixed false -x 81 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 478 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[23\] -fixed false -x 129 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_lOoi1 -fixed false -x 205 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_m_env_call_retr -fixed false -x 746 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[9\] -fixed false -x 744 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[5\] -fixed false -x 402 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[21\] -fixed false -x 540 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[16\] -fixed false -x 874 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[26\] -fixed false -x 329 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_191 -fixed false -x 669 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[13\] -fixed false -x 311 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[6\] -fixed false -x 335 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[19\] -fixed false -x 390 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_784 -fixed false -x 798 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1 -fixed false -x 501 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0s2 -fixed false -x 503 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[2\] -fixed false -x 73 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m227 -fixed false -x 261 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_0\[1\] -fixed false -x 261 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[30\] -fixed false -x 558 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_2_0_0_o2 -fixed false -x 183 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[13\] -fixed false -x 92 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[3\] -fixed false -x 366 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[16\] -fixed false -x 769 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[7\] -fixed false -x 790 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[0\] -fixed false -x 546 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[15\] -fixed false -x 461 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[7\] -fixed false -x 370 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38 -fixed false -x 716 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[2\] -fixed false -x 490 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1\[7\] -fixed false -x 80 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[3\] -fixed false -x 345 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[16\] -fixed false -x 463 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_2 -fixed false -x 217 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_392 -fixed false -x 730 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_3_tz -fixed false -x 786 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[11\] -fixed false -x 325 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[8\] -fixed false -x 209 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_4 -fixed false -x 107 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un99_I1Oi1_1 -fixed false -x 17 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO_1 -fixed false -x 842 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[21\] -fixed false -x 875 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand0_mux_sel_ex\[0\] -fixed false -x 781 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[28\] -fixed false -x 958 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[33\].BUFD_BLK -fixed false -x 549 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_919 -fixed false -x 631 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[10\] -fixed false -x 847 -y 136
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[4\] -fixed false -x 70 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[38\] -fixed false -x 388 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[23\] -fixed false -x 893 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[1\] -fixed false -x 158 -y 178
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[27\] -fixed false -x 416 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr\[1\] -fixed false -x 783 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[7\] -fixed false -x 854 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23_sx -fixed false -x 804 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_1\[0\] -fixed false -x 630 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1\[13\] -fixed false -x 74 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[25\] -fixed false -x 22 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout_RNO -fixed false -x 786 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_34\[9\] -fixed false -x 286 -y 177
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_6 -fixed false -x 437 -y 3
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[6\] -fixed false -x 495 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[0\] -fixed false -x 144 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[6\] -fixed false -x 423 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I11l1 -fixed false -x 385 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1 -fixed false -x 481 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3\[6\] -fixed false -x 91 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol17 -fixed false -x 356 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[31\] -fixed false -x 667 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0\[6\] -fixed false -x 565 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[3\] -fixed false -x 60 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[17\] -fixed false -x 429 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[19\] -fixed false -x 876 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_994 -fixed false -x 608 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO\[0\] -fixed false -x 752 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[11\] -fixed false -x 697 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[4\] -fixed false -x 349 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0iOo -fixed false -x 109 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[15\] -fixed false -x 668 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[3\] -fixed false -x 725 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[11\] -fixed false -x 401 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo -fixed false -x 340 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[8\] -fixed false -x 788 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_0 -fixed false -x 104 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a3_0 -fixed false -x 633 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[9\] -fixed false -x 700 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[21\].BUFD_BLK -fixed false -x 491 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[27\] -fixed false -x 151 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_sel_iv_0 -fixed false -x 719 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1062 -fixed false -x 619 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[1\] -fixed false -x 405 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIlIo -fixed false -x 245 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 479 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[4\] -fixed false -x 128 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[12\] -fixed false -x 829 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_407 -fixed false -x 667 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[14\] -fixed false -x 876 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[15\] -fixed false -x 693 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8\[7\] -fixed false -x 753 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1295 -fixed false -x 651 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[33\] -fixed false -x 335 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val\[2\] -fixed false -x 772 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[11\] -fixed false -x 933 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[4\] -fixed false -x 220 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[1\] -fixed false -x 292 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[6\] -fixed false -x 773 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1215 -fixed false -x 713 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[15\] -fixed false -x 24 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[46\] -fixed false -x 565 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[2\] -fixed false -x 399 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[5\] -fixed false -x 526 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI9SGBH_0\[0\] -fixed false -x 28 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[0\] -fixed false -x 84 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[20\] -fixed false -x 755 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[12\] -fixed false -x 272 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[1\] -fixed false -x 146 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_lOOl1 -fixed false -x 404 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNIB4J0C\[10\] -fixed false -x 861 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[8\] -fixed false -x 709 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_5_u -fixed false -x 537 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[19\] -fixed false -x 86 -y 183
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[2\] -fixed false -x 490 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[12\].BUFD_BLK -fixed false -x 490 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[13\] -fixed false -x 776 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_shift_op_complete_ex -fixed false -x 790 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO_1 -fixed false -x 773 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1 -fixed false -x 188 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[23\] -fixed false -x 465 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[3\] -fixed false -x 410 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNIFA4LE\[4\] -fixed false -x 793 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOIi1 -fixed false -x 164 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_branch_cond_2\[0\] -fixed false -x 674 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un11_i0lo1\[4\] -fixed false -x 285 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[0\] -fixed false -x 819 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[4\] -fixed false -x 299 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[13\] -fixed false -x 379 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_o2 -fixed false -x 700 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_PADDR_3 -fixed false -x 392 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[8\] -fixed false -x 922 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[6\] -fixed false -x 107 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OlOOo_0_a3 -fixed false -x 121 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4 -fixed false -x 754 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_683 -fixed false -x 691 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[2\] -fixed false -x 315 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIBIAGO\[31\] -fixed false -x 866 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_s -fixed false -x 812 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_a3 -fixed false -x 693 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[7\] -fixed false -x 713 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[9\] -fixed false -x 513 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[8\] -fixed false -x 505 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[14\] -fixed false -x 498 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[12\] -fixed false -x 80 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto3_0_RNIGLV5B1 -fixed false -x 168 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[28\] -fixed false -x 674 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m4 -fixed false -x 687 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[25\] -fixed false -x 896 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIKVKJ31 -fixed false -x 765 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto4 -fixed false -x 142 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioi11 -fixed false -x 309 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_0 -fixed false -x 658 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo\[0\] -fixed false -x 389 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_fenci -fixed false -x 799 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 477 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[27\] -fixed false -x 945 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17_1_1 -fixed false -x 673 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[3\] -fixed false -x 497 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m6_e -fixed false -x 798 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[14\] -fixed false -x 370 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_21\[22\] -fixed false -x 262 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[0\] -fixed false -x 374 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[12\] -fixed false -x 574 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.un2_haltreq_debug_enter_taken -fixed false -x 772 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/gen_bit_reset.state_val\[0\] -fixed false -x 788 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_1 -fixed false -x 148 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[2\] -fixed false -x 404 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[17\] -fixed false -x 898 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI8EFAU -fixed false -x 20 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[10\] -fixed false -x 631 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dcsr_debugger_wr_sel_1 -fixed false -x 718 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OO1i1 -fixed false -x 187 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[23\] -fixed false -x 454 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNID63E9\[10\] -fixed false -x 80 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[9\] -fixed false -x 46 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv_0\[10\] -fixed false -x 710 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1_RNIGPMR83 -fixed false -x 785 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/un1_iOI01_1_i_0 -fixed false -x 222 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2\[4\] -fixed false -x 294 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[12\] -fixed false -x 525 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[7\] -fixed false -x 781 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4927_2_0 -fixed false -x 624 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[0\] -fixed false -x 629 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[23\] -fixed false -x 837 -y 132
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ\[2\] -fixed false -x 511 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2129 -fixed false -x 662 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[8\] -fixed false -x 316 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_a2_0 -fixed false -x 676 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_valid -fixed false -x 761 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[19\] -fixed false -x 708 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 370 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_8_0_RNO -fixed false -x 800 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[15\] -fixed false -x 968 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[19\] -fixed false -x 350 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[22\] -fixed false -x 932 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err_12_iv -fixed false -x 468 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[8\] -fixed false -x 285 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[10\] -fixed false -x 405 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4_RNIL4ELG -fixed false -x 746 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_416 -fixed false -x 729 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_3 -fixed false -x 303 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid34 -fixed false -x 862 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_14_0_RNO -fixed false -x 825 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1 -fixed false -x 118 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[3\] -fixed false -x 519 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[31\] -fixed false -x 942 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[4\] -fixed false -x 379 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001\[3\] -fixed false -x 80 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[3\] -fixed false -x 167 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_ex_retr.ex_retr_pipe_trigger_retr\[0\] -fixed false -x 779 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1\[34\] -fixed false -x 473 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[10\] -fixed false -x 154 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[11\] -fixed false -x 922 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[19\] -fixed false -x 778 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[40\] -fixed false -x 629 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[14\] -fixed false -x 225 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[17\] -fixed false -x 322 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex\[3\] -fixed false -x 726 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[22\] -fixed false -x 659 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[23\] -fixed false -x 897 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[23\] -fixed false -x 818 -y 123
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt_RNIBKVI3\[0\] -fixed false -x 14 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[4\] -fixed false -x 166 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un16_I1Oi1_1 -fixed false -x 56 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[32\] -fixed false -x 550 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[17\] -fixed false -x 423 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv_RNO\[4\] -fixed false -x 499 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_0_1\[0\] -fixed false -x 138 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[2\] -fixed false -x 432 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q\[3\] -fixed false -x 500 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_q_1.CO2 -fixed false -x 506 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[4\] -fixed false -x 651 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO\[20\] -fixed false -x 187 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851_2 -fixed false -x 610 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo\[0\] -fixed false -x 363 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[1\] -fixed false -x 67 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_933 -fixed false -x 693 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26\[0\] -fixed false -x 272 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[19\] -fixed false -x 630 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[7\] -fixed false -x 380 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[11\] -fixed false -x 858 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[22\] -fixed false -x 909 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[22\] -fixed false -x 552 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3\[6\] -fixed false -x 957 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[17\] -fixed false -x 695 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state\[1\]\[3\] -fixed false -x 787 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a3_2 -fixed false -x 643 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1i01_0_o2 -fixed false -x 97 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 369 -y 190
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[28\] -fixed false -x 413 -y 244
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[0\] -fixed false -x 469 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[1\] -fixed false -x 121 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[7\] -fixed false -x 114 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30_2\[31\] -fixed false -x 933 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val\[0\] -fixed false -x 564 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[3\] -fixed false -x 898 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[28\] -fixed false -x 458 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[5\] -fixed false -x 466 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[9\] -fixed false -x 703 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[6\] -fixed false -x 445 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[16\] -fixed false -x 778 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[4\] -fixed false -x 81 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[2\] -fixed false -x 225 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_4 -fixed false -x 212 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[4\] -fixed false -x 437 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[1\] -fixed false -x 570 -y 148
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_RNO -fixed false -x 552 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[28\] -fixed false -x 932 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[4\] -fixed false -x 387 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_3\[0\] -fixed false -x 36 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_594 -fixed false -x 678 -y 174
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_1\[0\] -fixed false -x 751 -y 4
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0\[0\] -fixed false -x 41 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[4\] -fixed false -x 349 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1oo1 -fixed false -x 74 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto15_1 -fixed false -x 188 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[29\] -fixed false -x 627 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_81\[11\] -fixed false -x 301 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[8\] -fixed false -x 200 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[54\] -fixed false -x 909 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[7\] -fixed false -x 87 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[0\] -fixed false -x 422 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_0\[8\] -fixed false -x 157 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_0 -fixed false -x 824 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[22\] -fixed false -x 561 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[4\] -fixed false -x 153 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[3\] -fixed false -x 237 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[27\] -fixed false -x 423 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[17\] -fixed false -x 271 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1245 -fixed false -x 643 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[1\] -fixed false -x 287 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[0\] -fixed false -x 68 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[18\] -fixed false -x 911 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[23\] -fixed false -x 766 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_15_0_RNO -fixed false -x 806 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_1_RNO -fixed false -x 801 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[17\] -fixed false -x 690 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[5\] -fixed false -x 436 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[12\] -fixed false -x 32 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[6\] -fixed false -x 76 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un21_gpr_rd_rs2_completing_ex -fixed false -x 717 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[14\] -fixed false -x 346 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[15\] -fixed false -x 413 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel7 -fixed false -x 519 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[25\] -fixed false -x 696 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[6\] -fixed false -x 352 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[17\] -fixed false -x 515 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un59_OOOI1\[10\] -fixed false -x 439 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto2_0_RNI7C1QFK -fixed false -x 827 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[3\] -fixed false -x 853 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[22\] -fixed false -x 671 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[30\] -fixed false -x 934 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I0Ol1 -fixed false -x 452 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[16\] -fixed false -x 88 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_rd_1_tz -fixed false -x 794 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0\[0\] -fixed false -x 87 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[26\] -fixed false -x 651 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[5\] -fixed false -x 695 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[0\] -fixed false -x 65 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel\[4\] -fixed false -x 549 -y 145
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_ns_0_0\[0\] -fixed false -x 9 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[13\] -fixed false -x 707 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[27\] -fixed false -x 921 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[11\] -fixed false -x 370 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo -fixed false -x 267 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[26\] -fixed false -x 445 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt\[1\] -fixed false -x 556 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[5\] -fixed false -x 374 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[4\] -fixed false -x 308 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_559 -fixed false -x 632 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_m3 -fixed false -x 747 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNICIUT5 -fixed false -x 339 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iO0l1\[0\] -fixed false -x 445 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_req_count_i -fixed false -x 755 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write_8.m5_1_0 -fixed false -x 459 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[18\] -fixed false -x 842 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[1\] -fixed false -x 416 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1_4 -fixed false -x 502 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5_0\[0\] -fixed false -x 714 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[36\] -fixed false -x 379 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[20\] -fixed false -x 451 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[4\] -fixed false -x 868 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[12\] -fixed false -x 417 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[24\] -fixed false -x 342 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[13\] -fixed false -x 290 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[25\] -fixed false -x 858 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_182 -fixed false -x 751 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[54\] -fixed false -x 573 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/txrdy_int_1_sqmuxa_i -fixed false -x 451 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_empty_0_a2 -fixed false -x 633 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[0\] -fixed false -x 637 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[8\] -fixed false -x 74 -y 160
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i_o2 -fixed false -x 21 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13 -fixed false -x 636 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4919_1 -fixed false -x 619 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[2\] -fixed false -x 354 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l00o1 -fixed false -x 116 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_rd_ptr\[0\] -fixed false -x 792 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[1\] -fixed false -x 62 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIl11 -fixed false -x 285 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[9\] -fixed false -x 406 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[6\] -fixed false -x 149 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[21\] -fixed false -x 433 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_9\[0\] -fixed false -x 810 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un11_ool01 -fixed false -x 53 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[7\] -fixed false -x 405 -y 153
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_sqmuxa -fixed false -x 68 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[10\] -fixed false -x 403 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[1\] -fixed false -x 352 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[13\] -fixed false -x 862 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[9\] -fixed false -x 609 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[19\] -fixed false -x 602 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIiOo -fixed false -x 144 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1031 -fixed false -x 619 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa -fixed false -x 512 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[10\] -fixed false -x 42 -y 235
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[5\].BUFD_BLK -fixed false -x 538 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[9\] -fixed false -x 406 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_581 -fixed false -x 654 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[7\] -fixed false -x 621 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q\[0\] -fixed false -x 575 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1l1_u -fixed false -x 447 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[1\] -fixed false -x 768 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[12\] -fixed false -x 707 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[9\] -fixed false -x 383 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIL72R7\[11\] -fixed false -x 84 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_a2_2\[3\] -fixed false -x 751 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[4\] -fixed false -x 234 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1 -fixed false -x 435 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[28\] -fixed false -x 945 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[12\] -fixed false -x 417 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo_11 -fixed false -x 101 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[10\] -fixed false -x 372 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3\[4\] -fixed false -x 573 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1 -fixed false -x 816 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/haltreq_debug_enter_taken -fixed false -x 771 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[25\] -fixed false -x 609 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNI73I4J\[10\] -fixed false -x 480 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[9\] -fixed false -x 287 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m54 -fixed false -x 283 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[29\] -fixed false -x 418 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[0\] -fixed false -x 299 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1_4 -fixed false -x 72 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[31\] -fixed false -x 895 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[18\] -fixed false -x 472 -y 195
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_code_upd -fixed false -x 4 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[16\] -fixed false -x 849 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i\[0\] -fixed false -x 599 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[15\] -fixed false -x 877 -y 138
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[12\] -fixed false -x 558 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[24\] -fixed false -x 680 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io\[2\] -fixed false -x 402 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNIE6MPA -fixed false -x 185 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[3\] -fixed false -x 83 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_gpr_rs2_rd_data_valid_5 -fixed false -x 759 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex\[2\] -fixed false -x 792 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_684 -fixed false -x 727 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[1\] -fixed false -x 754 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[12\] -fixed false -x 424 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[13\] -fixed false -x 464 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_16_RNIHK2C8 -fixed false -x 813 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[20\] -fixed false -x 766 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_2_0_0_o2_0 -fixed false -x 202 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[6\] -fixed false -x 261 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i10l1\[0\] -fixed false -x 452 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[9\] -fixed false -x 640 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lloOo -fixed false -x 158 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[8\] -fixed false -x 213 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[12\] -fixed false -x 944 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1231 -fixed false -x 712 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[30\] -fixed false -x 687 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[4\] -fixed false -x 196 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1l11 -fixed false -x 243 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_a2_RNICGGQF\[4\] -fixed false -x 698 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001\[1\] -fixed false -x 76 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1_RNO -fixed false -x 70 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[3\] -fixed false -x 678 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_593 -fixed false -x 657 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[27\] -fixed false -x 635 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[28\] -fixed false -x 815 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/trigger_debug_enter_taken -fixed false -x 779 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[21\] -fixed false -x 864 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[24\] -fixed false -x 953 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[21\] -fixed false -x 658 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[16\] -fixed false -x 321 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv\[0\] -fixed false -x 817 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[9\] -fixed false -x 328 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[23\] -fixed false -x 145 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[23\] -fixed false -x 807 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13\[0\] -fixed false -x 773 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[4\] -fixed false -x 180 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[20\] -fixed false -x 644 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_13\[22\] -fixed false -x 261 -y 213
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b\[1\] -fixed false -x 39 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[10\] -fixed false -x 383 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u_2\[9\] -fixed false -x 897 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[26\] -fixed false -x 632 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[24\] -fixed false -x 965 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_2\[3\] -fixed false -x 535 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[19\] -fixed false -x 643 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[13\] -fixed false -x 281 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[26\] -fixed false -x 459 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[6\] -fixed false -x 70 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[30\].BUFD_BLK -fixed false -x 511 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[22\] -fixed false -x 391 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un22_OIoO1 -fixed false -x 59 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_exu_mux_result27_1 -fixed false -x 757 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_987 -fixed false -x 607 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[7\] -fixed false -x 96 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_922 -fixed false -x 573 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[1\] -fixed false -x 158 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[1\] -fixed false -x 160 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_1\[2\] -fixed false -x 718 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[24\] -fixed false -x 931 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_755 -fixed false -x 705 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIU7FO8 -fixed false -x 194 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[0\] -fixed false -x 283 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_535 -fixed false -x 700 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0\[8\] -fixed false -x 257 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[10\] -fixed false -x 743 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[27\] -fixed false -x 770 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3_5 -fixed false -x 441 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[13\] -fixed false -x 485 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_N_11_mux_i_N_6L11 -fixed false -x 793 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[22\] -fixed false -x 409 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[1\] -fixed false -x 809 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o11I1 -fixed false -x 439 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[4\] -fixed false -x 947 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_i0iIo -fixed false -x 439 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2124_1 -fixed false -x 646 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_4 -fixed false -x 663 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[1\] -fixed false -x 898 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_822_i -fixed false -x 261 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[28\] -fixed false -x 443 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_11 -fixed false -x 566 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[8\] -fixed false -x 396 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[6\] -fixed false -x 82 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[3\] -fixed false -x 327 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1_N_2L1 -fixed false -x 815 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[5\] -fixed false -x 404 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un17_start_div -fixed false -x 851 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[60\] -fixed false -x 592 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack_RNI8QQ8V -fixed false -x 887 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_2 -fixed false -x 496 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.g0 -fixed false -x 779 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864 -fixed false -x 1152 -y 162
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1181 -fixed false -x 667 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR\[1\] -fixed false -x 564 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[18\] -fixed false -x 848 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIMDE88\[10\] -fixed false -x 94 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_1 -fixed false -x 178 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[8\] -fixed false -x 298 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[44\] -fixed false -x 519 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[29\] -fixed false -x 164 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[9\] -fixed false -x 462 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[41\] -fixed false -x 144 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_1_0\[3\] -fixed false -x 748 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[24\] -fixed false -x 869 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[0\] -fixed false -x 797 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1\[0\] -fixed false -x 154 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[20\] -fixed false -x 449 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m106 -fixed false -x 172 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[3\] -fixed false -x 821 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[16\] -fixed false -x 821 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[6\] -fixed false -x 33 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNINS8GO\[28\] -fixed false -x 879 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[2\] -fixed false -x 765 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[1\] -fixed false -x 416 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[11\] -fixed false -x 160 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2_0_tz\[1\] -fixed false -x 20 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_1\[0\] -fixed false -x 743 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_903 -fixed false -x 759 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_17 -fixed false -x 572 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6_3 -fixed false -x 791 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[13\] -fixed false -x 555 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_85\[11\] -fixed false -x 236 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[2\] -fixed false -x 37 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[19\] -fixed false -x 600 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[13\] -fixed false -x 532 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ol1i1_0_a2 -fixed false -x 212 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[26\] -fixed false -x 681 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[7\] -fixed false -x 358 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/i1111 -fixed false -x 249 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_658 -fixed false -x 604 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[7\] -fixed false -x 403 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/rd_data -fixed false -x 787 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[0\] -fixed false -x 60 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[6\] -fixed false -x 210 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[0\] -fixed false -x 81 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[0\] -fixed false -x 43 -y 226
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa -fixed false -x 524 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[19\] -fixed false -x 460 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[3\] -fixed false -x 698 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_li1l1_axb_0_i_0 -fixed false -x 417 -y 216
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO\[1\] -fixed false -x 549 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q1 -fixed false -x 532 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[5\] -fixed false -x 772 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un4_cpu_i_req_is_apb -fixed false -x 807 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_OIoO1 -fixed false -x 78 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[31\] -fixed false -x 749 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[3\] -fixed false -x 425 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[4\] -fixed false -x 149 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_13_2 -fixed false -x 624 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[3\] -fixed false -x 739 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[4\] -fixed false -x 244 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[9\] -fixed false -x 562 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un33_Oo1Io -fixed false -x 406 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[3\] -fixed false -x 382 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO_1 -fixed false -x 177 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[25\] -fixed false -x 414 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[14\] -fixed false -x 645 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[9\] -fixed false -x 36 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[30\] -fixed false -x 718 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10\[2\] -fixed false -x 547 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_92 -fixed false -x 645 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_a3_RNO -fixed false -x 679 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_19 -fixed false -x 74 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_596 -fixed false -x 740 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0_a2_1 -fixed false -x 645 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_4 -fixed false -x 92 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[4\] -fixed false -x 339 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[12\] -fixed false -x 652 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0_a4_4\[0\] -fixed false -x 20 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_482 -fixed false -x 649 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0_o3\[3\] -fixed false -x 152 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[28\] -fixed false -x 660 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[4\] -fixed false -x 98 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_77 -fixed false -x 726 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_5 -fixed false -x 391 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNILC68E\[17\] -fixed false -x 627 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_47\[11\] -fixed false -x 303 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_21 -fixed false -x 833 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[3\] -fixed false -x 284 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[8\] -fixed false -x 139 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_o2 -fixed false -x 175 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[3\] -fixed false -x 388 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[63\] -fixed false -x 956 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1\[0\].machine_sw_wr_tdata2_match_data_wr_en_0_0 -fixed false -x 693 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[0\] -fixed false -x 895 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[26\] -fixed false -x 748 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[10\] -fixed false -x 144 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2 -fixed false -x 468 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1_1_1 -fixed false -x 67 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1_0\[2\] -fixed false -x 201 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[5\] -fixed false -x 98 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[1\] -fixed false -x 247 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_1 -fixed false -x 238 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_8\[1\] -fixed false -x 704 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m24 -fixed false -x 79 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[9\] -fixed false -x 237 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[15\] -fixed false -x 104 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[7\] -fixed false -x 153 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[13\] -fixed false -x 263 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[14\] -fixed false -x 594 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[10\] -fixed false -x 116 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2\[0\] -fixed false -x 668 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]\[1\] -fixed false -x 791 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01\[0\] -fixed false -x 208 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[9\] -fixed false -x 281 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[33\] -fixed false -x 490 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ooo01 -fixed false -x 88 -y 223
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[9\] -fixed false -x 50 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[9\] -fixed false -x 73 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[37\] -fixed false -x 654 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[14\] -fixed false -x 803 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_N_3L4 -fixed false -x 798 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[12\] -fixed false -x 934 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[19\] -fixed false -x 840 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[16\] -fixed false -x 351 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[23\] -fixed false -x 811 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[2\] -fixed false -x 780 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_places_1_.m9 -fixed false -x 704 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m63 -fixed false -x 33 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_c_1_RNITS2GK2 -fixed false -x 768 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg\[0\] -fixed false -x 566 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/un1_iOI01_1_i_0 -fixed false -x 331 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0\[11\] -fixed false -x 334 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3\[2\] -fixed false -x 200 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01 -fixed false -x 206 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1239 -fixed false -x 676 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[2\] -fixed false -x 283 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[1\] -fixed false -x 367 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[4\] -fixed false -x 403 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[1\] -fixed false -x 104 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1\[2\] -fixed false -x 278 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[5\] -fixed false -x 319 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooOIo -fixed false -x 126 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_strb\[1\] -fixed false -x 759 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[1\] -fixed false -x 115 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1234 -fixed false -x 698 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[1\] -fixed false -x 409 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIOOo_1_i_o3 -fixed false -x 127 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[30\] -fixed false -x 457 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[22\] -fixed false -x 783 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[25\] -fixed false -x 896 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1l11 -fixed false -x 262 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_461 -fixed false -x 643 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[19\] -fixed false -x 735 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[0\] -fixed false -x 237 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_0 -fixed false -x 687 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_762 -fixed false -x 788 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[32\] -fixed false -x 541 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[9\] -fixed false -x 197 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[7\] -fixed false -x 227 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[21\] -fixed false -x 714 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[15\] -fixed false -x 320 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mcause_excpt_code_wr_data_0\[3\] -fixed false -x 738 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_347 -fixed false -x 729 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15 -fixed false -x 150 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3\[2\] -fixed false -x 136 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[2\] -fixed false -x 385 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO\[11\] -fixed false -x 320 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[12\] -fixed false -x 436 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[28\] -fixed false -x 116 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[9\] -fixed false -x 178 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a2_0 -fixed false -x 164 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[12\] -fixed false -x 877 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_216 -fixed false -x 660 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[12\] -fixed false -x 380 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIGC0D6\[2\] -fixed false -x 299 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[18\] -fixed false -x 851 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un9_Io001 -fixed false -x 86 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_1\[2\] -fixed false -x 514 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[38\] -fixed false -x 912 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[9\] -fixed false -x 321 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[25\] -fixed false -x 741 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[9\] -fixed false -x 374 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[9\] -fixed false -x 831 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[9\] -fixed false -x 357 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[12\] -fixed false -x 122 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_1_0_a3_1 -fixed false -x 720 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[3\] -fixed false -x 366 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv\[28\] -fixed false -x 657 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1 -fixed false -x 190 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[7\] -fixed false -x 157 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type\[9\] -fixed false -x 826 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOl11 -fixed false -x 240 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo\[6\] -fixed false -x 67 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_o3 -fixed false -x 225 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[5\] -fixed false -x 143 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[10\] -fixed false -x 33 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_2\[5\] -fixed false -x 310 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_6_0_a2_0\[0\] -fixed false -x 791 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel\[0\] -fixed false -x 36 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[3\] -fixed false -x 176 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[11\] -fixed false -x 504 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_6\[8\] -fixed false -x 151 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[28\] -fixed false -x 707 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[5\] -fixed false -x 775 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_25 -fixed false -x 680 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[26\] -fixed false -x 779 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[7\] -fixed false -x 133 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[14\] -fixed false -x 383 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIUSMI5\[3\] -fixed false -x 256 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1_0\[1\] -fixed false -x 116 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[7\] -fixed false -x 920 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[10\] -fixed false -x 108 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_RNO -fixed false -x 825 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[22\] -fixed false -x 438 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o1il1 -fixed false -x 518 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[23\] -fixed false -x 657 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_accepted -fixed false -x 763 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[8\] -fixed false -x 930 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[2\] -fixed false -x 282 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOi01 -fixed false -x 40 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_2 -fixed false -x 385 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_410 -fixed false -x 642 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[26\] -fixed false -x 911 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc4 -fixed false -x 42 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[18\] -fixed false -x 846 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[0\] -fixed false -x 313 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[37\] -fixed false -x 392 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_RNO\[8\] -fixed false -x 73 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o1oo1_i_0_tz -fixed false -x 92 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[33\] -fixed false -x 642 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[2\] -fixed false -x 138 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[1\] -fixed false -x 284 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un16_valid_sba_0_a3_RNIDMOIC -fixed false -x 692 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[25\] -fixed false -x 663 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/IilI1 -fixed false -x 317 -y 160
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[2\] -fixed false -x 387 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60\[4\] -fixed false -x 956 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_61\[11\] -fixed false -x 271 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m25 -fixed false -x 57 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_505 -fixed false -x 752 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[6\] -fixed false -x 151 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[12\] -fixed false -x 525 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_RNII9A0H\[1\] -fixed false -x 17 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[3\] -fixed false -x 205 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m155 -fixed false -x 259 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[63\] -fixed false -x 599 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_381 -fixed false -x 617 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_386 -fixed false -x 716 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[3\] -fixed false -x 165 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[5\] -fixed false -x 285 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold\[1\] -fixed false -x 568 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[28\] -fixed false -x 743 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_9 -fixed false -x 741 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[23\] -fixed false -x 84 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[3\] -fixed false -x 239 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2\[0\] -fixed false -x 653 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3\[4\] -fixed false -x 92 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.per_trigger_debug\[0\] -fixed false -x 777 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[8\] -fixed false -x 67 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid39_0 -fixed false -x 783 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956 -fixed false -x 681 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[38\] -fixed false -x 509 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[0\] -fixed false -x 60 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[7\] -fixed false -x 139 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[14\] -fixed false -x 177 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv\[12\] -fixed false -x 734 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_valid_mux_RNISBJD7 -fixed false -x 824 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[9\] -fixed false -x 36 -y 204
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[3\] -fixed false -x 451 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[2\] -fixed false -x 156 -y 177
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m10 -fixed false -x 476 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[2\] -fixed false -x 236 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[17\] -fixed false -x 834 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[5\] -fixed false -x 785 -y 106
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un16_i00i1lto2_1 -fixed false -x 174 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI44QTM1\[0\] -fixed false -x 31 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[6\] -fixed false -x 273 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[7\] -fixed false -x 303 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[7\] -fixed false -x 162 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1\[16\] -fixed false -x 222 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[6\] -fixed false -x 430 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[4\] -fixed false -x 86 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0\[3\] -fixed false -x 689 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO -fixed false -x 796 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_750 -fixed false -x 680 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2 -fixed false -x 162 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO\[0\] -fixed false -x 715 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[2\] -fixed false -x 263 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[16\] -fixed false -x 419 -y 184
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[24\] -fixed false -x 417 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_7_RNIDO3BC -fixed false -x 106 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3_1 -fixed false -x 550 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0\[3\] -fixed false -x 130 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[1\] -fixed false -x 247 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1_0 -fixed false -x 129 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[14\] -fixed false -x 135 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo54_1 -fixed false -x 94 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[3\] -fixed false -x 378 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[11\] -fixed false -x 920 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[31\] -fixed false -x 384 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001\[0\] -fixed false -x 87 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[4\] -fixed false -x 600 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[7\] -fixed false -x 463 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[23\] -fixed false -x 472 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_15 -fixed false -x 633 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[2\] -fixed false -x 69 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[7\] -fixed false -x 692 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[11\] -fixed false -x 35 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[0\] -fixed false -x 162 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count\[1\] -fixed false -x 781 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[4\] -fixed false -x 903 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/ssel_rx_q1 -fixed false -x 519 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[5\] -fixed false -x 307 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oll11 -fixed false -x 290 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[5\] -fixed false -x 438 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[3\] -fixed false -x 884 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_7 -fixed false -x 218 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[24\] -fixed false -x 590 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[4\] -fixed false -x 473 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/data_rx_q2 -fixed false -x 513 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[28\] -fixed false -x 395 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[5\] -fixed false -x 390 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[0\] -fixed false -x 165 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[22\] -fixed false -x 958 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[28\] -fixed false -x 395 -y 154
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg\[2\] -fixed false -x 37 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv\[1\] -fixed false -x 730 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[17\] -fixed false -x 536 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[28\] -fixed false -x 870 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[14\] -fixed false -x 386 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[14\] -fixed false -x 509 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[7\] -fixed false -x 262 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[7\] -fixed false -x 115 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[8\] -fixed false -x 701 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[1\] -fixed false -x 247 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[5\] -fixed false -x 402 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op\[1\] -fixed false -x 812 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[19\] -fixed false -x 693 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[4\] -fixed false -x 360 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un8_l00o1_1 -fixed false -x 119 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_8\[4\] -fixed false -x 188 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_6\[13\] -fixed false -x 142 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[9\] -fixed false -x 830 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[51\] -fixed false -x 570 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize -fixed false -x 526 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_329 -fixed false -x 796 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit\[3\] -fixed false -x 466 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[12\] -fixed false -x 464 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[6\] -fixed false -x 176 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[7\] -fixed false -x 869 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[23\] -fixed false -x 893 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1053 -fixed false -x 640 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[2\] -fixed false -x 826 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1 -fixed false -x 186 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[25\] -fixed false -x 818 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/N_308_i -fixed false -x 751 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_471 -fixed false -x 689 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[14\] -fixed false -x 645 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_75 -fixed false -x 645 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oOio1 -fixed false -x 54 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_772 -fixed false -x 606 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[4\] -fixed false -x 403 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_0\[0\] -fixed false -x 19 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[9\] -fixed false -x 124 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[1\] -fixed false -x 369 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a0_0_0 -fixed false -x 826 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[3\] -fixed false -x 730 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[7\] -fixed false -x 259 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m6 -fixed false -x 660 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[9\] -fixed false -x 503 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[26\] -fixed false -x 408 -y 241
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[0\] -fixed false -x 515 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_5 -fixed false -x 639 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[26\] -fixed false -x 742 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[17\] -fixed false -x 442 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[28\] -fixed false -x 774 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[11\] -fixed false -x 411 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_strobetx -fixed false -x 529 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[25\] -fixed false -x 421 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[10\] -fixed false -x 378 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[5\] -fixed false -x 109 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[24\] -fixed false -x 673 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01\[3\] -fixed false -x 199 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[30\] -fixed false -x 958 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1092 -fixed false -x 668 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[11\] -fixed false -x 426 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[16\] -fixed false -x 894 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_7 -fixed false -x 141 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1012 -fixed false -x 657 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[7\] -fixed false -x 399 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[30\] -fixed false -x 382 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[3\] -fixed false -x 798 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[30\] -fixed false -x 595 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[10\] -fixed false -x 338 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m13 -fixed false -x 115 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[25\] -fixed false -x 895 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[19\] -fixed false -x 465 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2_3 -fixed false -x 704 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_RNIV073C\[1\] -fixed false -x 628 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/un1_Ioli0_1_0 -fixed false -x 248 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[20\] -fixed false -x 475 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[14\] -fixed false -x 957 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_699 -fixed false -x 668 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[29\] -fixed false -x 822 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[4\] -fixed false -x 740 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_u\[0\] -fixed false -x 970 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_iOiIo -fixed false -x 438 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[17\] -fixed false -x 847 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ\[12\] -fixed false -x 299 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/wr_en_data_or -fixed false -x 760 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_str_req_buff_addr_misalign_u -fixed false -x 741 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[1\] -fixed false -x 440 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[14\] -fixed false -x 141 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m5 -fixed false -x 57 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[27\] -fixed false -x 428 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[8\] -fixed false -x 430 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[14\] -fixed false -x 416 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_8 -fixed false -x 201 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[5\] -fixed false -x 305 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_3 -fixed false -x 174 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_80 -fixed false -x 703 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[4\] -fixed false -x 121 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[4\] -fixed false -x 196 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[9\] -fixed false -x 567 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[4\] -fixed false -x 834 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[4\] -fixed false -x 368 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1 -fixed false -x 732 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[22\] -fixed false -x 405 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un528_lIlo1_2 -fixed false -x 146 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_728 -fixed false -x 656 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[3\] -fixed false -x 571 -y 142
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa -fixed false -x 511 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[10\] -fixed false -x 36 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01_2 -fixed false -x 206 -y 186
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[7\] -fixed false -x 454 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[18\] -fixed false -x 883 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_98 -fixed false -x 641 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m28 -fixed false -x 607 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[10\] -fixed false -x 524 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_3\[13\] -fixed false -x 134 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[15\] -fixed false -x 272 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[11\] -fixed false -x 210 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[14\] -fixed false -x 745 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[13\] -fixed false -x 499 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid33 -fixed false -x 861 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[18\] -fixed false -x 434 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01\[4\] -fixed false -x 174 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[59\] -fixed false -x 568 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_rxfifo -fixed false -x 518 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_1398_i -fixed false -x 756 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[4\] -fixed false -x 168 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_1 -fixed false -x 500 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[7\] -fixed false -x 370 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[32\] -fixed false -x 486 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff_3_i_m2 -fixed false -x 683 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un26_Oo1Io_0 -fixed false -x 405 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_is_subsys_hart_soft_reg -fixed false -x 824 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_16\[20\] -fixed false -x 139 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_2\[0\] -fixed false -x 121 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_35\[9\] -fixed false -x 299 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO -fixed false -x 184 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[0\] -fixed false -x 374 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[7\] -fixed false -x 525 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[16\] -fixed false -x 801 -y 181
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[27\] -fixed false -x 415 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[25\] -fixed false -x 740 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[17\] -fixed false -x 382 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[9\] -fixed false -x 284 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[23\] -fixed false -x 741 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/IilI1 -fixed false -x 255 -y 166
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM\[1\] -fixed false -x 116 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1071 -fixed false -x 633 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[3\] -fixed false -x 47 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[12\] -fixed false -x 405 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt\[2\] -fixed false -x 31 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_65\[11\] -fixed false -x 314 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[21\] -fixed false -x 800 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111 -fixed false -x 388 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[14\] -fixed false -x 398 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[9\] -fixed false -x 212 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[21\] -fixed false -x 799 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[9\] -fixed false -x 788 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[3\] -fixed false -x 419 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[3\] -fixed false -x 62 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[7\] -fixed false -x 51 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[11\] -fixed false -x 831 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNIHT6E22_0 -fixed false -x 827 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/havereset_skip_pwrup -fixed false -x 803 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[12\] -fixed false -x 410 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[0\] -fixed false -x 335 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13\[2\] -fixed false -x 779 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iiO11 -fixed false -x 140 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[26\] -fixed false -x 692 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[9\] -fixed false -x 339 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[7\] -fixed false -x 259 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[15\] -fixed false -x 415 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[21\] -fixed false -x 441 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/il1i1_0_a3_1 -fixed false -x 223 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[3\] -fixed false -x 108 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4\[2\] -fixed false -x 785 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[8\] -fixed false -x 738 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[2\] -fixed false -x 281 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[8\] -fixed false -x 446 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[3\] -fixed false -x 308 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[7\] -fixed false -x 307 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[18\] -fixed false -x 760 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[5\] -fixed false -x 69 -y 168
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[14\] -fixed false -x 377 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/OOlo1 -fixed false -x 320 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[15\] -fixed false -x 911 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[2\] -fixed false -x 906 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[24\] -fixed false -x 816 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[4\] -fixed false -x 189 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[9\] -fixed false -x 118 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[7\] -fixed false -x 897 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error -fixed false -x 450 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[17\] -fixed false -x 749 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[9\] -fixed false -x 427 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_a3_1 -fixed false -x 164 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[6\] -fixed false -x 956 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_first -fixed false -x 543 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_RNI0LOMD\[1\] -fixed false -x 671 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[0\] -fixed false -x 569 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1271 -fixed false -x 717 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[6\] -fixed false -x 532 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[12\] -fixed false -x 478 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[17\] -fixed false -x 208 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_2_2 -fixed false -x 188 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[2\] -fixed false -x 440 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_8_3 -fixed false -x 696 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[26\] -fixed false -x 738 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[11\] -fixed false -x 803 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[14\] -fixed false -x 648 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO\[1\] -fixed false -x 746 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[9\] -fixed false -x 444 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[13\] -fixed false -x 65 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state\[3\] -fixed false -x 787 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_827 -fixed false -x 667 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_3\[1\] -fixed false -x 691 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[4\] -fixed false -x 244 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[3\] -fixed false -x 408 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex6 -fixed false -x 744 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[8\] -fixed false -x 575 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[29\] -fixed false -x 834 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[6\] -fixed false -x 435 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a4_1_1\[0\] -fixed false -x 42 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[7\] -fixed false -x 698 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM\[3\] -fixed false -x 80 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[11\] -fixed false -x 555 -y 199
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[10\].BUFD_BLK -fixed false -x 513 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[1\] -fixed false -x 85 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_0\[8\] -fixed false -x 112 -y 210
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_3 -fixed false -x 513 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[14\] -fixed false -x 320 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[36\] -fixed false -x 429 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_2 -fixed false -x 779 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[30\] -fixed false -x 631 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_O1Ii1 -fixed false -x 176 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[6\] -fixed false -x 764 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[7\] -fixed false -x 70 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_7\[10\] -fixed false -x 279 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv_1\[7\] -fixed false -x 734 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO_0 -fixed false -x 860 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[2\] -fixed false -x 345 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOol1 -fixed false -x 384 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[5\] -fixed false -x 782 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[14\] -fixed false -x 423 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0_o2_0\[15\] -fixed false -x 180 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IiI11 -fixed false -x 275 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]_3\[3\] -fixed false -x 742 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[6\] -fixed false -x 881 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[12\] -fixed false -x 209 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[31\] -fixed false -x 736 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[27\] -fixed false -x 390 -y 174
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[2\] -fixed false -x 471 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[8\] -fixed false -x 229 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[15\] -fixed false -x 470 -y 214
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata\[0\] -fixed false -x 510 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[8\] -fixed false -x 958 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[5\] -fixed false -x 368 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[15\] -fixed false -x 27 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[11\] -fixed false -x 348 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[5\] -fixed false -x 525 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[45\] -fixed false -x 530 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/IilI1_RNO -fixed false -x 323 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1042 -fixed false -x 704 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[29\] -fixed false -x 572 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[28\] -fixed false -x 385 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[6\] -fixed false -x 294 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand0_mux_sel\[0\] -fixed false -x 771 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb\[1\] -fixed false -x 593 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[18\] -fixed false -x 679 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[2\] -fixed false -x 55 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[3\] -fixed false -x 810 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_8 -fixed false -x 812 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1260 -fixed false -x 725 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[3\] -fixed false -x 821 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_1\[6\] -fixed false -x 116 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1\[4\] -fixed false -x 485 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[2\] -fixed false -x 737 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[6\] -fixed false -x 623 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[2\] -fixed false -x 612 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_78\[11\] -fixed false -x 273 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[5\] -fixed false -x 908 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[8\] -fixed false -x 524 -y 199
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[9\].BUFD_BLK -fixed false -x 512 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[29\] -fixed false -x 947 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[4\] -fixed false -x 301 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo -fixed false -x 32 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un13_OIoO1\[4\] -fixed false -x 86 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[13\] -fixed false -x 793 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[13\] -fixed false -x 653 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[5\] -fixed false -x 112 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m23 -fixed false -x 114 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[9\] -fixed false -x 514 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[9\] -fixed false -x 409 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m26 -fixed false -x 642 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m56_1_0 -fixed false -x 66 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_fault\[0\]\[0\] -fixed false -x 814 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[15\] -fixed false -x 237 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[8\] -fixed false -x 408 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[2\] -fixed false -x 712 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[1\] -fixed false -x 520 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1_2 -fixed false -x 655 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[10\] -fixed false -x 565 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_615 -fixed false -x 609 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_clock_int -fixed false -x 468 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4\[6\] -fixed false -x 106 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[7\] -fixed false -x 381 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[22\] -fixed false -x 789 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[4\] -fixed false -x 724 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[15\] -fixed false -x 188 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[6\] -fixed false -x 251 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_0\[2\] -fixed false -x 629 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[10\] -fixed false -x 307 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_a3\[0\] -fixed false -x 196 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[17\] -fixed false -x 664 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.I0li0 -fixed false -x 367 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[8\] -fixed false -x 645 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[42\] -fixed false -x 245 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un1_oOo01 -fixed false -x 90 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[12\] -fixed false -x 119 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[15\] -fixed false -x 27 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[2\] -fixed false -x 236 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1\[0\] -fixed false -x 94 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[12\] -fixed false -x 397 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[23\] -fixed false -x 207 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[9\] -fixed false -x 661 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[5\] -fixed false -x 183 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_1\[1\] -fixed false -x 44 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_sn_m2 -fixed false -x 754 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3 -fixed false -x 668 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[24\] -fixed false -x 880 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val\[0\] -fixed false -x 773 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[2\] -fixed false -x 490 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[13\] -fixed false -x 158 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places\[3\] -fixed false -x 872 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state\[1\] -fixed false -x 473 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z\[2\] -fixed false -x 337 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[1\] -fixed false -x 424 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[8\] -fixed false -x 409 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2\[4\] -fixed false -x 673 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_out27_i_a2 -fixed false -x 515 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[3\] -fixed false -x 106 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_4_1 -fixed false -x 525 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI45Q5C\[18\] -fixed false -x 636 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[13\] -fixed false -x 462 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[30\] -fixed false -x 808 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[11\] -fixed false -x 425 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[1\] -fixed false -x 37 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m67_0 -fixed false -x 285 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO -fixed false -x 835 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[21\] -fixed false -x 390 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO_0 -fixed false -x 907 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[18\] -fixed false -x 715 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa_2 -fixed false -x 470 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[7\] -fixed false -x 561 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un6_OoI01 -fixed false -x 186 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un31_next_quotient_0_a2_0 -fixed false -x 885 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig_0 -fixed false -x 812 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[1\] -fixed false -x 698 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNILF98E\[26\] -fixed false -x 631 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_929 -fixed false -x 702 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[3\] -fixed false -x 427 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_resume_ack -fixed false -x 771 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[0\] -fixed false -x 708 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[9\] -fixed false -x 304 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/IilI1_RNO -fixed false -x 317 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_2\[1\] -fixed false -x 637 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8\[11\] -fixed false -x 752 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0\[2\] -fixed false -x 68 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_28_0_RNO -fixed false -x 845 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/clk_en_dm_cmb_i_0_a3 -fixed false -x 802 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[13\] -fixed false -x 37 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[8\] -fixed false -x 405 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[3\] -fixed false -x 379 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[12\] -fixed false -x 393 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[5\] -fixed false -x 162 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[0\] -fixed false -x 254 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[13\] -fixed false -x 907 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[63\] -fixed false -x 599 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[5\] -fixed false -x 461 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[5\] -fixed false -x 523 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo56 -fixed false -x 93 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[3\] -fixed false -x 308 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[3\] -fixed false -x 294 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c -fixed false -x 817 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/ebreak_debug_enter_taken -fixed false -x 781 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[5\] -fixed false -x 388 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[0\] -fixed false -x 762 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[12\] -fixed false -x 678 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1279 -fixed false -x 786 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[2\] -fixed false -x 382 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2\[27\] -fixed false -x 933 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1163 -fixed false -x 628 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[25\] -fixed false -x 785 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_0 -fixed false -x 658 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[1\] -fixed false -x 168 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1274 -fixed false -x 655 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o2\[3\] -fixed false -x 144 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9\[0\] -fixed false -x 321 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc6 -fixed false -x 59 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[8\] -fixed false -x 80 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_3\[31\] -fixed false -x 625 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[15\] -fixed false -x 848 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[22\] -fixed false -x 717 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[0\] -fixed false -x 409 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[4\] -fixed false -x 883 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[5\] -fixed false -x 860 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_3 -fixed false -x 159 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[13\] -fixed false -x 408 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_0\[0\] -fixed false -x 101 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[21\] -fixed false -x 453 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[18\] -fixed false -x 91 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[5\] -fixed false -x 174 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[27\] -fixed false -x 861 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[28\] -fixed false -x 843 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[32\] -fixed false -x 421 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[4\] -fixed false -x 644 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_14 -fixed false -x 694 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[10\] -fixed false -x 494 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[10\] -fixed false -x 92 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO -fixed false -x 861 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[10\] -fixed false -x 920 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[27\] -fixed false -x 740 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[29\] -fixed false -x 835 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0_1_0\[0\] -fixed false -x 192 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_12\[9\] -fixed false -x 298 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto9_1 -fixed false -x 137 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[14\] -fixed false -x 237 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[7\] -fixed false -x 254 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_ilIl114_2_0 -fixed false -x 483 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[23\] -fixed false -x 916 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[9\] -fixed false -x 405 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[2\] -fixed false -x 79 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[27\] -fixed false -x 752 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39\[4\] -fixed false -x 257 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0\[12\] -fixed false -x 165 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[7\] -fixed false -x 284 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[7\] -fixed false -x 418 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[15\] -fixed false -x 561 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1\[10\] -fixed false -x 73 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[31\] -fixed false -x 390 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[12\] -fixed false -x 56 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[14\] -fixed false -x 861 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_Ooo11_1 -fixed false -x 365 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_1_0 -fixed false -x 817 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[27\] -fixed false -x 421 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_20 -fixed false -x 853 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2 -fixed false -x 643 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un129_i11Io -fixed false -x 418 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[6\] -fixed false -x 560 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ili11 -fixed false -x 391 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[8\] -fixed false -x 783 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI1UT441_0 -fixed false -x 729 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[0\] -fixed false -x 189 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0 -fixed false -x 202 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[16\] -fixed false -x 706 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[0\] -fixed false -x 341 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un159_I1Oi1 -fixed false -x 71 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[8\] -fixed false -x 911 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[18\] -fixed false -x 741 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[4\] -fixed false -x 411 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[16\] -fixed false -x 657 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[8\] -fixed false -x 123 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[13\] -fixed false -x 381 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[37\] -fixed false -x 422 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1005 -fixed false -x 715 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[2\] -fixed false -x 240 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un9_next_exu_result_reg_int -fixed false -x 829 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_12\[10\] -fixed false -x 292 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[1\] -fixed false -x 418 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[19\] -fixed false -x 931 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un13_instr_is_lsu_ldstr_ex -fixed false -x 748 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[1\] -fixed false -x 659 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[7\] -fixed false -x 85 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[15\] -fixed false -x 121 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[3\] -fixed false -x 123 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs2_rd_hzd_1 -fixed false -x 745 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo\[2\] -fixed false -x 150 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO -fixed false -x 85 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_345 -fixed false -x 667 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[8\] -fixed false -x 91 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[0\] -fixed false -x 383 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[0\] -fixed false -x 417 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_addr_align\[0\]_3\[1\] -fixed false -x 828 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[4\] -fixed false -x 654 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_implicit_pseudo_instr_ex_2 -fixed false -x 717 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO\[1\] -fixed false -x 431 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4950_0 -fixed false -x 700 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[9\] -fixed false -x 444 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[12\] -fixed false -x 128 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0Ii1 -fixed false -x 163 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[16\] -fixed false -x 532 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[10\] -fixed false -x 138 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_2\[22\] -fixed false -x 248 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[3\] -fixed false -x 306 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1285 -fixed false -x 700 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[5\] -fixed false -x 67 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001\[1\] -fixed false -x 85 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI0AFO8 -fixed false -x 299 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[5\] -fixed false -x 70 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m4 -fixed false -x 127 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2121_2 -fixed false -x 644 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[14\] -fixed false -x 935 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[43\] -fixed false -x 148 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[26\] -fixed false -x 931 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[9\] -fixed false -x 725 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[5\] -fixed false -x 341 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[6\] -fixed false -x 513 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a3_0 -fixed false -x 645 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[6\] -fixed false -x 308 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[2\] -fixed false -x 81 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_254 -fixed false -x 618 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[1\] -fixed false -x 48 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastbit -fixed false -x 541 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[41\] -fixed false -x 252 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[3\] -fixed false -x 693 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0IO1 -fixed false -x 161 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[8\] -fixed false -x 593 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_40\[8\] -fixed false -x 953 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[8\] -fixed false -x 885 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[1\] -fixed false -x 244 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1\[4\] -fixed false -x 122 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[2\] -fixed false -x 355 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[7\] -fixed false -x 50 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1309 -fixed false -x 775 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1203 -fixed false -x 655 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILBRQ8\[13\] -fixed false -x 649 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_uncompressed_full -fixed false -x 632 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[7\] -fixed false -x 338 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[25\] -fixed false -x 784 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[1\] -fixed false -x 599 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m3 -fixed false -x 125 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[4\] -fixed false -x 772 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[23\] -fixed false -x 559 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[27\] -fixed false -x 848 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[12\] -fixed false -x 465 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_426 -fixed false -x 644 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_0_sqmuxa -fixed false -x 865 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[5\] -fixed false -x 512 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex\[0\] -fixed false -x 723 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01\[0\] -fixed false -x 144 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[0\] -fixed false -x 81 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2\[8\] -fixed false -x 879 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[35\] -fixed false -x 471 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[14\] -fixed false -x 885 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[3\] -fixed false -x 164 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[12\] -fixed false -x 735 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[30\] -fixed false -x 785 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[4\] -fixed false -x 15 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m71_1_0 -fixed false -x 32 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[6\] -fixed false -x 148 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata2_sw_rd_sel_7 -fixed false -x 692 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO1 -fixed false -x 546 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[5\] -fixed false -x 436 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[30\] -fixed false -x 476 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[0\] -fixed false -x 133 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0\[1\] -fixed false -x 131 -y 210
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m13 -fixed false -x 506 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_o2 -fixed false -x 61 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[12\] -fixed false -x 103 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[2\] -fixed false -x 235 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0\[4\] -fixed false -x 16 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[7\] -fixed false -x 126 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_2_1 -fixed false -x 834 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[4\] -fixed false -x 510 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[18\] -fixed false -x 612 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[9\] -fixed false -x 267 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iIol1 -fixed false -x 354 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[16\] -fixed false -x 70 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[0\] -fixed false -x 707 -y 129
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_par_calc.tx_parity_5 -fixed false -x 445 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[17\] -fixed false -x 433 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[9\] -fixed false -x 399 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[2\] -fixed false -x 320 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[21\] -fixed false -x 558 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_8_RNO -fixed false -x 381 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2\[8\] -fixed false -x 46 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_23_RNI27LRM -fixed false -x 67 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0\[3\] -fixed false -x 128 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_rd_ptr_0\[0\] -fixed false -x 810 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[1\] -fixed false -x 880 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[24\] -fixed false -x 956 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/IilI1 -fixed false -x 194 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[5\] -fixed false -x 258 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_1_sqmuxa -fixed false -x 663 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[5\] -fixed false -x 174 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[26\] -fixed false -x 918 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_URSTB -fixed false -x 537 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[1\] -fixed false -x 145 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[27\] -fixed false -x 489 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[10\] -fixed false -x 375 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[5\] -fixed false -x 433 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001_RNO_0 -fixed false -x 92 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[23\] -fixed false -x 556 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[23\] -fixed false -x 446 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lii11 -fixed false -x 304 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[9\] -fixed false -x 79 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10\[4\] -fixed false -x 549 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[6\] -fixed false -x 422 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_10 -fixed false -x 245 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oOIOo -fixed false -x 47 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1\[0\] -fixed false -x 255 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[29\] -fixed false -x 866 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[3\] -fixed false -x 721 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready -fixed false -x 787 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[26\] -fixed false -x 400 -y 157
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[32\].BUFD_BLK -fixed false -x 487 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4\[3\] -fixed false -x 575 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[28\] -fixed false -x 548 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[8\] -fixed false -x 373 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_o4\[5\] -fixed false -x 315 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[28\] -fixed false -x 599 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1\[29\] -fixed false -x 218 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m11 -fixed false -x 112 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1 -fixed false -x 189 -y 198
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[3\] -fixed false -x 400 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_tz_tz -fixed false -x 696 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[23\] -fixed false -x 686 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_2_0 -fixed false -x 124 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[0\] -fixed false -x 121 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[6\] -fixed false -x 272 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[11\] -fixed false -x 128 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[29\] -fixed false -x 799 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[18\] -fixed false -x 931 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[1\] -fixed false -x 103 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[1\] -fixed false -x 156 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1 -fixed false -x 820 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[6\] -fixed false -x 277 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI1o1_i_0 -fixed false -x 53 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q0 -fixed false -x 740 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[4\] -fixed false -x 946 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[12\] -fixed false -x 843 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel_1_0 -fixed false -x 718 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.step_debug_enter_pending -fixed false -x 769 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[5\] -fixed false -x 837 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_363 -fixed false -x 621 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[24\] -fixed false -x 142 -y 169
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[7\] -fixed false -x 59 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[8\] -fixed false -x 861 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_2_2 -fixed false -x 685 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid_3_2_RNIJQMMM1 -fixed false -x 823 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_0_sqmuxa_0 -fixed false -x 200 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIV8FO8 -fixed false -x 292 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNI7T9PR6 -fixed false -x 791 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1060 -fixed false -x 762 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO_0 -fixed false -x 680 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[6\] -fixed false -x 609 -y 154
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2\[1\] -fixed false -x 384 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[2\] -fixed false -x 384 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_7 -fixed false -x 14 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[23\] -fixed false -x 807 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_1 -fixed false -x 92 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[5\] -fixed false -x 61 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6_3 -fixed false -x 810 -y 129
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_RNO\[1\] -fixed false -x 32 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m80 -fixed false -x 30 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[8\] -fixed false -x 860 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_213 -fixed false -x 656 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[18\] -fixed false -x 636 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[19\] -fixed false -x 743 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_hword_high_only_u_i_m2 -fixed false -x 868 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftIR_0_sqmuxa_i -fixed false -x 573 -y 114
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[19\] -fixed false -x 391 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[9\] -fixed false -x 390 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIi01\[3\] -fixed false -x 97 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[6\] -fixed false -x 155 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_110 -fixed false -x 644 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[19\] -fixed false -x 694 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[8\] -fixed false -x 703 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[4\] -fixed false -x 293 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[3\] -fixed false -x 741 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[22\] -fixed false -x 440 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[5\] -fixed false -x 126 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_2 -fixed false -x 353 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv_tz\[0\] -fixed false -x 769 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[55\] -fixed false -x 940 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[4\] -fixed false -x 188 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_94 -fixed false -x 765 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 257 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40\[3\] -fixed false -x 359 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[23\] -fixed false -x 853 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[3\] -fixed false -x 54 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel -fixed false -x 706 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM\[3\] -fixed false -x 235 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[21\] -fixed false -x 860 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand0_mux_sel_u\[0\] -fixed false -x 683 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[7\] -fixed false -x 410 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO_0 -fixed false -x 831 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[31\] -fixed false -x 625 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1 -fixed false -x 182 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[5\] -fixed false -x 859 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIK1L9D -fixed false -x 787 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[14\] -fixed false -x 79 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_19_RNIE9UC8 -fixed false -x 845 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OlO11 -fixed false -x 18 -y 210
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE17_2 -fixed false -x 19 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_1 -fixed false -x 238 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[24\] -fixed false -x 433 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[34\] -fixed false -x 414 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[29\] -fixed false -x 879 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[29\] -fixed false -x 226 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_set_wfi_waiting -fixed false -x 762 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1266 -fixed false -x 669 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un38_OIoO1 -fixed false -x 61 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[31\] -fixed false -x 384 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr\[1\] -fixed false -x 870 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/un1_iOI01_1_i_0 -fixed false -x 291 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/O0lo1 -fixed false -x 335 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 -fixed false -x 324 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo -fixed false -x 98 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[10\] -fixed false -x 134 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[4\] -fixed false -x 521 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[5\] -fixed false -x 376 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[14\] -fixed false -x 32 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_3 -fixed false -x 211 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa_1_1 -fixed false -x 775 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[4\] -fixed false -x 848 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto9 -fixed false -x 136 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[31\] -fixed false -x 237 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[11\] -fixed false -x 516 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNIRGP6H\[9\] -fixed false -x 853 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[15\] -fixed false -x 649 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[0\] -fixed false -x 268 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_36 -fixed false -x 839 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_141 -fixed false -x 654 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[0\] -fixed false -x 79 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[5\] -fixed false -x 98 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO_0 -fixed false -x 843 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_0 -fixed false -x 694 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[3\] -fixed false -x 189 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[8\] -fixed false -x 415 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_1\[4\] -fixed false -x 721 -y 135
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4 -fixed false -x 459 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[13\] -fixed false -x 746 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_o2_0\[2\] -fixed false -x 716 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[0\] -fixed false -x 49 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[1\] -fixed false -x 62 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_lIII110_4 -fixed false -x 472 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[7\] -fixed false -x 392 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0\[12\] -fixed false -x 137 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u\[8\] -fixed false -x 957 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr\[1\] -fixed false -x 704 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIQUT5C\[31\] -fixed false -x 623 -y 156
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_6\[0\] -fixed false -x 753 -y 43
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[2\] -fixed false -x 739 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_342 -fixed false -x 654 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/io1Io_RNO -fixed false -x 415 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOIIo_0_a3 -fixed false -x 149 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[3\] -fixed false -x 529 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[6\] -fixed false -x 71 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0iIo -fixed false -x 435 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un93_I1Oi1_1 -fixed false -x 15 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[1\] -fixed false -x 358 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1\[32\] -fixed false -x 468 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[0\] -fixed false -x 254 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2131 -fixed false -x 660 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[1\] -fixed false -x 762 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_232 -fixed false -x 644 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[25\] -fixed false -x 411 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[13\] -fixed false -x 776 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[23\] -fixed false -x 818 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[26\] -fixed false -x 813 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[1\] -fixed false -x 781 -y 106
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO -fixed false -x 392 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[20\] -fixed false -x 863 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0ll1 -fixed false -x 201 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0\[5\] -fixed false -x 327 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[1\] -fixed false -x 872 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[4\] -fixed false -x 86 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m_a0_3_1\[0\] -fixed false -x 836 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1131 -fixed false -x 702 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[10\] -fixed false -x 703 -y 126
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_7\[0\] -fixed false -x 752 -y 43
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[18\] -fixed false -x 445 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[2\] -fixed false -x 511 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[28\] -fixed false -x 782 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[9\] -fixed false -x 724 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[1\] -fixed false -x 806 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[25\] -fixed false -x 844 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto4 -fixed false -x 142 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[11\] -fixed false -x 495 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[27\] -fixed false -x 408 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[3\] -fixed false -x 48 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[11\] -fixed false -x 108 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIS5FO8 -fixed false -x 288 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/cause_excpt_code_excpt_1\[1\] -fixed false -x 732 -y 168
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2\[0\] -fixed false -x 373 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[62\] -fixed false -x 598 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[19\] -fixed false -x 50 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_944 -fixed false -x 751 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[7\] -fixed false -x 694 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_tz\[5\] -fixed false -x 767 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[23\] -fixed false -x 935 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[3\] -fixed false -x 208 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39\[2\] -fixed false -x 271 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[3\] -fixed false -x 869 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[5\] -fixed false -x 219 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[0\] -fixed false -x 196 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[5\] -fixed false -x 426 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[21\] -fixed false -x 434 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0\[0\] -fixed false -x 669 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[22\] -fixed false -x 553 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[11\] -fixed false -x 771 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[4\] -fixed false -x 494 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[14\] -fixed false -x 357 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[27\] -fixed false -x 482 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIDJUT5 -fixed false -x 345 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO\[4\] -fixed false -x 165 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101\[0\] -fixed false -x 54 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[17\] -fixed false -x 562 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[14\] -fixed false -x 536 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[23\] -fixed false -x 447 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[10\] -fixed false -x 367 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[8\] -fixed false -x 697 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[21\] -fixed false -x 550 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[25\] -fixed false -x 934 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_373 -fixed false -x 799 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[26\] -fixed false -x 441 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[7\] -fixed false -x 56 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[29\] -fixed false -x 692 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c -fixed false -x 776 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[1\] -fixed false -x 871 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[2\] -fixed false -x 353 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_465 -fixed false -x 716 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_0\[0\] -fixed false -x 507 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6_1_RNO\[0\] -fixed false -x 710 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[12\] -fixed false -x 944 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1\[3\] -fixed false -x 465 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[20\] -fixed false -x 448 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[17\] -fixed false -x 306 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[16\] -fixed false -x 386 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiOOo -fixed false -x 49 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m19 -fixed false -x 131 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[2\] -fixed false -x 387 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m13 -fixed false -x 13 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[30\] -fixed false -x 849 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_2 -fixed false -x 755 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[6\] -fixed false -x 506 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[6\] -fixed false -x 407 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[12\] -fixed false -x 660 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[1\] -fixed false -x 123 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[0\] -fixed false -x 956 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_314 -fixed false -x 619 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/IilI1 -fixed false -x 294 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m116 -fixed false -x 221 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0\[4\] -fixed false -x 730 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[10\] -fixed false -x 73 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[10\] -fixed false -x 435 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[0\] -fixed false -x 38 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[11\] -fixed false -x 307 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_Ol0Oo -fixed false -x 286 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[9\] -fixed false -x 175 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv\[3\] -fixed false -x 729 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[8\] -fixed false -x 852 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[6\] -fixed false -x 513 -y 166
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full_0_sqmuxa -fixed false -x 398 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[24\] -fixed false -x 540 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_2_RNIEG8TB\[0\] -fixed false -x 658 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01\[2\] -fixed false -x 203 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[23\] -fixed false -x 892 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[21\] -fixed false -x 761 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO\[2\] -fixed false -x 428 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[15\] -fixed false -x 755 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[5\] -fixed false -x 824 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en\[0\] -fixed false -x 736 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[9\] -fixed false -x 299 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m21 -fixed false -x 46 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state62 -fixed false -x 522 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[1\] -fixed false -x 392 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1_0 -fixed false -x 125 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1\[8\] -fixed false -x 200 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[2\] -fixed false -x 306 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOol1_RNI8LGPL -fixed false -x 404 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[7\] -fixed false -x 310 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO\[0\] -fixed false -x 82 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[3\] -fixed false -x 54 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[13\] -fixed false -x 142 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[15\] -fixed false -x 728 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_6 -fixed false -x 393 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo263 -fixed false -x 56 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[3\] -fixed false -x 775 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[45\] -fixed false -x 536 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_194 -fixed false -x 699 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[10\] -fixed false -x 792 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[25\] -fixed false -x 400 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[6\] -fixed false -x 305 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u_2\[3\] -fixed false -x 906 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/IilI1 -fixed false -x 462 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_O0li1_1 -fixed false -x 126 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[8\] -fixed false -x 445 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_9 -fixed false -x 740 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[11\] -fixed false -x 380 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[10\] -fixed false -x 501 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[9\] -fixed false -x 381 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/m61_a1 -fixed false -x 825 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[11\] -fixed false -x 170 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[37\] -fixed false -x 630 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[17\] -fixed false -x 110 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[20\] -fixed false -x 717 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[14\] -fixed false -x 340 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[24\] -fixed false -x 382 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[8\] -fixed false -x 514 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_d_1_sqmuxa -fixed false -x 515 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[39\] -fixed false -x 656 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[2\] -fixed false -x 187 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[49\] -fixed false -x 505 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[8\] -fixed false -x 188 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[29\] -fixed false -x 472 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKY1\[0\] -fixed false -x 724 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[18\] -fixed false -x 718 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[0\] -fixed false -x 251 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[32\] -fixed false -x 486 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[7\] -fixed false -x 702 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[0\] -fixed false -x 807 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[25\] -fixed false -x 736 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_2 -fixed false -x 138 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un17_Oi1O1\[31\] -fixed false -x 405 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[2\] -fixed false -x 883 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[18\] -fixed false -x 656 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[0\] -fixed false -x 251 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[5\] -fixed false -x 164 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un75_I1Oi1 -fixed false -x 39 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/IilI1 -fixed false -x 401 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOiI1 -fixed false -x 337 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1128 -fixed false -x 667 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[12\] -fixed false -x 662 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[7\] -fixed false -x 248 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[6\] -fixed false -x 728 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_387 -fixed false -x 678 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_addr_align\[1\] -fixed false -x 823 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/l01l1_RNO -fixed false -x 384 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_10\[3\] -fixed false -x 729 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_places_1_.m8_e -fixed false -x 667 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[13\] -fixed false -x 899 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[26\] -fixed false -x 591 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[24\] -fixed false -x 944 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_at_flush_0_sqmuxa -fixed false -x 786 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[57\] -fixed false -x 540 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_lsu_stall_sw -fixed false -x 758 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[7\] -fixed false -x 451 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lli01_i_a2 -fixed false -x 114 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[20\] -fixed false -x 858 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[16\] -fixed false -x 384 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[12\] -fixed false -x 757 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_5\[0\] -fixed false -x 612 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[0\] -fixed false -x 850 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[7\] -fixed false -x 130 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_864 -fixed false -x 666 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[8\] -fixed false -x 822 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[15\] -fixed false -x 563 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_a1_0\[3\] -fixed false -x 749 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_2 -fixed false -x 500 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_ac0_3_0 -fixed false -x 497 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[21\] -fixed false -x 806 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[16\] -fixed false -x 862 -y 148
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[11\] -fixed false -x 382 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[6\] -fixed false -x 215 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[21\] -fixed false -x 805 -y 111
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/stop_strobe_1_sqmuxa_0_a2 -fixed false -x 479 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO\[1\] -fixed false -x 322 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIGCTP4\[7\] -fixed false -x 79 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[3\] -fixed false -x 427 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[11\] -fixed false -x 201 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[16\] -fixed false -x 966 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un145_lIlo1 -fixed false -x 178 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_226 -fixed false -x 697 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[35\] -fixed false -x 487 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[8\] -fixed false -x 62 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[16\] -fixed false -x 705 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[1\] -fixed false -x 415 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[18\] -fixed false -x 847 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[12\] -fixed false -x 759 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_rd_valid -fixed false -x 717 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un77_ool01 -fixed false -x 185 -y 213
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[2\] -fixed false -x 437 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[8\] -fixed false -x 429 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[1\] -fixed false -x 522 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Il111 -fixed false -x 99 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1o11_1 -fixed false -x 340 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[27\] -fixed false -x 905 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[5\] -fixed false -x 260 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto8_2 -fixed false -x 152 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_0_0 -fixed false -x 626 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mcause_sw_wr_sel_3 -fixed false -x 746 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[11\] -fixed false -x 241 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[8\] -fixed false -x 447 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_4_0 -fixed false -x 69 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[15\].BUFD_BLK -fixed false -x 534 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIJO8GO\[26\] -fixed false -x 862 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[13\] -fixed false -x 850 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m16 -fixed false -x 606 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[24\] -fixed false -x 969 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[10\] -fixed false -x 117 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_3 -fixed false -x 634 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1 -fixed false -x 795 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[35\] -fixed false -x 426 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[4\] -fixed false -x 696 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_5_1 -fixed false -x 670 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[15\] -fixed false -x 955 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_158 -fixed false -x 641 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff\[1\] -fixed false -x 701 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un28_il0Oo_1 -fixed false -x 154 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[2\] -fixed false -x 55 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[6\] -fixed false -x 375 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2\[23\] -fixed false -x 125 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzerott_m2_0_a2 -fixed false -x 482 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_544 -fixed false -x 679 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0ii1 -fixed false -x 132 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff15_0 -fixed false -x 806 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel\[1\] -fixed false -x 549 -y 151
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cnt_5_1.CO1 -fixed false -x 26 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[8\] -fixed false -x 419 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_8 -fixed false -x 46 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_2\[9\] -fixed false -x 57 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[26\] -fixed false -x 544 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_475 -fixed false -x 691 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_420 -fixed false -x 729 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1290 -fixed false -x 571 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[11\] -fixed false -x 232 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[6\] -fixed false -x 447 -y 196
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_11 -fixed false -x 7 -y 164
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_202 -fixed false -x 677 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[26\] -fixed false -x 933 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[15\] -fixed false -x 814 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[20\] -fixed false -x 400 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1210 -fixed false -x 670 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[21\] -fixed false -x 934 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[12\] -fixed false -x 574 -y 154
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast\[6\] -fixed false -x 489 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[4\] -fixed false -x 135 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/o0IIo -fixed false -x 272 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2\[1\] -fixed false -x 722 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo\[0\] -fixed false -x 51 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[3\] -fixed false -x 239 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[6\] -fixed false -x 295 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val\[2\] -fixed false -x 720 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[8\] -fixed false -x 882 -y 139
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_7 -fixed false -x 498 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_0_sqmuxa_0_a2 -fixed false -x 199 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO -fixed false -x 854 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_968 -fixed false -x 750 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_0_sqmuxa_0_a3_0 -fixed false -x 201 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un77_lIlo1lto15_4 -fixed false -x 143 -y 177
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_o9 -fixed false -x 513 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[24\] -fixed false -x 760 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[21\] -fixed false -x 386 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_o1i11_0_a2 -fixed false -x 343 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[20\] -fixed false -x 898 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_en_retr -fixed false -x 788 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_6 -fixed false -x 161 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[8\] -fixed false -x 187 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[31\] -fixed false -x 837 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_1397_i -fixed false -x 758 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[11\] -fixed false -x 246 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2 -fixed false -x 271 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un49_i11Io\[2\] -fixed false -x 440 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1\[12\] -fixed false -x 859 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[14\] -fixed false -x 713 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IiOOo -fixed false -x 59 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[7\] -fixed false -x 405 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[29\] -fixed false -x 793 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[28\] -fixed false -x 543 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[27\] -fixed false -x 849 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo0o1_0_o2 -fixed false -x 91 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[8\] -fixed false -x 129 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[5\] -fixed false -x 766 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oiol1 -fixed false -x 280 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[18\] -fixed false -x 659 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[15\] -fixed false -x 226 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OOOl1 -fixed false -x 440 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ioIO1 -fixed false -x 153 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[26\] -fixed false -x 939 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[6\] -fixed false -x 243 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_sw_enable_2 -fixed false -x 757 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oll01 -fixed false -x 185 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[29\] -fixed false -x 836 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[6\] -fixed false -x 854 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[12\] -fixed false -x 273 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[25\] -fixed false -x 421 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1\[0\] -fixed false -x 98 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[5\] -fixed false -x 79 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[7\] -fixed false -x 229 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[11\] -fixed false -x 456 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4\[8\] -fixed false -x 142 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[30\] -fixed false -x 869 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[2\] -fixed false -x 969 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_15_RNI63LRM -fixed false -x 35 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_761 -fixed false -x 632 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[16\] -fixed false -x 535 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[12\] -fixed false -x 347 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/un1_iOI01_1_0_a3_i -fixed false -x 381 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oooo1 -fixed false -x 61 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[3\] -fixed false -x 199 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO_0\[1\] -fixed false -x 615 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m5 -fixed false -x 58 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_667 -fixed false -x 608 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[21\] -fixed false -x 684 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_766 -fixed false -x 667 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[30\] -fixed false -x 653 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[1\] -fixed false -x 235 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[4\] -fixed false -x 86 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1006 -fixed false -x 770 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[14\] -fixed false -x 566 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[14\] -fixed false -x 678 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1o11 -fixed false -x 297 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[1\] -fixed false -x 517 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/m_env_call -fixed false -x 751 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[14\] -fixed false -x 75 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[3\] -fixed false -x 752 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[7\] -fixed false -x 573 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo_RNIR06IC -fixed false -x 274 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_halt_ack -fixed false -x 778 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[17\] -fixed false -x 47 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[31\] -fixed false -x 726 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[0\] -fixed false -x 777 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[8\] -fixed false -x 955 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[6\] -fixed false -x 348 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_874 -fixed false -x 644 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[1\] -fixed false -x 930 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un31_I1Oi1_2 -fixed false -x 55 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1193 -fixed false -x 643 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[1\] -fixed false -x 427 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int\[0\] -fixed false -x 801 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1113 -fixed false -x 607 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[29\] -fixed false -x 702 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[1\] -fixed false -x 156 -y 204
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[5\] -fixed false -x 501 -y 97
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/empty_RNO -fixed false -x 393 -y 237
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc4 -fixed false -x 41 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_543 -fixed false -x 727 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[7\] -fixed false -x 575 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVNTQ8\[27\] -fixed false -x 655 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].un30_req_buff_load_os -fixed false -x 807 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[0\] -fixed false -x 734 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un71_ool01 -fixed false -x 199 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[8\] -fixed false -x 512 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_0_3_i\[0\] -fixed false -x 648 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[10\] -fixed false -x 164 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[7\] -fixed false -x 261 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[1\] -fixed false -x 537 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[34\] -fixed false -x 904 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first_RNO_0 -fixed false -x 510 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/wr_en_data -fixed false -x 725 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_RNO\[1\] -fixed false -x 358 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[7\] -fixed false -x 56 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[16\] -fixed false -x 850 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[8\] -fixed false -x 409 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[5\] -fixed false -x 390 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[3\] -fixed false -x 715 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0IIo_i_m3 -fixed false -x 131 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oiOi1 -fixed false -x 175 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_3_RNIQG4NV -fixed false -x 36 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[29\] -fixed false -x 426 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[2\] -fixed false -x 802 -y 120
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[2\] -fixed false -x 564 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[14\] -fixed false -x 920 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[22\] -fixed false -x 555 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[21\] -fixed false -x 112 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[6\] -fixed false -x 444 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_OOoi1_0_a3 -fixed false -x 187 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[16\] -fixed false -x 247 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mcause_excpt_code_wr_data\[4\] -fixed false -x 726 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[6\] -fixed false -x 129 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[1\] -fixed false -x 86 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m5 -fixed false -x 47 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[15\] -fixed false -x 344 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_797 -fixed false -x 752 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/un1_Ioli0_1_0 -fixed false -x 277 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[1\] -fixed false -x 115 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[7\] -fixed false -x 104 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO -fixed false -x 182 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[21\] -fixed false -x 877 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[19\] -fixed false -x 762 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[6\] -fixed false -x 195 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[25\] -fixed false -x 228 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNI7606A3 -fixed false -x 798 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[7\] -fixed false -x 35 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe -fixed false -x 523 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_22 -fixed false -x 84 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[20\] -fixed false -x 815 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_8\[10\] -fixed false -x 308 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[13\] -fixed false -x 129 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[25\] -fixed false -x 846 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[27\] -fixed false -x 932 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIiO1 -fixed false -x 226 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1_2 -fixed false -x 161 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[32\] -fixed false -x 125 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[29\] -fixed false -x 793 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[7\] -fixed false -x 722 -y 121
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_RNI5PDQ7\[2\] -fixed false -x 424 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[5\] -fixed false -x 466 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001\[2\] -fixed false -x 84 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[14\] -fixed false -x 571 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IiII1 -fixed false -x 228 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[11\] -fixed false -x 472 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[4\] -fixed false -x 367 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0\[4\] -fixed false -x 17 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[7\] -fixed false -x 321 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[26\] -fixed false -x 713 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m16_0 -fixed false -x 265 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[17\] -fixed false -x 305 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[4\] -fixed false -x 97 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_6\[0\] -fixed false -x 100 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII110 -fixed false -x 488 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[0\] -fixed false -x 315 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_978 -fixed false -x 703 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1240 -fixed false -x 711 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[1\] -fixed false -x 405 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un8_l00o1_2 -fixed false -x 119 -y 195
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[29\].BUFD_BLK -fixed false -x 548 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_22_0_RNO -fixed false -x 835 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_899 -fixed false -x 667 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1082 -fixed false -x 657 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo_RNO -fixed false -x 16 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[2\] -fixed false -x 102 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_2 -fixed false -x 677 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_a3_0 -fixed false -x 790 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un32_o1Oi1 -fixed false -x 83 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6_4 -fixed false -x 789 -y 105
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[2\] -fixed false -x 82 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[5\] -fixed false -x 732 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[0\] -fixed false -x 336 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[0\] -fixed false -x 788 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1028 -fixed false -x 710 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[8\] -fixed false -x 100 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_or\[0\] -fixed false -x 743 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/IilI1_RNO -fixed false -x 464 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO\[3\] -fixed false -x 128 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[9\] -fixed false -x 724 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[2\] -fixed false -x 276 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[6\] -fixed false -x 403 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[23\] -fixed false -x 598 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[7\] -fixed false -x 265 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI7H0P9\[4\] -fixed false -x 105 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5s2 -fixed false -x 721 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[28\] -fixed false -x 943 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_alu_op_sel_ex7_RNIV8T8M2 -fixed false -x 770 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[14\] -fixed false -x 652 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[22\] -fixed false -x 715 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[15\] -fixed false -x 849 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[3\] -fixed false -x 286 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[19\] -fixed false -x 463 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l0Ol1 -fixed false -x 414 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oioOo -fixed false -x 174 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_0_0 -fixed false -x 53 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_i_m3\[1\] -fixed false -x 348 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[27\] -fixed false -x 922 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[28\] -fixed false -x 955 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_3 -fixed false -x 627 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3\[7\] -fixed false -x 905 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto15 -fixed false -x 141 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m6 -fixed false -x 20 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[28\] -fixed false -x 112 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_546 -fixed false -x 740 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[15\] -fixed false -x 179 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[20\] -fixed false -x 671 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[10\] -fixed false -x 467 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[3\] -fixed false -x 544 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1_x4\[10\] -fixed false -x 131 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[3\] -fixed false -x 284 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[8\] -fixed false -x 171 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[3\] -fixed false -x 148 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv\[10\] -fixed false -x 716 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[0\] -fixed false -x 858 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[20\] -fixed false -x 943 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[2\] -fixed false -x 471 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4\[24\] -fixed false -x 138 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[1\] -fixed false -x 365 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_771 -fixed false -x 666 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/m61_a0_0 -fixed false -x 812 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_30_0_RNO -fixed false -x 821 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[23\] -fixed false -x 829 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[8\] -fixed false -x 52 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_0\[4\] -fixed false -x 22 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[20\] -fixed false -x 594 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[2\] -fixed false -x 70 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re -fixed false -x 530 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[10\] -fixed false -x 17 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[12\] -fixed false -x 96 -y 226
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_i_a2_0\[3\] -fixed false -x 420 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28\[11\] -fixed false -x 227 -y 168
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[14\] -fixed false -x 384 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[9\] -fixed false -x 299 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_1_0 -fixed false -x 831 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[10\] -fixed false -x 499 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[5\] -fixed false -x 149 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[27\] -fixed false -x 902 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[15\] -fixed false -x 708 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_677 -fixed false -x 811 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_6 -fixed false -x 15 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[14\] -fixed false -x 761 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[5\] -fixed false -x 687 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[27\] -fixed false -x 482 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_776 -fixed false -x 728 -y 198
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[20\] -fixed false -x 398 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2\[30\] -fixed false -x 971 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3\[12\] -fixed false -x 858 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[4\] -fixed false -x 962 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[24\].BUFD_BLK -fixed false -x 547 -y 114
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE_0_sqmuxa -fixed false -x 34 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[12\] -fixed false -x 478 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[30\] -fixed false -x 225 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1O11 -fixed false -x 85 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[8\] -fixed false -x 365 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[10\] -fixed false -x 946 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[12\] -fixed false -x 125 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[1\] -fixed false -x 32 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[1\] -fixed false -x 469 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[10\] -fixed false -x 814 -y 114
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_en_0_a2_0_o2 -fixed false -x 405 -y 234
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3\[1\] -fixed false -x 57 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_2\[2\] -fixed false -x 860 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[23\] -fixed false -x 440 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[7\] -fixed false -x 308 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[16\] -fixed false -x 275 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[11\] -fixed false -x 475 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1171 -fixed false -x 666 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[16\] -fixed false -x 674 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[13\] -fixed false -x 291 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[14\] -fixed false -x 78 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_2 -fixed false -x 19 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[9\] -fixed false -x 968 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[2\] -fixed false -x 398 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IoIOo -fixed false -x 20 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0_0 -fixed false -x 644 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc5 -fixed false -x 476 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io -fixed false -x 70 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM\[0\] -fixed false -x 94 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[6\] -fixed false -x 236 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2_1_0 -fixed false -x 56 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[19\] -fixed false -x 298 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[0\] -fixed false -x 518 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[16\] -fixed false -x 445 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick -fixed false -x 573 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[30\] -fixed false -x 860 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[14\] -fixed false -x 498 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1\[4\] -fixed false -x 140 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[16\] -fixed false -x 593 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_2_0 -fixed false -x 706 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s\[2\] -fixed false -x 520 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[10\] -fixed false -x 307 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[11\] -fixed false -x 298 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un47_ool01 -fixed false -x 200 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[27\] -fixed false -x 752 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[5\] -fixed false -x 401 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_733 -fixed false -x 719 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1143 -fixed false -x 727 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[12\] -fixed false -x 942 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_269 -fixed false -x 785 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[4\] -fixed false -x 69 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[4\] -fixed false -x 122 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_u -fixed false -x 575 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[27\] -fixed false -x 851 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1i11 -fixed false -x 308 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[2\] -fixed false -x 110 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[16\] -fixed false -x 351 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[12\] -fixed false -x 427 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[15\] -fixed false -x 764 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_3 -fixed false -x 333 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[19\] -fixed false -x 87 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m5 -fixed false -x 45 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[38\] -fixed false -x 912 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[9\] -fixed false -x 513 -y 174
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_ac0_7_a0 -fixed false -x 45 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[4\] -fixed false -x 720 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[11\] -fixed false -x 867 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNI79ENN1 -fixed false -x 905 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[21\] -fixed false -x 684 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[7\] -fixed false -x 90 -y 190
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE17 -fixed false -x 18 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[26\] -fixed false -x 597 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0_a3_1\[15\] -fixed false -x 211 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O0I01 -fixed false -x 207 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[34\] -fixed false -x 462 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[23\] -fixed false -x 707 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff\[2\] -fixed false -x 692 -y 118
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[13\].BUFD_BLK -fixed false -x 489 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_3\[4\] -fixed false -x 260 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3_1 -fixed false -x 706 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_pulse -fixed false -x 455 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/UCLKMUX1/clkout -fixed false -x 532 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iliO1 -fixed false -x 194 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[11\] -fixed false -x 393 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[28\] -fixed false -x 751 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_Ilio1 -fixed false -x 56 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[12\] -fixed false -x 737 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[24\] -fixed false -x 661 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv\[0\] -fixed false -x 775 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_519 -fixed false -x 736 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[11\] -fixed false -x 236 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[11\] -fixed false -x 591 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fetch_valid_de_0 -fixed false -x 694 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[35\] -fixed false -x 314 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_1 -fixed false -x 226 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[1\] -fixed false -x 170 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[0\] -fixed false -x 427 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[26\] -fixed false -x 596 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[8\] -fixed false -x 364 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[16\] -fixed false -x 701 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_4_0_RNO -fixed false -x 801 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_0\[0\] -fixed false -x 352 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[2\] -fixed false -x 890 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[27\] -fixed false -x 889 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1090 -fixed false -x 621 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[8\] -fixed false -x 235 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_0 -fixed false -x 265 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[20\] -fixed false -x 466 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[9\] -fixed false -x 722 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[4\] -fixed false -x 86 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[1\] -fixed false -x 188 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1010 -fixed false -x 639 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[6\] -fixed false -x 327 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[30\] -fixed false -x 550 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[2\] -fixed false -x 333 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_625 -fixed false -x 666 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[6\] -fixed false -x 97 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[3\] -fixed false -x 535 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[4\] -fixed false -x 419 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[39\] -fixed false -x 914 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[24\] -fixed false -x 682 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_8 -fixed false -x 227 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oloo1 -fixed false -x 106 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO019_1 -fixed false -x 367 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_650 -fixed false -x 704 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_wr_en -fixed false -x 728 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiIO1_Z -fixed false -x 278 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/un1_iOI01_1_i_0 -fixed false -x 242 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[22\] -fixed false -x 422 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[16\] -fixed false -x 474 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[11\] -fixed false -x 730 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[41\] -fixed false -x 538 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_trigger_wr_hzd_de_RNI41LM3 -fixed false -x 741 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[10\] -fixed false -x 418 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[13\] -fixed false -x 75 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa_1 -fixed false -x 525 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg\[0\] -fixed false -x 743 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_895 -fixed false -x 701 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_0_sqmuxa_1_i_0_o3_0 -fixed false -x 779 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un18_Oo1Io_0 -fixed false -x 404 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[5\] -fixed false -x 527 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[7\] -fixed false -x 297 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[9\] -fixed false -x 860 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[31\] -fixed false -x 778 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a2\[24\] -fixed false -x 738 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0\[0\] -fixed false -x 335 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[18\] -fixed false -x 247 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_RNO -fixed false -x 805 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[1\] -fixed false -x 256 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/IilI1_RNO -fixed false -x 255 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_458 -fixed false -x 656 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2\[9\] -fixed false -x 152 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state_1_sqmuxa -fixed false -x 558 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_0\[18\] -fixed false -x 645 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIDG6GO\[14\] -fixed false -x 864 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_1 -fixed false -x 105 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex -fixed false -x 760 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOi11 -fixed false -x 370 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_5_0 -fixed false -x 698 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[10\] -fixed false -x 514 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[9\] -fixed false -x 723 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[2\] -fixed false -x 178 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_wfi_retr -fixed false -x 777 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_0\[15\] -fixed false -x 165 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_0_a4_RNO\[3\] -fixed false -x 900 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[7\] -fixed false -x 85 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[24\] -fixed false -x 845 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_360 -fixed false -x 630 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1296 -fixed false -x 665 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 -fixed false -x 233 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[1\] -fixed false -x 247 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[10\] -fixed false -x 429 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_2 -fixed false -x 120 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a3_0\[0\] -fixed false -x 641 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[16\] -fixed false -x 382 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[16\] -fixed false -x 117 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[1\] -fixed false -x 728 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[14\] -fixed false -x 446 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[3\] -fixed false -x 535 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_d_RNI12TLE5 -fixed false -x 800 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[8\] -fixed false -x 304 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1216 -fixed false -x 643 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[0\] -fixed false -x 766 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[27\] -fixed false -x 856 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10_RNIT2V2H -fixed false -x 44 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[8\] -fixed false -x 182 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[19\] -fixed false -x 695 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I01Oo\[0\] -fixed false -x 146 -y 154
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE_9\[10\] -fixed false -x 33 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3\[13\] -fixed false -x 116 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[4\] -fixed false -x 570 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[8\] -fixed false -x 535 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[3\] -fixed false -x 574 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[13\] -fixed false -x 102 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[3\] -fixed false -x 365 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[14\] -fixed false -x 491 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[10\] -fixed false -x 507 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1011 -fixed false -x 251 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[2\] -fixed false -x 763 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[10\] -fixed false -x 123 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_emi_req_os_at_flush\[1\] -fixed false -x 790 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[27\] -fixed false -x 591 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_1_sqmuxa_i_0 -fixed false -x 466 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[10\] -fixed false -x 155 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[7\] -fixed false -x 48 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[2\] -fixed false -x 54 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/IilI1 -fixed false -x 256 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa -fixed false -x 512 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[6\] -fixed false -x 208 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[6\] -fixed false -x 142 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[13\] -fixed false -x 111 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[8\] -fixed false -x 296 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[6\] -fixed false -x 77 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIBFA84\[25\] -fixed false -x 932 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[30\] -fixed false -x 800 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[9\] -fixed false -x 235 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[8\] -fixed false -x 536 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[13\] -fixed false -x 518 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[27\] -fixed false -x 421 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_84\[11\] -fixed false -x 196 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[9\] -fixed false -x 267 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/l0IO1 -fixed false -x 231 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_6 -fixed false -x 667 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_715 -fixed false -x 602 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[22\] -fixed false -x 405 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14_1\[17\] -fixed false -x 391 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[6\] -fixed false -x 133 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2 -fixed false -x 393 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[0\] -fixed false -x 882 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[18\] -fixed false -x 434 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[50\] -fixed false -x 926 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[5\] -fixed false -x 348 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[2\] -fixed false -x 279 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa -fixed false -x 502 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[27\] -fixed false -x 706 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[7\] -fixed false -x 702 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/un1_Ioli0_1_0 -fixed false -x 315 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[32\] -fixed false -x 313 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[8\] -fixed false -x 446 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[24\] -fixed false -x 835 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[2\] -fixed false -x 722 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[14\] -fixed false -x 734 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[27\] -fixed false -x 741 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_0_a3_0\[29\] -fixed false -x 359 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[23\] -fixed false -x 446 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[13\] -fixed false -x 708 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[4\] -fixed false -x 698 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un41_ool01 -fixed false -x 184 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_165 -fixed false -x 702 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold -fixed false -x 782 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_279 -fixed false -x 643 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo\[8\] -fixed false -x 350 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[1\] -fixed false -x 32 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[29\] -fixed false -x 592 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0i01 -fixed false -x 98 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[20\] -fixed false -x 655 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[3\] -fixed false -x 509 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[19\] -fixed false -x 793 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[8\] -fixed false -x 884 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINFFFD\[5\] -fixed false -x 647 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[27\] -fixed false -x 673 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_385 -fixed false -x 590 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[12\] -fixed false -x 619 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_trap_ret_ex -fixed false -x 733 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0\[1\] -fixed false -x 348 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x2_1\[2\] -fixed false -x 115 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[6\] -fixed false -x 365 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[4\] -fixed false -x 180 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001\[2\] -fixed false -x 75 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv\[11\] -fixed false -x 644 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlOI1_RNO -fixed false -x 360 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[19\] -fixed false -x 924 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[9\] -fixed false -x 197 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_26\[32\] -fixed false -x 468 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[28\] -fixed false -x 478 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_1 -fixed false -x 687 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[20\] -fixed false -x 533 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[0\] -fixed false -x 104 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[3\] -fixed false -x 763 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1\[0\] -fixed false -x 142 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m27 -fixed false -x 55 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1235 -fixed false -x 765 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/un1_iOI01_1_i_0 -fixed false -x 359 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_3 -fixed false -x 735 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_0\[2\] -fixed false -x 99 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_29 -fixed false -x 764 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[6\] -fixed false -x 261 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[6\] -fixed false -x 373 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[7\] -fixed false -x 502 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_618 -fixed false -x 688 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un331_lIlo1_1 -fixed false -x 171 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[0\] -fixed false -x 417 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[32\] -fixed false -x 627 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[6\] -fixed false -x 63 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[8\] -fixed false -x 64 -y 228
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive_0_sqmuxa -fixed false -x 508 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_1 -fixed false -x 164 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[9\] -fixed false -x 902 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[10\] -fixed false -x 407 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_649 -fixed false -x 655 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[26\] -fixed false -x 120 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1I11_RNIL0RR8 -fixed false -x 176 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[9\] -fixed false -x 438 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[27\] -fixed false -x 659 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[34\] -fixed false -x 474 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[18\] -fixed false -x 968 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[20\] -fixed false -x 907 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[6\] -fixed false -x 513 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[3\] -fixed false -x 716 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_iIOl1_2_0 -fixed false -x 355 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[16\] -fixed false -x 463 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[7\] -fixed false -x 80 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_op_sel_ex -fixed false -x 748 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[25\] -fixed false -x 115 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_IoIi1_i_a2 -fixed false -x 200 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[6\] -fixed false -x 179 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_dataerr -fixed false -x 512 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[28\] -fixed false -x 462 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_strb\[0\] -fixed false -x 766 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[6\] -fixed false -x 946 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[7\] -fixed false -x 637 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_l_En_0_a2 -fixed false -x 502 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[9\] -fixed false -x 895 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[6\] -fixed false -x 663 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.IloIo -fixed false -x 474 -y 175
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[2\] -fixed false -x 518 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[24\] -fixed false -x 827 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3\[0\] -fixed false -x 641 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[1\] -fixed false -x 194 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[1\] -fixed false -x 151 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1040 -fixed false -x 653 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_703 -fixed false -x 665 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIB7I4J\[12\] -fixed false -x 603 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[16\] -fixed false -x 471 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1_cZ\[5\] -fixed false -x 350 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[0\] -fixed false -x 793 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[19\] -fixed false -x 465 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIEP2E54 -fixed false -x 253 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[9\] -fixed false -x 321 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[20\] -fixed false -x 477 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[16\] -fixed false -x 471 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m14 -fixed false -x 46 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/dbreakpoint_iv -fixed false -x 750 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1 -fixed false -x 113 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[5\] -fixed false -x 853 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_0 -fixed false -x 821 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un8_req_addr_mux\[1\] -fixed false -x 637 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc6 -fixed false -x 56 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_11 -fixed false -x 738 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[15\] -fixed false -x 126 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_q1 -fixed false -x 535 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_2 -fixed false -x 945 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[24\] -fixed false -x 880 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[1\] -fixed false -x 283 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_497 -fixed false -x 758 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_370 -fixed false -x 654 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q\[4\] -fixed false -x 573 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[20\] -fixed false -x 148 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_6 -fixed false -x 78 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m10 -fixed false -x 83 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol117 -fixed false -x 334 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_0 -fixed false -x 64 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[1\] -fixed false -x 218 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[6\] -fixed false -x 826 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int35_0 -fixed false -x 782 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2125.rv32c_dec_mnemonic2125_2 -fixed false -x 645 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[28\] -fixed false -x 850 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write14 -fixed false -x 458 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de -fixed false -x 715 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[5\] -fixed false -x 792 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_error_resp.gen_buff_loop\[0\].buff_entry_error_resp_ram3__RNO\[0\] -fixed false -x 663 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0\[0\] -fixed false -x 651 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i_o2 -fixed false -x 904 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_2\[15\] -fixed false -x 615 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[15\] -fixed false -x 799 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[22\] -fixed false -x 66 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2_0\[8\] -fixed false -x 356 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[5\] -fixed false -x 452 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1306 -fixed false -x 693 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47_2 -fixed false -x 755 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_c_0_a0_RNIDK2M81 -fixed false -x 775 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[1\] -fixed false -x 53 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_4 -fixed false -x 100 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1246 -fixed false -x 662 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI9NTEQ\[12\] -fixed false -x 105 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[46\] -fixed false -x 505 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_2 -fixed false -x 509 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[10\] -fixed false -x 942 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1\[2\] -fixed false -x 476 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[3\] -fixed false -x 97 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[29\] -fixed false -x 869 -y 138
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[4\] -fixed false -x 481 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[7\] -fixed false -x 396 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi1o1_i_a2 -fixed false -x 105 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ill11 -fixed false -x 254 -y 184
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[4\] -fixed false -x 378 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_1_242_a2 -fixed false -x 319 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[7\] -fixed false -x 55 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[19\] -fixed false -x 708 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_5 -fixed false -x 243 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2 -fixed false -x 32 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[7\] -fixed false -x 445 -y 196
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_7 -fixed false -x 487 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11\[9\] -fixed false -x 116 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[28\] -fixed false -x 398 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_21 -fixed false -x 718 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[3\] -fixed false -x 649 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[7\] -fixed false -x 265 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[11\] -fixed false -x 242 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[27\] -fixed false -x 912 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[1\] -fixed false -x 847 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[12\] -fixed false -x 607 -y 139
|
|
set_location -inst_name SSDetect_0/is_match_0.un3_is_match_2 -fixed false -x 12 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[22\] -fixed false -x 736 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[3\] -fixed false -x 177 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state_valid\[1\] -fixed false -x 799 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[29\] -fixed false -x 837 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/IilI1 -fixed false -x 246 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_3 -fixed false -x 219 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[0\] -fixed false -x 504 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m10 -fixed false -x 117 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_m_env_call_ex -fixed false -x 755 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[4\] -fixed false -x 356 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iooi1 -fixed false -x 274 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.N_5_i -fixed false -x 86 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0_RNO\[5\] -fixed false -x 79 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_valid_de_2 -fixed false -x 709 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[28\] -fixed false -x 469 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_IOOl1_2_0 -fixed false -x 423 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/next_buff_valid\[1\] -fixed false -x 764 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Io1Io -fixed false -x 398 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[4\] -fixed false -x 94 -y 207
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/iPSELS\[2\] -fixed false -x 476 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_hword_high_only_req\[2\] -fixed false -x 884 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oool1 -fixed false -x 395 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[21\] -fixed false -x 876 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[46\] -fixed false -x 909 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_175 -fixed false -x 691 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_2 -fixed false -x 781 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_3_0 -fixed false -x 804 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m66 -fixed false -x 286 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_269_i -fixed false -x 286 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_4 -fixed false -x 196 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1 -fixed false -x 31 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_error_sig -fixed false -x 800 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_0\[0\] -fixed false -x 33 -y 201
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full6_5 -fixed false -x 394 -y 255
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[12\] -fixed false -x 502 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[4\] -fixed false -x 319 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[18\] -fixed false -x 95 -y 222
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_RNO\[3\] -fixed false -x 493 -y 96
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[3\].BUFD_BLK -fixed false -x 536 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_oIiO1 -fixed false -x 280 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[23\] -fixed false -x 910 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO_0 -fixed false -x 849 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II0l1\[0\] -fixed false -x 449 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4\[2\] -fixed false -x 523 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel_1_1 -fixed false -x 717 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[16\] -fixed false -x 195 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOIi1 -fixed false -x 183 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[5\] -fixed false -x 923 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[23\] -fixed false -x 765 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3\[2\] -fixed false -x 141 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[6\] -fixed false -x 68 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iiOi1 -fixed false -x 175 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[0\] -fixed false -x 424 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/un1_iOI01_1_i_0 -fixed false -x 292 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[9\] -fixed false -x 242 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[7\] -fixed false -x 310 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[3\] -fixed false -x 360 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt\[2\] -fixed false -x 737 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[16\] -fixed false -x 396 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[30\] -fixed false -x 736 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[2\] -fixed false -x 75 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[2\] -fixed false -x 886 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_223 -fixed false -x 715 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[33\] -fixed false -x 901 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[6\] -fixed false -x 48 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_2_0_0 -fixed false -x 705 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[15\] -fixed false -x 299 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold\[0\] -fixed false -x 573 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_a1\[3\] -fixed false -x 748 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_120 -fixed false -x 753 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001\[2\] -fixed false -x 73 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[6\] -fixed false -x 81 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[15\] -fixed false -x 383 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un7_cpu_d_resp_error_rd_4 -fixed false -x 799 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[17\] -fixed false -x 908 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[15\] -fixed false -x 464 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIIOo -fixed false -x 40 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41_cZ\[7\] -fixed false -x 256 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un1_Oo1Io -fixed false -x 403 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[15\] -fixed false -x 598 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[31\] -fixed false -x 597 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/count_en_0_a3 -fixed false -x 809 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_RNO -fixed false -x 427 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[6\] -fixed false -x 273 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[2\] -fixed false -x 507 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIJM6GO\[17\] -fixed false -x 903 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff_RNO -fixed false -x 727 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[24\] -fixed false -x 471 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[19\] -fixed false -x 928 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1107 -fixed false -x 701 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[6\] -fixed false -x 406 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z\[1\] -fixed false -x 319 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_0 -fixed false -x 104 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[2\] -fixed false -x 501 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIio1 -fixed false -x 61 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[10\] -fixed false -x 449 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[6\] -fixed false -x 398 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[7\] -fixed false -x 102 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[15\] -fixed false -x 55 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[8\] -fixed false -x 356 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[15\] -fixed false -x 345 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_3 -fixed false -x 691 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[5\] -fixed false -x 704 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[5\] -fixed false -x 677 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[6\] -fixed false -x 522 -y 160
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[1\] -fixed false -x 398 -y 256
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIDVFUI\[5\] -fixed false -x 906 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[16\] -fixed false -x 834 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_710 -fixed false -x 642 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[0\] -fixed false -x 197 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[10\] -fixed false -x 87 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_181 -fixed false -x 619 -y 168
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_ns_0_0_m2\[0\] -fixed false -x 15 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_1\[3\] -fixed false -x 896 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[0\] -fixed false -x 393 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[14\] -fixed false -x 879 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[8\] -fixed false -x 139 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[9\] -fixed false -x 836 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_2\[29\] -fixed false -x 429 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1 -fixed false -x 506 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[20\] -fixed false -x 806 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[1\] -fixed false -x 823 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[6\] -fixed false -x 339 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data_1_3\[7\] -fixed false -x 831 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[13\] -fixed false -x 537 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[9\] -fixed false -x 369 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr\[0\] -fixed false -x 756 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIIIo -fixed false -x 137 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow_1_sqmuxa_i -fixed false -x 473 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[6\] -fixed false -x 234 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[21\] -fixed false -x 659 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[16\] -fixed false -x 861 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[0\] -fixed false -x 350 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_mux_sel_ex\[0\] -fixed false -x 784 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[7\] -fixed false -x 87 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[13\] -fixed false -x 779 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s\[5\] -fixed false -x 527 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[3\] -fixed false -x 751 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_1\[42\] -fixed false -x 133 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[22\] -fixed false -x 450 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2\[0\] -fixed false -x 319 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[1\] -fixed false -x 408 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_382 -fixed false -x 632 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/li1o1 -fixed false -x 102 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[25\] -fixed false -x 674 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[27\] -fixed false -x 876 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[7\] -fixed false -x 517 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_0_a2_0_2 -fixed false -x 837 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[23\] -fixed false -x 764 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[35\] -fixed false -x 465 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_at_flush\[1\] -fixed false -x 782 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIM3L9D -fixed false -x 784 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[1\] -fixed false -x 306 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[8\] -fixed false -x 921 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_71\[11\] -fixed false -x 271 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_ioIO1 -fixed false -x 145 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un5_lsu_emi_req_rd_byte_en_RNI2K78S -fixed false -x 740 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[30\] -fixed false -x 956 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[17\] -fixed false -x 358 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_1_0 -fixed false -x 163 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIPOET22\[0\] -fixed false -x 27 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1_1_1\[7\] -fixed false -x 91 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM\[3\] -fixed false -x 46 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[9\] -fixed false -x 967 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_27\[10\] -fixed false -x 286 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oi0i1 -fixed false -x 179 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[2\] -fixed false -x 754 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_4 -fixed false -x 68 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[3\] -fixed false -x 383 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0 -fixed false -x 84 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[23\] -fixed false -x 680 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2\[0\] -fixed false -x 644 -y 120
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2\[0\] -fixed false -x 374 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0_18\[22\] -fixed false -x 260 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[13\] -fixed false -x 716 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[6\] -fixed false -x 68 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1 -fixed false -x 77 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_alu_op_sel_ex7 -fixed false -x 778 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo_RNO\[0\] -fixed false -x 124 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_early\[0\] -fixed false -x 728 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1\[0\] -fixed false -x 130 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_984 -fixed false -x 665 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNILFFGI\[8\] -fixed false -x 482 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[6\] -fixed false -x 728 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[13\] -fixed false -x 374 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un203_I1Oi1_2_0 -fixed false -x 66 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0\[0\] -fixed false -x 141 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_2\[4\] -fixed false -x 127 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[14\] -fixed false -x 487 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[36\] -fixed false -x 913 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[8\] -fixed false -x 83 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[27\] -fixed false -x 849 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[1\] -fixed false -x 338 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3\[8\] -fixed false -x 857 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex_1\[0\] -fixed false -x 751 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0\[4\] -fixed false -x 693 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[0\] -fixed false -x 820 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_6\[1\] -fixed false -x 784 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun -fixed false -x 537 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[25\] -fixed false -x 759 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/IilI1 -fixed false -x 278 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_o2_1 -fixed false -x 117 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_83 -fixed false -x 655 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[11\] -fixed false -x 137 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[30\] -fixed false -x 687 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[6\] -fixed false -x 448 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIUJ7VA\[12\] -fixed false -x 658 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_858 -fixed false -x 774 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ol111 -fixed false -x 102 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftBP_ne_0 -fixed false -x 559 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[23\] -fixed false -x 555 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38_1_RNINTK4B3 -fixed false -x 769 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_RNO_1\[0\] -fixed false -x 753 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[8\] -fixed false -x 878 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[31\] -fixed false -x 399 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted\[0\] -fixed false -x 849 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_3\[5\] -fixed false -x 127 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[14\] -fixed false -x 134 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[26\] -fixed false -x 490 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[9\] -fixed false -x 379 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[0\] -fixed false -x 838 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_64\[11\] -fixed false -x 336 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2_RNIR49V42 -fixed false -x 821 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[2\] -fixed false -x 204 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_req_ready_0_o2 -fixed false -x 664 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_230 -fixed false -x 652 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[3\] -fixed false -x 525 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[16\] -fixed false -x 344 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[14\] -fixed false -x 383 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[0\] -fixed false -x 220 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[17\] -fixed false -x 91 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[6\] -fixed false -x 249 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[26\] -fixed false -x 901 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[3\] -fixed false -x 689 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[39\] -fixed false -x 355 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[16\] -fixed false -x 606 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[30\] -fixed false -x 414 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[36\] -fixed false -x 915 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z\[0\] -fixed false -x 550 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns\[1\] -fixed false -x 486 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[4\] -fixed false -x 259 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01\[5\] -fixed false -x 198 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[25\] -fixed false -x 867 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_324 -fixed false -x 702 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[5\] -fixed false -x 440 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_datareg_3_sqmuxa -fixed false -x 564 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i_o2_0 -fixed false -x 17 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[21\] -fixed false -x 819 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto3_0 -fixed false -x 151 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[18\] -fixed false -x 832 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo18 -fixed false -x 297 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[5\] -fixed false -x 233 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m5 -fixed false -x 59 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[20\] -fixed false -x 187 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[22\] -fixed false -x 550 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_1_0 -fixed false -x 82 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[28\] -fixed false -x 903 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i\[0\] -fixed false -x 43 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_26 -fixed false -x 750 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[18\] -fixed false -x 56 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[7\] -fixed false -x 289 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m18 -fixed false -x 273 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ii1Oo -fixed false -x 151 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[30\] -fixed false -x 788 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[13\] -fixed false -x 534 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[7\] -fixed false -x 248 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_stall_csr_1_0 -fixed false -x 770 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[11\] -fixed false -x 307 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[3\] -fixed false -x 291 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0\[7\] -fixed false -x 133 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m2 -fixed false -x 45 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[29\] -fixed false -x 809 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[12\] -fixed false -x 59 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[6\] -fixed false -x 255 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[7\] -fixed false -x 535 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[31\] -fixed false -x 399 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[13\] -fixed false -x 74 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_meie/gen_bit_no_reset.state_val\[0\] -fixed false -x 762 -y 127
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17_1 -fixed false -x 547 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_s_31_RNO -fixed false -x 831 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[3\] -fixed false -x 399 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[3\] -fixed false -x 513 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[1\] -fixed false -x 130 -y 208
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast\[8\] -fixed false -x 481 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO\[1\] -fixed false -x 22 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[13\] -fixed false -x 920 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OIiIo -fixed false -x 437 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[8\] -fixed false -x 72 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[6\] -fixed false -x 82 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[12\] -fixed false -x 592 -y 142
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane -fixed false -x 6 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_s -fixed false -x 788 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[31\] -fixed false -x 666 -y 123
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1 -fixed false -x 577 -y 260
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_RNO\[0\] -fixed false -x 726 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[4\] -fixed false -x 819 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/un1_iOI01_1_i_0 -fixed false -x 317 -y 168
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[7\] -fixed false -x 540 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[29\] -fixed false -x 628 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[26\] -fixed false -x 447 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[7\] -fixed false -x 81 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[13\] -fixed false -x 355 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_2_4 -fixed false -x 501 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[1\] -fixed false -x 52 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[29\] -fixed false -x 694 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_4 -fixed false -x 218 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[1\] -fixed false -x 278 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[19\] -fixed false -x 445 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[19\] -fixed false -x 422 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_6\[35\] -fixed false -x 479 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[42\] -fixed false -x 278 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1II1 -fixed false -x 248 -y 190
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[9\].BUFD_BLK -fixed false -x 533 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[7\] -fixed false -x 690 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[14\] -fixed false -x 368 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[13\] -fixed false -x 75 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIK4OV44\[0\] -fixed false -x 16 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959 -fixed false -x 686 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_167 -fixed false -x 677 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[4\] -fixed false -x 100 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[22\] -fixed false -x 659 -y 118
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[3\] -fixed false -x 447 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1158 -fixed false -x 692 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR21 -fixed false -x 573 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[7\] -fixed false -x 787 -y 106
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o25_0_a3 -fixed false -x 141 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3\[0\] -fixed false -x 502 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[10\] -fixed false -x 372 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[28\] -fixed false -x 657 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Olll1 -fixed false -x 522 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[9\] -fixed false -x 385 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[9\] -fixed false -x 559 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[19\] -fixed false -x 90 -y 222
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone -fixed false -x 506 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[20\] -fixed false -x 177 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[4\] -fixed false -x 79 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNIC92011 -fixed false -x 787 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[4\] -fixed false -x 372 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_251 -fixed false -x 562 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[29\] -fixed false -x 652 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[31\] -fixed false -x 741 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_1\[9\] -fixed false -x 298 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[15\] -fixed false -x 379 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_hword_high_only_req\[1\] -fixed false -x 875 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19_3 -fixed false -x 665 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[2\] -fixed false -x 435 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNICJS9T -fixed false -x 175 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/un1_PADDR -fixed false -x 393 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_15_RNIFI1C8 -fixed false -x 839 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[22\].BUFD_BLK -fixed false -x 507 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_lsu_op_complete_ex_RNIM3F8B -fixed false -x 790 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[17\] -fixed false -x 763 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_75\[11\] -fixed false -x 223 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[10\] -fixed false -x 805 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_1\[0\] -fixed false -x 661 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_pktsel -fixed false -x 518 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_993 -fixed false -x 701 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[15\] -fixed false -x 560 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[27\] -fixed false -x 385 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[6\] -fixed false -x 444 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[5\] -fixed false -x 381 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[27\] -fixed false -x 847 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff14_i_o3_0 -fixed false -x 765 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[17\] -fixed false -x 249 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_sel_1_iv_0\[0\] -fixed false -x 722 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lliO1_1_iv_0_cZ\[1\] -fixed false -x 43 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[12\] -fixed false -x 157 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[15\] -fixed false -x 783 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[7\] -fixed false -x 406 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[17\] -fixed false -x 418 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[10\] -fixed false -x 76 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[11\] -fixed false -x 412 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[0\] -fixed false -x 145 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[1\] -fixed false -x 756 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/II1Oo -fixed false -x 150 -y 175
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/fifo_valid -fixed false -x 384 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[2\] -fixed false -x 73 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_153 -fixed false -x 666 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_764 -fixed false -x 620 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIQ7C8H -fixed false -x 259 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2\[0\] -fixed false -x 192 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[4\] -fixed false -x 81 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_retr_2_1 -fixed false -x 774 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_584 -fixed false -x 763 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[4\] -fixed false -x 762 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[13\] -fixed false -x 899 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[0\] -fixed false -x 347 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[18\] -fixed false -x 434 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI67Q5C\[19\] -fixed false -x 679 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un87_I1Oi1_1 -fixed false -x 30 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[30\] -fixed false -x 657 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[22\] -fixed false -x 634 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[40\] -fixed false -x 346 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel\[3\] -fixed false -x 548 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[3\] -fixed false -x 695 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[8\] -fixed false -x 93 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[42\] -fixed false -x 922 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[2\] -fixed false -x 136 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read_1 -fixed false -x 398 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[3\] -fixed false -x 872 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[28\] -fixed false -x 668 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[6\] -fixed false -x 59 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_o3_RNIUOLVM_1 -fixed false -x 224 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[3\] -fixed false -x 129 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[23\] -fixed false -x 146 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[4\] -fixed false -x 428 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_10 -fixed false -x 481 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[7\] -fixed false -x 865 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_833 -fixed false -x 722 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[26\] -fixed false -x 544 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[4\] -fixed false -x 792 -y 142
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[8\] -fixed false -x 393 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[31\] -fixed false -x 623 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60\[3\] -fixed false -x 904 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[30\] -fixed false -x 427 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIDHA84\[27\] -fixed false -x 946 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[9\] -fixed false -x 166 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[13\] -fixed false -x 836 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IOOo1 -fixed false -x 298 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[6\] -fixed false -x 212 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1275 -fixed false -x 656 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[8\] -fixed false -x 75 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1_0_0 -fixed false -x 825 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_3_0_RNO -fixed false -x 772 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0_1_0\[0\] -fixed false -x 220 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat\[1\] -fixed false -x 622 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[13\] -fixed false -x 378 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[11\] -fixed false -x 426 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIGDF031\[24\] -fixed false -x 738 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[3\] -fixed false -x 347 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO\[2\] -fixed false -x 772 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[6\] -fixed false -x 838 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m19_1 -fixed false -x 619 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_0 -fixed false -x 103 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz\[0\] -fixed false -x 654 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[22\] -fixed false -x 590 -y 121
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count\[0\] -fixed false -x 491 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[5\] -fixed false -x 678 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[21\] -fixed false -x 445 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_238 -fixed false -x 594 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[27\] -fixed false -x 679 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[13\] -fixed false -x 263 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_1_i_m4\[1\] -fixed false -x 784 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1_RNIAB63H -fixed false -x 273 -y 204
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/parity_err_1_sqmuxa_i -fixed false -x 472 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[11\] -fixed false -x 300 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[1\] -fixed false -x 689 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[5\] -fixed false -x 215 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31\[1\] -fixed false -x 269 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2_4 -fixed false -x 700 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_13_RNIBEVB8 -fixed false -x 828 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.haltreq_debug_enter_pending -fixed false -x 775 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[3\] -fixed false -x 224 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[5\] -fixed false -x 531 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_2 -fixed false -x 28 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[10\] -fixed false -x 120 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[12\] -fixed false -x 34 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[4\] -fixed false -x 360 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[5\] -fixed false -x 332 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[27\] -fixed false -x 415 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI7A6GO\[11\] -fixed false -x 858 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[2\] -fixed false -x 855 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[7\] -fixed false -x 390 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[17\] -fixed false -x 465 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a2_a1 -fixed false -x 783 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m_a0_3_1_RNIEFM3A\[0\] -fixed false -x 843 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1__RNI0980D\[6\] -fixed false -x 631 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[4\] -fixed false -x 237 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[13\] -fixed false -x 377 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[16\] -fixed false -x 218 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q\[0\] -fixed false -x 597 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m7 -fixed false -x 689 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2121.rv32c_dec_mnemonic2121_1 -fixed false -x 646 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[10\] -fixed false -x 452 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[3\] -fixed false -x 511 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel -fixed false -x 712 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[1\] -fixed false -x 521 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[19\] -fixed false -x 451 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_o2\[3\] -fixed false -x 40 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[3\] -fixed false -x 882 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un17_trap_val -fixed false -x 727 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[1\] -fixed false -x 415 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[21\] -fixed false -x 804 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[2\] -fixed false -x 248 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_instr_inhibit_ex_0 -fixed false -x 806 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_17_RNIJM3C8 -fixed false -x 842 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[40\] -fixed false -x 882 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1 -fixed false -x 791 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_oIIi1_4 -fixed false -x 161 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[9\] -fixed false -x 896 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[23\] -fixed false -x 788 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o2 -fixed false -x 697 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[11\] -fixed false -x 150 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[0\] -fixed false -x 412 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[4\] -fixed false -x 378 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[4\] -fixed false -x 424 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[11\] -fixed false -x 234 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex9 -fixed false -x 757 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[14\] -fixed false -x 620 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1 -fixed false -x 137 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[11\] -fixed false -x 152 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0OIo -fixed false -x 152 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[5\] -fixed false -x 121 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[8\] -fixed false -x 493 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a1_0_0 -fixed false -x 819 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[37\] -fixed false -x 535 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[15\] -fixed false -x 871 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[21\] -fixed false -x 834 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[23\] -fixed false -x 442 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_1\[2\] -fixed false -x 618 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[9\] -fixed false -x 787 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_o2\[4\] -fixed false -x 780 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_16 -fixed false -x 841 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[14\] -fixed false -x 281 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[26\] -fixed false -x 921 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_2 -fixed false -x 657 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_200 -fixed false -x 692 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[2\] -fixed false -x 126 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[22\] -fixed false -x 626 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/set_wfi_waiting -fixed false -x 777 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIT6CS7\[9\] -fixed false -x 941 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_O1Oo1 -fixed false -x 289 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[3\] -fixed false -x 430 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[11\] -fixed false -x 91 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[5\] -fixed false -x 44 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[11\] -fixed false -x 874 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/li0I1 -fixed false -x 542 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0\[5\] -fixed false -x 139 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1280 -fixed false -x 727 -y 186
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_RNO -fixed false -x 6 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[14\] -fixed false -x 955 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_2_0 -fixed false -x 647 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[12\] -fixed false -x 343 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[16\] -fixed false -x 872 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_0_i_m2\[1\] -fixed false -x 598 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[0\] -fixed false -x 490 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[18\] -fixed false -x 90 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5 -fixed false -x 809 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[3\] -fixed false -x 228 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[0\] -fixed false -x 415 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo_RNI8G024 -fixed false -x 13 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_177 -fixed false -x 665 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[10\] -fixed false -x 724 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[8\] -fixed false -x 702 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[27\] -fixed false -x 842 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[4\] -fixed false -x 783 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[12\] -fixed false -x 356 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[5\] -fixed false -x 367 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_ioIl18_1 -fixed false -x 446 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[22\] -fixed false -x 902 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_663 -fixed false -x 654 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[8\] -fixed false -x 329 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[27\] -fixed false -x 654 -y 117
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_0_sqmuxa_0_a2 -fixed false -x 482 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[12\] -fixed false -x 706 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[5\] -fixed false -x 861 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_583 -fixed false -x 653 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_4\[24\] -fixed false -x 375 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[15\] -fixed false -x 392 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1i01 -fixed false -x 127 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[30\] -fixed false -x 115 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[19\] -fixed false -x 736 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[8\] -fixed false -x 63 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[10\] -fixed false -x 499 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOOl1 -fixed false -x 433 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1\[0\] -fixed false -x 86 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7BA84\[21\] -fixed false -x 898 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60\[5\] -fixed false -x 906 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[31\] -fixed false -x 16 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[19\] -fixed false -x 743 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_26_0_RNO -fixed false -x 820 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i_m3 -fixed false -x 391 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[2\] -fixed false -x 534 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_9 -fixed false -x 45 -y 225
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[18\] -fixed false -x 506 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[30\] -fixed false -x 416 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooO11 -fixed false -x 87 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[31\] -fixed false -x 941 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[10\] -fixed false -x 552 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[6\] -fixed false -x 375 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[25\] -fixed false -x 829 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_o3\[4\] -fixed false -x 353 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[5\] -fixed false -x 223 -y 201
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_15 -fixed false -x 9 -y 164
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[23\] -fixed false -x 790 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[26\] -fixed false -x 597 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_0 -fixed false -x 620 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[1\] -fixed false -x 857 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/un4_exu_res_req_retr -fixed false -x 754 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2s2_0 -fixed false -x 798 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[14\] -fixed false -x 81 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6\[1\] -fixed false -x 282 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[30\] -fixed false -x 419 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[19\] -fixed false -x 397 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[18\] -fixed false -x 749 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[12\] -fixed false -x 607 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA\[7\] -fixed false -x 542 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un13_i0oi1 -fixed false -x 226 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_28 -fixed false -x 143 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[7\] -fixed false -x 803 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_6\[10\] -fixed false -x 295 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_1\[3\] -fixed false -x 80 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_18\[20\] -fixed false -x 140 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[11\] -fixed false -x 915 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/i0111 -fixed false -x 131 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[16\] -fixed false -x 856 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOIo1 -fixed false -x 319 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[20\] -fixed false -x 733 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[14\] -fixed false -x 352 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_774 -fixed false -x 642 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_595 -fixed false -x 727 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/I0iI1 -fixed false -x 330 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IolOo\[0\] -fixed false -x 178 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[1\] -fixed false -x 731 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[1\] -fixed false -x 158 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[23\] -fixed false -x 679 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0\[15\] -fixed false -x 184 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lolIo -fixed false -x 116 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_652 -fixed false -x 619 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[4\] -fixed false -x 237 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[23\] -fixed false -x 826 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_2_236_a2 -fixed false -x 322 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[17\] -fixed false -x 249 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[38\] -fixed false -x 356 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1308 -fixed false -x 757 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa_0_0 -fixed false -x 525 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[11\] -fixed false -x 603 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_14_0_i -fixed false -x 223 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_4_1\[3\] -fixed false -x 39 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[4\] -fixed false -x 257 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_13_128_a2 -fixed false -x 425 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_557 -fixed false -x 794 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[3\] -fixed false -x 380 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[9\] -fixed false -x 630 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0_1_0\[0\] -fixed false -x 314 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO\[5\] -fixed false -x 163 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[4\] -fixed false -x 498 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_4 -fixed false -x 649 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[30\] -fixed false -x 191 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n1 -fixed false -x 193 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[16\] -fixed false -x 833 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_1\[3\] -fixed false -x 316 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[4\] -fixed false -x 945 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[0\] -fixed false -x 180 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_il0Oo -fixed false -x 123 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI75FRQ1\[5\] -fixed false -x 802 -y 150
|
|
set_location -inst_name SSDetect_0/is_match_0.un6_is_match_4 -fixed false -x 16 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[14\] -fixed false -x 944 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[5\] -fixed false -x 277 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[16\] -fixed false -x 536 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex\[3\] -fixed false -x 810 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[7\] -fixed false -x 445 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1032 -fixed false -x 750 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[13\] -fixed false -x 174 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o1111 -fixed false -x 41 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIT6FO8 -fixed false -x 259 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[9\] -fixed false -x 122 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITJRQ8\[17\] -fixed false -x 652 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO\[7\] -fixed false -x 127 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/l11l1 -fixed false -x 389 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[29\] -fixed false -x 901 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[31\] -fixed false -x 751 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[12\] -fixed false -x 290 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[15\] -fixed false -x 299 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001\[7\] -fixed false -x 126 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1024 -fixed false -x 596 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_lsu_stall.un14_gpr_rs1_stall_lsu -fixed false -x 787 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[10\] -fixed false -x 243 -y 178
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[5\] -fixed false -x 385 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un17_full_wr_NE_RNIC67MH -fixed false -x 632 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[8\] -fixed false -x 782 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_penable_0_sqmuxa_0_0_o2 -fixed false -x 616 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Iio01_RNIU8EJP1 -fixed false -x 78 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1183 -fixed false -x 642 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[13\] -fixed false -x 905 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o1iO1 -fixed false -x 190 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2\[26\] -fixed false -x 160 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[8\] -fixed false -x 30 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[23\] -fixed false -x 718 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[5\] -fixed false -x 850 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[12\] -fixed false -x 273 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[18\] -fixed false -x 776 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1\[1\] -fixed false -x 133 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[16\] -fixed false -x 753 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[6\] -fixed false -x 491 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[9\] -fixed false -x 460 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO_1 -fixed false -x 883 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[26\] -fixed false -x 789 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[5\] -fixed false -x 272 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNI8QC4T -fixed false -x 899 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[4\] -fixed false -x 184 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_214 -fixed false -x 703 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[9\] -fixed false -x 525 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_wr_rd_state_Z\[1\] -fixed false -x 752 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_axb_0_i_0 -fixed false -x 523 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[13\] -fixed false -x 343 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[14\] -fixed false -x 837 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[31\] -fixed false -x 491 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_11\[0\] -fixed false -x 824 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[18\] -fixed false -x 823 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lOIOo -fixed false -x 43 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_7_176_a2 -fixed false -x 438 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[1\] -fixed false -x 391 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_2_0 -fixed false -x 632 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[20\] -fixed false -x 759 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4914_1 -fixed false -x 660 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[14\] -fixed false -x 384 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[3\] -fixed false -x 400 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_586 -fixed false -x 721 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1058 -fixed false -x 676 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_52 -fixed false -x 872 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv\[2\] -fixed false -x 497 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioIi1_0 -fixed false -x 113 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[19\] -fixed false -x 135 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/branch_cond_0_iv\[1\] -fixed false -x 753 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[4\] -fixed false -x 335 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid46 -fixed false -x 739 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_803 -fixed false -x 641 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_liOI1_4 -fixed false -x 471 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[27\] -fixed false -x 744 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[8\] -fixed false -x 225 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[1\] -fixed false -x 17 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[11\] -fixed false -x 126 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[23\] -fixed false -x 436 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/l01l1 -fixed false -x 384 -y 214
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_0 -fixed false -x 395 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OoO11_0_a2 -fixed false -x 106 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[7\] -fixed false -x 351 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4955 -fixed false -x 679 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[17\] -fixed false -x 652 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[14\] -fixed false -x 438 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[8\] -fixed false -x 38 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL_RNO -fixed false -x 21 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/g0_2_1 -fixed false -x 774 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un37_ool01\[4\] -fixed false -x 181 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[4\] -fixed false -x 686 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m53 -fixed false -x 34 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_830 -fixed false -x 661 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_0_sqmuxa_0_a3 -fixed false -x 701 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[8\] -fixed false -x 575 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[9\] -fixed false -x 209 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr\[0\] -fixed false -x 645 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[15\] -fixed false -x 188 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[7\] -fixed false -x 40 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNIIOONM -fixed false -x 794 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[23\] -fixed false -x 414 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_208 -fixed false -x 607 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[27\] -fixed false -x 596 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[21\] -fixed false -x 655 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[15\] -fixed false -x 668 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[13\] -fixed false -x 318 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg\[3\] -fixed false -x 726 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[5\] -fixed false -x 335 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_144 -fixed false -x 618 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[10\] -fixed false -x 144 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1\[0\] -fixed false -x 139 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[17\] -fixed false -x 924 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO1Oo -fixed false -x 153 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[3\] -fixed false -x 295 -y 198
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[1\] -fixed false -x 398 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[16\] -fixed false -x 750 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[25\] -fixed false -x 748 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[14\] -fixed false -x 732 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[12\] -fixed false -x 532 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[10\] -fixed false -x 404 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[7\] -fixed false -x 764 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[3\] -fixed false -x 664 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_673 -fixed false -x 631 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[25\] -fixed false -x 931 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/IilI1 -fixed false -x 294 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[0\] -fixed false -x 295 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[11\] -fixed false -x 508 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0 -fixed false -x 619 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2_0\[2\] -fixed false -x 650 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_3 -fixed false -x 287 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ilOo1 -fixed false -x 306 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2\[3\] -fixed false -x 289 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ioIO1_0 -fixed false -x 146 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/write_subsys_hart_gpr_ded_reset -fixed false -x 693 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[5\] -fixed false -x 849 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[3\] -fixed false -x 392 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1228 -fixed false -x 742 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[14\] -fixed false -x 769 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[15\] -fixed false -x 126 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[0\] -fixed false -x 411 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[33\] -fixed false -x 649 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[19\] -fixed false -x 882 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14\[1\] -fixed false -x 283 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_162 -fixed false -x 606 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0\[4\] -fixed false -x 126 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[23\] -fixed false -x 61 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[8\] -fixed false -x 317 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[11\] -fixed false -x 750 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_0_sqmuxa_0_a2 -fixed false -x 198 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[1\] -fixed false -x 168 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[15\] -fixed false -x 360 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1\[2\] -fixed false -x 482 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[1\] -fixed false -x 273 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un23_next_buff_resp_wr_ptr_0_sqmuxa -fixed false -x 715 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_ff_4 -fixed false -x 820 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[9\] -fixed false -x 65 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[4\] -fixed false -x 311 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001\[1\] -fixed false -x 72 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[31\] -fixed false -x 866 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[12\] -fixed false -x 391 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[27\] -fixed false -x 860 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[3\] -fixed false -x 532 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[18\] -fixed false -x 761 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[13\] -fixed false -x 86 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDMI_ne_0 -fixed false -x 556 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_valid_mux -fixed false -x 814 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[6\] -fixed false -x 421 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_x2 -fixed false -x 116 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_561 -fixed false -x 608 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout_4 -fixed false -x 783 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[6\] -fixed false -x 331 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[25\] -fixed false -x 913 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_1\[14\] -fixed false -x 620 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI23Q5C\[17\] -fixed false -x 704 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[24\] -fixed false -x 683 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[20\] -fixed false -x 470 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[5\] -fixed false -x 673 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[18\] -fixed false -x 191 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[5\] -fixed false -x 906 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[1\] -fixed false -x 453 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[2\] -fixed false -x 771 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0\[9\] -fixed false -x 117 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_12 -fixed false -x 400 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2123_1_0_RNIGC4EC -fixed false -x 641 -y 141
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[6\] -fixed false -x 565 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO_1 -fixed false -x 897 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[22\] -fixed false -x 468 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_4 -fixed false -x 834 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_664 -fixed false -x 561 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1\[1\] -fixed false -x 350 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNIJE4LE\[6\] -fixed false -x 795 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_529 -fixed false -x 630 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/IilI1 -fixed false -x 396 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[4\] -fixed false -x 417 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[48\] -fixed false -x 116 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv\[1\] -fixed false -x 22 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[5\] -fixed false -x 236 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[3\] -fixed false -x 245 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[3\] -fixed false -x 360 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[24\] -fixed false -x 662 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[25\] -fixed false -x 595 -y 120
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1\[4\] -fixed false -x 516 -y 99
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RE_d1 -fixed false -x 395 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1\[15\] -fixed false -x 142 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[2\] -fixed false -x 61 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_Ol0i1_0_0 -fixed false -x 102 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[3\] -fixed false -x 571 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[4\] -fixed false -x 134 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[7\] -fixed false -x 168 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i -fixed false -x 766 -y 126
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[5\] -fixed false -x 498 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/genblk1.rst_synch_reg\[0\] -fixed false -x 630 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_rd_0 -fixed false -x 797 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[26\] -fixed false -x 916 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[30\] -fixed false -x 657 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un12_lolIo_1 -fixed false -x 117 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[6\] -fixed false -x 517 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[6\] -fixed false -x 61 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[16\] -fixed false -x 52 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[17\] -fixed false -x 742 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_l00o1_2 -fixed false -x 113 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2 -fixed false -x 820 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[16\] -fixed false -x 710 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o1ol1 -fixed false -x 357 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[7\] -fixed false -x 259 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[10\] -fixed false -x 90 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[15\] -fixed false -x 29 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z\[2\] -fixed false -x 338 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[0\] -fixed false -x 534 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[5\] -fixed false -x 796 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIF1GUI\[6\] -fixed false -x 898 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_967 -fixed false -x 631 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[12\] -fixed false -x 236 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO\[12\] -fixed false -x 148 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[12\] -fixed false -x 722 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[18\] -fixed false -x 43 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[21\] -fixed false -x 560 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_fence_os\[1\] -fixed false -x 813 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[0\] -fixed false -x 842 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IOoO1 -fixed false -x 273 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto15_4_0_4 -fixed false -x 140 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un9_gpr_rd_rs2_completing_ex -fixed false -x 712 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[14\] -fixed false -x 712 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_6\[1\] -fixed false -x 259 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[3\] -fixed false -x 501 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0Ii1_RNI73OH4 -fixed false -x 174 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_7\[29\] -fixed false -x 680 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO\[6\] -fixed false -x 125 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[41\] -fixed false -x 945 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[1\] -fixed false -x 477 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m17 -fixed false -x 81 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[26\] -fixed false -x 772 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[34\] -fixed false -x 517 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un59_Oi1O1\[5\] -fixed false -x 412 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m3_i_1 -fixed false -x 798 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[11\] -fixed false -x 348 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[16\] -fixed false -x 859 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[16\] -fixed false -x 799 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_4 -fixed false -x 423 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[8\] -fixed false -x 372 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.i4_mux_i -fixed false -x 126 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI7DM4C\[4\] -fixed false -x 656 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex -fixed false -x 764 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[18\] -fixed false -x 215 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[15\] -fixed false -x 954 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[18\] -fixed false -x 437 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[21\] -fixed false -x 435 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_5\[29\] -fixed false -x 319 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[4\] -fixed false -x 495 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_RNO\[8\] -fixed false -x 74 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[9\] -fixed false -x 72 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[8\] -fixed false -x 417 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[8\] -fixed false -x 263 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1 -fixed false -x 748 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[16\] -fixed false -x 381 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[6\] -fixed false -x 423 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[9\] -fixed false -x 730 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[4\] -fixed false -x 158 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[10\] -fixed false -x 130 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un7_trap_val -fixed false -x 750 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_psel_0_a2 -fixed false -x 480 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO\[3\] -fixed false -x 314 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[3\] -fixed false -x 441 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[53\] -fixed false -x 897 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ilIo1 -fixed false -x 280 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[4\] -fixed false -x 319 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[4\] -fixed false -x 100 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[9\] -fixed false -x 771 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[29\] -fixed false -x 681 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[8\] -fixed false -x 224 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1080 -fixed false -x 655 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[28\] -fixed false -x 460 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[7\] -fixed false -x 895 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[3\] -fixed false -x 813 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_42\[10\] -fixed false -x 284 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[5\] -fixed false -x 80 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_27 -fixed false -x 665 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[2\] -fixed false -x 512 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[11\] -fixed false -x 39 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u_2\[0\] -fixed false -x 955 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_936 -fixed false -x 739 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[17\] -fixed false -x 423 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_22\[20\] -fixed false -x 137 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[27\] -fixed false -x 249 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m16_1_0 -fixed false -x 605 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0\[3\] -fixed false -x 90 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[5\] -fixed false -x 78 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[24\] -fixed false -x 906 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[22\] -fixed false -x 667 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIQ3CS7\[6\] -fixed false -x 908 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[20\] -fixed false -x 671 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[2\] -fixed false -x 135 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3\[0\] -fixed false -x 195 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_40\[9\] -fixed false -x 874 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_725 -fixed false -x 619 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/li1Oo -fixed false -x 151 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[31\] -fixed false -x 875 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[14\] -fixed false -x 475 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_1_sqmuxa_1_0_a3 -fixed false -x 675 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[54\] -fixed false -x 553 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[3\] -fixed false -x 395 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_d_1_sqmuxa -fixed false -x 494 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIEKUT5 -fixed false -x 242 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[1\] -fixed false -x 221 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO\[3\] -fixed false -x 124 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_RNO_0 -fixed false -x 638 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_0\[0\] -fixed false -x 766 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[16\] -fixed false -x 539 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[7\] -fixed false -x 764 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[25\] -fixed false -x 386 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[11\] -fixed false -x 402 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[18\] -fixed false -x 859 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[20\] -fixed false -x 655 -y 118
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO\[2\] -fixed false -x 31 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1\[1\] -fixed false -x 48 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_172 -fixed false -x 728 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[2\] -fixed false -x 767 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[7\] -fixed false -x 197 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO -fixed false -x 727 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[1\] -fixed false -x 383 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ol1I1 -fixed false -x 419 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/looIo_3_0_.m6 -fixed false -x 60 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[28\].BUFD_BLK -fixed false -x 510 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_31 -fixed false -x 666 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_800 -fixed false -x 773 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[5\] -fixed false -x 699 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[13\] -fixed false -x 693 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[31\] -fixed false -x 874 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_462 -fixed false -x 712 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1286 -fixed false -x 667 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_9 -fixed false -x 485 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[14\] -fixed false -x 154 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_1\[28\] -fixed false -x 942 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[7\] -fixed false -x 331 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[16\] -fixed false -x 406 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_T_h_En_0_a2 -fixed false -x 501 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack -fixed false -x 902 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[1\] -fixed false -x 688 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[4\] -fixed false -x 465 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[7\] -fixed false -x 96 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[9\] -fixed false -x 79 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[15\] -fixed false -x 755 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[10\] -fixed false -x 466 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_1 -fixed false -x 755 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[12\] -fixed false -x 728 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[1\] -fixed false -x 324 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4_1\[1\] -fixed false -x 525 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[4\] -fixed false -x 762 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31\[11\] -fixed false -x 235 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[51\] -fixed false -x 153 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un16_OOOI1\[10\] -fixed false -x 376 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITLFFD\[8\] -fixed false -x 643 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0\[11\] -fixed false -x 726 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[9\] -fixed false -x 220 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_571 -fixed false -x 668 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[9\] -fixed false -x 314 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[22\] -fixed false -x 763 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_689 -fixed false -x 653 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[33\].BUFD_BLK -fixed false -x 561 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[6\] -fixed false -x 206 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[11\] -fixed false -x 39 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_m3\[2\] -fixed false -x 505 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_0_o2\[3\] -fixed false -x 606 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_1\[0\] -fixed false -x 330 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[7\] -fixed false -x 381 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[25\] -fixed false -x 893 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand1_mux_sel_1_0_iv\[0\] -fixed false -x 776 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiOo1 -fixed false -x 300 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[4\] -fixed false -x 184 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un16_i00i1lto4 -fixed false -x 173 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto10 -fixed false -x 199 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_628 -fixed false -x 716 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[11\] -fixed false -x 701 -y 126
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow_int -fixed false -x 474 -y 148
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag\[1\] -fixed false -x 26 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[9\] -fixed false -x 899 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[13\] -fixed false -x 735 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[4\] -fixed false -x 239 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31 -fixed false -x 588 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[13\] -fixed false -x 923 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m58_0 -fixed false -x 281 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[1\] -fixed false -x 694 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_674 -fixed false -x 652 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un3_ili01_0_a3 -fixed false -x 107 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[3\] -fixed false -x 919 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[12\] -fixed false -x 316 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[6\] -fixed false -x 744 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[25\] -fixed false -x 743 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg\[4\] -fixed false -x 569 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[22\] -fixed false -x 436 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[4\] -fixed false -x 526 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1_RNO -fixed false -x 186 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[2\] -fixed false -x 710 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[4\] -fixed false -x 64 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl18_i -fixed false -x 451 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oo1o1 -fixed false -x 78 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oioOo -fixed false -x 125 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[12\] -fixed false -x 560 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[0\] -fixed false -x 741 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0\[3\] -fixed false -x 132 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[3\] -fixed false -x 752 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[19\] -fixed false -x 686 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_3 -fixed false -x 714 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_747 -fixed false -x 654 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2_0_0 -fixed false -x 126 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1_2 -fixed false -x 68 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_valid -fixed false -x 692 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[20\] -fixed false -x 892 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[1\] -fixed false -x 785 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_9\[9\] -fixed false -x 326 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2\[1\] -fixed false -x 614 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[5\] -fixed false -x 687 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/un1_Ioli0_1_0 -fixed false -x 224 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO\[2\] -fixed false -x 216 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.CO0 -fixed false -x 201 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[19\] -fixed false -x 813 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex\[0\] -fixed false -x 775 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_RNO -fixed false -x 534 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1__RNIOKV7D\[2\] -fixed false -x 637 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[19\] -fixed false -x 898 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[4\] -fixed false -x 214 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIEIA84\[28\] -fixed false -x 930 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[13\] -fixed false -x 757 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O1lIo_1_0_.m6 -fixed false -x 31 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1 -fixed false -x 580 -y 122
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[5\] -fixed false -x 380 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[13\] -fixed false -x 295 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_0_2 -fixed false -x 543 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI7C8GO\[20\] -fixed false -x 877 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[27\] -fixed false -x 715 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[14\] -fixed false -x 941 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[19\] -fixed false -x 674 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[1\] -fixed false -x 85 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[15\] -fixed false -x 237 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIOo1 -fixed false -x 306 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01\[2\] -fixed false -x 179 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_977 -fixed false -x 630 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[10\] -fixed false -x 911 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[24\] -fixed false -x 682 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[7\] -fixed false -x 396 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[9\] -fixed false -x 421 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_2\[26\] -fixed false -x 121 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_shifter_unit_op_sel_ex7_RNIHHH8P2 -fixed false -x 779 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[2\] -fixed false -x 284 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[4\] -fixed false -x 157 -y 202
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2_0 -fixed false -x 475 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[1\] -fixed false -x 271 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[11\] -fixed false -x 752 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[6\] -fixed false -x 913 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[3\] -fixed false -x 533 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[23\] -fixed false -x 874 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[5\] -fixed false -x 598 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[1\] -fixed false -x 489 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[5\] -fixed false -x 293 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un219_I1Oi1_2 -fixed false -x 46 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed\[14\] -fixed false -x 617 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[16\] -fixed false -x 747 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[9\] -fixed false -x 805 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1\[8\] -fixed false -x 418 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[23\] -fixed false -x 464 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_849 -fixed false -x 681 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO_0 -fixed false -x 862 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[14\] -fixed false -x 597 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[7\] -fixed false -x 245 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[8\] -fixed false -x 344 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[6\] -fixed false -x 199 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[1\] -fixed false -x 104 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[27\] -fixed false -x 483 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftBP_1_sqmuxa_i -fixed false -x 572 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_0_0 -fixed false -x 803 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[30\] -fixed false -x 455 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[0\] -fixed false -x 432 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0\[4\] -fixed false -x 754 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[18\] -fixed false -x 865 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i -fixed false -x 676 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[7\] -fixed false -x 401 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[27\] -fixed false -x 919 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[0\] -fixed false -x 628 -y 154
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_2\[2\] -fixed false -x 117 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[5\] -fixed false -x 336 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[0\] -fixed false -x 417 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[62\] -fixed false -x 952 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iIIi1 -fixed false -x 180 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1102 -fixed false -x 570 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[35\] -fixed false -x 357 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[7\] -fixed false -x 371 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[13\] -fixed false -x 897 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[26\] -fixed false -x 858 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[0\] -fixed false -x 375 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[27\] -fixed false -x 591 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_0\[5\] -fixed false -x 326 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[14\] -fixed false -x 648 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[6\] -fixed false -x 522 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[7\] -fixed false -x 215 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[7\] -fixed false -x 345 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[30\] -fixed false -x 876 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[8\] -fixed false -x 262 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[4\] -fixed false -x 376 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[6\] -fixed false -x 445 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[14\] -fixed false -x 42 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff14_i_o3 -fixed false -x 797 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[8\] -fixed false -x 352 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[9\] -fixed false -x 305 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un42_o1Oi1 -fixed false -x 94 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[10\] -fixed false -x 829 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_1_sqmuxa_2_0_a2 -fixed false -x 16 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[15\] -fixed false -x 858 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[0\] -fixed false -x 824 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO_0 -fixed false -x 770 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[6\] -fixed false -x 709 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt\[0\] -fixed false -x 459 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[21\] -fixed false -x 878 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_capture_reg -fixed false -x 757 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_836 -fixed false -x 663 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[11\] -fixed false -x 840 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo17_0_a3 -fixed false -x 395 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[8\] -fixed false -x 444 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[23\] -fixed false -x 751 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oOoi1 -fixed false -x 185 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[29\] -fixed false -x 428 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[2\] -fixed false -x 815 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m9 -fixed false -x 57 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[7\] -fixed false -x 448 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[12\] -fixed false -x 500 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[0\] -fixed false -x 859 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_5 -fixed false -x 397 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[4\] -fixed false -x 496 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[12\] -fixed false -x 51 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[22\] -fixed false -x 772 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i01Oo\[0\] -fixed false -x 122 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[9\] -fixed false -x 150 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_361 -fixed false -x 631 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_366 -fixed false -x 678 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr\[3\] -fixed false -x 729 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m322 -fixed false -x 281 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel_2 -fixed false -x 714 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel\[2\] -fixed false -x 428 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[8\] -fixed false -x 274 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[23\] -fixed false -x 652 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[20\] -fixed false -x 964 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[28\] -fixed false -x 903 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs2_rd_hzd_4 -fixed false -x 747 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[0\] -fixed false -x 409 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Iool1 -fixed false -x 391 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[0\] -fixed false -x 726 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[16\] -fixed false -x 970 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[17\] -fixed false -x 919 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count\[1\] -fixed false -x 480 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNI2EN6Q\[0\] -fixed false -x 747 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[13\] -fixed false -x 129 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[4\] -fixed false -x 401 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[13\] -fixed false -x 723 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[1\] -fixed false -x 887 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_472 -fixed false -x 677 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1063 -fixed false -x 740 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[7\] -fixed false -x 138 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo_RNO -fixed false -x 17 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[25\] -fixed false -x 251 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[30\] -fixed false -x 830 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[17\] -fixed false -x 872 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[5\] -fixed false -x 369 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid -fixed false -x 817 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_118 -fixed false -x 618 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[7\] -fixed false -x 417 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[11\] -fixed false -x 86 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m42 -fixed false -x 80 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[8\] -fixed false -x 714 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_235 -fixed false -x 764 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op\[1\] -fixed false -x 804 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[9\] -fixed false -x 706 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[2\] -fixed false -x 569 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[17\] -fixed false -x 454 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[7\] -fixed false -x 377 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0i1_0 -fixed false -x 96 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[0\] -fixed false -x 361 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[26\] -fixed false -x 481 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913 -fixed false -x 687 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_42 -fixed false -x 749 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[22\] -fixed false -x 655 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_906 -fixed false -x 691 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[5\] -fixed false -x 215 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_penable_0_sqmuxa_0_0 -fixed false -x 601 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[30\] -fixed false -x 887 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[4\] -fixed false -x 648 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[2\] -fixed false -x 424 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[9\] -fixed false -x 726 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[10\] -fixed false -x 437 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1072 -fixed false -x 699 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0_RNIB598DQ -fixed false -x 799 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[11\] -fixed false -x 720 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err -fixed false -x 773 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0Oo -fixed false -x 122 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1\[1\] -fixed false -x 290 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[16\] -fixed false -x 56 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[15\] -fixed false -x 54 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIl11 -fixed false -x 251 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[20\] -fixed false -x 449 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI4TN4A\[0\] -fixed false -x 30 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0\[25\] -fixed false -x 141 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_35\[11\] -fixed false -x 296 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[11\] -fixed false -x 239 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[8\] -fixed false -x 526 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[3\] -fixed false -x 56 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[15\] -fixed false -x 929 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[23\] -fixed false -x 55 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[41\] -fixed false -x 138 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1oOo -fixed false -x 122 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_6\[24\] -fixed false -x 380 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone -fixed false -x 526 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[18\] -fixed false -x 859 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[23\] -fixed false -x 787 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_3 -fixed false -x 237 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2\[6\] -fixed false -x 292 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2\[14\] -fixed false -x 881 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[26\] -fixed false -x 896 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[4\] -fixed false -x 349 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[3\] -fixed false -x 801 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[10\] -fixed false -x 124 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[29\] -fixed false -x 841 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_I1iIo -fixed false -x 437 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1_2 -fixed false -x 136 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[13\] -fixed false -x 861 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[4\] -fixed false -x 132 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[2\] -fixed false -x 380 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[4\] -fixed false -x 367 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_0 -fixed false -x 436 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_0\[3\] -fixed false -x 674 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[18\] -fixed false -x 827 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNI54164\[2\] -fixed false -x 254 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[16\] -fixed false -x 643 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_87 -fixed false -x 653 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[18\] -fixed false -x 618 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_0\[4\] -fixed false -x 252 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[2\] -fixed false -x 201 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[18\] -fixed false -x 770 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[3\] -fixed false -x 503 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1104 -fixed false -x 735 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[6\] -fixed false -x 87 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[15\] -fixed false -x 378 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_720 -fixed false -x 762 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0\[1\] -fixed false -x 329 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[7\] -fixed false -x 376 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.trigger_debug_enter_pending6 -fixed false -x 749 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[7\] -fixed false -x 520 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[18\] -fixed false -x 56 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I0o01_RNO -fixed false -x 65 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[28\] -fixed false -x 944 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[10\] -fixed false -x 241 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[5\] -fixed false -x 241 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_5 -fixed false -x 680 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[4\] -fixed false -x 459 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[0\] -fixed false -x 652 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_36 -fixed false -x 642 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[8\] -fixed false -x 88 -y 177
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_4_c5 -fixed false -x 102 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[4\] -fixed false -x 736 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[19\] -fixed false -x 903 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[23\] -fixed false -x 437 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[18\] -fixed false -x 702 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo -fixed false -x 177 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[26\] -fixed false -x 406 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[31\] -fixed false -x 733 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[35\] -fixed false -x 628 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0_tz\[0\] -fixed false -x 754 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[14\] -fixed false -x 404 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[23\] -fixed false -x 416 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_845 -fixed false -x 605 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0\[15\] -fixed false -x 121 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto18_8 -fixed false -x 772 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_ackhavereset -fixed false -x 757 -y 112
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy -fixed false -x 502 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un12_lsu_resp_ready_a0_0 -fixed false -x 775 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[6\] -fixed false -x 337 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[36\] -fixed false -x 514 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_2 -fixed false -x 234 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[0\] -fixed false -x 436 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.m7_1_0 -fixed false -x 79 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I0OIo\[0\] -fixed false -x 153 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[19\] -fixed false -x 448 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[24\] -fixed false -x 949 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiO1 -fixed false -x 128 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_3_tz -fixed false -x 68 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[30\] -fixed false -x 423 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[7\] -fixed false -x 375 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[31\] -fixed false -x 669 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIERK9D -fixed false -x 721 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[0\] -fixed false -x 704 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[3\] -fixed false -x 382 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO_0 -fixed false -x 811 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[21\] -fixed false -x 565 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ii1i1_2_0_0_a2 -fixed false -x 203 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[8\] -fixed false -x 245 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_1 -fixed false -x 199 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[21\] -fixed false -x 919 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_3_0 -fixed false -x 514 -y 90
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[39\] -fixed false -x 284 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[11\] -fixed false -x 137 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_4_RNO -fixed false -x 293 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[13\] -fixed false -x 688 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[13\] -fixed false -x 342 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[29\] -fixed false -x 694 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[29\] -fixed false -x 222 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[2\] -fixed false -x 212 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNI6UE88\[14\] -fixed false -x 95 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[3\] -fixed false -x 255 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0\[6\] -fixed false -x 104 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2117_2 -fixed false -x 670 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[2\] -fixed false -x 885 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[31\] -fixed false -x 882 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[63\] -fixed false -x 597 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[23\] -fixed false -x 891 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[3\] -fixed false -x 387 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un23_I1Oi1_2 -fixed false -x 30 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_0\[0\] -fixed false -x 613 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/un1_iOI01_1_i_0 -fixed false -x 341 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[9\] -fixed false -x 262 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[22\] -fixed false -x 557 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[20\] -fixed false -x 459 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O01i1_i_o2 -fixed false -x 199 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_ooli1\[0\] -fixed false -x 194 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m4 -fixed false -x 57 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[11\] -fixed false -x 655 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[1\] -fixed false -x 79 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[39\] -fixed false -x 525 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[20\] -fixed false -x 93 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[19\] -fixed false -x 440 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_strb\[1\] -fixed false -x 761 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_RNO\[1\] -fixed false -x 784 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_371 -fixed false -x 700 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[0\] -fixed false -x 350 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_376 -fixed false -x 676 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[19\] -fixed false -x 538 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1_cZ\[19\] -fixed false -x 353 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[23\] -fixed false -x 865 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[10\] -fixed false -x 810 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[12\] -fixed false -x 149 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[18\] -fixed false -x 605 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[7\] -fixed false -x 371 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[13\] -fixed false -x 499 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[5\] -fixed false -x 533 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_1\[1\] -fixed false -x 788 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[31\] -fixed false -x 550 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[0\] -fixed false -x 442 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[5\] -fixed false -x 402 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[27\] -fixed false -x 656 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_11\[9\] -fixed false -x 283 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[52\] -fixed false -x 895 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[5\] -fixed false -x 369 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[9\] -fixed false -x 764 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[17\] -fixed false -x 454 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[2\] -fixed false -x 720 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1\[1\] -fixed false -x 717 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_4\[9\] -fixed false -x 124 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[2\] -fixed false -x 68 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[1\] -fixed false -x 337 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[27\] -fixed false -x 546 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[19\] -fixed false -x 464 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_3 -fixed false -x 162 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs2_rd_hzd_4 -fixed false -x 750 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[3\] -fixed false -x 202 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[7\] -fixed false -x 178 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[3\] -fixed false -x 306 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[4\] -fixed false -x 834 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[3\] -fixed false -x 728 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[1\] -fixed false -x 793 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[12\] -fixed false -x 241 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[3\] -fixed false -x 127 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[3\] -fixed false -x 506 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0\[2\] -fixed false -x 848 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[21\] -fixed false -x 853 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 385 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[1\] -fixed false -x 85 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_3\[4\] -fixed false -x 765 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[13\] -fixed false -x 732 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_5_0_RNO -fixed false -x 774 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/un1_read_rx_byte_1 -fixed false -x 457 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[20\] -fixed false -x 316 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1\[3\] -fixed false -x 133 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[0\] -fixed false -x 129 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[0\] -fixed false -x 427 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex -fixed false -x 752 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[5\] -fixed false -x 730 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[6\] -fixed false -x 236 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0\[7\] -fixed false -x 317 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[29\] -fixed false -x 226 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[23\] -fixed false -x 457 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[0\] -fixed false -x 493 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[17\] -fixed false -x 908 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[5\] -fixed false -x 78 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[23\] -fixed false -x 727 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O0i01_0 -fixed false -x 104 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[1\] -fixed false -x 417 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/IilI1 -fixed false -x 218 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[7\] -fixed false -x 246 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_3_0_1_0 -fixed false -x 774 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_oIIi1 -fixed false -x 160 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl15 -fixed false -x 546 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_806 -fixed false -x 659 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_20\[22\] -fixed false -x 260 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[8\] -fixed false -x 668 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[23\] -fixed false -x 931 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[19\] -fixed false -x 444 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un27_loOo1\[1\] -fixed false -x 280 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[30\] -fixed false -x 830 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[23\] -fixed false -x 454 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un95_i11Io -fixed false -x 415 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[6\] -fixed false -x 451 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[1\] -fixed false -x 386 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[37\] -fixed false -x 630 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[0\] -fixed false -x 31 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[4\] -fixed false -x 932 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_2 -fixed false -x 308 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_0_1\[0\] -fixed false -x 118 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un50_OilI1\[21\] -fixed false -x 385 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_13_0_RNO -fixed false -x 810 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[4\] -fixed false -x 81 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[17\] -fixed false -x 448 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3\[0\] -fixed false -x 657 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[11\] -fixed false -x 416 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[2\] -fixed false -x 332 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[7\] -fixed false -x 49 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0i11 -fixed false -x 390 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[0\] -fixed false -x 414 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[7\] -fixed false -x 303 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[7\] -fixed false -x 868 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32\[0\] -fixed false -x 287 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[0\] -fixed false -x 681 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[22\] -fixed false -x 719 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_RNO\[9\] -fixed false -x 75 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_curr_fetch_ptr\[1\] -fixed false -x 889 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[1\] -fixed false -x 369 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[21\] -fixed false -x 684 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[13\] -fixed false -x 376 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9_4 -fixed false -x 67 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[29\] -fixed false -x 940 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25\[11\] -fixed false -x 339 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_0 -fixed false -x 133 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1 -fixed false -x 517 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oIoOolto3 -fixed false -x 249 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[25\] -fixed false -x 115 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[19\] -fixed false -x 686 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[26\] -fixed false -x 658 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[13\] -fixed false -x 126 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[7\] -fixed false -x 206 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[29\] -fixed false -x 802 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[11\] -fixed false -x 93 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[17\] -fixed false -x 935 -y 138
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m14 -fixed false -x 469 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid37_0 -fixed false -x 790 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr_2_f0\[1\] -fixed false -x 764 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv\[3\] -fixed false -x 629 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[10\] -fixed false -x 301 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[16\] -fixed false -x 778 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIoo1 -fixed false -x 104 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_rd -fixed false -x 802 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_205 -fixed false -x 698 -y 207
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state\[3\] -fixed false -x 523 -y 100
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[4\] -fixed false -x 273 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[2\] -fixed false -x 511 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[12\] -fixed false -x 843 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[11\] -fixed false -x 841 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_9 -fixed false -x 226 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[22\] -fixed false -x 470 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[24\] -fixed false -x 808 -y 181
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_0_sqmuxa -fixed false -x 450 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[1\] -fixed false -x 390 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[13\] -fixed false -x 907 -y 150
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[8\] -fixed false -x 405 -y 256
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/count_en_0_sqmuxa_1_0_a3 -fixed false -x 761 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand0_mux_sel_1_iv_2_RNO\[0\] -fixed false -x 747 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo_RNO -fixed false -x 23 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2 -fixed false -x 718 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[1\] -fixed false -x 688 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[19\] -fixed false -x 876 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_451 -fixed false -x 715 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2\[0\] -fixed false -x 122 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_752 -fixed false -x 642 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[6\] -fixed false -x 493 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[18\] -fixed false -x 623 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[0\] -fixed false -x 424 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[6\] -fixed false -x 258 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0\[0\] -fixed false -x 724 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2_0\[2\] -fixed false -x 571 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[4\] -fixed false -x 496 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter_req -fixed false -x 775 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[0\] -fixed false -x 99 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[48\] -fixed false -x 934 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[13\] -fixed false -x 372 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[37\] -fixed false -x 922 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_addr_align\[0\]\[1\] -fixed false -x 826 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[11\] -fixed false -x 394 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_exit -fixed false -x 770 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[5\] -fixed false -x 276 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0 -fixed false -x 143 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[5\] -fixed false -x 261 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[13\] -fixed false -x 372 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[2\] -fixed false -x 77 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_21_0_RNO -fixed false -x 837 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[39\] -fixed false -x 321 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[10\] -fixed false -x 73 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_26_RNIJO5D8 -fixed false -x 817 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_a3\[1\] -fixed false -x 423 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr\[0\] -fixed false -x 626 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[1\] -fixed false -x 777 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[15\] -fixed false -x 133 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[5\] -fixed false -x 233 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_447 -fixed false -x 681 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_10_RNIJJE6D -fixed false -x 480 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic847 -fixed false -x 609 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[7\] -fixed false -x 43 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[11\] -fixed false -x 283 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_alloc -fixed false -x 783 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_llOo1 -fixed false -x 311 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[17\] -fixed false -x 909 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_85 -fixed false -x 653 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[5\] -fixed false -x 494 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[1\] -fixed false -x 828 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv\[16\] -fixed false -x 740 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[24\] -fixed false -x 589 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[5\] -fixed false -x 533 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[8\] -fixed false -x 195 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[6\] -fixed false -x 327 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ooI11 -fixed false -x 267 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIH3GUI\[7\] -fixed false -x 869 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i00o1_0_a2 -fixed false -x 90 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[31\] -fixed false -x 720 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[8\] -fixed false -x 379 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I019_RNIBEMUF1 -fixed false -x 178 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10\[1\] -fixed false -x 320 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii101_RNO -fixed false -x 102 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[3\] -fixed false -x 330 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[30\] -fixed false -x 427 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m4_e_1 -fixed false -x 818 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[4\] -fixed false -x 100 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_iooo1_0 -fixed false -x 52 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_2 -fixed false -x 111 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoOo -fixed false -x 237 -y 154
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n\[1\] -fixed false -x 19 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[1\] -fixed false -x 722 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_11\[10\] -fixed false -x 282 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_0_sqmuxa -fixed false -x 772 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[6\] -fixed false -x 616 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[12\] -fixed false -x 260 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OOIOo -fixed false -x 45 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[25\] -fixed false -x 221 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[17\] -fixed false -x 439 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[23\] -fixed false -x 901 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[14\] -fixed false -x 796 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIHD0D6\[3\] -fixed false -x 298 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[25\] -fixed false -x 858 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[23\] -fixed false -x 458 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo_RNIKP865 -fixed false -x 41 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2\[5\] -fixed false -x 111 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[28\] -fixed false -x 857 -y 151
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO\[2\] -fixed false -x 511 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_48 -fixed false -x 747 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[9\] -fixed false -x 858 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[8\] -fixed false -x 245 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un83_ool01 -fixed false -x 183 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[7\] -fixed false -x 411 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[5\] -fixed false -x 83 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/un1_Ioli0_1_0 -fixed false -x 345 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[25\] -fixed false -x 815 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[13\] -fixed false -x 812 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[1\] -fixed false -x 139 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retrce\[0\] -fixed false -x 772 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[8\] -fixed false -x 641 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[58\] -fixed false -x 841 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[5\] -fixed false -x 90 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[2\] -fixed false -x 449 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[5\] -fixed false -x 36 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOoO1 -fixed false -x 137 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[7\] -fixed false -x 42 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel_1 -fixed false -x 705 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[8\] -fixed false -x 428 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[2\] -fixed false -x 766 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[11\] -fixed false -x 644 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[13\] -fixed false -x 347 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0101 -fixed false -x 138 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m28 -fixed false -x 77 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[1\] -fixed false -x 386 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[53\] -fixed false -x 891 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[2\] -fixed false -x 63 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[16\] -fixed false -x 778 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[0\] -fixed false -x 74 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[4\] -fixed false -x 376 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[3\] -fixed false -x 379 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[9\] -fixed false -x 187 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[31\] -fixed false -x 954 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic849 -fixed false -x 608 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[2\] -fixed false -x 740 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[29\] -fixed false -x 791 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_lsu_req_valid -fixed false -x 818 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_iili1\[0\] -fixed false -x 193 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[13\] -fixed false -x 356 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_4\[0\] -fixed false -x 145 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_48\[6\] -fixed false -x 501 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[34\] -fixed false -x 281 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[15\] -fixed false -x 469 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO -fixed false -x 188 -y 192
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[4\] -fixed false -x 376 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNI6EB8H -fixed false -x 783 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_2\[31\] -fixed false -x 738 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[9\] -fixed false -x 45 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[7\] -fixed false -x 283 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[36\] -fixed false -x 125 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OiOo1 -fixed false -x 289 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_mux_sel_ex\[1\] -fixed false -x 741 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[24\] -fixed false -x 319 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[12\] -fixed false -x 538 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[4\] -fixed false -x 449 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_610 -fixed false -x 631 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[4\] -fixed false -x 630 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[9\] -fixed false -x 235 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[0\] -fixed false -x 101 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2\[4\] -fixed false -x 567 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[14\] -fixed false -x 351 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_99 -fixed false -x 617 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0\[0\] -fixed false -x 115 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m9 -fixed false -x 124 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[20\] -fixed false -x 951 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[12\] -fixed false -x 44 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m4 -fixed false -x 67 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[17\] -fixed false -x 805 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[4\] -fixed false -x 660 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[6\] -fixed false -x 214 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[9\] -fixed false -x 731 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_2 -fixed false -x 169 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2 -fixed false -x 140 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[6\] -fixed false -x 423 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_PADDR_2 -fixed false -x 505 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[26\] -fixed false -x 769 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[5\] -fixed false -x 366 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[13\] -fixed false -x 437 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_1_0 -fixed false -x 792 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[4\] -fixed false -x 512 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_0\[2\] -fixed false -x 944 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_taken -fixed false -x 726 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI7HOH1K -fixed false -x 825 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[19\] -fixed false -x 427 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_418 -fixed false -x 630 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo\[4\] -fixed false -x 256 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[24\] -fixed false -x 468 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[30\] -fixed false -x 954 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[8\] -fixed false -x 866 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_RNO\[10\] -fixed false -x 141 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_3 -fixed false -x 737 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[63\] -fixed false -x 956 -y 169
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[3\] -fixed false -x 484 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[26\] -fixed false -x 776 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_busy_cmb_mux.un1_debug_csr_rd_en_1 -fixed false -x 731 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[28\] -fixed false -x 906 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[44\] -fixed false -x 969 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u -fixed false -x 807 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13\[0\] -fixed false -x 282 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3\[1\] -fixed false -x 779 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[14\] -fixed false -x 347 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[11\] -fixed false -x 852 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1230 -fixed false -x 569 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[22\] -fixed false -x 676 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[6\] -fixed false -x 200 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[27\] -fixed false -x 611 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i_1 -fixed false -x 747 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[3\] -fixed false -x 223 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2\[0\] -fixed false -x 721 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_tz -fixed false -x 112 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr_1\[8\] -fixed false -x 694 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[0\] -fixed false -x 280 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[19\] -fixed false -x 813 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_valid -fixed false -x 713 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1307 -fixed false -x 738 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[24\] -fixed false -x 373 -y 174
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/genblk1.RXRDY5 -fixed false -x 475 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un14_i00i1_i_0 -fixed false -x 177 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i_o2_0 -fixed false -x 900 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[13\] -fixed false -x 849 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[5\] -fixed false -x 910 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[14\] -fixed false -x 621 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_32\[10\] -fixed false -x 196 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[17\] -fixed false -x 261 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_2_tz_tz -fixed false -x 170 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_ready_reg -fixed false -x 759 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[20\] -fixed false -x 746 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[6\] -fixed false -x 72 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un47_I1Oi1_1 -fixed false -x 29 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[15\] -fixed false -x 895 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_59\[11\] -fixed false -x 327 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[18\] -fixed false -x 784 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr\[2\] -fixed false -x 775 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[16\] -fixed false -x 469 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_27_RNILQ6D8 -fixed false -x 806 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO_1 -fixed false -x 864 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNI42K8A -fixed false -x 96 -y 213
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO\[2\] -fixed false -x 490 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[8\] -fixed false -x 344 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[8\] -fixed false -x 418 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_2 -fixed false -x 796 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0\[7\] -fixed false -x 66 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[29\] -fixed false -x 738 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[0\] -fixed false -x 543 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[1\] -fixed false -x 673 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[28\] -fixed false -x 116 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i01i1 -fixed false -x 210 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[9\] -fixed false -x 882 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIi1_1 -fixed false -x 120 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO1o1 -fixed false -x 21 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/o01Io_1 -fixed false -x 72 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[0\] -fixed false -x 170 -y 207
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_1 -fixed false -x 512 -y 93
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_1_1 -fixed false -x 478 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[5\] -fixed false -x 438 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[34\] -fixed false -x 480 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rtex_1 -fixed false -x 41 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[10\] -fixed false -x 944 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0\[1\] -fixed false -x 655 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[12\] -fixed false -x 417 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[0\] -fixed false -x 859 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_1\[0\] -fixed false -x 629 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a2_a2 -fixed false -x 789 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2122_i -fixed false -x 869 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m23 -fixed false -x 56 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[1\] -fixed false -x 67 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[5\] -fixed false -x 782 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[23\] -fixed false -x 563 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1\[1\] -fixed false -x 523 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_active_retr -fixed false -x 774 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[16\] -fixed false -x 93 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[15\] -fixed false -x 787 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[7\] -fixed false -x 186 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[6\] -fixed false -x 157 -y 213
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDODRV -fixed false -x 503 -y 97
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[8\] -fixed false -x 537 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[4\] -fixed false -x 770 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[6\] -fixed false -x 448 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[10\] -fixed false -x 248 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[6\] -fixed false -x 447 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_292 -fixed false -x 633 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[3\] -fixed false -x 337 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IoI11_RNO -fixed false -x 355 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[25\] -fixed false -x 830 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[18\] -fixed false -x 609 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo_RNIA6DF9 -fixed false -x 176 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dpc_debugger_wr_sel -fixed false -x 715 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[18\] -fixed false -x 223 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40_cZ\[7\] -fixed false -x 360 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[23\] -fixed false -x 447 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[7\] -fixed false -x 883 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[28\] -fixed false -x 788 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_5_RNIDV17D -fixed false -x 844 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIBG8GO\[22\] -fixed false -x 864 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[19\] -fixed false -x 422 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olIOo -fixed false -x 31 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[6\] -fixed false -x 496 -y 151
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg\[0\] -fixed false -x 36 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[8\] -fixed false -x 968 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[14\] -fixed false -x 276 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[24\] -fixed false -x 854 -y 135
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE9_0 -fixed false -x 15 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[8\] -fixed false -x 557 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[6\] -fixed false -x 422 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[7\] -fixed false -x 259 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[3\] -fixed false -x 503 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[9\] -fixed false -x 438 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0\[4\] -fixed false -x 58 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[5\] -fixed false -x 251 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1ce\[0\] -fixed false -x 121 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_1_0_RNO -fixed false -x 823 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[13\] -fixed false -x 35 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[2\] -fixed false -x 122 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[6\] -fixed false -x 387 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[4\] -fixed false -x 699 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[58\] -fixed false -x 541 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[25\] -fixed false -x 784 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_i_m3\[1\] -fixed false -x 704 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI1NRKJ\[11\] -fixed false -x 104 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[24\] -fixed false -x 719 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[10\] -fixed false -x 481 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[23\] -fixed false -x 390 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[4\] -fixed false -x 366 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[61\] -fixed false -x 950 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[2\] -fixed false -x 282 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1133 -fixed false -x 700 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_25_1 -fixed false -x 703 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_3 -fixed false -x 75 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[5\] -fixed false -x 838 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[10\] -fixed false -x 662 -y 127
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/endofshift -fixed false -x 486 -y 97
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_IOiOo -fixed false -x 234 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[24\] -fixed false -x 650 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[9\] -fixed false -x 155 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[55\] -fixed false -x 938 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[2\] -fixed false -x 443 -y 160
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_3_sqmuxa -fixed false -x 66 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI5NHJL1 -fixed false -x 750 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2\[3\] -fixed false -x 743 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[31\] -fixed false -x 422 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_636 -fixed false -x 831 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_2_RNO -fixed false -x 622 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[5\] -fixed false -x 439 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[18\] -fixed false -x 692 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[10\] -fixed false -x 838 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[17\] -fixed false -x 706 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[22\] -fixed false -x 209 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[1\] -fixed false -x 396 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[0\] -fixed false -x 410 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[16\] -fixed false -x 471 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[8\] -fixed false -x 163 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_8 -fixed false -x 86 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[10\] -fixed false -x 501 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[18\] -fixed false -x 381 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1054 -fixed false -x 711 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_7\[1\] -fixed false -x 687 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[5\] -fixed false -x 305 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[2\] -fixed false -x 816 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[26\] -fixed false -x 813 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_o1oOo -fixed false -x 146 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[3\] -fixed false -x 48 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2 -fixed false -x 702 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[4\] -fixed false -x 760 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[6\] -fixed false -x 212 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[12\] -fixed false -x 379 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un31_ool01\[5\] -fixed false -x 61 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[9\] -fixed false -x 345 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7\[0\] -fixed false -x 312 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_a2_0\[24\] -fixed false -x 736 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[31\] -fixed false -x 874 -y 130
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD -fixed false -x 1 -y 163
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1_0\[0\] -fixed false -x 285 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0\[1\] -fixed false -x 67 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[16\] -fixed false -x 222 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0\[12\] -fixed false -x 132 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_224 -fixed false -x 723 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[7\] -fixed false -x 402 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO3 -fixed false -x 544 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[10\] -fixed false -x 914 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[14\] -fixed false -x 123 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/IilI1 -fixed false -x 383 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[7\] -fixed false -x 363 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[22\] -fixed false -x 655 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[4\] -fixed false -x 380 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[3\] -fixed false -x 353 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[28\].BUFD_BLK -fixed false -x 546 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[19\] -fixed false -x 868 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[0\] -fixed false -x 798 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_139 -fixed false -x 726 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[26\] -fixed false -x 687 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[11\] -fixed false -x 537 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[5\] -fixed false -x 499 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[13\] -fixed false -x 692 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[0\] -fixed false -x 504 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[20\] -fixed false -x 528 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oii01\[1\] -fixed false -x 38 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1 -fixed false -x 517 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_1_2 -fixed false -x 393 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/PRDDATA\[2\] -fixed false -x 489 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[50\] -fixed false -x 926 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[27\] -fixed false -x 939 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[28\] -fixed false -x 161 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[29\] -fixed false -x 890 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[0\] -fixed false -x 643 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[15\] -fixed false -x 351 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex\[0\] -fixed false -x 723 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[25\] -fixed false -x 913 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIFB0D6\[1\] -fixed false -x 297 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[21\] -fixed false -x 386 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[10\] -fixed false -x 283 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i10i1 -fixed false -x 189 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel\[0\] -fixed false -x 541 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKX0\[0\] -fixed false -x 721 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[26\] -fixed false -x 456 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_184 -fixed false -x 675 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[0\] -fixed false -x 546 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_s_29_RNIB63NI -fixed false -x 836 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0\[2\] -fixed false -x 291 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[18\] -fixed false -x 847 -y 144
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/iPSELS_raw_2_adflt -fixed false -x 475 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0OIo_0 -fixed false -x 114 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[9\] -fixed false -x 326 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[2\] -fixed false -x 72 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3\[2\] -fixed false -x 686 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[1\] -fixed false -x 420 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[4\] -fixed false -x 456 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[28\] -fixed false -x 942 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[6\] -fixed false -x 257 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg\[1\] -fixed false -x 805 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv\[4\] -fixed false -x 738 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_8 -fixed false -x 198 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff -fixed false -x 682 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[1\] -fixed false -x 505 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3_0_RNO -fixed false -x 863 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[2\] -fixed false -x 573 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[28\] -fixed false -x 667 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/next_buff_valid\[0\] -fixed false -x 796 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[16\] -fixed false -x 739 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un1_interrupt_taken_timer_2 -fixed false -x 779 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un291_rv32i_dec_sw_csr_wr_op -fixed false -x 695 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[1\] -fixed false -x 302 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[15\] -fixed false -x 376 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[53\] -fixed false -x 968 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[13\] -fixed false -x 594 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[6\] -fixed false -x 368 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[10\] -fixed false -x 338 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[23\] -fixed false -x 450 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un31_I1Oi1_2_0 -fixed false -x 37 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_2\[10\] -fixed false -x 297 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[26\] -fixed false -x 837 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[6\] -fixed false -x 776 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[0\] -fixed false -x 742 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit -fixed false -x 545 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[9\] -fixed false -x 883 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[5\] -fixed false -x 918 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[12\] -fixed false -x 64 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[8\] -fixed false -x 496 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[20\] -fixed false -x 654 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_1 -fixed false -x 743 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[17\] -fixed false -x 753 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_538 -fixed false -x 665 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[0\] -fixed false -x 569 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i_a2 -fixed false -x 74 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io\[0\] -fixed false -x 392 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[0\] -fixed false -x 69 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1_RNIS235T -fixed false -x 114 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[5\] -fixed false -x 207 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioOo1 -fixed false -x 304 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m12 -fixed false -x 103 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6\[0\] -fixed false -x 709 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[8\] -fixed false -x 224 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_9 -fixed false -x 39 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[0\] -fixed false -x 304 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1258 -fixed false -x 715 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[12\] -fixed false -x 920 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[22\] -fixed false -x 763 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[10\] -fixed false -x 182 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[24\] -fixed false -x 859 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[6\] -fixed false -x 546 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[12\] -fixed false -x 800 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[2\] -fixed false -x 506 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tbi_tx_1 -fixed false -x 366 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[6\] -fixed false -x 826 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z\[37\] -fixed false -x 444 -y 193
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code_5_f0_i_a2 -fixed false -x 0 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6 -fixed false -x 819 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a3_1\[2\] -fixed false -x 715 -y 114
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[2\] -fixed false -x 38 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[11\] -fixed false -x 672 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[29\] -fixed false -x 834 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[5\] -fixed false -x 748 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/Ol1Io_3\[0\] -fixed false -x 43 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un32_o1Oi1_0 -fixed false -x 74 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[31\] -fixed false -x 857 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[3\] -fixed false -x 116 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/stage_ready_ex_2_RNI1AD2B -fixed false -x 740 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[21\] -fixed false -x 842 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[31\] -fixed false -x 228 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[30\] -fixed false -x 953 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[18\] -fixed false -x 873 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[4\] -fixed false -x 776 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[0\] -fixed false -x 505 -y 151
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_2 -fixed false -x 507 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_0\[29\] -fixed false -x 905 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIB76IG2\[6\] -fixed false -x 103 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_13 -fixed false -x 862 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_943 -fixed false -x 796 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0_1_0\[0\] -fixed false -x 318 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[4\] -fixed false -x 341 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[17\] -fixed false -x 859 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1093 -fixed false -x 690 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[0\] -fixed false -x 52 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[9\] -fixed false -x 321 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[17\] -fixed false -x 534 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11\[3\] -fixed false -x 57 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[2\] -fixed false -x 39 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[27\] -fixed false -x 489 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[8\] -fixed false -x 162 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1013 -fixed false -x 761 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[12\] -fixed false -x 352 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[7\] -fixed false -x 49 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNI8KJNO -fixed false -x 825 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte_1_sqmuxa -fixed false -x 471 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[8\] -fixed false -x 408 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_1 -fixed false -x 93 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[11\] -fixed false -x 264 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_83\[11\] -fixed false -x 222 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[23\] -fixed false -x 766 -y 172
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag\[1\] -fixed false -x 71 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[12\] -fixed false -x 361 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_0 -fixed false -x 694 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[4\] -fixed false -x 425 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[41\] -fixed false -x 538 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[16\] -fixed false -x 78 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[7\] -fixed false -x 909 -y 141
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1 -fixed false -x 575 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0\[2\] -fixed false -x 727 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[15\] -fixed false -x 638 -y 124
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st\[0\] -fixed false -x 25 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/iliI1 -fixed false -x 365 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[17\] -fixed false -x 908 -y 135
|
|
set_location -inst_name PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL -fixed false -x 11 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter\[2\] -fixed false -x 785 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[0\] -fixed false -x 698 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[2\] -fixed false -x 279 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[4\] -fixed false -x 509 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[10\] -fixed false -x 865 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[22\] -fixed false -x 557 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11\[0\] -fixed false -x 101 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_2_0_RNIVVPG81 -fixed false -x 953 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[20\] -fixed false -x 608 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[31\] -fixed false -x 908 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[11\] -fixed false -x 707 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[27\] -fixed false -x 392 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l01015_0_a3 -fixed false -x 139 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.IloIo -fixed false -x 377 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[1\] -fixed false -x 425 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo\[0\] -fixed false -x 204 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[2\] -fixed false -x 102 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[30\] -fixed false -x 380 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m46 -fixed false -x 29 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIA0FQD\[6\] -fixed false -x 82 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[9\] -fixed false -x 894 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[11\] -fixed false -x 100 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[5\] -fixed false -x 198 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[28\] -fixed false -x 688 -y 120
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_11\[0\] -fixed false -x 751 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 373 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[5\] -fixed false -x 119 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[44\] -fixed false -x 521 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[4\] -fixed false -x 368 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[24\] -fixed false -x 892 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[19\] -fixed false -x 933 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[0\] -fixed false -x 505 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[5\] -fixed false -x 690 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[14\] -fixed false -x 748 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI0Oo -fixed false -x 279 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_0 -fixed false -x 76 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[2\] -fixed false -x 856 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[17\] -fixed false -x 470 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112 -fixed false -x 663 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int\[2\] -fixed false -x 779 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[24\] -fixed false -x 411 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1i01_0 -fixed false -x 126 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_2 -fixed false -x 834 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[10\] -fixed false -x 714 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_5 -fixed false -x 106 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[25\] -fixed false -x 331 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1_2 -fixed false -x 64 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRSH -fixed false -x 513 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[9\] -fixed false -x 453 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[1\] -fixed false -x 217 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0_1_0\[0\] -fixed false -x 261 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_7 -fixed false -x 660 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[45\] -fixed false -x 967 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_ba_err_ff_0_sqmuxa -fixed false -x 773 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1030 -fixed false -x 641 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[40\] -fixed false -x 906 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[7\] -fixed false -x 392 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[23\] -fixed false -x 932 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[28\] -fixed false -x 807 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[4\] -fixed false -x 710 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[0\] -fixed false -x 262 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0\[4\] -fixed false -x 859 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[23\] -fixed false -x 871 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_14\[0\] -fixed false -x 819 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[20\] -fixed false -x 547 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[20\] -fixed false -x 449 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[8\] -fixed false -x 452 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[9\] -fixed false -x 425 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n1 -fixed false -x 556 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_606 -fixed false -x 640 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[15\] -fixed false -x 389 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIio1 -fixed false -x 82 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel_0_sqmuxa -fixed false -x 553 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[20\] -fixed false -x 469 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[6\] -fixed false -x 383 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[10\] -fixed false -x 766 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[20\] -fixed false -x 738 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[27\] -fixed false -x 870 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[5\] -fixed false -x 838 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[6\] -fixed false -x 250 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_9 -fixed false -x 733 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[3\] -fixed false -x 887 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[42\] -fixed false -x 920 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[3\] -fixed false -x 354 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[2\] -fixed false -x 503 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[9\] -fixed false -x 394 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNIE69PD1 -fixed false -x 789 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[6\] -fixed false -x 813 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[7\] -fixed false -x 123 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[6\] -fixed false -x 426 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OIoOo_1_0 -fixed false -x 125 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val\[3\] -fixed false -x 725 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[0\] -fixed false -x 240 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[24\] -fixed false -x 693 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOo11 -fixed false -x 145 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[7\] -fixed false -x 364 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNIIJ4R9 -fixed false -x 797 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[2\] -fixed false -x 82 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_3_RNIEQTOL -fixed false -x 402 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[11\] -fixed false -x 933 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_pslverr_net_0 -fixed false -x 486 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[26\] -fixed false -x 655 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[13\] -fixed false -x 253 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[9\] -fixed false -x 510 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[44\] -fixed false -x 563 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10\[0\] -fixed false -x 540 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0 -fixed false -x 821 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[30\] -fixed false -x 936 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1236 -fixed false -x 666 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO\[1\] -fixed false -x 716 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_109 -fixed false -x 726 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[19\] -fixed false -x 55 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[12\] -fixed false -x 129 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/l0lIo_1_i_a7_0_0 -fixed false -x 102 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted\[6\] -fixed false -x 836 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25_1\[9\] -fixed false -x 338 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[5\] -fixed false -x 509 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR\[2\] -fixed false -x 570 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OIoI1 -fixed false -x 413 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2\[22\] -fixed false -x 758 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[20\] -fixed false -x 130 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_a3_0\[0\] -fixed false -x 113 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[19\] -fixed false -x 939 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff\[1\] -fixed false -x 690 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_0 -fixed false -x 826 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[27\] -fixed false -x 470 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O0lI1 -fixed false -x 372 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_out -fixed false -x 533 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[12\] -fixed false -x 96 -y 169
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_a3\[5\] -fixed false -x 447 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[27\] -fixed false -x 249 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0\[0\] -fixed false -x 665 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_85_u\[9\] -fixed false -x 905 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_818 -fixed false -x 629 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[27\] -fixed false -x 703 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[3\] -fixed false -x 339 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_2\[4\] -fixed false -x 40 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[7\] -fixed false -x 260 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[14\] -fixed false -x 487 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[9\] -fixed false -x 379 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[19\] -fixed false -x 89 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[5\] -fixed false -x 296 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1011 -fixed false -x 265 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[14\] -fixed false -x 922 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 473 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1II1 -fixed false -x 323 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[12\] -fixed false -x 99 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[1\] -fixed false -x 282 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_0\[1\] -fixed false -x 722 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0\[4\] -fixed false -x 723 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[9\] -fixed false -x 381 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[11\] -fixed false -x 848 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[12\] -fixed false -x 356 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[15\] -fixed false -x 232 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1\[2\] -fixed false -x 245 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1 -fixed false -x 65 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_23 -fixed false -x 164 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_44 -fixed false -x 734 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[1\] -fixed false -x 324 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[0\] -fixed false -x 164 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[25\] -fixed false -x 893 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[11\] -fixed false -x 363 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[30\] -fixed false -x 873 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4_RNO\[1\] -fixed false -x 717 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout -fixed false -x 783 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[5\] -fixed false -x 45 -y 232
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[5\] -fixed false -x 509 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[3\] -fixed false -x 392 -y 208
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un6_countnext -fixed false -x 524 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0_1_0\[0\] -fixed false -x 260 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[1\] -fixed false -x 285 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OOI11 -fixed false -x 134 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[19\] -fixed false -x 817 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_787 -fixed false -x 632 -y 174
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[9\] -fixed false -x 406 -y 256
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[18\] -fixed false -x 432 -y 195
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_10\[0\] -fixed false -x 750 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[12\] -fixed false -x 68 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[10\] -fixed false -x 887 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[25\] -fixed false -x 340 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[5\] -fixed false -x 282 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[1\] -fixed false -x 50 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[4\] -fixed false -x 458 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_545 -fixed false -x 800 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_508 -fixed false -x 738 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13\[1\] -fixed false -x 795 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c_RNI746RL -fixed false -x 773 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo\[3\] -fixed false -x 126 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1043 -fixed false -x 681 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_1 -fixed false -x 220 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_1_RNO -fixed false -x 798 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[4\] -fixed false -x 711 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[19\] -fixed false -x 460 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_367 -fixed false -x 724 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[24\] -fixed false -x 675 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[25\] -fixed false -x 274 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[11\] -fixed false -x 127 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[15\] -fixed false -x 140 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_2\[4\] -fixed false -x 267 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[5\] -fixed false -x 848 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_0 -fixed false -x 137 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_2\[0\] -fixed false -x 55 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[27\] -fixed false -x 409 -y 244
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3\[4\] -fixed false -x 496 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0\[0\] -fixed false -x 512 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[20\] -fixed false -x 442 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[24\] -fixed false -x 476 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[37\] -fixed false -x 528 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[29\] -fixed false -x 882 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O0lI1 -fixed false -x 468 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31_0 -fixed false -x 557 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_ptr\[0\] -fixed false -x 768 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[17\] -fixed false -x 110 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a2_0 -fixed false -x 826 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[3\] -fixed false -x 429 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_0 -fixed false -x 44 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid46 -fixed false -x 738 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[28\] -fixed false -x 133 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[20\] -fixed false -x 675 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[34\] -fixed false -x 481 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[16\] -fixed false -x 827 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_0_3 -fixed false -x 162 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[21\] -fixed false -x 327 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[14\] -fixed false -x 293 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[4\] -fixed false -x 214 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[3\] -fixed false -x 286 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[7\] -fixed false -x 550 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/hipri_req_ptr\[0\] -fixed false -x 721 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1_1\[7\] -fixed false -x 74 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[15\] -fixed false -x 729 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[31\] -fixed false -x 598 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_889 -fixed false -x 606 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[8\] -fixed false -x 311 -y 157
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[5\] -fixed false -x 20 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_RNO\[6\] -fixed false -x 738 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO_1 -fixed false -x 806 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lOl01_2_iv_i -fixed false -x 181 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[19\] -fixed false -x 689 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[1\] -fixed false -x 247 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[25\] -fixed false -x 922 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[10\] -fixed false -x 279 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIoo1 -fixed false -x 103 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[23\] -fixed false -x 725 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1270 -fixed false -x 652 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_strobe -fixed false -x 517 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_74\[11\] -fixed false -x 192 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[19\] -fixed false -x 885 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[3\] -fixed false -x 357 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[0\] -fixed false -x 702 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[0\] -fixed false -x 237 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[7\] -fixed false -x 834 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[4\] -fixed false -x 216 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0\[19\] -fixed false -x 129 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[0\] -fixed false -x 653 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[3\] -fixed false -x 651 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1_cZ\[4\] -fixed false -x 359 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m293 -fixed false -x 287 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[16\] -fixed false -x 322 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/un1_Ioli0_1_0 -fixed false -x 268 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[2\] -fixed false -x 379 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[9\] -fixed false -x 613 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/genblk1.rst_synch_reg\[0\] -fixed false -x 666 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[12\] -fixed false -x 469 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[31\] -fixed false -x 267 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[7\] -fixed false -x 680 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[11\] -fixed false -x 101 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[2\] -fixed false -x 56 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_631 -fixed false -x 605 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[7\] -fixed false -x 728 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[0\] -fixed false -x 680 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_i_1_m2\[1\] -fixed false -x 776 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo -fixed false -x 272 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oI1I18 -fixed false -x 473 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_RNO\[3\] -fixed false -x 491 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[3\] -fixed false -x 414 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i_a2_0 -fixed false -x 616 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_211 -fixed false -x 560 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[1\] -fixed false -x 78 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/valid_out_RNIIN0NG1 -fixed false -x 795 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1\[1\] -fixed false -x 138 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i -fixed false -x 588 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[0\] -fixed false -x 476 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_1 -fixed false -x 432 -y 9
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/looi1 -fixed false -x 266 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0_1_0\[0\] -fixed false -x 203 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[14\] -fixed false -x 919 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i\[11\] -fixed false -x 269 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6\[4\] -fixed false -x 728 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[23\] -fixed false -x 562 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un1_oOo11_1_i -fixed false -x 144 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state_valid_3\[0\] -fixed false -x 814 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6\[0\] -fixed false -x 280 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[5\] -fixed false -x 658 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[22\] -fixed false -x 915 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[27\] -fixed false -x 223 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[26\] -fixed false -x 651 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[5\] -fixed false -x 207 -y 214
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto7_2 -fixed false -x 64 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0_a3_2\[7\] -fixed false -x 321 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[12\] -fixed false -x 270 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/IilI1 -fixed false -x 284 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[28\] -fixed false -x 857 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_illegal_instr_retr -fixed false -x 810 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[1\] -fixed false -x 61 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[7\] -fixed false -x 214 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[21\] -fixed false -x 825 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[3\] -fixed false -x 193 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid_RNIOMPV2A -fixed false -x 808 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[7\] -fixed false -x 400 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic847_2 -fixed false -x 607 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z\[3\] -fixed false -x 237 -y 205
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r4_i_o2 -fixed false -x 384 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[13\] -fixed false -x 914 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3\[1\] -fixed false -x 197 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[9\] -fixed false -x 804 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[23\] -fixed false -x 413 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_113 -fixed false -x 700 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_353 -fixed false -x 640 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[17\] -fixed false -x 55 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[6\] -fixed false -x 841 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[23\] -fixed false -x 677 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[1\] -fixed false -x 894 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[6\] -fixed false -x 429 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_237 -fixed false -x 679 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4_RNO\[2\] -fixed false -x 47 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[31\] -fixed false -x 88 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_1_a0_3_3 -fixed false -x 834 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNIVVL4E\[5\] -fixed false -x 488 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2\[0\] -fixed false -x 98 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[31\] -fixed false -x 471 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[21\] -fixed false -x 777 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[0\] -fixed false -x 367 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[22\] -fixed false -x 719 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_128 -fixed false -x 749 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[11\] -fixed false -x 757 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[8\] -fixed false -x 498 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i\[0\] -fixed false -x 272 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m20_0 -fixed false -x 264 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[1\] -fixed false -x 284 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lOlIo -fixed false -x 240 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_read -fixed false -x 740 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[9\] -fixed false -x 763 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[12\] -fixed false -x 337 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_793 -fixed false -x 748 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[1\] -fixed false -x 521 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_liol17_1 -fixed false -x 343 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[1\] -fixed false -x 541 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1173 -fixed false -x 725 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ioIIo_RNO -fixed false -x 270 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_1\[1\] -fixed false -x 716 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[20\] -fixed false -x 836 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_82\[11\] -fixed false -x 234 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 391 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[5\] -fixed false -x 136 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1 -fixed false -x 78 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[6\] -fixed false -x 39 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[31\] -fixed false -x 874 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[0\] -fixed false -x 69 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_4 -fixed false -x 730 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state_valid_9\[1\] -fixed false -x 812 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[15\] -fixed false -x 901 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_1\[0\] -fixed false -x 788 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_o2_1_0 -fixed false -x 785 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILDTQ8\[22\] -fixed false -x 666 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIMJQQD -fixed false -x 778 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[5\] -fixed false -x 173 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[23\] -fixed false -x 908 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[13\] -fixed false -x 448 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_52\[8\] -fixed false -x 955 -y 141
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[11\] -fixed false -x 389 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1\[0\] -fixed false -x 289 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[24\] -fixed false -x 699 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO -fixed false -x 817 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[1\] -fixed false -x 323 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[29\] -fixed false -x 648 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid36 -fixed false -x 858 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_377 -fixed false -x 654 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[5\] -fixed false -x 500 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un16_I1Oi1 -fixed false -x 48 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[21\] -fixed false -x 799 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[9\] -fixed false -x 220 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNI0E7JA\[0\] -fixed false -x 755 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[15\] -fixed false -x 226 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[8\] -fixed false -x 366 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_832 -fixed false -x 641 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n4 -fixed false -x 176 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[35\] -fixed false -x 483 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[3\] -fixed false -x 108 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ll1i1_0_a2 -fixed false -x 198 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[9\] -fixed false -x 555 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[8\] -fixed false -x 915 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[24\] -fixed false -x 67 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[2\] -fixed false -x 705 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[3\] -fixed false -x 359 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[2\] -fixed false -x 128 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0oo1_0 -fixed false -x 74 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01_1_sqmuxa_i -fixed false -x 374 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_885 -fixed false -x 618 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[17\] -fixed false -x 845 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[20\] -fixed false -x 603 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/IilI1 -fixed false -x 262 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un52_oIiOo_1.CO3 -fixed false -x 342 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[8\] -fixed false -x 135 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[12\] -fixed false -x 766 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[21\] -fixed false -x 779 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_63\[11\] -fixed false -x 233 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[9\] -fixed false -x 126 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol15 -fixed false -x 376 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[3\] -fixed false -x 906 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[14\] -fixed false -x 445 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[13\] -fixed false -x 774 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913_2_0_RNIBGU5A1 -fixed false -x 636 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1\[4\] -fixed false -x 122 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_0\[0\] -fixed false -x 656 -y 138
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[4\] -fixed false -x 401 -y 256
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[12\] -fixed false -x 291 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr\[1\] -fixed false -x 644 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0\[2\] -fixed false -x 564 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5\[14\] -fixed false -x 136 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.psel -fixed false -x 590 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[13\] -fixed false -x 330 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO -fixed false -x 808 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851 -fixed false -x 608 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[4\] -fixed false -x 257 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/IilI1_RNO -fixed false -x 278 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_fr_1 -fixed false -x 364 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_15_2 -fixed false -x 713 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OIIl1 -fixed false -x 547 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.un1_dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset -fixed false -x 571 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/l0iI1 -fixed false -x 325 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un10_ioOOo_2 -fixed false -x 58 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].un1_lsu_flush -fixed false -x 820 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_7_1 -fixed false -x 640 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[18\] -fixed false -x 437 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[14\] -fixed false -x 404 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oOil1 -fixed false -x 417 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[2\] -fixed false -x 573 -y 148
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[27\].BUFD_BLK -fixed false -x 509 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]_3\[1\] -fixed false -x 741 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1\[0\].machine_sw_wr_tdata2_match_data_wr_en_0 -fixed false -x 714 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[12\] -fixed false -x 765 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[2\] -fixed false -x 61 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[8\] -fixed false -x 188 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[2\] -fixed false -x 69 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo -fixed false -x 310 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_alu_op_complete_ex_0 -fixed false -x 783 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_57\[11\] -fixed false -x 285 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[1\] -fixed false -x 258 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[4\] -fixed false -x 457 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[9\] -fixed false -x 444 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i1I11_cZ -fixed false -x 302 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1 -fixed false -x 91 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIoO1 -fixed false -x 173 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[8\] -fixed false -x 530 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[5\] -fixed false -x 164 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[60\] -fixed false -x 592 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[8\] -fixed false -x 714 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[7\] -fixed false -x 268 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[11\] -fixed false -x 480 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_3_iv_i\[0\] -fixed false -x 171 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[26\] -fixed false -x 19 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[10\] -fixed false -x 236 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un195_I1Oi1 -fixed false -x 41 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[33\] -fixed false -x 334 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[4\] -fixed false -x 465 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_m17 -fixed false -x 684 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[9\] -fixed false -x 857 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[12\] -fixed false -x 397 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m5_1 -fixed false -x 28 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIHNM4C\[9\] -fixed false -x 716 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[15\] -fixed false -x 818 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[30\] -fixed false -x 380 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un91_ool01\[9\] -fixed false -x 150 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[15\] -fixed false -x 861 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[6\] -fixed false -x 448 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[9\] -fixed false -x 171 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/IilI1 -fixed false -x 258 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[34\] -fixed false -x 424 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[24\] -fixed false -x 709 -y 129
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[9\] -fixed false -x 380 -y 240
|
|
set_location -inst_name PF_IOD_CDR_C0_0/PF_IOD_CDR_LANECTRL_OVERLAY_0/I_IOD_0 -fixed false -x 0 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[38\] -fixed false -x 385 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_olli1lto15_0_0 -fixed false -x 198 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[5\] -fixed false -x 79 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[10\] -fixed false -x 26 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[7\] -fixed false -x 126 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex\[2\] -fixed false -x 779 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001\[5\] -fixed false -x 162 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[9\] -fixed false -x 92 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[2\] -fixed false -x 637 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOlOo -fixed false -x 25 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_612 -fixed false -x 638 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[8\] -fixed false -x 455 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_20 -fixed false -x 607 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_int -fixed false -x 471 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_455 -fixed false -x 711 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_4 -fixed false -x 711 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4\[1\] -fixed false -x 258 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[28\] -fixed false -x 515 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[23\] -fixed false -x 145 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_517 -fixed false -x 737 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_a2_0\[31\] -fixed false -x 815 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate\[12\] -fixed false -x 691 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[5\] -fixed false -x 500 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[6\] -fixed false -x 154 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m29 -fixed false -x 54 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_601 -fixed false -x 702 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[7\] -fixed false -x 363 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1_2_0 -fixed false -x 489 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[17\] -fixed false -x 906 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[4\] -fixed false -x 255 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[16\] -fixed false -x 643 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ilOl1 -fixed false -x 415 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[8\] -fixed false -x 611 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4_1\[1\] -fixed false -x 620 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[17\] -fixed false -x 898 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[9\] -fixed false -x 833 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_10_m\[0\] -fixed false -x 844 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[9\] -fixed false -x 348 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_c_0_a1 -fixed false -x 777 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m234 -fixed false -x 249 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[6\] -fixed false -x 685 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv -fixed false -x 648 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[30\] -fixed false -x 736 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO\[1\] -fixed false -x 512 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[12\] -fixed false -x 696 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[16\] -fixed false -x 392 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2\[0\] -fixed false -x 152 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIoo1_RNO -fixed false -x 111 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[9\] -fixed false -x 802 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[2\] -fixed false -x 54 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[9\] -fixed false -x 679 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex\[1\] -fixed false -x 711 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[4\] -fixed false -x 776 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[10\] -fixed false -x 176 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[4\] -fixed false -x 148 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1_RNO -fixed false -x 345 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[7\] -fixed false -x 834 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[7\] -fixed false -x 428 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[28\] -fixed false -x 349 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[36\] -fixed false -x 631 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[8\] -fixed false -x 45 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[6\] -fixed false -x 512 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un4_llii1lto4 -fixed false -x 143 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[26\] -fixed false -x 870 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[41\] -fixed false -x 560 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3\[0\] -fixed false -x 328 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1_5 -fixed false -x 34 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_532 -fixed false -x 627 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[5\] -fixed false -x 39 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int\[3\] -fixed false -x 775 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[1\] -fixed false -x 235 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[4\] -fixed false -x 534 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[27\] -fixed false -x 698 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0\[5\] -fixed false -x 75 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2_2\[28\] -fixed false -x 197 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[19\] -fixed false -x 887 -y 136
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_SWITCH_LANE_0_sqmuxa_2_0 -fixed false -x 14 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[0\] -fixed false -x 797 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[6\] -fixed false -x 265 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[4\] -fixed false -x 686 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[10\] -fixed false -x 765 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[4\] -fixed false -x 401 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4\[0\] -fixed false -x 782 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_IoOOo\[0\] -fixed false -x 56 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[5\] -fixed false -x 433 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[20\] -fixed false -x 805 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[0\] -fixed false -x 131 -y 211
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[0\] -fixed false -x 80 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNIQ580A -fixed false -x 800 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match\[0\] -fixed false -x 747 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_207 -fixed false -x 712 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[54\] -fixed false -x 553 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[0\] -fixed false -x 635 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[0\] -fixed false -x 549 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_2\[3\] -fixed false -x 684 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mscratch_sw_rd_sel_1 -fixed false -x 700 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[4\] -fixed false -x 248 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[9\] -fixed false -x 917 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[8\] -fixed false -x 527 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[45\] -fixed false -x 530 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[2\] -fixed false -x 36 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo -fixed false -x 520 -y 100
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[14\] -fixed false -x 352 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[2\] -fixed false -x 372 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i1lOo -fixed false -x 26 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[31\] -fixed false -x 456 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOOIo\[0\] -fixed false -x 107 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1070 -fixed false -x 699 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/un1_iOI01_1_i_0 -fixed false -x 317 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ii0i1 -fixed false -x 183 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[10\] -fixed false -x 261 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op\[0\] -fixed false -x 732 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[2\] -fixed false -x 281 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo_4_0_4 -fixed false -x 104 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[31\] -fixed false -x 668 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_6 -fixed false -x 652 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[8\] -fixed false -x 76 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[2\] -fixed false -x 650 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[9\] -fixed false -x 231 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI3LFUI\[0\] -fixed false -x 879 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[25\] -fixed false -x 665 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[2\] -fixed false -x 214 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[7\] -fixed false -x 397 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_a2_0_1\[0\] -fixed false -x 484 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[29\] -fixed false -x 422 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex\[0\] -fixed false -x 806 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1\[29\] -fixed false -x 739 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_12_i_1 -fixed false -x 720 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[26\] -fixed false -x 394 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[20\] -fixed false -x 881 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[33\] -fixed false -x 901 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_487 -fixed false -x 655 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m256 -fixed false -x 272 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_854 -fixed false -x 701 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIF998E\[24\] -fixed false -x 678 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[40\] -fixed false -x 633 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[17\] -fixed false -x 54 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[2\] -fixed false -x 378 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_2 -fixed false -x 149 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[17\] -fixed false -x 529 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[14\] -fixed false -x 774 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch\[0\] -fixed false -x 635 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[2\] -fixed false -x 877 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1\[2\] -fixed false -x 133 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[6\] -fixed false -x 66 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/loI01 -fixed false -x 204 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM\[4\] -fixed false -x 38 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[7\] -fixed false -x 654 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[1\] -fixed false -x 242 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel -fixed false -x 731 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[6\] -fixed false -x 127 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0_1\[30\] -fixed false -x 943 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_136 -fixed false -x 716 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[25\] -fixed false -x 653 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[2\] -fixed false -x 270 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[7\] -fixed false -x 353 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4\[0\] -fixed false -x 566 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[8\] -fixed false -x 329 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[3\] -fixed false -x 588 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[4\] -fixed false -x 767 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[0\] -fixed false -x 161 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_802 -fixed false -x 713 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[5\] -fixed false -x 269 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[6\] -fixed false -x 431 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[30\] -fixed false -x 954 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2\[1\] -fixed false -x 143 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_res_pos_neg_3 -fixed false -x 869 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[31\] -fixed false -x 802 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[1\] -fixed false -x 148 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_20_0_RNO -fixed false -x 809 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1276 -fixed false -x 712 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[17\] -fixed false -x 341 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[9\] -fixed false -x 503 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_15_116_a2 -fixed false -x 460 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[17\] -fixed false -x 396 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[9\] -fixed false -x 705 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[14\] -fixed false -x 352 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_0_0_a2_0\[15\] -fixed false -x 138 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[15\] -fixed false -x 952 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[5\] -fixed false -x 803 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[11\] -fixed false -x 318 -y 171
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[5\] -fixed false -x 38 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[1\] -fixed false -x 373 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0IOo -fixed false -x 15 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[8\] -fixed false -x 883 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[15\] -fixed false -x 658 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z\[2\] -fixed false -x 297 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[1\] -fixed false -x 356 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.req_complete_reg -fixed false -x 799 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[9\] -fixed false -x 34 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa -fixed false -x 524 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0\[5\] -fixed false -x 539 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0\[8\] -fixed false -x 349 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0_1_0\[0\] -fixed false -x 328 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_1\[5\] -fixed false -x 125 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[10\] -fixed false -x 92 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[8\] -fixed false -x 548 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1 -fixed false -x 100 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[3\] -fixed false -x 873 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[0\] -fixed false -x 138 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[3\] -fixed false -x 423 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[2\] -fixed false -x 394 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[24\] -fixed false -x 459 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lO0o1 -fixed false -x 90 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[0\] -fixed false -x 144 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_14\[22\] -fixed false -x 264 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[30\] -fixed false -x 857 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[16\] -fixed false -x 777 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex\[0\] -fixed false -x 684 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[17\] -fixed false -x 554 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/un1_Ioli0_1_0 -fixed false -x 394 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_0_0 -fixed false -x 662 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[20\] -fixed false -x 751 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1\[30\] -fixed false -x 753 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[30\] -fixed false -x 813 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[20\] -fixed false -x 835 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[18\] -fixed false -x 790 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_4 -fixed false -x 526 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[5\] -fixed false -x 174 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_4\[0\] -fixed false -x 657 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[5\] -fixed false -x 347 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[4\] -fixed false -x 536 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[26\] -fixed false -x 466 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[11\] -fixed false -x 803 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[1\] -fixed false -x 51 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[17\] -fixed false -x 440 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/un1_iOI01_1_i_0 -fixed false -x 315 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[27\] -fixed false -x 470 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_958 -fixed false -x 605 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_m2_e_1_2 -fixed false -x 844 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_m7_i_a4_1_1 -fixed false -x 66 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[3\] -fixed false -x 152 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[16\] -fixed false -x 458 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[6\] -fixed false -x 335 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0\[6\] -fixed false -x 68 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_25 -fixed false -x 719 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[0\] -fixed false -x 734 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIIVK9D -fixed false -x 729 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[19\] -fixed false -x 464 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_1_1 -fixed false -x 621 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[13\] -fixed false -x 917 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[25\] -fixed false -x 900 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[18\] -fixed false -x 713 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[4\] -fixed false -x 185 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO\[1\] -fixed false -x 622 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[4\] -fixed false -x 233 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[18\] -fixed false -x 400 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[2\] -fixed false -x 146 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[5\] -fixed false -x 380 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[4\] -fixed false -x 294 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[27\] -fixed false -x 783 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_h_En_0_a2 -fixed false -x 500 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[9\] -fixed false -x 149 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[2\] -fixed false -x 71 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_620 -fixed false -x 591 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[3\] -fixed false -x 47 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[24\] -fixed false -x 105 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[6\] -fixed false -x 809 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m1 -fixed false -x 658 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_o4_0 -fixed false -x 796 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[5\] -fixed false -x 422 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[1\] -fixed false -x 194 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0\[1\] -fixed false -x 543 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[15\] -fixed false -x 477 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[25\] -fixed false -x 764 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[15\] -fixed false -x 350 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[1\] -fixed false -x 777 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[2\] -fixed false -x 269 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[33\] -fixed false -x 643 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO_0 -fixed false -x 836 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[26\] -fixed false -x 945 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_5 -fixed false -x 302 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_428 -fixed false -x 596 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_1_0_0 -fixed false -x 783 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[5\] -fixed false -x 150 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[5\] -fixed false -x 138 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[29\] -fixed false -x 952 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[5\] -fixed false -x 368 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[3\] -fixed false -x 129 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[4\] -fixed false -x 322 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[0\] -fixed false -x 415 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[24\] -fixed false -x 425 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[10\] -fixed false -x 421 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_0\[0\] -fixed false -x 642 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[18\] -fixed false -x 271 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[10\] -fixed false -x 852 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[8\] -fixed false -x 857 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[17\] -fixed false -x 899 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_62\[11\] -fixed false -x 221 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[34\] -fixed false -x 475 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[17\] -fixed false -x 88 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_751 -fixed false -x 617 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_axb_0_i_0 -fixed false -x 522 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[1\] -fixed false -x 71 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[19\] -fixed false -x 775 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[5\] -fixed false -x 319 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[17\] -fixed false -x 860 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[5\] -fixed false -x 421 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[4\] -fixed false -x 414 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[13\] -fixed false -x 71 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[18\] -fixed false -x 885 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[1\] -fixed false -x 300 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_657 -fixed false -x 639 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_6_212_a2 -fixed false -x 312 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[24\] -fixed false -x 851 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[23\] -fixed false -x 750 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_756 -fixed false -x 715 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_22 -fixed false -x 792 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[6\] -fixed false -x 420 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[18\] -fixed false -x 39 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i\[9\] -fixed false -x 285 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s -fixed false -x 757 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[13\] -fixed false -x 601 -y 138
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[4\] -fixed false -x 57 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[11\] -fixed false -x 234 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[17\] -fixed false -x 917 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[11\] -fixed false -x 128 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_0_a2\[2\] -fixed false -x 739 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[18\] -fixed false -x 865 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[22\] -fixed false -x 708 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[3\] -fixed false -x 395 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack -fixed false -x 907 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_365 -fixed false -x 752 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO\[12\] -fixed false -x 241 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_502 -fixed false -x 666 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[2\] -fixed false -x 294 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25\[4\] -fixed false -x 254 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4\[6\] -fixed false -x 139 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[30\] -fixed false -x 666 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[3\] -fixed false -x 605 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[30\] -fixed false -x 477 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2\[3\] -fixed false -x 241 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[26\] -fixed false -x 853 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un5_mul_mc -fixed false -x 802 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1 -fixed false -x 91 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[11\] -fixed false -x 481 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[11\] -fixed false -x 426 -y 154
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit_RNO\[0\] -fixed false -x 461 -y 144
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_10_iv -fixed false -x 520 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[7\] -fixed false -x 850 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[9\] -fixed false -x 266 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[4\] -fixed false -x 14 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_hword_high_only_req\[0\] -fixed false -x 867 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O11Oo\[0\] -fixed false -x 106 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[7\] -fixed false -x 339 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IOlo1 -fixed false -x 318 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[1\] -fixed false -x 403 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o2_0\[0\] -fixed false -x 45 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[4\] -fixed false -x 268 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[10\] -fixed false -x 725 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[30\] -fixed false -x 703 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[20\] -fixed false -x 130 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/io101 -fixed false -x 114 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[5\] -fixed false -x 539 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[8\] -fixed false -x 880 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_0_0_a2_0\[1\] -fixed false -x 703 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[23\] -fixed false -x 270 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[10\] -fixed false -x 838 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_5_1\[12\] -fixed false -x 114 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv\[3\] -fixed false -x 759 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[30\] -fixed false -x 243 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[17\] -fixed false -x 90 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[2\] -fixed false -x 187 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[19\] -fixed false -x 446 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[5\] -fixed false -x 213 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[2\] -fixed false -x 896 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[19\] -fixed false -x 897 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1_0\[9\] -fixed false -x 212 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[17\] -fixed false -x 407 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/wr_data -fixed false -x 762 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[3\] -fixed false -x 932 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[11\] -fixed false -x 497 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_17 -fixed false -x 829 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[6\] -fixed false -x 390 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[15\] -fixed false -x 560 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0_1\[31\] -fixed false -x 942 -y 135
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[0\] -fixed false -x 7 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[6\] -fixed false -x 899 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[2\] -fixed false -x 235 -y 213
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_8 -fixed false -x 484 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[9\] -fixed false -x 84 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_illegal_instr_ex -fixed false -x 718 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel -fixed false -x 721 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[13\] -fixed false -x 183 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[17\] -fixed false -x 696 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/debug_reset_pending_2 -fixed false -x 776 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_1_i_o2 -fixed false -x 64 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO -fixed false -x 888 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO -fixed false -x 829 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[26\] -fixed false -x 453 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1 -fixed false -x 54 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[18\] -fixed false -x 736 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[7\] -fixed false -x 157 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2\[2\] -fixed false -x 153 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1\[15\] -fixed false -x 28 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[11\] -fixed false -x 547 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[6\] -fixed false -x 720 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_2 -fixed false -x 163 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o10Oo -fixed false -x 155 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[7\] -fixed false -x 183 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[1\] -fixed false -x 482 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[0\] -fixed false -x 346 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_106 -fixed false -x 601 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[3\] -fixed false -x 164 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1 -fixed false -x 767 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un6_IOII1 -fixed false -x 403 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iO0i1 -fixed false -x 145 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OlIOo -fixed false -x 118 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo\[0\] -fixed false -x 128 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[5\] -fixed false -x 525 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[3\] -fixed false -x 533 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[10\] -fixed false -x 509 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[20\] -fixed false -x 857 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[3\] -fixed false -x 507 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[26\] -fixed false -x 754 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[3\] -fixed false -x 330 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR\[0\] -fixed false -x 572 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_0_a2\[1\] -fixed false -x 735 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[5\] -fixed false -x 378 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[2\] -fixed false -x 794 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOiI1 -fixed false -x 342 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[23\] -fixed false -x 413 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/wr_en_data_or_0 -fixed false -x 748 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_44\[9\] -fixed false -x 281 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[5\] -fixed false -x 309 -y 186
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0 -fixed false -x 2 -y 377
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI9E8GO\[21\] -fixed false -x 883 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO\[11\] -fixed false -x 155 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[17\] -fixed false -x 419 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[6\] -fixed false -x 450 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[3\] -fixed false -x 385 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_290 -fixed false -x 811 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[2\] -fixed false -x 718 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[3\] -fixed false -x 265 -y 151
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[15\].BUFD_BLK -fixed false -x 511 -y 105
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[7\] -fixed false -x 373 -y 241
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg2Seq.controlReg25 -fixed false -x 461 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[12\] -fixed false -x 379 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1_0 -fixed false -x 33 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_c2 -fixed false -x 201 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[9\] -fixed false -x 380 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[6\] -fixed false -x 316 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1\[3\] -fixed false -x 142 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[8\] -fixed false -x 151 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[4\] -fixed false -x 498 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[30\] -fixed false -x 346 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OIOl1 -fixed false -x 440 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[14\] -fixed false -x 890 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[31\] -fixed false -x 384 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[10\] -fixed false -x 688 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[17\] -fixed false -x 671 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_e_0 -fixed false -x 796 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_lO1O1 -fixed false -x 433 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un83_rv32i_dec_gpr_wr_valid -fixed false -x 709 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_0\[1\] -fixed false -x 873 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_5\[0\] -fixed false -x 337 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lliOo_0\[6\] -fixed false -x 354 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[10\] -fixed false -x 261 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38_1 -fixed false -x 785 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[25\] -fixed false -x 425 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O00o1_f0\[2\] -fixed false -x 14 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_930 -fixed false -x 677 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[22\] -fixed false -x 750 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[0\] -fixed false -x 73 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOi01 -fixed false -x 31 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4\[4\] -fixed false -x 260 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[62\] -fixed false -x 952 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_10\[9\] -fixed false -x 280 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m18 -fixed false -x 64 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m4 -fixed false -x 53 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[18\] -fixed false -x 854 -y 141
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_0_a2 -fixed false -x 65 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_m2_0 -fixed false -x 631 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[7\] -fixed false -x 104 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un13_mul_mc_3_0_RNIKK0HI1 -fixed false -x 795 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/write_en_1 -fixed false -x 643 -y 114
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[5\] -fixed false -x 402 -y 256
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[30\] -fixed false -x 846 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[6\] -fixed false -x 146 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[4\] -fixed false -x 389 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[20\] -fixed false -x 465 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0 -fixed false -x 751 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[23\] -fixed false -x 787 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[13\] -fixed false -x 381 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[2\] -fixed false -x 346 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[10\] -fixed false -x 370 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[11\] -fixed false -x 551 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[30\] -fixed false -x 786 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/wfi_waiting_reg -fixed false -x 769 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[14\] -fixed false -x 832 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1\[7\] -fixed false -x 309 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I15 -fixed false -x 385 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[29\] -fixed false -x 932 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0\[3\] -fixed false -x 544 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[1\] -fixed false -x 690 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[20\] -fixed false -x 424 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_0_sqmuxa -fixed false -x 531 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[26\] -fixed false -x 485 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[2\] -fixed false -x 277 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNILQ8GO\[27\] -fixed false -x 902 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmcontrol_ndmreset13_4_0_o2_0 -fixed false -x 699 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/I0OI1 -fixed false -x 246 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI10U4D -fixed false -x 763 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[0\] -fixed false -x 269 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_9 -fixed false -x 679 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNI96C8E\[31\] -fixed false -x 612 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_14 -fixed false -x 713 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_27 -fixed false -x 163 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5\[2\] -fixed false -x 236 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_375 -fixed false -x 751 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_m6_0_a2_3_RNIV0MS12 -fixed false -x 811 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_434 -fixed false -x 699 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[19\] -fixed false -x 902 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3_0_0\[0\] -fixed false -x 664 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[19\] -fixed false -x 442 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[2\] -fixed false -x 243 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[3\] -fixed false -x 134 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_cZ\[0\] -fixed false -x 652 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_0_sqmuxa_i_a2 -fixed false -x 686 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[23\] -fixed false -x 471 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[25\] -fixed false -x 678 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[32\] -fixed false -x 482 -y 208
|
|
set_location -inst_name AND2_2 -fixed false -x 47 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un59_OOOI1\[21\] -fixed false -x 465 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[3\] -fixed false -x 25 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[6\] -fixed false -x 158 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_0 -fixed false -x 627 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OI0l1\[0\] -fixed false -x 444 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_0\[22\] -fixed false -x 824 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[29\] -fixed false -x 430 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[8\] -fixed false -x 377 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[6\] -fixed false -x 55 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i_o4 -fixed false -x 288 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[5\] -fixed false -x 66 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[4\] -fixed false -x 191 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_259 -fixed false -x 595 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv\[4\] -fixed false -x 498 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[9\] -fixed false -x 323 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[8\] -fixed false -x 786 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[28\] -fixed false -x 941 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[5\] -fixed false -x 283 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[16\] -fixed false -x 861 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[1\] -fixed false -x 181 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[7\] -fixed false -x 789 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001_0\[7\] -fixed false -x 93 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[22\] -fixed false -x 970 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_3_0_a2_0\[30\] -fixed false -x 159 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un12_lolIo -fixed false -x 116 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_firstrx -fixed false -x 505 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[5\] -fixed false -x 137 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00017 -fixed false -x 61 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[23\] -fixed false -x 760 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_3 -fixed false -x 227 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[27\] -fixed false -x 800 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[2\] -fixed false -x 441 -y 214
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[8\] -fixed false -x 567 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34\[11\] -fixed false -x 270 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[11\] -fixed false -x 383 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_0_1 -fixed false -x 616 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[29\] -fixed false -x 919 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_rs2_rd_hzd_5 -fixed false -x 724 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[14\] -fixed false -x 424 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[19\] -fixed false -x 858 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_983 -fixed false -x 801 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[28\] -fixed false -x 782 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[13\] -fixed false -x 600 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2\[3\] -fixed false -x 117 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z\[38\] -fixed false -x 427 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/un9_req_wr_byte_en_mux\[0\] -fixed false -x 723 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[21\] -fixed false -x 870 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[2\] -fixed false -x 415 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1\[4\] -fixed false -x 644 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[5\] -fixed false -x 298 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[35\] -fixed false -x 483 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[0\] -fixed false -x 234 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un5_lsu_emi_req_rd_byte_en -fixed false -x 740 -y 129
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[21\].BUFD_BLK -fixed false -x 531 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO\[1\] -fixed false -x 768 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_161 -fixed false -x 665 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[17\] -fixed false -x 375 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[27\] -fixed false -x 735 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[16\] -fixed false -x 238 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[0\] -fixed false -x 182 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[10\] -fixed false -x 456 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[7\] -fixed false -x 38 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[22\] -fixed false -x 761 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto15 -fixed false -x 184 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[18\] -fixed false -x 678 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[7\] -fixed false -x 234 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[29\] -fixed false -x 548 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oil11 -fixed false -x 278 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[10\] -fixed false -x 675 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[14\] -fixed false -x 367 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[19\] -fixed false -x 733 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[62\] -fixed false -x 924 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[13\] -fixed false -x 265 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0_1\[1\] -fixed false -x 651 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m56 -fixed false -x 31 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[3\] -fixed false -x 638 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[23\] -fixed false -x 550 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[2\] -fixed false -x 164 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[11\] -fixed false -x 195 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_7 -fixed false -x 189 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1 -fixed false -x 166 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_mux -fixed false -x 518 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_362 -fixed false -x 685 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_28_u_2\[31\] -fixed false -x 928 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[10\] -fixed false -x 371 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958 -fixed false -x 678 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[2\] -fixed false -x 429 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_26\[10\] -fixed false -x 283 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[0\] -fixed false -x 241 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_msie/gen_bit_no_reset.state_val\[0\] -fixed false -x 763 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[3\] -fixed false -x 302 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a2_0_0 -fixed false -x 197 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[4\] -fixed false -x 165 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_893 -fixed false -x 690 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[12\] -fixed false -x 486 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124_2 -fixed false -x 664 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_9 -fixed false -x 633 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[6\] -fixed false -x 597 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[1\] -fixed false -x 521 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[13\] -fixed false -x 904 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[14\] -fixed false -x 711 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[16\] -fixed false -x 434 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[7\] -fixed false -x 345 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2_0\[1\] -fixed false -x 119 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok -fixed false -x 520 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[0\] -fixed false -x 475 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[3\] -fixed false -x 588 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un41_trap_val -fixed false -x 720 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q\[2\] -fixed false -x 501 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[4\] -fixed false -x 674 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/un1_Ioli0_1_0 -fixed false -x 289 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[0\] -fixed false -x 199 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[2\] -fixed false -x 163 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_instr_decoded_1 -fixed false -x 680 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[20\] -fixed false -x 733 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_7 -fixed false -x 78 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[15\] -fixed false -x 190 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[3\] -fixed false -x 59 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[13\] -fixed false -x 30 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[9\] -fixed false -x 97 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_lsu_stall.un14_gpr_rs1_stall_lsu_RNINNK3H -fixed false -x 791 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter_0 -fixed false -x 780 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0_1_0\[0\] -fixed false -x 200 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_298 -fixed false -x 699 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_RNO_1 -fixed false -x 43 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7\[13\] -fixed false -x 80 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_350 -fixed false -x 664 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[4\] -fixed false -x 421 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0_RNI6HAHHG1 -fixed false -x 821 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/un1_iOI01_1_0_a3_i -fixed false -x 277 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[3\] -fixed false -x 322 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[2\] -fixed false -x 852 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_964 -fixed false -x 677 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[18\] -fixed false -x 640 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[5\] -fixed false -x 411 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNILO6GO\[18\] -fixed false -x 885 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_3 -fixed false -x 185 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[11\] -fixed false -x 374 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29\[1\] -fixed false -x 250 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_3\[9\] -fixed false -x 296 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[59\] -fixed false -x 951 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[14\] -fixed false -x 571 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[17\] -fixed false -x 316 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[18\] -fixed false -x 472 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1\[0\] -fixed false -x 115 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2\[0\] -fixed false -x 684 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o2\[8\] -fixed false -x 123 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[9\] -fixed false -x 409 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_8\[13\] -fixed false -x 642 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[11\] -fixed false -x 343 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[16\] -fixed false -x 740 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[5\] -fixed false -x 905 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_10\[10\] -fixed false -x 279 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[26\] -fixed false -x 403 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_3 -fixed false -x 704 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o12_2 -fixed false -x 691 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_10 -fixed false -x 752 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[13\] -fixed false -x 375 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[27\] -fixed false -x 151 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1 -fixed false -x 271 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[24\] -fixed false -x 930 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/sw_csr_wr_valid_qual -fixed false -x 767 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[2\] -fixed false -x 123 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[4\] -fixed false -x 730 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1083 -fixed false -x 643 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1IO1 -fixed false -x 162 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1 -fixed false -x 145 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[1\] -fixed false -x 247 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[1\] -fixed false -x 322 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iII11 -fixed false -x 113 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[21\] -fixed false -x 877 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[6\] -fixed false -x 423 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l1lIo.m5 -fixed false -x 58 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[7\] -fixed false -x 830 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[1\] -fixed false -x 798 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[9\] -fixed false -x 722 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un23_ool01 -fixed false -x 198 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[16\] -fixed false -x 891 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[13\] -fixed false -x 122 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_32\[9\] -fixed false -x 195 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[26\] -fixed false -x 771 -y 145
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_30_f0\[0\] -fixed false -x 520 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2\[1\] -fixed false -x 118 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[34\] -fixed false -x 414 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z\[2\] -fixed false -x 138 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m3 -fixed false -x 114 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[25\] -fixed false -x 287 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tbi_rx_1 -fixed false -x 47 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[14\] -fixed false -x 857 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[2\] -fixed false -x 611 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[20\] -fixed false -x 411 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[4\] -fixed false -x 422 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_4_1_0\[5\] -fixed false -x 719 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[11\] -fixed false -x 228 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[2\] -fixed false -x 416 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[26\] -fixed false -x 721 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[37\] -fixed false -x 143 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[10\] -fixed false -x 467 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_7 -fixed false -x 222 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[18\] -fixed false -x 893 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[4\] -fixed false -x 235 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[8\] -fixed false -x 358 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2_1 -fixed false -x 79 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO_0 -fixed false -x 850 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[28\] -fixed false -x 814 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe_1_sqmuxa_1 -fixed false -x 537 -y 144
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[16\] -fixed false -x 378 -y 238
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q3 -fixed false -x 537 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count\[0\] -fixed false -x 785 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_1_sqmuxa_i -fixed false -x 785 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[2\] -fixed false -x 237 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un35_ool01 -fixed false -x 182 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_1 -fixed false -x 830 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_155 -fixed false -x 710 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_7\[5\] -fixed false -x 306 -y 204
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO\[1\] -fixed false -x 524 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[32\] -fixed false -x 490 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[34\] -fixed false -x 915 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en\[1\] -fixed false -x 710 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IloOo -fixed false -x 118 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[30\] -fixed false -x 929 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[2\] -fixed false -x 716 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_900 -fixed false -x 739 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[11\] -fixed false -x 150 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[7\] -fixed false -x 760 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[30\] -fixed false -x 269 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[4\].BUFD_BLK -fixed false -x 535 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[28\] -fixed false -x 682 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[1\] -fixed false -x 67 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[35\] -fixed false -x 918 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0_1_0\[0\] -fixed false -x 293 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[3\] -fixed false -x 186 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[10\] -fixed false -x 89 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[14\] -fixed false -x 32 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o01i1_0_a3 -fixed false -x 197 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[11\] -fixed false -x 499 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_m8_i_a5_1_d_0_1 -fixed false -x 805 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1o11 -fixed false -x 270 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1\[10\] -fixed false -x 140 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[4\] -fixed false -x 691 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1168 -fixed false -x 690 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[2\] -fixed false -x 894 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[24\] -fixed false -x 588 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_9_0\[0\] -fixed false -x 792 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[6\] -fixed false -x 642 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un5_ool01_0 -fixed false -x 54 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[6\] -fixed false -x 355 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0_o2 -fixed false -x 62 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_828 -fixed false -x 701 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[3\] -fixed false -x 236 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_14\[0\] -fixed false -x 333 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[26\] -fixed false -x 864 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI0o1 -fixed false -x 66 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNIFR1EB -fixed false -x 168 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_1_2 -fixed false -x 196 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[5\] -fixed false -x 63 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[22\] -fixed false -x 818 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24\[11\] -fixed false -x 295 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_m1_0_a2_a1_0 -fixed false -x 791 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IOi01 -fixed false -x 39 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_valid -fixed false -x 729 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_171 -fixed false -x 617 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[2\] -fixed false -x 163 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1\[1\] -fixed false -x 137 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un2_Oil01 -fixed false -x 182 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_585 -fixed false -x 593 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[1\] -fixed false -x 377 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_404 -fixed false -x 651 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[17\] -fixed false -x 62 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[5\] -fixed false -x 421 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_242 -fixed false -x 665 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[4\] -fixed false -x 944 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_clock8 -fixed false -x 447 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[11\] -fixed false -x 47 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[3\] -fixed false -x 271 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[4\] -fixed false -x 847 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_access_parity_error_0_sqmuxa -fixed false -x 857 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[15\] -fixed false -x 842 -y 141
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_5 -fixed false -x 508 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIFCF031\[24\] -fixed false -x 765 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[14\] -fixed false -x 777 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[6\] -fixed false -x 177 -y 214
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0 -fixed false -x 1154 -y 162
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[10\].BUFD_BLK -fixed false -x 532 -y 102
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un170_i11Io -fixed false -x 417 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/i1lIo_1_0_.m5 -fixed false -x 18 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_372 -fixed false -x 652 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[4\] -fixed false -x 260 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe -fixed false -x 527 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_0 -fixed false -x 195 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo\[2\] -fixed false -x 299 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0\[8\] -fixed false -x 123 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_ioOOo_2_0 -fixed false -x 48 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[25\] -fixed false -x 386 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[6\] -fixed false -x 297 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_RNO\[0\] -fixed false -x 476 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[61\] -fixed false -x 934 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[13\] -fixed false -x 647 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[4\] -fixed false -x 184 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OiO01 -fixed false -x 384 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[16\] -fixed false -x 932 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[10\] -fixed false -x 444 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[6\] -fixed false -x 69 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[1\] -fixed false -x 270 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un10_Oo1Io -fixed false -x 419 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[5\] -fixed false -x 397 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[6\] -fixed false -x 224 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[5\] -fixed false -x 440 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO001 -fixed false -x 228 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_reg\[1\] -fixed false -x 793 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[12\] -fixed false -x 517 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1025 -fixed false -x 690 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un150_i11Io -fixed false -x 416 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[8\] -fixed false -x 371 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_0 -fixed false -x 488 -y 159
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state13_i_o4_0_o2 -fixed false -x 22 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[5\] -fixed false -x 358 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[2\] -fixed false -x 345 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[12\] -fixed false -x 717 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[25\] -fixed false -x 656 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[35\] -fixed false -x 496 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_c2 -fixed false -x 559 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_int -fixed false -x 741 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[28\] -fixed false -x 669 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoiO1 -fixed false -x 159 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_974 -fixed false -x 755 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[4\] -fixed false -x 188 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[29\] -fixed false -x 738 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_9 -fixed false -x 140 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_sqmuxa_0 -fixed false -x 522 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[5\] -fixed false -x 505 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[13\] -fixed false -x 350 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[33\] -fixed false -x 678 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo0Oo -fixed false -x 155 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[3\] -fixed false -x 929 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[7\] -fixed false -x 48 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[11\] -fixed false -x 91 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[31\] -fixed false -x 741 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[3\] -fixed false -x 152 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[13\] -fixed false -x 303 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3_0_RNO_2 -fixed false -x 854 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_2 -fixed false -x 656 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[5\] -fixed false -x 503 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[11\] -fixed false -x 775 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex\[1\] -fixed false -x 835 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[2\] -fixed false -x 371 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_0\[9\] -fixed false -x 335 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_q_1.CO0 -fixed false -x 512 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[6\] -fixed false -x 516 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9\[5\] -fixed false -x 200 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr_RNINOH7A\[0\] -fixed false -x 761 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[3\] -fixed false -x 301 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[7\] -fixed false -x 380 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[24\] -fixed false -x 817 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[16\] -fixed false -x 880 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[27\] -fixed false -x 385 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[4\] -fixed false -x 339 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[7\] -fixed false -x 494 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[25\] -fixed false -x 866 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[28\] -fixed false -x 593 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[10\] -fixed false -x 207 -y 181
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[24\] -fixed false -x 409 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[19\] -fixed false -x 817 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_liOI1_4_RNIG18PA -fixed false -x 476 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[4\] -fixed false -x 422 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[4\] -fixed false -x 839 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_411 -fixed false -x 650 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_fault\[1\]\[0\] -fixed false -x 804 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_564 -fixed false -x 664 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[10\] -fixed false -x 401 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[14\] -fixed false -x 732 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_712 -fixed false -x 604 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[13\] -fixed false -x 459 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[7\] -fixed false -x 66 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_5\[29\] -fixed false -x 647 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en_RNIGRABC -fixed false -x 747 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_29_0_RNO -fixed false -x 828 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_ff -fixed false -x 820 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_ex -fixed false -x 781 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1223 -fixed false -x 698 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[9\] -fixed false -x 736 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[3\] -fixed false -x 298 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[30\] -fixed false -x 744 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_1_RNILR2O6\[3\] -fixed false -x 712 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1_RNO_0 -fixed false -x 186 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[3\] -fixed false -x 46 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_890 -fixed false -x 606 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlI01 -fixed false -x 192 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid_2 -fixed false -x 819 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_0_248_a2 -fixed false -x 318 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[27\] -fixed false -x 743 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_221 -fixed false -x 568 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[19\] -fixed false -x 736 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNI9398E\[22\] -fixed false -x 632 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0IO1\[0\] -fixed false -x 136 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[6\] -fixed false -x 423 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[31\] -fixed false -x 683 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_3_230_a2 -fixed false -x 321 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[3\] -fixed false -x 121 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[23\] -fixed false -x 368 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[3\] -fixed false -x 762 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[13\] -fixed false -x 102 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[9\] -fixed false -x 391 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[3\] -fixed false -x 152 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[3\] -fixed false -x 187 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[7\] -fixed false -x 370 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[11\] -fixed false -x 391 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[22\] -fixed false -x 773 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_1_sqmuxa_i_RNIDERNL -fixed false -x 823 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[14\] -fixed false -x 776 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[10\] -fixed false -x 944 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_Ol0i1_2 -fixed false -x 101 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[7\] -fixed false -x 35 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_8 -fixed false -x 617 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[7\] -fixed false -x 153 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIO11_3 -fixed false -x 77 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv\[0\] -fixed false -x 655 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[4\] -fixed false -x 230 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[0\] -fixed false -x 857 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30_1_1 -fixed false -x 930 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_3 -fixed false -x 745 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[23\] -fixed false -x 465 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[1\] -fixed false -x 454 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_en_retr10 -fixed false -x 773 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[15\] -fixed false -x 648 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z\[2\] -fixed false -x 236 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[6\] -fixed false -x 502 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[15\] -fixed false -x 709 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH7RQ8\[11\] -fixed false -x 667 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[2\] -fixed false -x 682 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiO1 -fixed false -x 111 -y 160
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/empty_r_fwft -fixed false -x 407 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[10\] -fixed false -x 492 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_123 -fixed false -x 616 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[29\] -fixed false -x 608 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[4\] -fixed false -x 540 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[3\] -fixed false -x 167 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo\[9\] -fixed false -x 69 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1011_RNO -fixed false -x 265 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[15\] -fixed false -x 467 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[16\] -fixed false -x 859 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[6\] -fixed false -x 222 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[5\] -fixed false -x 917 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[5\] -fixed false -x 258 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[25\] -fixed false -x 736 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[2\] -fixed false -x 378 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag\[1\] -fixed false -x 67 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[59\] -fixed false -x 929 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[3\] -fixed false -x 413 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[19\] -fixed false -x 454 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1100 -fixed false -x 763 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig\[24\] -fixed false -x 703 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[14\] -fixed false -x 714 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[20\] -fixed false -x 53 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[17\] -fixed false -x 918 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[3\] -fixed false -x 357 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un107_i11Io -fixed false -x 415 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1_3_0_a2 -fixed false -x 196 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2\[26\] -fixed false -x 943 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_1 -fixed false -x 827 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m24_2_0 -fixed false -x 24 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[2\] -fixed false -x 354 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[8\] -fixed false -x 212 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[3\] -fixed false -x 436 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_2_2 -fixed false -x 126 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_IOlOo_12_1 -fixed false -x 42 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[9\] -fixed false -x 520 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[25\] -fixed false -x 850 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O00Oo -fixed false -x 169 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[3\] -fixed false -x 351 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_iIOl1 -fixed false -x 354 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m5 -fixed false -x 64 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_18 -fixed false -x 79 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[7\] -fixed false -x 718 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_17_0_i -fixed false -x 222 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[0\] -fixed false -x 223 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Iii11 -fixed false -x 293 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_30 -fixed false -x 687 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[28\] -fixed false -x 398 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m19 -fixed false -x 773 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0o11 -fixed false -x 346 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f1_0 -fixed false -x 693 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m319 -fixed false -x 260 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[4\] -fixed false -x 319 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_1 -fixed false -x 166 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_4 -fixed false -x 65 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO_1 -fixed false -x 889 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[20\] -fixed false -x 386 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[14\] -fixed false -x 883 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[27\] -fixed false -x 656 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[0\] -fixed false -x 543 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[1\] -fixed false -x 319 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIFLUT5 -fixed false -x 383 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[19\] -fixed false -x 73 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[15\] -fixed false -x 751 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0_RNO_0 -fixed false -x 692 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3_1\[14\] -fixed false -x 141 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[37\] -fixed false -x 312 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[0\] -fixed false -x 282 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[1\] -fixed false -x 393 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic852 -fixed false -x 607 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0Oo_RNO -fixed false -x 122 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I10i1 -fixed false -x 160 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_338 -fixed false -x 666 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[2\] -fixed false -x 199 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_5 -fixed false -x 218 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[22\] -fixed false -x 82 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[20\] -fixed false -x 881 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m10 -fixed false -x 45 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[3\] -fixed false -x 82 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[11\] -fixed false -x 844 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[9\] -fixed false -x 67 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i1101 -fixed false -x 110 -y 211
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[6\] -fixed false -x 377 -y 244
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3\[1\] -fixed false -x 570 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO\[1\] -fixed false -x 781 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[23\] -fixed false -x 890 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[60\] -fixed false -x 933 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO_0 -fixed false -x 657 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_ptr_RNIIHIB7\[0\] -fixed false -x 633 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i0Ol1 -fixed false -x 433 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[9\] -fixed false -x 274 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[2\] -fixed false -x 369 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_18\[1\] -fixed false -x 313 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[2\] -fixed false -x 366 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[1\] -fixed false -x 395 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_563 -fixed false -x 711 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[11\] -fixed false -x 213 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_34\[9\] -fixed false -x 921 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[18\] -fixed false -x 434 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[3\] -fixed false -x 700 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[25\] -fixed false -x 680 -y 123
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[15\] -fixed false -x 385 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[4\] -fixed false -x 50 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[36\] -fixed false -x 631 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[0\] -fixed false -x 364 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2128 -fixed false -x 653 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_831 -fixed false -x 692 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[0\] -fixed false -x 747 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[7\] -fixed false -x 452 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[11\] -fixed false -x 558 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI9QCOL2\[0\] -fixed false -x 21 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[13\] -fixed false -x 138 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[3\] -fixed false -x 271 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OO1Oo -fixed false -x 127 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[1\] -fixed false -x 451 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[12\] -fixed false -x 853 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3_0_RNI66NRP -fixed false -x 771 -y 138
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr\[3\] -fixed false -x 451 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[30\] -fixed false -x 921 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[28\] -fixed false -x 723 -y 118
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[0\] -fixed false -x 37 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1\[5\] -fixed false -x 746 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[2\] -fixed false -x 185 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[3\] -fixed false -x 378 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/io1I1 -fixed false -x 403 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[10\] -fixed false -x 396 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1\[1\] -fixed false -x 221 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[11\] -fixed false -x 854 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[16\] -fixed false -x 260 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[23\] -fixed false -x 129 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIi11 -fixed false -x 351 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[8\] -fixed false -x 154 -y 211
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write8_1 -fixed false -x 457 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[7\] -fixed false -x 536 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[0\] -fixed false -x 66 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23\[2\] -fixed false -x 336 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[3\] -fixed false -x 410 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1007 -fixed false -x 724 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel\[2\] -fixed false -x 547 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_574 -fixed false -x 760 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc3 -fixed false -x 49 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg\[4\] -fixed false -x 732 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[8\] -fixed false -x 672 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[25\] -fixed false -x 674 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m18_1_0 -fixed false -x 604 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[16\] -fixed false -x 849 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[3\] -fixed false -x 164 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[31\] -fixed false -x 486 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[22\].BUFD_BLK -fixed false -x 545 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abs_busy_cmb_mux.abstractcs_busy_cmb7_0_a3_RNIHOBJ9 -fixed false -x 669 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[11\] -fixed false -x 416 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2128_2 -fixed false -x 621 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[2\] -fixed false -x 61 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[22\] -fixed false -x 772 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1068 -fixed false -x 664 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[34\] -fixed false -x 318 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[2\] -fixed false -x 199 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[0\] -fixed false -x 312 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioo11 -fixed false -x 389 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[11\] -fixed false -x 357 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lliO1_1_iv_0_RNO\[0\] -fixed false -x 90 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2\[0\] -fixed false -x 259 -y 201
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_4_f0_i_o2_RNI4OQGP -fixed false -x 1 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIF5RQ8\[10\] -fixed false -x 662 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1_2_0_a2 -fixed false -x 209 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[0\] -fixed false -x 258 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[11\] -fixed false -x 41 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[9\] -fixed false -x 45 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff_2_sqmuxa_i -fixed false -x 791 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_oi1l15 -fixed false -x 402 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[11\] -fixed false -x 360 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[15\] -fixed false -x 830 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIi1 -fixed false -x 163 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0_a3_0_1\[3\] -fixed false -x 545 -y 192
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/load_lane_3_f0 -fixed false -x 8 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un16_valid_sba_0_a3 -fixed false -x 690 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[9\] -fixed false -x 422 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[1\] -fixed false -x 548 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[2\] -fixed false -x 337 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid_1 -fixed false -x 606 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv\[3\] -fixed false -x 686 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_63\[31\] -fixed false -x 929 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[4\] -fixed false -x 397 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo52_1 -fixed false -x 47 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_1 -fixed false -x 161 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_996 -fixed false -x 761 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_uar_err_ff_0_sqmuxa -fixed false -x 779 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0\[0\] -fixed false -x 702 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[9\] -fixed false -x 205 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[4\] -fixed false -x 129 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/i1lIo_1_0_.m2 -fixed false -x 17 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[4\] -fixed false -x 361 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_20_0_i -fixed false -x 64 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_7 -fixed false -x 397 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_0 -fixed false -x 474 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0\[2\] -fixed false -x 492 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[9\] -fixed false -x 43 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[26\] -fixed false -x 883 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_il0Oo_2 -fixed false -x 144 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[26\] -fixed false -x 354 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid -fixed false -x 725 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[16\] -fixed false -x 414 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_5 -fixed false -x 747 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[7\] -fixed false -x 919 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg4 -fixed false -x 744 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[13\] -fixed false -x 530 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv\[4\] -fixed false -x 758 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_2 -fixed false -x 797 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[0\] -fixed false -x 225 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[28\] -fixed false -x 841 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[2\] -fixed false -x 110 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_622 -fixed false -x 714 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[56\] -fixed false -x 877 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1\[1\] -fixed false -x 135 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO\[1\] -fixed false -x 788 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3 -fixed false -x 272 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[0\] -fixed false -x 59 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[22\] -fixed false -x 759 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto8_2 -fixed false -x 150 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_527 -fixed false -x 727 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[13\] -fixed false -x 594 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_566 -fixed false -x 749 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[7\] -fixed false -x 89 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[12\] -fixed false -x 272 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[7\] -fixed false -x 89 -y 222
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[14\].BUFD_BLK -fixed false -x 488 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[31\] -fixed false -x 820 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex\[0\] -fixed false -x 751 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_RNO\[9\] -fixed false -x 82 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[9\] -fixed false -x 713 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[2\] -fixed false -x 206 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[0\] -fixed false -x 182 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[12\] -fixed false -x 495 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7\[14\] -fixed false -x 82 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[24\] -fixed false -x 709 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[9\] -fixed false -x 233 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[10\] -fixed false -x 356 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[4\] -fixed false -x 79 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_Tc0_h_En_0_a2_0 -fixed false -x 629 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[0\] -fixed false -x 422 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_1\[2\] -fixed false -x 738 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[5\] -fixed false -x 28 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[16\] -fixed false -x 458 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un117_I1Oi1_2 -fixed false -x 53 -y 177
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[5\].BUFD_BLK -fixed false -x 486 -y 93
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/cdr_start -fixed false -x 22 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.I1li0 -fixed false -x 41 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[17\] -fixed false -x 93 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[27\] -fixed false -x 796 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_1\[14\] -fixed false -x 117 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11_RNO\[0\] -fixed false -x 101 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[20\] -fixed false -x 461 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[25\] -fixed false -x 675 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[23\] -fixed false -x 562 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[29\] -fixed false -x 139 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic849_2 -fixed false -x 606 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[14\] -fixed false -x 323 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[19\] -fixed false -x 448 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[7\] -fixed false -x 66 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE -fixed false -x 24 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[5\] -fixed false -x 509 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO_0 -fixed false -x 821 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[4\] -fixed false -x 708 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4927_0 -fixed false -x 615 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[16\] -fixed false -x 417 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_o2_1 -fixed false -x 635 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[13\] -fixed false -x 297 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[4\] -fixed false -x 405 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[7\] -fixed false -x 289 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m7 -fixed false -x 123 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[4\] -fixed false -x 903 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[20\] -fixed false -x 850 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[11\] -fixed false -x 452 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[8\] -fixed false -x 415 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO -fixed false -x 875 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iooi1 -fixed false -x 110 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.lloIo -fixed false -x 442 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9\[7\] -fixed false -x 749 -y 171
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[6\] -fixed false -x 491 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[3\] -fixed false -x 128 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/resp_dest\[1\] -fixed false -x 797 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[23\] -fixed false -x 464 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_3\[1\] -fixed false -x 162 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_4 -fixed false -x 699 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_2_0_RNO -fixed false -x 539 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[14\] -fixed false -x 711 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[0\] -fixed false -x 851 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[4\] -fixed false -x 235 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[7\] -fixed false -x 246 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[14\] -fixed false -x 470 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_573 -fixed false -x 629 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioli1 -fixed false -x 202 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[17\] -fixed false -x 451 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lOil1 -fixed false -x 413 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_3 -fixed false -x 103 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[1\] -fixed false -x 822 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[11\] -fixed false -x 595 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[29\] -fixed false -x 175 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[24\] -fixed false -x 951 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[49\] -fixed false -x 505 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[10\] -fixed false -x 26 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[6\] -fixed false -x 362 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[27\] -fixed false -x 417 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[28\] -fixed false -x 593 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[5\] -fixed false -x 178 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[1\] -fixed false -x 377 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIDAF031\[24\] -fixed false -x 742 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[15\] -fixed false -x 130 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[5\] -fixed false -x 494 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[49\] -fixed false -x 966 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO_0 -fixed false -x 813 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[4\] -fixed false -x 129 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[21\] -fixed false -x 931 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIS5CS7\[8\] -fixed false -x 898 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[24\] -fixed false -x 772 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_157 -fixed false -x 631 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_3\[4\] -fixed false -x 511 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[37\] -fixed false -x 654 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[3\] -fixed false -x 354 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[19\] -fixed false -x 793 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/wr_en_data_or -fixed false -x 801 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[14\] -fixed false -x 855 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[9\] -fixed false -x 96 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u\[9\] -fixed false -x 894 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_0_sqmuxa_0_a2 -fixed false -x 200 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os_RNIE15QF -fixed false -x 789 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[19\] -fixed false -x 942 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[13\] -fixed false -x 302 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_1_0 -fixed false -x 812 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKY0\[0\] -fixed false -x 724 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[23\] -fixed false -x 930 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0OOo_i_a2 -fixed false -x 121 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI0o1_1 -fixed false -x 70 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un12_O0001 -fixed false -x 81 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_s_RNILMF18T -fixed false -x 812 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[28\] -fixed false -x 697 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io\[0\] -fixed false -x 260 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l00Oo -fixed false -x 160 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_308 -fixed false -x 748 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff -fixed false -x 784 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_m9_i_1 -fixed false -x 55 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/o0IO1 -fixed false -x 185 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_5\[15\] -fixed false -x 657 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[19\] -fixed false -x 670 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un37_ool01\[8\] -fixed false -x 187 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[13\] -fixed false -x 239 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[23\] -fixed false -x 874 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIR9T5J -fixed false -x 756 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[54\] -fixed false -x 908 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[11\] -fixed false -x 195 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_0_3\[4\] -fixed false -x 18 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[7\] -fixed false -x 77 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_0\[6\] -fixed false -x 24 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iiOl1_2_0 -fixed false -x 488 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo -fixed false -x 275 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[22\] -fixed false -x 897 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[3\] -fixed false -x 790 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[5\] -fixed false -x 825 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[6\] -fixed false -x 835 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[5\] -fixed false -x 364 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_rd_op_retr_2_iv -fixed false -x 768 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_0\[3\] -fixed false -x 774 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[2\] -fixed false -x 190 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_5 -fixed false -x 534 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_86\[11\] -fixed false -x 232 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_lsu_op_retr9 -fixed false -x 772 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_0 -fixed false -x 481 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[30\] -fixed false -x 917 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2126 -fixed false -x 652 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_754 -fixed false -x 620 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_s_0_RNICB3SM -fixed false -x 769 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_801 -fixed false -x 784 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[10\] -fixed false -x 725 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto5 -fixed false -x 192 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[17\] -fixed false -x 330 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[26\] -fixed false -x 631 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_6\[0\] -fixed false -x 259 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[7\] -fixed false -x 511 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[9\] -fixed false -x 421 -y 217
|
|
set_location -inst_name SSDetect_0/rx_start\[0\] -fixed false -x 13 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1\[0\] -fixed false -x 139 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O11Io -fixed false -x 71 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[8\] -fixed false -x 429 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[3\] -fixed false -x 62 -y 190
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_RNO\[1\] -fixed false -x 41 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[12\] -fixed false -x 719 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[4\] -fixed false -x 244 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[4\] -fixed false -x 184 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_896 -fixed false -x 747 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_1\[1\] -fixed false -x 58 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[1\] -fixed false -x 768 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINFTQ8\[23\] -fixed false -x 654 -y 126
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[4\] -fixed false -x 53 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[10\] -fixed false -x 608 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[25\] -fixed false -x 740 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[19\] -fixed false -x 669 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_1 -fixed false -x 159 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[31\] -fixed false -x 795 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m224 -fixed false -x 247 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[47\] -fixed false -x 960 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_gpr_wr_valid_int_3 -fixed false -x 739 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/un1_iOI01_1_i_0 -fixed false -x 195 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_2\[1\] -fixed false -x 744 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[2\] -fixed false -x 118 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[10\] -fixed false -x 796 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[11\] -fixed false -x 317 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[20\] -fixed false -x 891 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[20\] -fixed false -x 671 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1_RNO -fixed false -x 100 -y 201
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4_i_0 -fixed false -x 466 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[22\] -fixed false -x 789 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch\[1\] -fixed false -x 670 -y 115
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m4_2_0 -fixed false -x 481 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff_RNO -fixed false -x 682 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m15 -fixed false -x 38 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f1_0_RNO -fixed false -x 691 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[11\] -fixed false -x 31 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[18\] -fixed false -x 510 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[3\].BUFD_BLK -fixed false -x 490 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR19_1_0 -fixed false -x 569 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_576 -fixed false -x 616 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2_5 -fixed false -x 267 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[20\] -fixed false -x 245 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO\[3\] -fixed false -x 18 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[15\] -fixed false -x 273 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[13\] -fixed false -x 836 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/count_en_0 -fixed false -x 780 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoOi1 -fixed false -x 190 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7\[1\] -fixed false -x 318 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[4\] -fixed false -x 168 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[2\] -fixed false -x 506 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[33\].BUFD_BLK -fixed false -x 508 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_haltreq -fixed false -x 745 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l10i1 -fixed false -x 160 -y 199
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_4_f0_i_o2 -fixed false -x 10 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[2\] -fixed false -x 38 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[31\] -fixed false -x 592 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_a2_RNISGK18\[4\] -fixed false -x 753 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IOll1 -fixed false -x 453 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr\[1\] -fixed false -x 778 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[3\] -fixed false -x 265 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_Ilio1 -fixed false -x 55 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[6\] -fixed false -x 366 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[15\] -fixed false -x 88 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[6\] -fixed false -x 676 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[31\] -fixed false -x 486 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[6\] -fixed false -x 916 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[15\] -fixed false -x 710 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[56\] -fixed false -x 922 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4\[1\] -fixed false -x 574 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_295 -fixed false -x 663 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5\[2\] -fixed false -x 257 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilIOo -fixed false -x 31 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[43\] -fixed false -x 507 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[14\] -fixed false -x 928 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[31\] -fixed false -x 819 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[22\] -fixed false -x 759 -y 157
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[5\] -fixed false -x 482 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0_1_0\[0\] -fixed false -x 311 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_ii0Oo_2 -fixed false -x 123 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_0_sqmuxa_0 -fixed false -x 199 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[22\] -fixed false -x 910 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[8\] -fixed false -x 527 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19_0 -fixed false -x 664 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o1oo1_i -fixed false -x 77 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m16 -fixed false -x 44 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_1_1\[3\] -fixed false -x 256 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[0\] -fixed false -x 434 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_div_0 -fixed false -x 815 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_743 -fixed false -x 630 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1109 -fixed false -x 787 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[28\] -fixed false -x 662 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_RNI1R9MH -fixed false -x 735 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124 -fixed false -x 663 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[2\] -fixed false -x 315 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o2\[1\] -fixed false -x 56 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[18\] -fixed false -x 855 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[9\] -fixed false -x 762 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_0_sqmuxa_0 -fixed false -x 197 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un27_ili01_i_o2 -fixed false -x 129 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[0\] -fixed false -x 424 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz_0\[0\] -fixed false -x 651 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[13\] -fixed false -x 915 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[25\] -fixed false -x 399 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[12\] -fixed false -x 823 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[31\] -fixed false -x 804 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[21\] -fixed false -x 618 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IoOl1 -fixed false -x 449 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[5\] -fixed false -x 79 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[6\] -fixed false -x 199 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[7\] -fixed false -x 547 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[9\] -fixed false -x 313 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/llIOo -fixed false -x 46 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[21\] -fixed false -x 112 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIi01\[4\] -fixed false -x 105 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0\[13\] -fixed false -x 275 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[29\] -fixed false -x 457 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[9\] -fixed false -x 431 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[0\] -fixed false -x 189 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[26\] -fixed false -x 842 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[1\] -fixed false -x 410 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs2_rd_hzd_4_3 -fixed false -x 751 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[23\] -fixed false -x 725 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[33\] -fixed false -x 343 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[12\] -fixed false -x 479 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[4\] -fixed false -x 295 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[13\] -fixed false -x 216 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_3 -fixed false -x 437 -y 9
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[59\] -fixed false -x 590 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[9\] -fixed false -x 54 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[1\] -fixed false -x 514 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNI2G7JA\[1\] -fixed false -x 745 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[4\] -fixed false -x 375 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[13\] -fixed false -x 343 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_trigger_wr_hzd_de -fixed false -x 722 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[18\] -fixed false -x 909 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs1_rd_hzd_4_3 -fixed false -x 732 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[14\] -fixed false -x 533 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[8\] -fixed false -x 112 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic853_3 -fixed false -x 605 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1ll1 -fixed false -x 211 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIA6V5D -fixed false -x 258 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol19 -fixed false -x 408 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[6\] -fixed false -x 660 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_653 -fixed false -x 676 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[18\] -fixed false -x 432 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[14\] -fixed false -x 350 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[24\] -fixed false -x 649 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_implicit_pseudo_instr_ex -fixed false -x 775 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_2\[13\] -fixed false -x 751 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[22\] -fixed false -x 250 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo\[0\] -fixed false -x 275 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[10\] -fixed false -x 47 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OlIi1 -fixed false -x 170 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIoOo -fixed false -x 124 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt\[3\] -fixed false -x 457 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mvendorid_sw_rd_sel -fixed false -x 707 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[14\] -fixed false -x 412 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OoiOo_1\[3\] -fixed false -x 130 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[6\] -fixed false -x 765 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_7 -fixed false -x 510 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[50\] -fixed false -x 573 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[13\] -fixed false -x 274 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[1\] -fixed false -x 747 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[6\] -fixed false -x 744 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0_o4\[0\] -fixed false -x 64 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[7\] -fixed false -x 776 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[38\] -fixed false -x 635 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[16\] -fixed false -x 762 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_669 -fixed false -x 691 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9 -fixed false -x 64 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[19\] -fixed false -x 840 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_23\[1\] -fixed false -x 324 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[28\] -fixed false -x 634 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[18\] -fixed false -x 446 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[24\] -fixed false -x 863 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[7\] -fixed false -x 895 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_RNO\[1\] -fixed false -x 720 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[13\] -fixed false -x 904 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[10\] -fixed false -x 875 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[15\] -fixed false -x 477 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[0\] -fixed false -x 798 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[22\] -fixed false -x 885 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[3\] -fixed false -x 608 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0\[1\] -fixed false -x 39 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_RNO\[0\] -fixed false -x 198 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O1111 -fixed false -x 75 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[1\] -fixed false -x 441 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[9\] -fixed false -x 369 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[2\] -fixed false -x 462 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[23\] -fixed false -x 786 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[5\] -fixed false -x 76 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr -fixed false -x 781 -y 129
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3\[2\] -fixed false -x 493 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0_1 -fixed false -x 473 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1_1_0 -fixed false -x 195 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[27\] -fixed false -x 487 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 443 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_6 -fixed false -x 702 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_RNO\[0\] -fixed false -x 168 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[5\] -fixed false -x 63 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[0\] -fixed false -x 594 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/Oi001 -fixed false -x 38 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[13\] -fixed false -x 571 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_3 -fixed false -x 704 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[20\] -fixed false -x 785 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[10\] -fixed false -x 343 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[4\] -fixed false -x 234 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[3\] -fixed false -x 424 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOI11_0_a2 -fixed false -x 137 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[6\] -fixed false -x 270 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[12\] -fixed false -x 148 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[14\] -fixed false -x 705 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[4\] -fixed false -x 246 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[13\] -fixed false -x 222 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1\[2\] -fixed false -x 136 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_0 -fixed false -x 102 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[14\] -fixed false -x 614 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_1\[3\] -fixed false -x 44 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1026 -fixed false -x 559 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftBP -fixed false -x 595 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[39\] -fixed false -x 526 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[9\] -fixed false -x 43 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[16\] -fixed false -x 700 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_2_sqmuxa -fixed false -x 566 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[5\] -fixed false -x 376 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_0_sqmuxa_i_RNO -fixed false -x 359 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1198 -fixed false -x 726 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 254 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa_2 -fixed false -x 504 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/IilI1 -fixed false -x 323 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[3\] -fixed false -x 678 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[1\] -fixed false -x 386 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/oo1Io_2_tz -fixed false -x 411 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1118 -fixed false -x 567 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_21 -fixed false -x 607 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA -fixed false -x 523 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol15 -fixed false -x 392 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[1\] -fixed false -x 417 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[9\] -fixed false -x 235 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11_i_0_tz\[0\] -fixed false -x 69 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[9\] -fixed false -x 137 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[10\] -fixed false -x 631 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_valid_mux_i_o3 -fixed false -x 731 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[22\] -fixed false -x 969 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_3 -fixed false -x 752 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[16\] -fixed false -x 969 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[10\] -fixed false -x 839 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[13\] -fixed false -x 497 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un135_I1Oi1 -fixed false -x 65 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[5\] -fixed false -x 250 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z\[2\] -fixed false -x 256 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[27\].BUFD_BLK -fixed false -x 485 -y 114
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[8\].BUFD_BLK -fixed false -x 510 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[10\] -fixed false -x 736 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[1\] -fixed false -x 878 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[27\] -fixed false -x 564 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[22\] -fixed false -x 847 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lolOo\[0\] -fixed false -x 170 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[15\] -fixed false -x 560 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNIA9JKF\[0\] -fixed false -x 892 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 255 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto15_4_0_3 -fixed false -x 139 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[17\] -fixed false -x 94 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex\[0\] -fixed false -x 762 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[0\] -fixed false -x 638 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4_0\[1\] -fixed false -x 630 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_d_RNI9QM7R2 -fixed false -x 776 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_834_i -fixed false -x 275 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[14\] -fixed false -x 775 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[5\] -fixed false -x 745 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[26\] -fixed false -x 784 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[23\] -fixed false -x 875 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2 -fixed false -x 89 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[6\] -fixed false -x 148 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate\[31\] -fixed false -x 761 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m14 -fixed false -x 40 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10_RNIEPCN26 -fixed false -x 38 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[15\] -fixed false -x 460 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oOoo1_i_0 -fixed false -x 117 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_10 -fixed false -x 34 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[5\] -fixed false -x 564 -y 118
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_0\[0\] -fixed false -x 755 -y 4
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO\[4\] -fixed false -x 205 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[2\] -fixed false -x 353 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o1I01 -fixed false -x 210 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[3\] -fixed false -x 649 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[5\] -fixed false -x 12 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1_RNI6B1NA -fixed false -x 522 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_3_0 -fixed false -x 777 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_2 -fixed false -x 650 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[4\] -fixed false -x 263 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_3_0\[64\] -fixed false -x 957 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[22\] -fixed false -x 842 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[9\] -fixed false -x 128 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_5 -fixed false -x 701 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en\[1\] -fixed false -x 762 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_midbit_3 -fixed false -x 530 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_i\[1\] -fixed false -x 622 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state\[2\] -fixed false -x 527 -y 100
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_2_RNO -fixed false -x 654 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/llll1 -fixed false -x 413 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2\[1\] -fixed false -x 128 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[4\] -fixed false -x 126 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[30\] -fixed false -x 921 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[13\] -fixed false -x 127 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[14\] -fixed false -x 856 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_11 -fixed false -x 440 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[14\] -fixed false -x 718 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[17\] -fixed false -x 735 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[15\] -fixed false -x 78 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO\[0\] -fixed false -x 101 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[1\] -fixed false -x 219 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iO0o1 -fixed false -x 93 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO -fixed false -x 893 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[7\] -fixed false -x 234 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[1\] -fixed false -x 280 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[29\] -fixed false -x 875 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[5\] -fixed false -x 90 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[8\] -fixed false -x 393 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/io1Io -fixed false -x 402 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_0 -fixed false -x 235 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO_1 -fixed false -x 892 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[26\] -fixed false -x 391 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[3\] -fixed false -x 301 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[8\] -fixed false -x 43 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6_3_1 -fixed false -x 796 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_433 -fixed false -x 662 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O01I1 -fixed false -x 484 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[1\] -fixed false -x 194 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_5 -fixed false -x 237 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[2\] -fixed false -x 607 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1\[0\] -fixed false -x 72 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OOii1 -fixed false -x 145 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_6_0_RNO -fixed false -x 802 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[27\] -fixed false -x 735 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[27\] -fixed false -x 487 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[2\] -fixed false -x 509 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[33\] -fixed false -x 849 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[24\] -fixed false -x 738 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[8\] -fixed false -x 337 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[18\] -fixed false -x 436 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 380 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[1\] -fixed false -x 247 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNI9QUVH -fixed false -x 822 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[2\] -fixed false -x 199 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[12\] -fixed false -x 469 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[10\] -fixed false -x 205 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_29\[9\] -fixed false -x 231 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex9 -fixed false -x 750 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1_N_3L3 -fixed false -x 803 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[35\] -fixed false -x 487 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[9\] -fixed false -x 56 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_3 -fixed false -x 162 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_4_224_a2 -fixed false -x 316 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_valid_de_2_RNINIJB6 -fixed false -x 718 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_en_retr -fixed false -x 771 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_679 -fixed false -x 713 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[1\] -fixed false -x 723 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oiIl1 -fixed false -x 456 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places\[4\] -fixed false -x 870 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[54\] -fixed false -x 909 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_152 -fixed false -x 619 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[28\] -fixed false -x 694 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[6\] -fixed false -x 720 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[19\] -fixed false -x 735 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[11\] -fixed false -x 480 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0 -fixed false -x 690 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[28\] -fixed false -x 544 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[28\] -fixed false -x 630 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[10\] -fixed false -x 848 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[11\] -fixed false -x 751 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m13 -fixed false -x 777 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[17\] -fixed false -x 237 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[26\] -fixed false -x 880 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[12\] -fixed false -x 372 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[8\] -fixed false -x 854 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[8\] -fixed false -x 150 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[10\] -fixed false -x 524 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_2\[7\] -fixed false -x 904 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[2\] -fixed false -x 156 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[3\] -fixed false -x 808 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[6\] -fixed false -x 355 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[16\] -fixed false -x 257 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[3\] -fixed false -x 505 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[21\] -fixed false -x 878 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[21\] -fixed false -x 765 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_551 -fixed false -x 701 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_313 -fixed false -x 603 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un4_I1Oi1_1 -fixed false -x 25 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[31\] -fixed false -x 952 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[28\] -fixed false -x 762 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[3\] -fixed false -x 255 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[13\] -fixed false -x 465 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read_0 -fixed false -x 378 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29\[0\] -fixed false -x 248 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIoO1_RNO -fixed false -x 172 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[15\] -fixed false -x 471 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m9 -fixed false -x 702 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[1\] -fixed false -x 319 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_1 -fixed false -x 84 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_fault\[0\]\[2\] -fixed false -x 805 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[13\] -fixed false -x 815 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[2\] -fixed false -x 79 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel -fixed false -x 715 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[24\] -fixed false -x 893 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_654 -fixed false -x 676 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_1 -fixed false -x 225 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[15\] -fixed false -x 165 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_valid_de_2_RNICBFGP -fixed false -x 708 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[8\] -fixed false -x 310 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[8\] -fixed false -x 931 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[10\] -fixed false -x 455 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[17\] -fixed false -x 315 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex\[1\] -fixed false -x 711 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[43\] -fixed false -x 918 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[3\] -fixed false -x 651 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[3\] -fixed false -x 386 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_66\[11\] -fixed false -x 322 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[6\] -fixed false -x 546 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[7\] -fixed false -x 511 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[2\] -fixed false -x 217 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_iooo1 -fixed false -x 51 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[9\] -fixed false -x 910 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[3\] -fixed false -x 210 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel_2 -fixed false -x 690 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1148 -fixed false -x 605 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1\[1\] -fixed false -x 142 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[22\] -fixed false -x 922 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[28\] -fixed false -x 861 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[20\] -fixed false -x 53 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[6\] -fixed false -x 773 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[20\] -fixed false -x 670 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iiii1_3 -fixed false -x 140 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[14\] -fixed false -x 718 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[7\] -fixed false -x 365 -y 160
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_0_sqmuxa -fixed false -x 482 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_i1oOo -fixed false -x 120 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_33\[1\] -fixed false -x 516 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[12\] -fixed false -x 366 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[13\] -fixed false -x 95 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2_0\[6\] -fixed false -x 351 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI47S5C\[27\] -fixed false -x 624 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0\[3\] -fixed false -x 333 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[14\] -fixed false -x 723 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[26\] -fixed false -x 918 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1I11_RNO -fixed false -x 127 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[3\] -fixed false -x 290 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_957 -fixed false -x 664 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_63_RNIH51Q7 -fixed false -x 760 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[27\] -fixed false -x 744 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[27\] -fixed false -x 956 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[8\] -fixed false -x 381 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid_RNIM98PA -fixed false -x 778 -y 132
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/genblk1.RXRDY -fixed false -x 474 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a4\[0\] -fixed false -x 54 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex\[4\] -fixed false -x 768 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[8\] -fixed false -x 58 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[20\] -fixed false -x 594 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[13\] -fixed false -x 601 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1\[3\] -fixed false -x 141 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2\[28\] -fixed false -x 214 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[6\] -fixed false -x 151 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[7\] -fixed false -x 259 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[4\] -fixed false -x 114 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1033 -fixed false -x 653 -y 183
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_6 -fixed false -x 523 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr_0\[0\] -fixed false -x 786 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[12\] -fixed false -x 319 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[27\] -fixed false -x 864 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[21\] -fixed false -x 215 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[27\] -fixed false -x 672 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[15\] -fixed false -x 345 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[7\] -fixed false -x 547 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_739 -fixed false -x 614 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[6\] -fixed false -x 290 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[8\] -fixed false -x 415 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[16\] -fixed false -x 477 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[9\] -fixed false -x 212 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[2\] -fixed false -x 104 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[9\] -fixed false -x 887 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1\[5\] -fixed false -x 541 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[0\] -fixed false -x 259 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_4 -fixed false -x 201 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[5\] -fixed false -x 233 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOiO1 -fixed false -x 322 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[26\] -fixed false -x 955 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[20\] -fixed false -x 951 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_a2_4 -fixed false -x 273 -y 210
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0\[4\] -fixed false -x 522 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0_RNO\[4\] -fixed false -x 63 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[17\] -fixed false -x 653 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[9\] -fixed false -x 386 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_2_0 -fixed false -x 712 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[13\] -fixed false -x 743 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[28\] -fixed false -x 733 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[11\] -fixed false -x 274 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_11\[2\] -fixed false -x 443 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[1\] -fixed false -x 791 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int -fixed false -x 468 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_6\[6\] -fixed false -x 145 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_O0io1_1 -fixed false -x 76 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[7\] -fixed false -x 89 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_div_0_RNING2EQ -fixed false -x 821 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_6\[4\] -fixed false -x 190 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[5\] -fixed false -x 893 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[17\] -fixed false -x 319 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[25\] -fixed false -x 814 -y 120
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[0\] -fixed false -x 13 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[15\] -fixed false -x 846 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_lsu_op_complete_ex -fixed false -x 741 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[5\] -fixed false -x 272 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_26 -fixed false -x 665 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[15\] -fixed false -x 763 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_i_m3_RNI3639C1\[1\] -fixed false -x 701 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0\[2\] -fixed false -x 148 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c_RNO -fixed false -x 754 -y 132
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_byte_2\[7\] -fixed false -x 488 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[11\] -fixed false -x 532 -y 196
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel\[1\] -fixed false -x 431 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[13\] -fixed false -x 419 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[29\] -fixed false -x 904 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[0\] -fixed false -x 786 -y 160
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[0\] -fixed false -x 430 -y 148
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[1\] -fixed false -x 572 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid48 -fixed false -x 736 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[9\] -fixed false -x 175 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[30\] -fixed false -x 779 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[2\] -fixed false -x 195 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[5\] -fixed false -x 28 -y 208
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[6\] -fixed false -x 449 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[1\] -fixed false -x 368 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[28\] -fixed false -x 451 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[21\] -fixed false -x 878 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[21\] -fixed false -x 805 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[14\] -fixed false -x 690 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[10\] -fixed false -x 301 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[15\] -fixed false -x 783 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[8\] -fixed false -x 476 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[8\] -fixed false -x 449 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[8\] -fixed false -x 710 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_o4\[0\] -fixed false -x 618 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[51\] -fixed false -x 606 -y 175
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/active_1 -fixed false -x 499 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[27\] -fixed false -x 918 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_iI0Oo -fixed false -x 283 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIKVKJ31_0 -fixed false -x 758 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1101 -fixed false -x 122 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un52_Oi1O1\[22\] -fixed false -x 440 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[25\] -fixed false -x 877 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_m4_0_a4_0 -fixed false -x 784 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[2\] -fixed false -x 340 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[3\] -fixed false -x 525 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[14\] -fixed false -x 855 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[28\] -fixed false -x 733 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[12\] -fixed false -x 864 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[10\] -fixed false -x 414 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oioo1_1 -fixed false -x 84 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1098 -fixed false -x 678 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[5\] -fixed false -x 258 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1018 -fixed false -x 640 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[4\] -fixed false -x 714 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[0\] -fixed false -x 884 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[30\] -fixed false -x 868 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_3_0_1_0_RNO -fixed false -x 776 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_452 -fixed false -x 639 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en\[1\] -fixed false -x 782 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_23 -fixed false -x 692 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_73\[11\] -fixed false -x 334 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[14\] -fixed false -x 354 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_q_1.CO2 -fixed false -x 596 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1o11_1 -fixed false -x 324 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[7\] -fixed false -x 829 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[31\] -fixed false -x 590 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIANK9D_0 -fixed false -x 816 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[6\] -fixed false -x 33 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[19\] -fixed false -x 176 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[6\] -fixed false -x 149 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[10\] -fixed false -x 435 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[19\] -fixed false -x 775 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[5\] -fixed false -x 150 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[7\] -fixed false -x 463 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[5\] -fixed false -x 337 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lII11 -fixed false -x 132 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[11\] -fixed false -x 550 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[1\] -fixed false -x 47 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[28\] -fixed false -x 950 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_403 -fixed false -x 642 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[5\] -fixed false -x 256 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_415 -fixed false -x 689 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[30\] -fixed false -x 674 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[22\] -fixed false -x 845 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[4\] -fixed false -x 400 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_2\[1\] -fixed false -x 787 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[29\] -fixed false -x 124 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[11\] -fixed false -x 530 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4\[4\] -fixed false -x 124 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_282 -fixed false -x 686 -y 171
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[3\] -fixed false -x 486 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[7\] -fixed false -x 286 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[0\] -fixed false -x 166 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_1_tz_0 -fixed false -x 66 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1 -fixed false -x 420 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_10\[8\] -fixed false -x 180 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[5\] -fixed false -x 766 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[24\] -fixed false -x 408 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2\[0\] -fixed false -x 57 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[46\] -fixed false -x 909 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[17\] -fixed false -x 442 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_9 -fixed false -x 596 -y 141
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_4_i_a2 -fixed false -x 26 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[6\] -fixed false -x 226 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olo01 -fixed false -x 97 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q\[0\] -fixed false -x 506 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[3\] -fixed false -x 62 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex\[0\] -fixed false -x 769 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIi1 -fixed false -x 121 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[20\] -fixed false -x 379 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_1735_fast -fixed false -x 773 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO\[2\] -fixed false -x 540 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[17\] -fixed false -x 918 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[13\].BUFD_BLK -fixed false -x 509 -y 105
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[5\] -fixed false -x 474 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[15\] -fixed false -x 333 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[29\] -fixed false -x 669 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv\[14\] -fixed false -x 712 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0_a3\[1\] -fixed false -x 806 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[1\] -fixed false -x 503 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2124_1_RNICC9EV -fixed false -x 643 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[5\] -fixed false -x 272 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNI33MKF -fixed false -x 793 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[31\] -fixed false -x 741 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[11\] -fixed false -x 137 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_1_sqmuxa -fixed false -x 536 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1\[3\] -fixed false -x 137 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_439 -fixed false -x 590 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_0\[3\] -fixed false -x 46 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_IoI017_1 -fixed false -x 211 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abs_busy_cmb_mux.abstractcs_busy_cmb7_0_a3 -fixed false -x 707 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[7\] -fixed false -x 254 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[9\] -fixed false -x 377 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[6\] -fixed false -x 495 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRCAP -fixed false -x 512 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[13\] -fixed false -x 766 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[5\] -fixed false -x 250 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[29\] -fixed false -x 814 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[25\] -fixed false -x 788 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001_3 -fixed false -x 84 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_5 -fixed false -x 742 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_931 -fixed false -x 641 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m37 -fixed false -x 24 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[60\] -fixed false -x 927 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo_2 -fixed false -x 331 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[1\] -fixed false -x 419 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRSH -fixed false -x 511 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs2_rd_hzd_4_1 -fixed false -x 749 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[39\] -fixed false -x 656 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[10\] -fixed false -x 828 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[3\] -fixed false -x 624 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2\[3\] -fixed false -x 132 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_696 -fixed false -x 736 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_31\[10\] -fixed false -x 230 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[7\] -fixed false -x 894 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_2\[5\] -fixed false -x 128 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[5\] -fixed false -x 481 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1055 -fixed false -x 735 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[3\] -fixed false -x 255 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[3\] -fixed false -x 131 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[8\] -fixed false -x 45 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs1_rd_hzd_4_1 -fixed false -x 739 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[9\] -fixed false -x 831 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[2\] -fixed false -x 777 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_x2\[2\] -fixed false -x 297 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[29\] -fixed false -x 593 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IIiO1_RNO -fixed false -x 246 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1I11 -fixed false -x 167 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNICR75C\[11\] -fixed false -x 102 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[7\] -fixed false -x 271 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[4\] -fixed false -x 662 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[7\] -fixed false -x 207 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_irq_reg/gen_bit_reset.state_val\[0\] -fixed false -x 695 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[0\] -fixed false -x 198 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[17\] -fixed false -x 563 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/IilI1 -fixed false -x 289 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[21\] -fixed false -x 437 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1\[3\] -fixed false -x 65 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_RNO\[8\] -fixed false -x 80 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[2\] -fixed false -x 280 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[10\] -fixed false -x 833 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[48\] -fixed false -x 965 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[11\] -fixed false -x 382 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_240 -fixed false -x 733 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[22\] -fixed false -x 439 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[6\] -fixed false -x 92 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[2\] -fixed false -x 716 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[6\] -fixed false -x 271 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[0\] -fixed false -x 790 -y 106
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_0_RNICHLUR -fixed false -x 806 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1 -fixed false -x 696 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[22\] -fixed false -x 871 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_199 -fixed false -x 566 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[4\] -fixed false -x 211 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1\[37\] -fixed false -x 422 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[8\] -fixed false -x 478 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_o2_0 -fixed false -x 641 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[2\] -fixed false -x 72 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[15\] -fixed false -x 687 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[12\] -fixed false -x 660 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[62\] -fixed false -x 596 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO_0 -fixed false -x 820 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_421 -fixed false -x 764 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[9\] -fixed false -x 691 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_814 -fixed false -x 810 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_722 -fixed false -x 664 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m21 -fixed false -x 626 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[5\] -fixed false -x 206 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[17\] -fixed false -x 852 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[3\] -fixed false -x 118 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[22\] -fixed false -x 928 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[9\] -fixed false -x 704 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[6\] -fixed false -x 64 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[2\] -fixed false -x 794 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[14\] -fixed false -x 811 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[0\] -fixed false -x 251 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1253 -fixed false -x 614 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[2\] -fixed false -x 424 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o0I01_2 -fixed false -x 210 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1_0_a2\[22\] -fixed false -x 349 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[24\] -fixed false -x 674 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[25\] -fixed false -x 551 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[8\] -fixed false -x 668 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[9\] -fixed false -x 144 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[11\] -fixed false -x 365 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[9\] -fixed false -x 367 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[6\] -fixed false -x 198 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2\[2\] -fixed false -x 695 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[4\] -fixed false -x 80 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[14\] -fixed false -x 296 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_351 -fixed false -x 714 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0 -fixed false -x 719 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/un1_Ioli0_1_0 -fixed false -x 258 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_356 -fixed false -x 606 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[4\] -fixed false -x 564 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM\[0\] -fixed false -x 210 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[3\] -fixed false -x 304 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[3\] -fixed false -x 25 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3 -fixed false -x 545 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[0\] -fixed false -x 299 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo\[1\] -fixed false -x 122 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2\[3\] -fixed false -x 255 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[4\] -fixed false -x 176 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oooI1 -fixed false -x 439 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un52_o1Oi1 -fixed false -x 82 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_I1Ii1 -fixed false -x 287 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[3\] -fixed false -x 160 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_709 -fixed false -x 759 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[23\] -fixed false -x 550 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_2 -fixed false -x 631 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0_1_0\[0\] -fixed false -x 257 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[14\] -fixed false -x 141 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0101 -fixed false -x 122 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2\[3\] -fixed false -x 700 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[28\] -fixed false -x 768 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOOl1 -fixed false -x 439 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[16\] -fixed false -x 458 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0_a3_0_2 -fixed false -x 174 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[9\] -fixed false -x 367 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel\[3\] -fixed false -x 422 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_iOii1lto2 -fixed false -x 138 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_2_0_RNO -fixed false -x 797 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[35\] -fixed false -x 460 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[14\] -fixed false -x 342 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[26\].BUFD_BLK -fixed false -x 544 -y 114
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane9_0_a2 -fixed false -x 18 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_gpr_rs1_rd_sel_19_m_1\[3\] -fixed false -x 681 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1048 -fixed false -x 617 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[16\] -fixed false -x 87 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_598 -fixed false -x 594 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iOiO1 -fixed false -x 526 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0\[1\] -fixed false -x 136 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[19\] -fixed false -x 652 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVNFFD\[9\] -fixed false -x 613 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[12\] -fixed false -x 417 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_2 -fixed false -x 703 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i_a2_0 -fixed false -x 290 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ii0I1_RNO -fixed false -x 524 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[5\] -fixed false -x 564 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[5\] -fixed false -x 594 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[5\] -fixed false -x 176 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24\[0\] -fixed false -x 270 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m10 -fixed false -x 44 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un2_next_stage_state_de -fixed false -x 741 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[28\] -fixed false -x 903 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[25\] -fixed false -x 64 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[6\] -fixed false -x 270 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[3\] -fixed false -x 444 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[21\] -fixed false -x 656 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[4\] -fixed false -x 571 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[10\] -fixed false -x 847 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[8\] -fixed false -x 762 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[31\] -fixed false -x 114 -y 150
|
|
set_location -inst_name SSDetect_0/is_match_0.un6_is_match_2 -fixed false -x 14 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001\[1\] -fixed false -x 81 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_2 -fixed false -x 731 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[12\] -fixed false -x 662 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[13\] -fixed false -x 414 -y 198
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_13\[0\] -fixed false -x 749 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_2 -fixed false -x 181 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[9\] -fixed false -x 704 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[13\] -fixed false -x 852 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[4\] -fixed false -x 43 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_1 -fixed false -x 705 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[9\] -fixed false -x 902 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_hit/wr_en_data_or_1 -fixed false -x 805 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[8\] -fixed false -x 420 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_a3_0_RNO -fixed false -x 786 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[11\] -fixed false -x 412 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[0\] -fixed false -x 240 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[7\].BUFD_BLK -fixed false -x 489 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_1 -fixed false -x 722 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_918 -fixed false -x 714 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_10 -fixed false -x 724 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1 -fixed false -x 163 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_at_flush\[0\] -fixed false -x 780 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/wr_data_1 -fixed false -x 790 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_10\[9\] -fixed false -x 144 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[11\] -fixed false -x 917 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[0\] -fixed false -x 83 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIOI98E\[27\] -fixed false -x 625 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO -fixed false -x 858 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[6\] -fixed false -x 556 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[6\] -fixed false -x 830 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo\[1\] -fixed false -x 122 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z\[0\] -fixed false -x 336 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data\[9\] -fixed false -x 719 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[2\] -fixed false -x 727 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1\[1\] -fixed false -x 486 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[6\] -fixed false -x 812 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[2\] -fixed false -x 208 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[15\] -fixed false -x 130 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_6 -fixed false -x 194 -y 198
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9_5 -fixed false -x 506 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[16\] -fixed false -x 809 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[20\] -fixed false -x 823 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[22\] -fixed false -x 460 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[1\] -fixed false -x 246 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel_1 -fixed false -x 714 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo -fixed false -x 21 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_44 -fixed false -x 701 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m4_e_3 -fixed false -x 639 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[22\] -fixed false -x 786 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_debug_enter_req_ex -fixed false -x 811 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_sx -fixed false -x 810 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a2_a0 -fixed false -x 818 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[20\] -fixed false -x 703 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[29\] -fixed false -x 671 -y 123
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_1\[4\] -fixed false -x 39 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_c3_RNIRCS1B -fixed false -x 309 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[6\] -fixed false -x 917 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[11\] -fixed false -x 238 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[5\] -fixed false -x 108 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[2\] -fixed false -x 514 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[16\] -fixed false -x 687 -y 123
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[2\] -fixed false -x 476 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/un1_Ioli0_1_0 -fixed false -x 258 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[2\] -fixed false -x 722 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[4\] -fixed false -x 412 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[7\] -fixed false -x 114 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[14\] -fixed false -x 445 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[13\] -fixed false -x 415 -y 174
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[0\] -fixed false -x 39 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[19\] -fixed false -x 40 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24\[8\] -fixed false -x 210 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[4\] -fixed false -x 872 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[12\] -fixed false -x 366 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l0111 -fixed false -x 124 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_12_2 -fixed false -x 604 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[32\] -fixed false -x 491 -y 208
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_7 -fixed false -x 533 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[9\] -fixed false -x 821 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[30\] -fixed false -x 690 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[2\] -fixed false -x 438 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_711 -fixed false -x 652 -y 183
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[13\].BUFD_BLK -fixed false -x 531 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_843 -fixed false -x 674 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[22\] -fixed false -x 412 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[1\] -fixed false -x 73 -y 223
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[4\] -fixed false -x 353 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave0_PWRITE_s0 -fixed false -x 548 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_8_3_1 -fixed false -x 698 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l0IOo -fixed false -x 15 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[28\] -fixed false -x 701 -y 123
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[9\] -fixed false -x 568 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[8\] -fixed false -x 129 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[8\] -fixed false -x 367 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1064 -fixed false -x 738 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[4\] -fixed false -x 379 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[1\] -fixed false -x 786 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_617 -fixed false -x 602 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[25\] -fixed false -x 720 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[21\] -fixed false -x 857 -y 130
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3\[2\] -fixed false -x 592 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_716 -fixed false -x 664 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPHFFD\[6\] -fixed false -x 626 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[3\] -fixed false -x 173 -y 214
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[28\].BUFD_BLK -fixed false -x 484 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a3 -fixed false -x 176 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[3\] -fixed false -x 608 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m32 -fixed false -x 35 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[18\] -fixed false -x 931 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[2\] -fixed false -x 107 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1127 -fixed false -x 714 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[3\] -fixed false -x 411 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO019_4 -fixed false -x 407 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_0\[29\] -fixed false -x 443 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.lloIo -fixed false -x 375 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0\[4\] -fixed false -x 106 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_248 -fixed false -x 665 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[12\] -fixed false -x 765 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Ii111 -fixed false -x 240 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1_0\[3\] -fixed false -x 189 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_409 -fixed false -x 629 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_5 -fixed false -x 236 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[26\] -fixed false -x 866 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_3 -fixed false -x 702 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[11\] -fixed false -x 831 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[8\] -fixed false -x 446 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[26\] -fixed false -x 453 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[11\] -fixed false -x 182 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[19\] -fixed false -x 460 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[0\] -fixed false -x 16 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv\[2\] -fixed false -x 756 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[0\] -fixed false -x 394 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io1o1_i_0 -fixed false -x 88 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[6\] -fixed false -x 339 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_901 -fixed false -x 680 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I15 -fixed false -x 519 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[1\] -fixed false -x 180 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[35\] -fixed false -x 484 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[9\] -fixed false -x 731 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011 -fixed false -x 268 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m290 -fixed false -x 286 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[2\] -fixed false -x 434 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[42\] -fixed false -x 921 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[39\] -fixed false -x 900 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_l1ll1 -fixed false -x 452 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1009 -fixed false -x 628 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[2\] -fixed false -x 49 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[13\] -fixed false -x 263 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_6_0_a2_0\[15\] -fixed false -x 142 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[18\] -fixed false -x 893 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[7\] -fixed false -x 850 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oo111 -fixed false -x 391 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[2\] -fixed false -x 69 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0\[3\] -fixed false -x 724 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[28\] -fixed false -x 869 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[13\] -fixed false -x 122 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIAGUT5 -fixed false -x 294 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_o3_0\[3\] -fixed false -x 223 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[0\] -fixed false -x 430 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[12\] -fixed false -x 726 -y 154
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_wmux_0_RNIUMTG1\[4\] -fixed false -x 38 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[30\] -fixed false -x 767 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[6\] -fixed false -x 433 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un9_IOIOo -fixed false -x 27 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[4\] -fixed false -x 296 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_72\[11\] -fixed false -x 339 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[14\] -fixed false -x 497 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[7\] -fixed false -x 189 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_RNO -fixed false -x 88 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex -fixed false -x 819 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[1\] -fixed false -x 906 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[14\] -fixed false -x 122 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a2 -fixed false -x 349 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[27\] -fixed false -x 624 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[21\] -fixed false -x 926 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[14\] -fixed false -x 688 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIFBI4J\[14\] -fixed false -x 449 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/next_buff_valid\[0\] -fixed false -x 785 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a2 -fixed false -x 689 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[1\] -fixed false -x 424 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un19_cpu_d_resp_rd_data_sig\[3\] -fixed false -x 761 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[28\] -fixed false -x 940 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/liOi1 -fixed false -x 180 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_0_sqmuxa_RNIRM0K14 -fixed false -x 777 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[10\] -fixed false -x 828 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[7\] -fixed false -x 788 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[14\] -fixed false -x 398 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1\[3\] -fixed false -x 544 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3\[0\] -fixed false -x 257 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_2 -fixed false -x 664 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 379 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[9\] -fixed false -x 454 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[0\] -fixed false -x 120 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[11\] -fixed false -x 838 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[18\] -fixed false -x 804 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll15 -fixed false -x 522 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2\[3\] -fixed false -x 768 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[6\] -fixed false -x 111 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[11\] -fixed false -x 845 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[4\] -fixed false -x 182 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[13\] -fixed false -x 676 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[51\] -fixed false -x 888 -y 181
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[4\] -fixed false -x 488 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[5\] -fixed false -x 279 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Illl1 -fixed false -x 419 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 378 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[0\] -fixed false -x 629 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[12\] -fixed false -x 355 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o3\[3\] -fixed false -x 129 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[9\] -fixed false -x 297 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_49 -fixed false -x 663 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_8 -fixed false -x 722 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01\[21\] -fixed false -x 214 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[5\] -fixed false -x 510 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[13\] -fixed false -x 680 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[36\] -fixed false -x 514 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un74_i11Io -fixed false -x 414 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23 -fixed false -x 798 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[9\] -fixed false -x 678 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[22\] -fixed false -x 893 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[14\] -fixed false -x 492 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m12 -fixed false -x 55 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m20_2_1 -fixed false -x 38 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1268 -fixed false -x 629 -y 180
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[2\] -fixed false -x 23 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[12\] -fixed false -x 823 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_samples6_1_0 -fixed false -x 463 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[24\] -fixed false -x 967 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_164 -fixed false -x 666 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m15 -fixed false -x 732 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[15\] -fixed false -x 272 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un1_Oo1Io_2 -fixed false -x 402 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[7\] -fixed false -x 748 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[15\] -fixed false -x 382 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[14\] -fixed false -x 354 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[17\] -fixed false -x 447 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[5\] -fixed false -x 303 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[28\] -fixed false -x 811 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[3\] -fixed false -x 544 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto10 -fixed false -x 401 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[17\] -fixed false -x 92 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[2\] -fixed false -x 326 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto2_0_RNIJEH7NO -fixed false -x 816 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[15\] -fixed false -x 669 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[2\] -fixed false -x 99 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[23\] -fixed false -x 705 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5\[2\] -fixed false -x 151 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI8BS5C\[29\] -fixed false -x 627 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_a8 -fixed false -x 630 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[24\] -fixed false -x 466 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_4\[1\] -fixed false -x 127 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iil11 -fixed false -x 280 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[6\] -fixed false -x 969 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[6\] -fixed false -x 258 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1\[1\] -fixed false -x 129 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[8\] -fixed false -x 797 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[6\] -fixed false -x 360 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[2\] -fixed false -x 126 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1\[8\] -fixed false -x 79 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[15\] -fixed false -x 288 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[5\] -fixed false -x 445 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0\[0\] -fixed false -x 684 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[27\] -fixed false -x 869 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_48\[11\] -fixed false -x 323 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/havereset_skip_pwrup_4_u_0 -fixed false -x 803 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[8\] -fixed false -x 95 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28\[1\] -fixed false -x 249 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[27\] -fixed false -x 596 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[1\] -fixed false -x 414 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_reg\[0\] -fixed false -x 727 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[5\] -fixed false -x 377 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[9\] -fixed false -x 514 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNI1QTQ8\[28\] -fixed false -x 667 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[14\] -fixed false -x 663 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1073 -fixed false -x 671 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oOll1 -fixed false -x 450 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_0\[0\] -fixed false -x 53 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[4\] -fixed false -x 362 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[2\] -fixed false -x 276 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_26\[33\] -fixed false -x 472 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I15 -fixed false -x 523 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[26\] -fixed false -x 452 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_1\[0\] -fixed false -x 52 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llo01_0 -fixed false -x 106 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[5\] -fixed false -x 391 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2\[24\] -fixed false -x 200 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_RNIP1M96 -fixed false -x 72 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_6 -fixed false -x 110 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iii01\[0\] -fixed false -x 36 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[26\] -fixed false -x 485 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2\[8\] -fixed false -x 640 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[29\] -fixed false -x 593 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_0_0\[1\] -fixed false -x 631 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIO11\[1\] -fixed false -x 13 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_0_sqmuxa_0_a3_0 -fixed false -x 196 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[11\] -fixed false -x 185 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27\[5\] -fixed false -x 251 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0_2\[0\] -fixed false -x 631 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un10_I0io1_0 -fixed false -x 81 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[27\] -fixed false -x 859 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[1\] -fixed false -x 162 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_1\[11\] -fixed false -x 852 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[15\] -fixed false -x 799 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[9\] -fixed false -x 918 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[0\] -fixed false -x 394 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_0_0 -fixed false -x 101 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0\[0\] -fixed false -x 617 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[5\] -fixed false -x 79 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[24\] -fixed false -x 787 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[7\] -fixed false -x 294 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un6_l1I01_2 -fixed false -x 245 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O1li0 -fixed false -x 363 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[21\] -fixed false -x 404 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[2\] -fixed false -x 700 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[3\] -fixed false -x 916 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd -fixed false -x 723 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un195_I1Oi1_0 -fixed false -x 43 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[9\] -fixed false -x 844 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOIi1 -fixed false -x 189 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[24\] -fixed false -x 850 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[10\] -fixed false -x 333 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[12\] -fixed false -x 757 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[1\] -fixed false -x 522 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0\[3\] -fixed false -x 725 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[56\] -fixed false -x 547 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[37\] -fixed false -x 535 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[1\] -fixed false -x 78 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[15\] -fixed false -x 709 -y 138
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[7\] -fixed false -x 79 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.un1_shiftDR20 -fixed false -x 568 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[11\] -fixed false -x 246 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[2\] -fixed false -x 169 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[13\] -fixed false -x 393 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m6 -fixed false -x 615 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34\[1\] -fixed false -x 281 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iii01\[1\] -fixed false -x 38 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_691 -fixed false -x 679 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_219 -fixed false -x 726 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDR_ne_0 -fixed false -x 554 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[21\] -fixed false -x 727 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IO011 -fixed false -x 248 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_62 -fixed false -x 700 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2_0\[15\] -fixed false -x 630 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_9_0_RNO -fixed false -x 794 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[5\] -fixed false -x 426 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[20\] -fixed false -x 770 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[6\] -fixed false -x 134 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[42\] -fixed false -x 493 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_17 -fixed false -x 72 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[1\] -fixed false -x 102 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0 -fixed false -x 104 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m10 -fixed false -x 512 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[0\] -fixed false -x 271 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_valid_mux_1 -fixed false -x 824 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[10\] -fixed false -x 463 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[52\] -fixed false -x 878 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[8\] -fixed false -x 194 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[22\] -fixed false -x 388 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m13 -fixed false -x 115 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_ioIO1_NE_1 -fixed false -x 124 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_840 -fixed false -x 616 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1_0_0 -fixed false -x 67 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[0\] -fixed false -x 320 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2\[7\] -fixed false -x 763 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[7\] -fixed false -x 208 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[38\] -fixed false -x 635 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111\[0\] -fixed false -x 161 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[24\] -fixed false -x 459 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[1\] -fixed false -x 103 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2_1\[0\] -fixed false -x 639 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[20\] -fixed false -x 877 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_0 -fixed false -x 652 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[4\] -fixed false -x 943 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack_RNO -fixed false -x 902 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[13\] -fixed false -x 723 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[7\] -fixed false -x 533 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg -fixed false -x 864 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[12\] -fixed false -x 943 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0\[0\] -fixed false -x 120 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_935 -fixed false -x 641 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[0\] -fixed false -x 73 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooOi1 -fixed false -x 187 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[0\] -fixed false -x 777 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[12\] -fixed false -x 560 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[24\] -fixed false -x 962 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m4 -fixed false -x 109 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_15 -fixed false -x 674 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[4\] -fixed false -x 171 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[29\] -fixed false -x 271 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[7\] -fixed false -x 495 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[24\] -fixed false -x 754 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_297 -fixed false -x 605 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4\[3\] -fixed false -x 457 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[13\] -fixed false -x 48 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[7\] -fixed false -x 428 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_530 -fixed false -x 593 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[10\] -fixed false -x 266 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[10\] -fixed false -x 41 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[6\] -fixed false -x 441 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_2\[6\] -fixed false -x 748 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_o2\[3\] -fixed false -x 642 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[0\] -fixed false -x 780 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_174 -fixed false -x 837 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[6\] -fixed false -x 517 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[0\] -fixed false -x 439 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[0\] -fixed false -x 454 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_4_RNIBT07D -fixed false -x 851 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[14\] -fixed false -x 554 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_783 -fixed false -x 690 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOiOo_NE_0 -fixed false -x 324 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01\[20\] -fixed false -x 213 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIO11 -fixed false -x 31 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[3\] -fixed false -x 251 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2\[3\] -fixed false -x 222 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_0\[0\] -fixed false -x 782 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[28\] -fixed false -x 469 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[0\] -fixed false -x 288 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m15_1 -fixed false -x 603 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO_1 -fixed false -x 837 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM_0\[2\] -fixed false -x 212 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[5\] -fixed false -x 78 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_misalign_error_ex -fixed false -x 752 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ioIIo -fixed false -x 270 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1 -fixed false -x 387 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[0\] -fixed false -x 769 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[7\] -fixed false -x 197 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[6\] -fixed false -x 363 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[21\] -fixed false -x 876 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel -fixed false -x 711 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un442_lIlo1 -fixed false -x 323 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[9\] -fixed false -x 89 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_1 -fixed false -x 390 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/un1_iOI01_1_i_0 -fixed false -x 256 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA_0 -fixed false -x 521 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_15 -fixed false -x 399 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[29\] -fixed false -x 836 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_3 -fixed false -x 67 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[5\] -fixed false -x 64 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[10\] -fixed false -x 148 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_310 -fixed false -x 675 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[11\] -fixed false -x 499 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed\[6\] -fixed false -x 628 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_sx_1 -fixed false -x 808 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_coarse_sel_0_sqmuxa_0 -fixed false -x 63 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_ptr_0\[0\] -fixed false -x 790 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[6\] -fixed false -x 452 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[2\] -fixed false -x 341 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_0\[0\] -fixed false -x 735 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[11\] -fixed false -x 369 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[62\] -fixed false -x 924 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[26\] -fixed false -x 399 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_sn_N_8_mux_i_i_o2 -fixed false -x 499 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[8\] -fixed false -x 379 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OloI1 -fixed false -x 415 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[14\] -fixed false -x 77 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_2 -fixed false -x 224 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1105 -fixed false -x 713 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s0_0_a2 -fixed false -x 487 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[17\] -fixed false -x 319 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[12\] -fixed false -x 700 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[2\] -fixed false -x 122 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O0o01 -fixed false -x 101 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[10\] -fixed false -x 668 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/ebreak_debug_enter_taken_RNIRN07L -fixed false -x 789 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[3\] -fixed false -x 304 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_892 -fixed false -x 675 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[14\] -fixed false -x 532 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oi1o1_0_m2\[0\] -fixed false -x 73 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[14\] -fixed false -x 63 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data\[30\] -fixed false -x 739 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOOo1 -fixed false -x 310 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex -fixed false -x 768 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_5_2 -fixed false -x 170 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[15\] -fixed false -x 385 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io_4 -fixed false -x 401 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o\[0\] -fixed false -x 138 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoo1_i_a2_0_0 -fixed false -x 116 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_resetn_tx -fixed false -x 525 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_addr_align\[1\]\[0\] -fixed false -x 821 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[13\] -fixed false -x 659 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949 -fixed false -x 673 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I0ll1 -fixed false -x 470 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_1\[6\] -fixed false -x 103 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[8\] -fixed false -x 248 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01_5 -fixed false -x 210 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[30\] -fixed false -x 910 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/un1_NxtPrdata23_0_RNI6GCHA -fixed false -x 463 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[28\] -fixed false -x 217 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_2 -fixed false -x 240 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[11\] -fixed false -x 481 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_holdsel -fixed false -x 509 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[8\] -fixed false -x 62 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[27\] -fixed false -x 400 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[2\] -fixed false -x 423 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[13\] -fixed false -x 815 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_Oio11_1 -fixed false -x 330 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_123_i -fixed false -x 767 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_o3 -fixed false -x 138 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[6\] -fixed false -x 111 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[2\] -fixed false -x 731 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[4\] -fixed false -x 421 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[5\] -fixed false -x 361 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un45_oIiOo_1.CO3 -fixed false -x 330 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[12\] -fixed false -x 376 -y 220
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out_RNO -fixed false -x 523 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[22\] -fixed false -x 863 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1202 -fixed false -x 773 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[8\] -fixed false -x 570 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m5 -fixed false -x 663 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_0 -fixed false -x 786 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[34\] -fixed false -x 314 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[2\] -fixed false -x 288 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[12\] -fixed false -x 54 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mscratch_sw_rd_sel -fixed false -x 701 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_767 -fixed false -x 809 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_115 -fixed false -x 631 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_0_sqmuxa_1 -fixed false -x 521 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_7_3_1 -fixed false -x 690 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[27\] -fixed false -x 770 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oo0l1\[0\] -fixed false -x 455 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[2\] -fixed false -x 503 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[14\] -fixed false -x 470 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m27 -fixed false -x 640 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[15\] -fixed false -x 844 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_3_RNIIAS0E3\[0\] -fixed false -x 44 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0\[1\] -fixed false -x 616 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[8\] -fixed false -x 762 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[32\] -fixed false -x 461 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo\[2\] -fixed false -x 37 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[24\] -fixed false -x 353 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[7\] -fixed false -x 893 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[28\] -fixed false -x 714 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/un1_Ioli0_1_0 -fixed false -x 330 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[5\] -fixed false -x 151 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[2\] -fixed false -x 261 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[5\] -fixed false -x 198 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[0\] -fixed false -x 894 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg\[2\] -fixed false -x 809 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[1\] -fixed false -x 256 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[4\] -fixed false -x 892 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[17\] -fixed false -x 740 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[3\] -fixed false -x 152 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match\[1\] -fixed false -x 746 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[8\] -fixed false -x 640 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[12\] -fixed false -x 792 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK -fixed false -x 561 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2\[2\] -fixed false -x 708 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[31\] -fixed false -x 883 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_7 -fixed false -x 209 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[6\] -fixed false -x 234 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1_2 -fixed false -x 45 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo\[3\] -fixed false -x 297 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[2\] -fixed false -x 226 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1 -fixed false -x 172 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1056 -fixed false -x 757 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state\[1\] -fixed false -x 524 -y 100
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1l1_u_1_1 -fixed false -x 444 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001\[0\] -fixed false -x 82 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[11\] -fixed false -x 892 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1301 -fixed false -x 749 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[8\] -fixed false -x 229 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII1118_0 -fixed false -x 131 -y 219
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[3\] -fixed false -x 486 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[39\] -fixed false -x 908 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_869 -fixed false -x 678 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_20\[20\] -fixed false -x 115 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.N_4_i -fixed false -x 44 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[17\] -fixed false -x 898 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[17\] -fixed false -x 237 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[0\] -fixed false -x 133 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[3\] -fixed false -x 669 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[19\] -fixed false -x 924 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[7\] -fixed false -x 744 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[26\] -fixed false -x 908 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[15\] -fixed false -x 536 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[10\] -fixed false -x 666 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[51\] -fixed false -x 611 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_946 -fixed false -x 663 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[14\] -fixed false -x 652 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO\[0\] -fixed false -x 787 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_i\[1\] -fixed false -x 726 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_N_4L6 -fixed false -x 794 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[57\] -fixed false -x 945 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[21\] -fixed false -x 888 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[14\] -fixed false -x 447 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[16\] -fixed false -x 698 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[13\] -fixed false -x 310 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_0_0_tz -fixed false -x 87 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[30\] -fixed false -x 440 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[9\] -fixed false -x 314 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m190 -fixed false -x 245 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[13\] -fixed false -x 400 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[2\] -fixed false -x 767 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_valid_reg -fixed false -x 752 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[7\] -fixed false -x 344 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[29\] -fixed false -x 955 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[17\] -fixed false -x 927 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[0\] -fixed false -x 129 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0\[15\] -fixed false -x 130 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_1\[0\] -fixed false -x 12 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_3\[5\] -fixed false -x 725 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[12\] -fixed false -x 789 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[29\] -fixed false -x 740 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[35\] -fixed false -x 485 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33\[11\] -fixed false -x 281 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr_0\[0\] -fixed false -x 763 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[33\] -fixed false -x 626 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_6 -fixed false -x 748 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2\[15\] -fixed false -x 629 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR\[3\] -fixed false -x 567 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi146 -fixed false -x 125 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_0_1 -fixed false -x 691 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1 -fixed false -x 738 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[14\] -fixed false -x 29 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_1\[13\] -fixed false -x 753 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[9\] -fixed false -x 34 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m40 -fixed false -x 257 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGTK9D -fixed false -x 724 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_0_0_RNI889TQ -fixed false -x 184 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[36\] -fixed false -x 357 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[34\] -fixed false -x 430 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[16\] -fixed false -x 808 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[5\] -fixed false -x 301 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[28\] -fixed false -x 747 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[8\] -fixed false -x 105 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[25\].BUFD_BLK -fixed false -x 483 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_28 -fixed false -x 827 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[1\] -fixed false -x 529 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_7 -fixed false -x 761 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[13\] -fixed false -x 770 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[6\] -fixed false -x 373 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[6\] -fixed false -x 881 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_592 -fixed false -x 630 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[25\] -fixed false -x 398 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un41_Oo1Io -fixed false -x 400 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNO -fixed false -x 812 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[14\] -fixed false -x 860 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo7 -fixed false -x 284 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[2\] -fixed false -x 838 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[6\] -fixed false -x 49 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[4\] -fixed false -x 660 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_905 -fixed false -x 665 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[11\] -fixed false -x 447 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_0 -fixed false -x 819 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_2_0 -fixed false -x 689 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[4\] -fixed false -x 258 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1188 -fixed false -x 616 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/llIIo\[0\] -fixed false -x 128 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[27\] -fixed false -x 122 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[5\] -fixed false -x 434 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[28\] -fixed false -x 408 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_m1_e -fixed false -x 796 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr\[2\] -fixed false -x 700 -y 115
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s1_0_a2 -fixed false -x 481 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[6\] -fixed false -x 422 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un18_lsu_op_str_ex -fixed false -x 756 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[10\] -fixed false -x 407 -y 214
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[27\].BUFD_BLK -fixed false -x 543 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_RNO\[1\] -fixed false -x 644 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[0\] -fixed false -x 71 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_10_158_a2 -fixed false -x 437 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[9\] -fixed false -x 262 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_500 -fixed false -x 734 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[9\] -fixed false -x 447 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[0\] -fixed false -x 621 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[4\] -fixed false -x 496 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15_1 -fixed false -x 692 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[30\] -fixed false -x 854 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[26\] -fixed false -x 918 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_6 -fixed false -x 472 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[5\] -fixed false -x 159 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_0\[8\] -fixed false -x 263 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[13\] -fixed false -x 280 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[25\] -fixed false -x 742 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1oo1 -fixed false -x 65 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[3\] -fixed false -x 163 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m3_e_1 -fixed false -x 803 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_0_sqmuxa_0 -fixed false -x 195 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[31\] -fixed false -x 663 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[28\] -fixed false -x 890 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIOST5C\[30\] -fixed false -x 619 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_4 -fixed false -x 398 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_68 -fixed false -x 798 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_2 -fixed false -x 261 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_IOOl1_1_0 -fixed false -x 436 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[27\] -fixed false -x 812 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_RNO_0\[4\] -fixed false -x 296 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[7\] -fixed false -x 785 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[23\] -fixed false -x 907 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[15\] -fixed false -x 897 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo_7 -fixed false -x 274 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[18\] -fixed false -x 904 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_2\[1\] -fixed false -x 122 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[4\] -fixed false -x 963 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[21\] -fixed false -x 59 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un35_ool01 -fixed false -x 50 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_41\[0\] -fixed false -x 269 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_0_0_a2\[1\] -fixed false -x 699 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[11\] -fixed false -x 855 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_loli1\[0\] -fixed false -x 198 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_777 -fixed false -x 699 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[40\] -fixed false -x 118 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[8\] -fixed false -x 905 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[23\] -fixed false -x 697 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[4\] -fixed false -x 75 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr5 -fixed false -x 787 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4\[2\] -fixed false -x 654 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[4\] -fixed false -x 271 -y 190
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0_a2 -fixed false -x 67 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.g0_0 -fixed false -x 777 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_0_0 -fixed false -x 760 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[5\] -fixed false -x 233 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[7\] -fixed false -x 136 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[19\] -fixed false -x 775 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_196 -fixed false -x 786 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[22\] -fixed false -x 654 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNI1JKNG1 -fixed false -x 654 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[18\] -fixed false -x 435 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[4\] -fixed false -x 269 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_m4_1 -fixed false -x 791 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[28\] -fixed false -x 746 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_323 -fixed false -x 689 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[2\] -fixed false -x 463 -y 193
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[2\] -fixed false -x 485 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1 -fixed false -x 271 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[8\] -fixed false -x 265 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[8\] -fixed false -x 73 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[4\] -fixed false -x 493 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un6_o1ll1_0 -fixed false -x 450 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[5\] -fixed false -x 45 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[6\] -fixed false -x 700 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[6\] -fixed false -x 430 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_m11_0_N_6L10 -fixed false -x 798 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m167 -fixed false -x 284 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[9\] -fixed false -x 689 -y 129
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[26\].BUFD_BLK -fixed false -x 482 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[10\] -fixed false -x 378 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olo11 -fixed false -x 311 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[11\] -fixed false -x 156 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_cZ\[1\] -fixed false -x 677 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.CO0 -fixed false -x 448 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa -fixed false -x 520 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_33 -fixed false -x 769 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[5\] -fixed false -x 67 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[13\] -fixed false -x 131 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[6\] -fixed false -x 154 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[19\] -fixed false -x 941 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1\[6\] -fixed false -x 102 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[12\] -fixed false -x 85 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[5\] -fixed false -x 140 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_879 -fixed false -x 604 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_865 -fixed false -x 615 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_i_m2_RNIJ12JA\[2\] -fixed false -x 727 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[17\] -fixed false -x 734 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_c_0_a1_RNILP91A4 -fixed false -x 790 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[3\] -fixed false -x 321 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1o11 -fixed false -x 342 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[16\] -fixed false -x 463 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[19\] -fixed false -x 538 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[14\] -fixed false -x 174 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[2\] -fixed false -x 307 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[10\] -fixed false -x 238 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_OOoo1_0_a3_1 -fixed false -x 104 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[20\] -fixed false -x 944 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[29\] -fixed false -x 798 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[22\] -fixed false -x 785 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[7\] -fixed false -x 232 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[11\] -fixed false -x 100 -y 225
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_URSTB -fixed false -x 534 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_846 -fixed false -x 677 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[1\] -fixed false -x 261 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr\[0\] -fixed false -x 763 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[15\] -fixed false -x 470 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[13\] -fixed false -x 390 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[35\] -fixed false -x 627 -y 120
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[4\] -fixed false -x 497 -y 145
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[11\].BUFD_BLK -fixed false -x 488 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff -fixed false -x 769 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[8\] -fixed false -x 317 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_0_sqmuxa_0 -fixed false -x 194 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNIE0S1U -fixed false -x 744 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/olOo1 -fixed false -x 302 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_strobe -fixed false -x 539 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_4 -fixed false -x 77 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OO011 -fixed false -x 277 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNID9I4J\[13\] -fixed false -x 606 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo_RNO -fixed false -x 129 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[29\] -fixed false -x 885 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_5 -fixed false -x 278 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1302 -fixed false -x 676 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[8\] -fixed false -x 93 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[9\] -fixed false -x 52 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_1_0 -fixed false -x 759 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_lIoO1 -fixed false -x 171 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[10\] -fixed false -x 494 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_5\[0\] -fixed false -x 666 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_2_0 -fixed false -x 700 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[0\] -fixed false -x 838 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0Ii1 -fixed false -x 121 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17 -fixed false -x 683 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_27 -fixed false -x 654 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[18\] -fixed false -x 827 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[3\] -fixed false -x 329 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I11i1_0_a2 -fixed false -x 208 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[29\] -fixed false -x 598 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[8\] -fixed false -x 257 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[6\] -fixed false -x 248 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un18_OilI1_0_a2 -fixed false -x 320 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[1\] -fixed false -x 403 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1l11 -fixed false -x 433 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[2\] -fixed false -x 868 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[13\] -fixed false -x 713 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[26\] -fixed false -x 676 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[10\] -fixed false -x 252 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1iOo -fixed false -x 111 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICPK9D_0 -fixed false -x 726 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0oI1 -fixed false -x 437 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[24\] -fixed false -x 904 -y 195
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.overflow_int_4 -fixed false -x 474 -y 147
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[6\] -fixed false -x 374 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un160_i11Io -fixed false -x 413 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o\[1\] -fixed false -x 139 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[25\] -fixed false -x 856 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[0\] -fixed false -x 156 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_80\[11\] -fixed false -x 287 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO\[2\] -fixed false -x 718 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[0\] -fixed false -x 681 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_245 -fixed false -x 674 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[2\] -fixed false -x 307 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[29\] -fixed false -x 696 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[8\] -fixed false -x 530 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[17\] -fixed false -x 862 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[17\] -fixed false -x 270 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[5\] -fixed false -x 426 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[30\] -fixed false -x 789 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[18\] -fixed false -x 37 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[10\] -fixed false -x 481 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_RNO\[64\] -fixed false -x 901 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[10\] -fixed false -x 208 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_fence -fixed false -x 735 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[15\] -fixed false -x 616 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[30\] -fixed false -x 812 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[12\] -fixed false -x 490 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2\[1\] -fixed false -x 312 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[1\] -fixed false -x 78 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_1 -fixed false -x 796 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[17\] -fixed false -x 897 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[17\] -fixed false -x 712 -y 118
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[0\] -fixed false -x 514 -y 94
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lIIl1 -fixed false -x 545 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_8 -fixed false -x 138 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[0\] -fixed false -x 89 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[23\] -fixed false -x 769 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15_1 -fixed false -x 467 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[2\] -fixed false -x 301 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[0\] -fixed false -x 282 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[7\] -fixed false -x 376 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[8\] -fixed false -x 835 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[7\] -fixed false -x 916 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[15\] -fixed false -x 930 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1094 -fixed false -x 689 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0\[4\] -fixed false -x 349 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[4\] -fixed false -x 322 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo_RNISIVKC -fixed false -x 245 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[9\] -fixed false -x 457 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[0\] -fixed false -x 883 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1 -fixed false -x 219 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1_4 -fixed false -x 25 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0 -fixed false -x 789 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1014 -fixed false -x 785 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[3\] -fixed false -x 147 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[6\] -fixed false -x 288 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/wr_en_data_or -fixed false -x 727 -y 129
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[14\] -fixed false -x 559 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_a2_0_0_0 -fixed false -x 759 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_olli1lto15_0_0_1 -fixed false -x 196 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3\[0\] -fixed false -x 320 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[14\] -fixed false -x 368 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[5\] -fixed false -x 365 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[4\] -fixed false -x 675 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[19\] -fixed false -x 607 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIIo1_0_o2\[0\] -fixed false -x 295 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[21\] -fixed false -x 275 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[7\] -fixed false -x 210 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_access_mem_error -fixed false -x 801 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[8\] -fixed false -x 91 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand0_mux_sel_1_iv\[0\] -fixed false -x 771 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[6\] -fixed false -x 97 -y 183
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync\[1\] -fixed false -x 5 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_1_0 -fixed false -x 774 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un13_OIoO1\[6\] -fixed false -x 91 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[10\] -fixed false -x 632 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_Olii1_4 -fixed false -x 146 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m12_1_0 -fixed false -x 63 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[11\] -fixed false -x 401 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0\[1\] -fixed false -x 892 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO -fixed false -x 677 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1OIo -fixed false -x 143 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[2\] -fixed false -x 614 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[6\] -fixed false -x 709 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_2\[4\] -fixed false -x 142 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[3\] -fixed false -x 807 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[25\] -fixed false -x 420 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[31\] -fixed false -x 939 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_1_0 -fixed false -x 787 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[4\] -fixed false -x 338 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[10\] -fixed false -x 453 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[20\] -fixed false -x 879 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9\[2\] -fixed false -x 735 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[9\] -fixed false -x 69 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[5\] -fixed false -x 43 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_0\[4\] -fixed false -x 641 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3\[4\] -fixed false -x 954 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[10\] -fixed false -x 159 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957_0_0 -fixed false -x 669 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001\[0\] -fixed false -x 160 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[24\] -fixed false -x 672 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[0\] -fixed false -x 179 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[4\] -fixed false -x 51 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_int\[0\] -fixed false -x 720 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_1\[4\] -fixed false -x 715 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO_1 -fixed false -x 878 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_0 -fixed false -x 208 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[34\] -fixed false -x 475 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[4\] -fixed false -x 241 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oiiI1 -fixed false -x 438 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[12\] -fixed false -x 36 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[3\] -fixed false -x 928 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i10I1 -fixed false -x 392 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[20\] -fixed false -x 894 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[27\] -fixed false -x 800 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oOOo1 -fixed false -x 302 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[24\] -fixed false -x 732 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[15\] -fixed false -x 130 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001\[0\] -fixed false -x 95 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_425 -fixed false -x 629 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[16\] -fixed false -x 132 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[1\] -fixed false -x 278 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO_1 -fixed false -x 819 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[17\] -fixed false -x 93 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[2\] -fixed false -x 164 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[12\] -fixed false -x 407 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_uncompressed_half_i_o2 -fixed false -x 628 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[5\] -fixed false -x 917 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[14\] -fixed false -x 927 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_7 -fixed false -x 682 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_932 -fixed false -x 558 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[3\] -fixed false -x 66 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2_1\[1\] -fixed false -x 644 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[0\] -fixed false -x 124 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[8\] -fixed false -x 372 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[7\] -fixed false -x 405 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI2BDEP\[5\] -fixed false -x 243 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[3\] -fixed false -x 388 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_875 -fixed false -x 746 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[13\] -fixed false -x 398 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_239_i -fixed false -x 178 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[42\] -fixed false -x 145 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264 -fixed false -x 41 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[31\] -fixed false -x 405 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m24 -fixed false -x 54 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i\[10\] -fixed false -x 293 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_OoI01_1 -fixed false -x 210 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[17\] -fixed false -x 45 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.penable -fixed false -x 614 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[21\] -fixed false -x 175 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_357 -fixed false -x 689 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[7\] -fixed false -x 157 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[7\] -fixed false -x 859 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo\[9\] -fixed false -x 300 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1_4_RNIT9LTE -fixed false -x 67 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[9\] -fixed false -x 451 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[2\] -fixed false -x 730 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[17\] -fixed false -x 447 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_s -fixed false -x 510 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1_1\[1\] -fixed false -x 677 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1298 -fixed false -x 697 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1088 -fixed false -x 677 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_1 -fixed false -x 194 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un118_i11Io -fixed false -x 412 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[16\] -fixed false -x 150 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNITOG631\[20\] -fixed false -x 72 -y 207
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_4_c3 -fixed false -x 101 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1218 -fixed false -x 712 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[10\] -fixed false -x 355 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32\[11\] -fixed false -x 194 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_467 -fixed false -x 741 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[3\] -fixed false -x 52 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_1\[2\] -fixed false -x 954 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_4\[31\] -fixed false -x 632 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1_cZ\[19\] -fixed false -x 440 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[12\] -fixed false -x 418 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[13\] -fixed false -x 143 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[1\] -fixed false -x 643 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_39\[3\] -fixed false -x 501 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[20\] -fixed false -x 398 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[58\] -fixed false -x 931 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m1 -fixed false -x 649 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO_0 -fixed false -x 887 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[0\] -fixed false -x 269 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_o2\[7\] -fixed false -x 750 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m80 -fixed false -x 198 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[5\] -fixed false -x 258 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[26\] -fixed false -x 313 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_3\[29\] -fixed false -x 426 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[4\] -fixed false -x 493 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[4\] -fixed false -x 378 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[5\] -fixed false -x 186 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Ii111_2 -fixed false -x 240 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[30\] -fixed false -x 866 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_2\[0\] -fixed false -x 641 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_280 -fixed false -x 808 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[17\] -fixed false -x 470 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Oi0I1 -fixed false -x 546 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[2\] -fixed false -x 765 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24\[4\] -fixed false -x 256 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[4\] -fixed false -x 155 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[27\] -fixed false -x 846 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Olol1 -fixed false -x 354 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[30\] -fixed false -x 487 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_4_tz_0\[0\] -fixed false -x 833 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[6\] -fixed false -x 376 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[1\] -fixed false -x 211 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[0\] -fixed false -x 621 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[22\] -fixed false -x 666 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[5\] -fixed false -x 726 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_117 -fixed false -x 604 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[30\] -fixed false -x 559 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[0\] -fixed false -x 638 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOoI1 -fixed false -x 410 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001\[2\] -fixed false -x 120 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex\[1\] -fixed false -x 774 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[3\] -fixed false -x 187 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[3\] -fixed false -x 149 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_axbxc5 -fixed false -x 311 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m19 -fixed false -x 602 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[17\] -fixed false -x 470 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[29\] -fixed false -x 575 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[30\] -fixed false -x 460 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[32\] -fixed false -x 900 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[3\] -fixed false -x 700 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_6\[15\] -fixed false -x 135 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[2\] -fixed false -x 55 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[13\] -fixed false -x 769 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_2\[3\] -fixed false -x 114 -y 186
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_DELAY -fixed false -x 2467 -y 4
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_RNIHD688 -fixed false -x 76 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[3\] -fixed false -x 421 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_990 -fixed false -x 658 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_0_RNO -fixed false -x 820 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[8\] -fixed false -x 32 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1\[30\] -fixed false -x 191 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0\[3\] -fixed false -x 496 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/g0_3 -fixed false -x 730 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[18\] -fixed false -x 332 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_10_RNO -fixed false -x 382 -y 216
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_1_0_RNO -fixed false -x 521 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[26\] -fixed false -x 828 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex_1\[1\] -fixed false -x 752 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_824 -fixed false -x 641 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3\[0\] -fixed false -x 65 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[5\] -fixed false -x 64 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[18\] -fixed false -x 457 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[1\] -fixed false -x 285 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m275 -fixed false -x 273 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/IilI1_RNO -fixed false -x 462 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[5\] -fixed false -x 24 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[2\] -fixed false -x 570 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_7 -fixed false -x 615 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[6\] -fixed false -x 316 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_o2 -fixed false -x 674 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_25 -fixed false -x 616 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[2\] -fixed false -x 342 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[1\] -fixed false -x 687 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1044 -fixed false -x 737 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[24\] -fixed false -x 243 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[2\] -fixed false -x 50 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[16\] -fixed false -x 626 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_read_mux -fixed false -x 760 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[14\] -fixed false -x 433 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30\[1\] -fixed false -x 199 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_1\[8\] -fixed false -x 688 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[3\] -fixed false -x 306 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_RNO\[0\] -fixed false -x 148 -y 216
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u -fixed false -x 535 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_714 -fixed false -x 665 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[39\] -fixed false -x 352 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_2 -fixed false -x 711 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[12\] -fixed false -x 265 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[0\] -fixed false -x 193 -y 193
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_1_1 -fixed false -x 65 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[6\] -fixed false -x 885 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oiol1_1 -fixed false -x 342 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[12\] -fixed false -x 606 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un31_ool01\[8\] -fixed false -x 57 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_494 -fixed false -x 568 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch\[1\] -fixed false -x 612 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOOl1 -fixed false -x 399 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_2\[3\] -fixed false -x 323 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[15\] -fixed false -x 132 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un8_req_addr_mux\[0\] -fixed false -x 722 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1122 -fixed false -x 772 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[15\] -fixed false -x 843 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m315 -fixed false -x 258 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[21\] -fixed false -x 374 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[0\] -fixed false -x 145 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un13_OlIi1 -fixed false -x 173 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z\[4\] -fixed false -x 288 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[30\] -fixed false -x 779 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_15\[10\] -fixed false -x 309 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2114_3 -fixed false -x 650 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIV779G -fixed false -x 766 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[0\] -fixed false -x 282 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[33\] -fixed false -x 457 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[1\] -fixed false -x 806 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[3\] -fixed false -x 56 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_1 -fixed false -x 102 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[2\] -fixed false -x 315 -y 171
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[1\] -fixed false -x 14 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0o01 -fixed false -x 88 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[7\] -fixed false -x 101 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[4\] -fixed false -x 400 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[2\] -fixed false -x 197 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l1i11 -fixed false -x 307 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_1 -fixed false -x 229 -y 192
|
|
set_location -inst_name pf_init_monitor_0_0/pf_init_monitor_0_0/I_BEN_6 -fixed false -x 1750 -y 1
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_r\[31\] -fixed false -x 518 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid_10 -fixed false -x 823 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[17\] -fixed false -x 724 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[6\] -fixed false -x 221 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[27\] -fixed false -x 877 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[6\] -fixed false -x 763 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[6\] -fixed false -x 363 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4_1_0\[3\] -fixed false -x 54 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oOoo1_i_a2 -fixed false -x 115 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[31\] -fixed false -x 928 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_3\[15\] -fixed false -x 133 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[4\] -fixed false -x 762 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_RNO -fixed false -x 689 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[20\] -fixed false -x 547 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1 -fixed false -x 161 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[14\] -fixed false -x 138 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1011_RNO -fixed false -x 251 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[25\] -fixed false -x 868 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[14\] -fixed false -x 472 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_shift_op_completing_ex_2_0 -fixed false -x 772 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[17\] -fixed false -x 739 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_928 -fixed false -x 664 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_28\[2\] -fixed false -x 217 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un8_I1Oi1_2 -fixed false -x 38 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un483_lIlo1 -fixed false -x 290 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control113 -fixed false -x 513 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[6\] -fixed false -x 511 -y 190
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state140 -fixed false -x 522 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[2\] -fixed false -x 165 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM\[0\] -fixed false -x 214 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[10\] -fixed false -x 303 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[1\] -fixed false -x 367 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[5\] -fixed false -x 364 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto3 -fixed false -x 750 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_i_m2\[2\] -fixed false -x 687 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_1 -fixed false -x 29 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt\[1\] -fixed false -x 27 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[8\] -fixed false -x 105 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[27\] -fixed false -x 856 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_91 -fixed false -x 663 -y 171
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/pll_inst_0 -fixed false -x 2460 -y 5
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m8 -fixed false -x 53 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[1\] -fixed false -x 207 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[10\] -fixed false -x 233 -y 213
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc4 -fixed false -x 66 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[2\] -fixed false -x 404 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[11\] -fixed false -x 232 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Iiol1 -fixed false -x 338 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_pos_RNO -fixed false -x 511 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1o01 -fixed false -x 104 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 365 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_477 -fixed false -x 640 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_a3 -fixed false -x 678 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_5\[1\] -fixed false -x 346 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_4_1 -fixed false -x 63 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33\[0\] -fixed false -x 317 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[13\] -fixed false -x 58 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo267 -fixed false -x 54 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_883 -fixed false -x 738 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[5\] -fixed false -x 166 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[3\] -fixed false -x 497 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[0\] -fixed false -x 129 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[22\] -fixed false -x 455 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1_RNO -fixed false -x 163 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[1\] -fixed false -x 523 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx_5_iv -fixed false -x 532 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1248 -fixed false -x 653 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[20\] -fixed false -x 839 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[2\] -fixed false -x 37 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[4\] -fixed false -x 389 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_error -fixed false -x 712 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[0\] -fixed false -x 198 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[15\] -fixed false -x 556 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[3\] -fixed false -x 497 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[4\] -fixed false -x 259 -y 187
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[30\] -fixed false -x 414 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo\[1\] -fixed false -x 131 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_902 -fixed false -x 762 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1\[12\] -fixed false -x 428 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_288 -fixed false -x 763 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.IliOo_1 -fixed false -x 303 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_721 -fixed false -x 639 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill016 -fixed false -x 186 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI8UM8I -fixed false -x 751 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[7\] -fixed false -x 376 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[5\] -fixed false -x 452 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m25 -fixed false -x 43 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[13\] -fixed false -x 683 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m22_s -fixed false -x 108 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[1\] -fixed false -x 482 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[3\] -fixed false -x 76 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitcnt_1 -fixed false -x 538 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO_1 -fixed false -x 886 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[2\] -fixed false -x 383 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[16\] -fixed false -x 420 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[10\] -fixed false -x 430 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[0\] -fixed false -x 746 -y 129
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[0\] -fixed false -x 375 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_627 -fixed false -x 774 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_613 -fixed false -x 674 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[12\] -fixed false -x 52 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[16\] -fixed false -x 94 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[18\] -fixed false -x 942 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m39 -fixed false -x 33 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_726 -fixed false -x 592 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[29\] -fixed false -x 130 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[15\] -fixed false -x 618 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_16 -fixed false -x 145 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[31\] -fixed false -x 907 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo -fixed false -x 17 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_21 -fixed false -x 149 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[5\] -fixed false -x 65 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[6\] -fixed false -x 609 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1157 -fixed false -x 620 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[4\] -fixed false -x 942 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[9\] -fixed false -x 92 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_2_0_RNICDV9E1 -fixed false -x 823 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[14\] -fixed false -x 825 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01 -fixed false -x 251 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_RNIBS411\[0\] -fixed false -x 92 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places58 -fixed false -x 865 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oil01 -fixed false -x 182 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[16\] -fixed false -x 402 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[1\] -fixed false -x 67 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1124 -fixed false -x 567 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[18\] -fixed false -x 910 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m28_2_1 -fixed false -x 55 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_28\[9\] -fixed false -x 220 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_31\[9\] -fixed false -x 246 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[19\] -fixed false -x 454 -y 213
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[3\] -fixed false -x 2 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo\[0\] -fixed false -x 376 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[30\] -fixed false -x 954 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[13\] -fixed false -x 844 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m76 -fixed false -x 28 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_60\[11\] -fixed false -x 306 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O0oo1 -fixed false -x 91 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff9 -fixed false -x 758 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3\[14\] -fixed false -x 110 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[13\] -fixed false -x 90 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[15\] -fixed false -x 685 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[5\] -fixed false -x 110 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[9\] -fixed false -x 680 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_d_RNI06GNV -fixed false -x 782 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[26\] -fixed false -x 889 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1207 -fixed false -x 640 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[13\] -fixed false -x 757 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[22\] -fixed false -x 783 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6_1\[0\] -fixed false -x 714 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_64 -fixed false -x 664 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[7\] -fixed false -x 790 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m5 -fixed false -x 123 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[26\] -fixed false -x 825 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOIIo -fixed false -x 139 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[20\] -fixed false -x 558 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[16\] -fixed false -x 397 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[33\] -fixed false -x 239 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1\[2\] -fixed false -x 127 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[45\] -fixed false -x 967 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[1\] -fixed false -x 798 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[1\] -fixed false -x 817 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[10\] -fixed false -x 859 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957_1_0_2 -fixed false -x 675 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_1\[8\] -fixed false -x 110 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[1\] -fixed false -x 115 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_1_1 -fixed false -x 67 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[31\] -fixed false -x 927 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIHNUQ61\[5\] -fixed false -x 867 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_0\[0\] -fixed false -x 135 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[30\] -fixed false -x 419 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[30\] -fixed false -x 786 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_0_1\[2\] -fixed false -x 101 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[19\] -fixed false -x 57 -y 235
|
|
set_location -inst_name PF_IOD_CDR_C0_0/RCLKINT_0 -fixed false -x 580 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIMVBS7\[2\] -fixed false -x 910 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[3\] -fixed false -x 734 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[12\] -fixed false -x 478 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[1\] -fixed false -x 50 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_0\[1\] -fixed false -x 769 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1 -fixed false -x 225 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[1\] -fixed false -x 811 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[0\] -fixed false -x 361 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[1\] -fixed false -x 247 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead_2_sqmuxa -fixed false -x 534 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[28\] -fixed false -x 760 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count\[2\] -fixed false -x 490 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[12\] -fixed false -x 357 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_339 -fixed false -x 691 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ill11 -fixed false -x 262 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[9\] -fixed false -x 75 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[6\] -fixed false -x 372 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_cnt.xmit_bit_sel_3_i_o2\[1\] -fixed false -x 429 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oioo1 -fixed false -x 69 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[1\] -fixed false -x 171 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[4\] -fixed false -x 98 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1\[3\] -fixed false -x 66 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/un1_Ioli0_1_0 -fixed false -x 193 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1\[9\] -fixed false -x 264 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/clr_wfi_waiting_0 -fixed false -x 763 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[30\] -fixed false -x 653 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[11\] -fixed false -x 751 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[27\] -fixed false -x 508 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1_4 -fixed false -x 29 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[27\] -fixed false -x 916 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[8\] -fixed false -x 515 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2130 -fixed false -x 629 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[27\] -fixed false -x 915 -y 138
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_resetn_rx -fixed false -x 516 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[3\] -fixed false -x 645 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[5\] -fixed false -x 332 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1 -fixed false -x 528 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_1_0_a3 -fixed false -x 688 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[6\] -fixed false -x 320 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2 -fixed false -x 807 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[5\] -fixed false -x 273 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv\[2\] -fixed false -x 729 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[2\] -fixed false -x 376 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[3\] -fixed false -x 371 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[12\] -fixed false -x 380 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2\[11\] -fixed false -x 562 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I0Oo1 -fixed false -x 300 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[1\] -fixed false -x 231 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[10\] -fixed false -x 555 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1\[39\] -fixed false -x 385 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_6\[0\] -fixed false -x 625 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[5\] -fixed false -x 245 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4\[9\] -fixed false -x 150 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a2_6 -fixed false -x 693 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex\[0\] -fixed false -x 721 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[4\] -fixed false -x 521 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1_0 -fixed false -x 52 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write\[0\] -fixed false -x 680 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[4\] -fixed false -x 268 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[15\] -fixed false -x 466 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[2\] -fixed false -x 639 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[5\] -fixed false -x 329 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[4\] -fixed false -x 167 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[13\] -fixed false -x 356 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3\[14\] -fixed false -x 357 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel17_0_a2_0 -fixed false -x 13 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[5\] -fixed false -x 90 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m10 -fixed false -x 16 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target -fixed false -x 800 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l10Oo_0 -fixed false -x 131 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[6\] -fixed false -x 63 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un159_I1Oi1_1 -fixed false -x 63 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[0\] -fixed false -x 895 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.CO4 -fixed false -x 873 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5_1\[1\] -fixed false -x 705 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[15\] -fixed false -x 29 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1310 -fixed false -x 592 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[1\] -fixed false -x 410 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO\[2\] -fixed false -x 16 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OlIi1 -fixed false -x 175 -y 198
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[30\] -fixed false -x 414 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un1_l0o01_0\[0\] -fixed false -x 128 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[4\] -fixed false -x 848 -y 124
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_7 -fixed false -x 532 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[11\] -fixed false -x 743 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg\[3\] -fixed false -x 40 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_14\[10\] -fixed false -x 295 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[2\] -fixed false -x 196 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1 -fixed false -x 676 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_31_RNO -fixed false -x 899 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[17\] -fixed false -x 842 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_5 -fixed false -x 239 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[7\] -fixed false -x 50 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[1\] -fixed false -x 774 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[26\] -fixed false -x 869 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_738 -fixed false -x 747 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[2\] -fixed false -x 231 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_1\[0\] -fixed false -x 797 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[3\] -fixed false -x 340 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_8 -fixed false -x 678 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[15\] -fixed false -x 891 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[29\] -fixed false -x 835 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_3 -fixed false -x 703 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[14\] -fixed false -x 218 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3_0_RNO_0 -fixed false -x 881 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[12\] -fixed false -x 829 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[10\] -fixed false -x 532 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI9GAGO\[30\] -fixed false -x 902 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO_0 -fixed false -x 856 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[0\] -fixed false -x 722 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_826_i -fixed false -x 266 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[9\] -fixed false -x 297 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch\[0\] -fixed false -x 660 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1_3_0 -fixed false -x 89 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[12\] -fixed false -x 845 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[7\] -fixed false -x 39 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0Oo -fixed false -x 285 -y 201
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1\[1\] -fixed false -x 474 -y 150
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane -fixed false -x 14 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[7\] -fixed false -x 127 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[2\] -fixed false -x 369 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[12\] -fixed false -x 779 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un36_ili01\[14\] -fixed false -x 122 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[33\] -fixed false -x 239 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[0\] -fixed false -x 385 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[9\] -fixed false -x 392 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[18\] -fixed false -x 231 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[12\] -fixed false -x 466 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[24\] -fixed false -x 966 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[13\] -fixed false -x 685 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[0\] -fixed false -x 847 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_646 -fixed false -x 690 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[3\] -fixed false -x 509 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_963 -fixed false -x 795 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[26\] -fixed false -x 707 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_4\[0\] -fixed false -x 700 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[4\] -fixed false -x 860 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[6\] -fixed false -x 710 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[2\] -fixed false -x 215 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid -fixed false -x 809 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[11\] -fixed false -x 731 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_a2 -fixed false -x 113 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_52 -fixed false -x 679 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[12\] -fixed false -x 52 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l1Ol1 -fixed false -x 413 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/frrst_1 -fixed false -x 477 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01\[1\] -fixed false -x 197 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6_1_1 -fixed false -x 767 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_4\[3\] -fixed false -x 45 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO\[24\] -fixed false -x 220 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val\[4\] -fixed false -x 723 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_1\[3\] -fixed false -x 38 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[12\] -fixed false -x 124 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_RNO\[0\] -fixed false -x 569 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[4\] -fixed false -x 878 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[12\] -fixed false -x 607 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[7\] -fixed false -x 172 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[24\] -fixed false -x 353 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[24\] -fixed false -x 953 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[19\] -fixed false -x 828 -y 132
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code_1_sqmuxa_i_i_a2 -fixed false -x 11 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[28\] -fixed false -x 588 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[10\] -fixed false -x 489 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[29\] -fixed false -x 737 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_112 -fixed false -x 615 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[1\] -fixed false -x 387 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9_5 -fixed false -x 62 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a1 -fixed false -x 815 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l0iO1 -fixed false -x 196 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_96 -fixed false -x 758 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[2\] -fixed false -x 267 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val_1799 -fixed false -x 750 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI8EFAU_0 -fixed false -x 16 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINDRQ8\[14\] -fixed false -x 620 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0\[2\] -fixed false -x 108 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_OOii1_0_a3_1 -fixed false -x 149 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[29\] -fixed false -x 483 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_149 -fixed false -x 591 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_880 -fixed false -x 814 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[26\] -fixed false -x 742 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[4\] -fixed false -x 403 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_req_resp_state_1 -fixed false -x 784 -y 123
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/empty -fixed false -x 393 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1\[1\] -fixed false -x 136 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1_2 -fixed false -x 62 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_229 -fixed false -x 621 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[1\] -fixed false -x 157 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/soft_reset_taken_retr -fixed false -x 799 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_4 -fixed false -x 640 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[14\] -fixed false -x 876 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[8\] -fixed false -x 34 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_511 -fixed false -x 618 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[1\] -fixed false -x 757 -y 166
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[2\] -fixed false -x 488 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3 -fixed false -x 435 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_1\[11\] -fixed false -x 846 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[8\] -fixed false -x 791 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[27\] -fixed false -x 392 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ii1o1 -fixed false -x 75 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_5 -fixed false -x 786 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[14\] -fixed false -x 864 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[26\] -fixed false -x 402 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q\[2\] -fixed false -x 592 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[26\] -fixed false -x 166 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[3\] -fixed false -x 326 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_30\[10\] -fixed false -x 219 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE_RNO_0 -fixed false -x 12 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[22\] -fixed false -x 667 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[14\] -fixed false -x 511 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[16\] -fixed false -x 332 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[1\] -fixed false -x 76 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[18\] -fixed false -x 537 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_837 -fixed false -x 603 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[11\] -fixed false -x 391 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[6\] -fixed false -x 67 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[11\] -fixed false -x 258 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[10\] -fixed false -x 802 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0\[5\] -fixed false -x 123 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[13\] -fixed false -x 168 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0_a2_0\[16\] -fixed false -x 88 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[13\] -fixed false -x 731 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I1iOo_1 -fixed false -x 109 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[27\] -fixed false -x 948 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[10\] -fixed false -x 727 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m\[0\] -fixed false -x 896 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[11\] -fixed false -x 62 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_614 -fixed false -x 673 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_2 -fixed false -x 360 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv\[0\] -fixed false -x 762 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[40\] -fixed false -x 882 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel -fixed false -x 713 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_18 -fixed false -x 138 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[1\] -fixed false -x 358 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01 -fixed false -x 226 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_0\[13\] -fixed false -x 134 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m8_e_0 -fixed false -x 700 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[16\] -fixed false -x 895 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1 -fixed false -x 230 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[28\] -fixed false -x 925 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[43\] -fixed false -x 917 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0\[31\] -fixed false -x 197 -y 171
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[20\].BUFD_BLK -fixed false -x 506 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[2\] -fixed false -x 109 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/un1_Ioli0_1_0 -fixed false -x 183 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2\[40\] -fixed false -x 382 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1\[6\] -fixed false -x 118 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3\[3\] -fixed false -x 63 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[2\] -fixed false -x 521 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[5\] -fixed false -x 230 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[29\] -fixed false -x 271 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[2\] -fixed false -x 710 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[3\] -fixed false -x 891 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[2\] -fixed false -x 147 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_3_sqmuxa_1 -fixed false -x 786 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[17\] -fixed false -x 420 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/branch_cond_iv_0\[0\] -fixed false -x 755 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[28\] -fixed false -x 548 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[9\] -fixed false -x 305 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ilio1_RNICD455 -fixed false -x 16 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/next_buff_valid\[1\] -fixed false -x 821 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_548 -fixed false -x 640 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[28\] -fixed false -x 690 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[6\] -fixed false -x 148 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[8\] -fixed false -x 366 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[10\] -fixed false -x 17 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[21\] -fixed false -x 853 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[10\] -fixed false -x 457 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_1_sqmuxa -fixed false -x 509 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI3M2R7\[18\] -fixed false -x 91 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[28\] -fixed false -x 738 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1_2 -fixed false -x 39 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un3_buff_resp_head_uncompressed_full -fixed false -x 627 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_917 -fixed false -x 663 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0_1_0\[0\] -fixed false -x 324 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[5\] -fixed false -x 312 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo_RNI4555G -fixed false -x 42 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_ld_addr_misalign -fixed false -x 793 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[54\] -fixed false -x 963 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[3\] -fixed false -x 220 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo\[1\] -fixed false -x 52 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[26\] -fixed false -x 416 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[32\] -fixed false -x 445 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[24\] -fixed false -x 859 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_1 -fixed false -x 669 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[3\] -fixed false -x 373 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[1\] -fixed false -x 643 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[29\] -fixed false -x 907 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2124.rv32c_dec_mnemonic2124_1_0 -fixed false -x 662 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3_RNO_0\[0\] -fixed false -x 640 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[40\] -fixed false -x 645 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[16\] -fixed false -x 321 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[1\] -fixed false -x 454 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[13\] -fixed false -x 414 -y 199
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/un1_diff_sync -fixed false -x 12 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.trigger_debug_enter_pending -fixed false -x 775 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[17\] -fixed false -x 849 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNII968E\[16\] -fixed false -x 707 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_pslverr_net -fixed false -x 484 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_309 -fixed false -x 697 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40\[4\] -fixed false -x 338 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[11\] -fixed false -x 241 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIll1 -fixed false -x 527 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_3 -fixed false -x 603 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_320 -fixed false -x 628 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_398 -fixed false -x 663 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[6\] -fixed false -x 337 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.un1_shiftDR20_RNIJ92RC -fixed false -x 567 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_20 -fixed false -x 148 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[11\] -fixed false -x 167 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[18\] -fixed false -x 952 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[24\] -fixed false -x 844 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_trap_ret_retr -fixed false -x 743 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_5 -fixed false -x 101 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[25\] -fixed false -x 595 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[18\] -fixed false -x 426 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_4 -fixed false -x 195 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[29\].BUFD_BLK -fixed false -x 481 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid38 -fixed false -x 780 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_2 -fixed false -x 826 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[6\] -fixed false -x 302 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_2\[0\] -fixed false -x 278 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[3\] -fixed false -x 689 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_wfi_ex -fixed false -x 775 -y 142
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[6\] -fixed false -x 391 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_2\[1\] -fixed false -x 643 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_76\[11\] -fixed false -x 274 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_6_0_a2\[15\] -fixed false -x 136 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[3\] -fixed false -x 929 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1OIo -fixed false -x 114 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[35\] -fixed false -x 378 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_355 -fixed false -x 761 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3_1 -fixed false -x 440 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[37\] -fixed false -x 423 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[9\] -fixed false -x 444 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_oIOl1 -fixed false -x 358 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[24\] -fixed false -x 745 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[4\] -fixed false -x 180 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[16\] -fixed false -x 764 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_Tc0_h_En_0_a2 -fixed false -x 498 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_0\[2\] -fixed false -x 628 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1\[2\] -fixed false -x 133 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[43\] -fixed false -x 887 -y 183
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/txrdy_int -fixed false -x 466 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_19_RNIR5LRM -fixed false -x 68 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_973 -fixed false -x 797 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[23\] -fixed false -x 387 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/un5_Ii001 -fixed false -x 40 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_891 -fixed false -x 682 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_sw_csr_rd_op_cnst -fixed false -x 696 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[20\] -fixed false -x 653 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[0\] -fixed false -x 782 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m16_0_1 -fixed false -x 651 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_c3 -fixed false -x 310 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO\[3\] -fixed false -x 206 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[10\] -fixed false -x 784 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[25\] -fixed false -x 868 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_12 -fixed false -x 664 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m0_i_tz\[2\] -fixed false -x 803 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[3\] -fixed false -x 271 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[3\] -fixed false -x 196 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[18\] -fixed false -x 890 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[22\] -fixed false -x 968 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[15\] -fixed false -x 463 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iil01 -fixed false -x 182 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[20\] -fixed false -x 746 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_565 -fixed false -x 631 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[3\] -fixed false -x 750 -y 136
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[6\] -fixed false -x 373 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIDI8GO\[23\] -fixed false -x 870 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[41\] -fixed false -x 916 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[13\] -fixed false -x 776 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_0 -fixed false -x 32 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[30\] -fixed false -x 487 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[0\] -fixed false -x 854 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiOIo -fixed false -x 134 -y 160
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864_1 -fixed false -x 576 -y 5
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc5 -fixed false -x 487 -y 96
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_5\[0\] -fixed false -x 748 -y 43
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[20\] -fixed false -x 805 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_708 -fixed false -x 671 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_939 -fixed false -x 761 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg -fixed false -x 760 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_412 -fixed false -x 713 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_125 -fixed false -x 628 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_1 -fixed false -x 62 -y 198
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_URSTB -fixed false -x 533 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[4\] -fixed false -x 519 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[27\] -fixed false -x 413 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[13\] -fixed false -x 509 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[4\] -fixed false -x 811 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[8\] -fixed false -x 87 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iliO1 -fixed false -x 195 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[17\] -fixed false -x 439 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[27\] -fixed false -x 825 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[27\] -fixed false -x 722 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_m1_0_a2_1 -fixed false -x 841 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[13\] -fixed false -x 239 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[9\] -fixed false -x 71 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[5\] -fixed false -x 803 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[4\] -fixed false -x 366 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[29\] -fixed false -x 333 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[19\] -fixed false -x 442 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[32\] -fixed false -x 335 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[0\] -fixed false -x 467 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_986 -fixed false -x 674 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q\[4\] -fixed false -x 565 -y 154
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[24\] -fixed false -x 409 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1 -fixed false -x 186 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01_1_0 -fixed false -x 81 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[1\] -fixed false -x 612 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[12\] -fixed false -x 320 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[4\] -fixed false -x 223 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_valid_0 -fixed false -x 797 -y 129
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[2\] -fixed false -x 372 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[4\] -fixed false -x 519 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[1\] -fixed false -x 651 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1\[13\] -fixed false -x 24 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[9\] -fixed false -x 871 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_0\[6\] -fixed false -x 115 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[18\] -fixed false -x 802 -y 124
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_RNO_0 -fixed false -x 538 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel_1 -fixed false -x 712 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I16 -fixed false -x 545 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_u_1_0 -fixed false -x 814 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[7\] -fixed false -x 137 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[11\] -fixed false -x 375 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[24\] -fixed false -x 877 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[7\] -fixed false -x 208 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[2\] -fixed false -x 126 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[8\] -fixed false -x 366 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[5\] -fixed false -x 851 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[3\] -fixed false -x 291 -y 199
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state142 -fixed false -x 509 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO\[1\] -fixed false -x 221 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ool11 -fixed false -x 298 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o0Il1 -fixed false -x 458 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[0\] -fixed false -x 372 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_a2\[27\] -fixed false -x 833 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[2\] -fixed false -x 794 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[14\] -fixed false -x 511 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[3\] -fixed false -x 282 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[11\] -fixed false -x 421 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_1\[31\] -fixed false -x 218 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_5_RNO -fixed false -x 104 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[29\] -fixed false -x 873 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[7\] -fixed false -x 727 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[22\] -fixed false -x 967 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[22\] -fixed false -x 550 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[8\] -fixed false -x 270 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_5 -fixed false -x 602 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[6\] -fixed false -x 292 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_RNO\[0\] -fixed false -x 514 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[5\] -fixed false -x 653 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[2\] -fixed false -x 219 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[5\] -fixed false -x 729 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1138 -fixed false -x 662 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[8\] -fixed false -x 310 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[5\] -fixed false -x 915 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[14\] -fixed false -x 789 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0\[1\] -fixed false -x 135 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[13\] -fixed false -x 126 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_ss0_0_a2_0_1 -fixed false -x 757 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[14\] -fixed false -x 334 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[3\] -fixed false -x 456 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[7\] -fixed false -x 107 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io\[0\] -fixed false -x 207 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_807 -fixed false -x 666 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[3\] -fixed false -x 796 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00Oo_0_a2_1 -fixed false -x 166 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[23\] -fixed false -x 471 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[30\] -fixed false -x 146 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii1Oo -fixed false -x 133 -y 157
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/REN_d1 -fixed false -x 393 -y 241
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[0\] -fixed false -x 397 -y 256
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un1_instruction_2 -fixed false -x 772 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[19\] -fixed false -x 799 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[2\] -fixed false -x 554 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_32_1\[0\] -fixed false -x 968 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_2_1\[1\] -fixed false -x 714 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_8\[8\] -fixed false -x 189 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_58 -fixed false -x 745 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m64_0 -fixed false -x 53 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[5\] -fixed false -x 200 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[14\] -fixed false -x 70 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_37 -fixed false -x 722 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_OoiOo\[5\] -fixed false -x 108 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3 -fixed false -x 714 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[19\] -fixed false -x 839 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tx_1 -fixed false -x 362 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_pktend8 -fixed false -x 527 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un12_gpr_rd_rs3_completing_ex_0 -fixed false -x 716 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[5\] -fixed false -x 151 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[3\] -fixed false -x 531 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un42_o1Oi1_1 -fixed false -x 88 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[13\] -fixed false -x 374 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_reset_pending -fixed false -x 776 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[14\] -fixed false -x 288 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_0_a4\[3\] -fixed false -x 868 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[5\] -fixed false -x 425 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[17\] -fixed false -x 271 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state\[1\] -fixed false -x 791 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[6\] -fixed false -x 69 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[19\] -fixed false -x 710 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[22\] -fixed false -x 453 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[6\] -fixed false -x 492 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[21\] -fixed false -x 592 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[11\] -fixed false -x 665 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[45\] -fixed false -x 907 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_o2_RNIK9BH2\[4\] -fixed false -x 788 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42\[1\] -fixed false -x 245 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0_RNIVJJ5N2 -fixed false -x 812 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[11\] -fixed false -x 350 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un7_cpu_d_resp_valid_rd_0_RNIRS7JR -fixed false -x 794 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[2\] -fixed false -x 189 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel_3 -fixed false -x 711 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_2_i_o3\[15\] -fixed false -x 124 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[1\] -fixed false -x 377 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIIo -fixed false -x 125 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto8_1 -fixed false -x 194 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IoO11 -fixed false -x 106 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_1_RNO -fixed false -x 797 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/un1_Ioli0_1_0 -fixed false -x 241 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[10\] -fixed false -x 666 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1 -fixed false -x 354 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[14\] -fixed false -x 476 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_d -fixed false -x 782 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0\[1\] -fixed false -x 694 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[13\] -fixed false -x 676 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41_cZ\[6\] -fixed false -x 270 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[26\] -fixed false -x 694 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[8\] -fixed false -x 174 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Olii1 -fixed false -x 154 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo\[0\] -fixed false -x 154 -y 157
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[31\] -fixed false -x 412 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_states2_i_a3 -fixed false -x 713 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[19\] -fixed false -x 750 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_575 -fixed false -x 748 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_311 -fixed false -x 772 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[10\] -fixed false -x 396 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_316 -fixed false -x 807 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z\[0\] -fixed false -x 356 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_436 -fixed false -x 712 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/trigger_op_addr_valid_de -fixed false -x 745 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[29\] -fixed false -x 648 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[8\] -fixed false -x 174 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[4\] -fixed false -x 397 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[14\] -fixed false -x 137 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2\[11\] -fixed false -x 37 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/IilI1_RNO -fixed false -x 246 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[13\] -fixed false -x 53 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[13\] -fixed false -x 812 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[6\] -fixed false -x 180 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[4\] -fixed false -x 268 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[24\] -fixed false -x 950 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[12\] -fixed false -x 619 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_o3 -fixed false -x 683 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[61\] -fixed false -x 594 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[8\] -fixed false -x 302 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[7\] -fixed false -x 398 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNIHT6E22 -fixed false -x 830 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_62_RNIMPPV21 -fixed false -x 940 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un459_lIlo1 -fixed false -x 112 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[12\] -fixed false -x 757 -y 171
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto1 -fixed false -x 80 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[28\] -fixed false -x 633 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[1\] -fixed false -x 896 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[1\] -fixed false -x 381 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_RNO\[2\] -fixed false -x 692 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[10\] -fixed false -x 805 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m14_2_0 -fixed false -x 52 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i1oi1 -fixed false -x 183 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[29\] -fixed false -x 630 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[6\] -fixed false -x 261 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_1_0 -fixed false -x 690 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001\[0\] -fixed false -x 72 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_151 -fixed false -x 664 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[5\] -fixed false -x 346 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_4 -fixed false -x 421 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[2\] -fixed false -x 520 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0o01 -fixed false -x 94 -y 214
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[12\] -fixed false -x 392 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90 -fixed false -x 61 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[5\] -fixed false -x 649 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI036Q8\[5\] -fixed false -x 801 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3\[1\] -fixed false -x 134 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[3\] -fixed false -x 248 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[27\] -fixed false -x 570 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/step_debug_enter_taken -fixed false -x 769 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo\[0\] -fixed false -x 202 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/OloIo -fixed false -x 366 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[6\] -fixed false -x 101 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[14\] -fixed false -x 417 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_886 -fixed false -x 651 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_641 -fixed false -x 688 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[6\] -fixed false -x 66 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[7\] -fixed false -x 605 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o1101 -fixed false -x 139 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[5\] -fixed false -x 340 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_352 -fixed false -x 616 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_7_1 -fixed false -x 216 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[15\] -fixed false -x 509 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0\[0\] -fixed false -x 727 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[28\] -fixed false -x 462 -y 208
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[4\] -fixed false -x 490 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_O0io1 -fixed false -x 75 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01\[1\] -fixed false -x 213 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[12\] -fixed false -x 844 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[0\] -fixed false -x 103 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_could_commit_0_RNIO598Q -fixed false -x 800 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_m2_e_1_2_sx -fixed false -x 845 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[20\] -fixed false -x 427 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2_1\[1\] -fixed false -x 879 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[25\] -fixed false -x 392 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[12\] -fixed false -x 103 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0\[2\] -fixed false -x 651 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_48\[9\] -fixed false -x 937 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[11\] -fixed false -x 508 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[9\] -fixed false -x 211 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[16\] -fixed false -x 706 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[16\] -fixed false -x 845 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_909 -fixed false -x 771 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first -fixed false -x 507 -y 142
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[11\] -fixed false -x 382 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[13\] -fixed false -x 253 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0\[1\] -fixed false -x 757 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1_2 -fixed false -x 74 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[20\] -fixed false -x 716 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[5\] -fixed false -x 211 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12\[2\] -fixed false -x 267 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[2\] -fixed false -x 495 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[4\] -fixed false -x 740 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int -fixed false -x 788 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[27\] -fixed false -x 588 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[22\] -fixed false -x 457 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[19\] -fixed false -x 832 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_20 -fixed false -x 591 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_0\[2\] -fixed false -x 739 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[9\] -fixed false -x 142 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_954 -fixed false -x 640 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_ready_reg_RNO -fixed false -x 795 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[9\] -fixed false -x 886 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state_0_sqmuxa_i -fixed false -x 711 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[26\] -fixed false -x 850 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.implicit_wr_dcsr_cause_wr_data_1_ss0 -fixed false -x 779 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[8\].BUFD_BLK -fixed false -x 532 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[12\] -fixed false -x 492 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_285 -fixed false -x 678 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_0 -fixed false -x 731 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIAD984\[15\] -fixed false -x 949 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[0\] -fixed false -x 322 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_2 -fixed false -x 231 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[5\] -fixed false -x 77 -y 213
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[7\] -fixed false -x 441 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1\[0\] -fixed false -x 615 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[7\] -fixed false -x 909 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[6\] -fixed false -x 350 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_5 -fixed false -x 672 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[1\] -fixed false -x 834 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[55\] -fixed false -x 954 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_247 -fixed false -x 709 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[25\] -fixed false -x 930 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[19\] -fixed false -x 880 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[28\] -fixed false -x 768 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_5 -fixed false -x 792 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/IilI1_RNO -fixed false -x 384 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1 -fixed false -x 345 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_24 -fixed false -x 831 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1\[4\] -fixed false -x 952 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIi1 -fixed false -x 173 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[0\] -fixed false -x 341 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z\[0\] -fixed false -x 107 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_10\[0\] -fixed false -x 816 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[11\] -fixed false -x 258 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[14\] -fixed false -x 392 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1_RNO -fixed false -x 182 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[3\] -fixed false -x 43 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[14\] -fixed false -x 878 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[0\] -fixed false -x 846 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001\[6\] -fixed false -x 122 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[43\] -fixed false -x 286 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_5 -fixed false -x 505 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_RNIBIU6J -fixed false -x 71 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[8\] -fixed false -x 47 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4\[5\] -fixed false -x 122 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[9\] -fixed false -x 455 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[31\] -fixed false -x 410 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_0\[0\] -fixed false -x 705 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[3\] -fixed false -x 835 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[23\] -fixed false -x 563 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[23\] -fixed false -x 651 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[30\] -fixed false -x 610 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[20\] -fixed false -x 881 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_18 -fixed false -x 761 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m121 -fixed false -x 162 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1 -fixed false -x 68 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1\[0\] -fixed false -x 776 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO\[25\] -fixed false -x 219 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[10\] -fixed false -x 37 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25\[0\] -fixed false -x 267 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[28\] -fixed false -x 397 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_i_o3\[31\] -fixed false -x 715 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[4\] -fixed false -x 232 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[4\] -fixed false -x 51 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[20\] -fixed false -x 956 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[9\] -fixed false -x 204 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[2\] -fixed false -x 118 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[15\] -fixed false -x 76 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[21\] -fixed false -x 884 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z\[1\] -fixed false -x 295 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[9\] -fixed false -x 38 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[1\] -fixed false -x 527 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[13\] -fixed false -x 310 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[11\] -fixed false -x 60 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[4\] -fixed false -x 53 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1 -fixed false -x 207 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[5\] -fixed false -x 173 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[14\] -fixed false -x 381 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_c2 -fixed false -x 310 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_7 -fixed false -x 78 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel_5 -fixed false -x 688 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[17\] -fixed false -x 89 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt\[0\] -fixed false -x 562 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[2\] -fixed false -x 458 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[21\] -fixed false -x 684 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOiOo_NE -fixed false -x 335 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en\[2\] -fixed false -x 714 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[28\] -fixed false -x 821 -y 181
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa -fixed false -x 456 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[0\] -fixed false -x 70 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[15\] -fixed false -x 47 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[0\] -fixed false -x 413 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[28\] -fixed false -x 484 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[1\] -fixed false -x 839 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2\[1\] -fixed false -x 56 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_ready_1 -fixed false -x 716 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[2\] -fixed false -x 872 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[1\] -fixed false -x 440 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO\[0\] -fixed false -x 14 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[53\] -fixed false -x 574 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv\[6\] -fixed false -x 27 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2_0_5 -fixed false -x 66 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_842 -fixed false -x 710 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[20\] -fixed false -x 430 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[21\] -fixed false -x 852 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[0\] -fixed false -x 820 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[42\] -fixed false -x 285 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[9\] -fixed false -x 150 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[2\] -fixed false -x 811 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[4\] -fixed false -x 891 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[6\] -fixed false -x 642 -y 124
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[6\] -fixed false -x 495 -y 150
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[16\] -fixed false -x 401 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0\[0\] -fixed false -x 256 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m249 -fixed false -x 269 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un207_I1Oi1_2 -fixed false -x 61 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[24\] -fixed false -x 542 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[2\] -fixed false -x 382 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[19\] -fixed false -x 896 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[3\] -fixed false -x 345 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[31\] -fixed false -x 802 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[18\] -fixed false -x 693 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/wr_en_data_or -fixed false -x 818 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[19\] -fixed false -x 707 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_3 -fixed false -x 225 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[14\] -fixed false -x 470 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un53_ool01 -fixed false -x 181 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[4\] -fixed false -x 898 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[0\] -fixed false -x 122 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIFJA84\[29\] -fixed false -x 954 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_35 -fixed false -x 626 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_i00i1lto15_3_0_0_o2_i_o2 -fixed false -x 179 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_strobetx -fixed false -x 534 -y 145
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[5\] -fixed false -x 521 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[10\] -fixed false -x 859 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[20\] -fixed false -x 671 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioOIo -fixed false -x 126 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[3\] -fixed false -x 419 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3 -fixed false -x 89 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[0\] -fixed false -x 281 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un51_i11Io -fixed false -x 410 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[8\] -fixed false -x 257 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/wr_en_data -fixed false -x 729 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_2\[1\] -fixed false -x 273 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m6 -fixed false -x 114 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[11\] -fixed false -x 688 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic536 -fixed false -x 800 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_1_RNO_0 -fixed false -x 801 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv\[0\] -fixed false -x 733 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR19_1 -fixed false -x 568 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[3\] -fixed false -x 472 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[23\] -fixed false -x 858 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[30\] -fixed false -x 599 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[20\] -fixed false -x 155 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m1 -fixed false -x 43 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[15\] -fixed false -x 273 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[4\] -fixed false -x 797 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un80_OilI1_0_a2_0 -fixed false -x 329 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[5\] -fixed false -x 896 -y 156
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2\[2\] -fixed false -x 372 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[2\] -fixed false -x 896 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[3\] -fixed false -x 717 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[15\] -fixed false -x 730 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un13_OIoO1\[2\] -fixed false -x 62 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[54\] -fixed false -x 963 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[14\] -fixed false -x 159 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oo101 -fixed false -x 103 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[20\] -fixed false -x 931 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[0\] -fixed false -x 529 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[29\] -fixed false -x 837 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[15\] -fixed false -x 413 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[2\] -fixed false -x 110 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1084 -fixed false -x 627 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[12\] -fixed false -x 149 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_37\[9\] -fixed false -x 871 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[11\] -fixed false -x 396 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1038 -fixed false -x 603 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv\[13\] -fixed false -x 743 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff -fixed false -x 772 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[24\] -fixed false -x 831 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14\[13\] -fixed false -x 926 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[8\] -fixed false -x 70 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[0\] -fixed false -x 286 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_ac0_1 -fixed false -x 52 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001\[7\] -fixed false -x 58 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_406 -fixed false -x 689 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[15\] -fixed false -x 130 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[19\] -fixed false -x 752 -y 123
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[31\].BUFD_BLK -fixed false -x 480 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[20\] -fixed false -x 730 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[4\] -fixed false -x 570 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[12\] -fixed false -x 887 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_error_resp.gen_buff_loop\[0\].buff_entry_error_resp_ram2_\[0\] -fixed false -x 626 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVLRQ8\[18\] -fixed false -x 617 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Iioi1 -fixed false -x 152 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[21\] -fixed false -x 685 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[5\] -fixed false -x 88 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un114_OOOI1\[16\] -fixed false -x 445 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[28\] -fixed false -x 743 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[25\] -fixed false -x 866 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr\[5\] -fixed false -x 720 -y 130
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_dataerr -fixed false -x 535 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[10\] -fixed false -x 718 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.debug_resume_req_3_1 -fixed false -x 770 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[4\] -fixed false -x 210 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[14\] -fixed false -x 416 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n3 -fixed false -x 555 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_2 -fixed false -x 105 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11\[1\] -fixed false -x 102 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_31 -fixed false -x 796 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[10\] -fixed false -x 189 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[21\] -fixed false -x 896 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n2 -fixed false -x 560 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_1\[1\] -fixed false -x 599 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[5\] -fixed false -x 97 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNIT880A -fixed false -x 814 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[6\] -fixed false -x 416 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[5\] -fixed false -x 782 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[22\] -fixed false -x 814 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_0 -fixed false -x 191 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[3\] -fixed false -x 116 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[10\] -fixed false -x 428 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig\[25\] -fixed false -x 662 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[28\] -fixed false -x 914 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[30\] -fixed false -x 550 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[8\] -fixed false -x 768 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op\[3\] -fixed false -x 737 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3\[7\] -fixed false -x 253 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un80_OilI1_0_a2 -fixed false -x 328 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un23_I1Oi1_1 -fixed false -x 45 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[1\] -fixed false -x 159 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_1_sqmuxa_1 -fixed false -x 63 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[20\] -fixed false -x 857 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[30\] -fixed false -x 546 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[3\] -fixed false -x 152 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_dataerr -fixed false -x 493 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[9\] -fixed false -x 889 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[30\] -fixed false -x 795 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[3\] -fixed false -x 131 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851_4 -fixed false -x 605 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[12\] -fixed false -x 883 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNIAB77FB -fixed false -x 780 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr\[0\] -fixed false -x 707 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1\[5\] -fixed false -x 174 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_554 -fixed false -x 639 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[8\] -fixed false -x 882 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_13_0_i -fixed false -x 221 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_127 -fixed false -x 675 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[26\] -fixed false -x 937 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[9\] -fixed false -x 545 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_lsu_op_ex_pipe\[2\] -fixed false -x 760 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[0\] -fixed false -x 36 -y 211
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[22\] -fixed false -x 380 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[13\] -fixed false -x 735 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[0\] -fixed false -x 435 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[60\] -fixed false -x 949 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122_4 -fixed false -x 656 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex5 -fixed false -x 762 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[31\] -fixed false -x 549 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[12\] -fixed false -x 266 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[22\] -fixed false -x 624 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_5 -fixed false -x 224 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2\[10\] -fixed false -x 41 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[19\] -fixed false -x 591 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[10\] -fixed false -x 405 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oIIl1 -fixed false -x 551 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[8\] -fixed false -x 197 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_542 -fixed false -x 650 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[10\] -fixed false -x 202 -y 174
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state\[0\] -fixed false -x 9 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_0\[1\] -fixed false -x 712 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[12\] -fixed false -x 726 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[18\] -fixed false -x 295 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1288 -fixed false -x 675 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[14\] -fixed false -x 453 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[21\] -fixed false -x 665 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo -fixed false -x 164 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[16\] -fixed false -x 739 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3\[3\] -fixed false -x 569 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_493 -fixed false -x 707 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_read -fixed false -x 529 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[1\] -fixed false -x 219 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[19\] -fixed false -x 429 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[4\] -fixed false -x 185 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1\[3\] -fixed false -x 491 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/IilI1 -fixed false -x 384 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1_2 -fixed false -x 487 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[16\] -fixed false -x 748 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mstatus_sw_rd_sel -fixed false -x 719 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_i_a2\[2\] -fixed false -x 547 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[2\] -fixed false -x 184 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx -fixed false -x 532 -y 151
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[0\] -fixed false -x 83 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[4\] -fixed false -x 506 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[7\] -fixed false -x 675 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[2\] -fixed false -x 692 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_3_2\[0\] -fixed false -x 329 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4_1_0\[7\] -fixed false -x 55 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OI111 -fixed false -x 187 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[12\] -fixed false -x 64 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38 -fixed false -x 801 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1106 -fixed false -x 726 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[14\] -fixed false -x 320 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_243_i -fixed false -x 164 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_724 -fixed false -x 725 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[14\] -fixed false -x 313 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[10\] -fixed false -x 443 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_data_gen_buff_loop\[0\].buff_data_0_0_RNO_1 -fixed false -x 818 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/IilI1_RNO -fixed false -x 284 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[5\] -fixed false -x 241 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[7\] -fixed false -x 31 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[23\] -fixed false -x 457 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[15\] -fixed false -x 415 -y 184
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_6 -fixed false -x 435 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[27\] -fixed false -x 851 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[2\] -fixed false -x 653 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[17\] -fixed false -x 735 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_lm_0_fast\[0\] -fixed false -x 790 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001\[0\] -fixed false -x 81 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa -fixed false -x 534 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[6\] -fixed false -x 800 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1152 -fixed false -x 724 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[10\] -fixed false -x 453 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3_3\[0\] -fixed false -x 649 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[6\] -fixed false -x 794 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO_0 -fixed false -x 882 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_0_sqmuxa_0 -fixed false -x 198 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_a2 -fixed false -x 691 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[4\] -fixed false -x 842 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb\[3\] -fixed false -x 591 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[30\] -fixed false -x 485 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_4 -fixed false -x 742 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr_2_iv\[0\] -fixed false -x 759 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[26\] -fixed false -x 314 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1_RNIQ13595 -fixed false -x 771 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[15\] -fixed false -x 75 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_1 -fixed false -x 228 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_RNIKN2L85 -fixed false -x 67 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[28\] -fixed false -x 511 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[12\] -fixed false -x 142 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un23_OOOI1\[7\] -fixed false -x 298 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[17\] -fixed false -x 94 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[3\] -fixed false -x 671 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[11\] -fixed false -x 357 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI25S5C\[26\] -fixed false -x 626 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[6\] -fixed false -x 734 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[9\] -fixed false -x 447 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[6\] -fixed false -x 434 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[11\] -fixed false -x 866 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3 -fixed false -x 827 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[20\] -fixed false -x 853 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_10_1\[3\] -fixed false -x 741 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[16\] -fixed false -x 420 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m1_0_a2 -fixed false -x 840 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[16\] -fixed false -x 262 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[6\] -fixed false -x 375 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1l1_u -fixed false -x 462 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[6\] -fixed false -x 155 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[3\] -fixed false -x 198 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[28\] -fixed false -x 376 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[10\] -fixed false -x 414 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_34\[8\] -fixed false -x 929 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_IioOo -fixed false -x 117 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1oO1\[2\] -fixed false -x 121 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi0o1 -fixed false -x 103 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_236 -fixed false -x 566 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO -fixed false -x 832 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[5\] -fixed false -x 867 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_146 -fixed false -x 725 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_1\[13\] -fixed false -x 135 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[1\] -fixed false -x 404 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOoOo -fixed false -x 175 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_28 -fixed false -x 865 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_2_0 -fixed false -x 698 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[13\] -fixed false -x 340 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[18\] -fixed false -x 506 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo\[1\] -fixed false -x 155 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[5\] -fixed false -x 223 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[2\] -fixed false -x 509 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[10\] -fixed false -x 243 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_1 -fixed false -x 100 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[12\] -fixed false -x 410 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[21\] -fixed false -x 751 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m12 -fixed false -x 770 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[7\] -fixed false -x 381 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[1\] -fixed false -x 157 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O1lIo_1_0_.m2_i -fixed false -x 45 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[7\] -fixed false -x 248 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO_0 -fixed false -x 810 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.i01Io -fixed false -x 66 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[6\] -fixed false -x 86 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0_1_0\[0\] -fixed false -x 199 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[27\] -fixed false -x 30 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[31\] -fixed false -x 590 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[30\] -fixed false -x 27 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_excpt_i_access_fault -fixed false -x 731 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_553 -fixed false -x 604 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_2_0 -fixed false -x 801 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[12\] -fixed false -x 266 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[12\] -fixed false -x 617 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[5\] -fixed false -x 522 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23_sx_0 -fixed false -x 813 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[30\] -fixed false -x 543 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[1\] -fixed false -x 119 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[1\] -fixed false -x 403 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_3\[2\] -fixed false -x 132 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[15\] -fixed false -x 314 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[11\] -fixed false -x 685 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un115_lIlo1_1 -fixed false -x 152 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[3\] -fixed false -x 32 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[3\] -fixed false -x 604 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_2\[11\] -fixed false -x 845 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[5\] -fixed false -x 751 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[3\] -fixed false -x 376 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_debug_enter_req_retr -fixed false -x 770 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[15\] -fixed false -x 920 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1178 -fixed false -x 613 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[0\] -fixed false -x 439 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_2 -fixed false -x 741 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o2_0 -fixed false -x 702 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state93 -fixed false -x 488 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[30\] -fixed false -x 849 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[8\] -fixed false -x 151 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[0\] -fixed false -x 84 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0\[15\] -fixed false -x 130 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIV80P9\[0\] -fixed false -x 99 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_430 -fixed false -x 674 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[11\] -fixed false -x 78 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_11 -fixed false -x 730 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[2\] -fixed false -x 255 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1\[7\] -fixed false -x 129 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1\[8\] -fixed false -x 854 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m10 -fixed false -x 122 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[22\] -fixed false -x 776 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI0l1\[0\] -fixed false -x 446 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/IilI1_RNO -fixed false -x 262 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_4 -fixed false -x 231 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[2\] -fixed false -x 875 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[2\] -fixed false -x 732 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[16\] -fixed false -x 853 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/un2_li001_1 -fixed false -x 39 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[18\] -fixed false -x 155 -y 166
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[6\] -fixed false -x 373 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[25\] -fixed false -x 892 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[0\] -fixed false -x 761 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNI3STQ8\[29\] -fixed false -x 634 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m3 -fixed false -x 113 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/un1_iOI01_1_i_0 -fixed false -x 221 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[18\] -fixed false -x 752 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[8\].BUFD_BLK -fixed false -x 487 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_54 -fixed false -x 711 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[1\] -fixed false -x 46 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[11\] -fixed false -x 14 -y 202
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1_0_1 -fixed false -x 496 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[15\] -fixed false -x 209 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr\[12\] -fixed false -x 839 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Io101 -fixed false -x 109 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_623 -fixed false -x 795 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[5\] -fixed false -x 45 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM\[2\] -fixed false -x 73 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_799 -fixed false -x 662 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch\[1\] -fixed false -x 641 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[19\] -fixed false -x 601 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_4\[15\] -fixed false -x 132 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[0\] -fixed false -x 41 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[21\] -fixed false -x 459 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[6\] -fixed false -x 64 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[7\] -fixed false -x 158 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0 -fixed false -x 726 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_Oiol1_3 -fixed false -x 393 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[5\] -fixed false -x 637 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[0\] -fixed false -x 808 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[3\] -fixed false -x 247 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[1\] -fixed false -x 402 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1154 -fixed false -x 662 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[3\] -fixed false -x 423 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_busy -fixed false -x 753 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[6\] -fixed false -x 375 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3\[6\] -fixed false -x 72 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[42\] -fixed false -x 342 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[2\] -fixed false -x 629 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[5\] -fixed false -x 401 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[39\] -fixed false -x 516 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[4\] -fixed false -x 610 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto3_1 -fixed false -x 149 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[8\] -fixed false -x 417 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[2\] -fixed false -x 500 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_1_RNO\[0\] -fixed false -x 675 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[34\] -fixed false -x 344 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid40 -fixed false -x 733 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI58984\[10\] -fixed false -x 912 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m57 -fixed false -x 287 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[8\] -fixed false -x 780 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[0\] -fixed false -x 518 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[16\] -fixed false -x 336 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_2\[1\] -fixed false -x 130 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[6\] -fixed false -x 532 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O1Ol1_1 -fixed false -x 434 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_5 -fixed false -x 223 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01\[0\] -fixed false -x 210 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1\[3\] -fixed false -x 773 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oO0Io_0 -fixed false -x 87 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[3\] -fixed false -x 808 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o0Ol1_1 -fixed false -x 435 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[14\] -fixed false -x 169 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[22\] -fixed false -x 759 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_genblk1.O0Il1_2_i_m3 -fixed false -x 489 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_16 -fixed false -x 849 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNIGEJG91 -fixed false -x 809 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[8\] -fixed false -x 396 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[17\] -fixed false -x 840 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[4\] -fixed false -x 617 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_556 -fixed false -x 615 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_iOI01_1_i -fixed false -x 446 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[8\] -fixed false -x 672 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[6\] -fixed false -x 257 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[25\] -fixed false -x 814 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_13 -fixed false -x 660 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[13\] -fixed false -x 851 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 387 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[29\] -fixed false -x 905 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2 -fixed false -x 101 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2\[2\] -fixed false -x 141 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[24\] -fixed false -x 919 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[14\] -fixed false -x 420 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4\[0\] -fixed false -x 36 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1_cZ\[6\] -fixed false -x 351 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/CLR_FLAGS_N -fixed false -x 47 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[1\] -fixed false -x 234 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[11\] -fixed false -x 107 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI5LHS6\[2\] -fixed false -x 222 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_5 -fixed false -x 531 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9\[8\] -fixed false -x 374 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[7\] -fixed false -x 157 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_0_1\[0\] -fixed false -x 97 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_OoiOo\[1\] -fixed false -x 131 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[23\] -fixed false -x 760 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[7\] -fixed false -x 259 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[16\] -fixed false -x 94 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[9\] -fixed false -x 83 -y 178
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[4\] -fixed false -x 532 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel -fixed false -x 710 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0\[2\] -fixed false -x 204 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[42\] -fixed false -x 502 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[3\] -fixed false -x 920 -y 141
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[1\] -fixed false -x 565 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_Oo1Oo_i_m3\[0\] -fixed false -x 150 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[0\] -fixed false -x 521 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[1\] -fixed false -x 503 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[4\] -fixed false -x 941 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O1ll1 -fixed false -x 453 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii101 -fixed false -x 102 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].un1_buff_req_wr_ptr_1_0_a2 -fixed false -x 842 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[30\] -fixed false -x 715 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2125_i -fixed false -x 870 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[13\] -fixed false -x 758 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[18\] -fixed false -x 789 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[0\] -fixed false -x 213 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2\[2\] -fixed false -x 804 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[6\] -fixed false -x 71 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[26\] -fixed false -x 841 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo_1\[7\] -fixed false -x 326 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[5\] -fixed false -x 855 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[18\] -fixed false -x 95 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[30\] -fixed false -x 795 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[19\] -fixed false -x 675 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioO11 -fixed false -x 101 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[7\] -fixed false -x 921 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_2_0_o3\[15\] -fixed false -x 832 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[5\] -fixed false -x 729 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[12\] -fixed false -x 353 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[4\] -fixed false -x 566 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[30\] -fixed false -x 430 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[26\] -fixed false -x 870 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[15\] -fixed false -x 224 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m23_0 -fixed false -x 44 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[2\] -fixed false -x 237 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid_RNIJL1L11 -fixed false -x 786 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2121_1 -fixed false -x 643 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO -fixed false -x 673 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[60\] -fixed false -x 591 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_8 -fixed false -x 651 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[5\] -fixed false -x 180 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[24\] -fixed false -x 965 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[4\] -fixed false -x 456 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_29 -fixed false -x 90 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[10\] -fixed false -x 880 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[6\] -fixed false -x 107 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[13\] -fixed false -x 846 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_4_fast\[5\] -fixed false -x 714 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2\[15\] -fixed false -x 941 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o0il1 -fixed false -x 484 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[18\] -fixed false -x 446 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[1\] -fixed false -x 505 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[4\] -fixed false -x 398 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[15\] -fixed false -x 940 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[9\] -fixed false -x 301 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[2\] -fixed false -x 177 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[11\] -fixed false -x 841 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_499 -fixed false -x 685 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/clk_en_dm -fixed false -x 802 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[14\] -fixed false -x 119 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[6\] -fixed false -x 915 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oIOo1 -fixed false -x 310 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[28\] -fixed false -x 807 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[22\] -fixed false -x 654 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[16\] -fixed false -x 753 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_valid_0 -fixed false -x 749 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI01Q5C\[16\] -fixed false -x 701 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[7\] -fixed false -x 221 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m24 -fixed false -x 42 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]2_0 -fixed false -x 874 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un91_OOOI1_cZ\[13\] -fixed false -x 279 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/empty_r_fwft_RNO -fixed false -x 407 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[12\] -fixed false -x 321 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un12_oioi1 -fixed false -x 150 -y 219
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_1_sqmuxa_i -fixed false -x 508 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[29\] -fixed false -x 807 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_991 -fixed false -x 687 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_686 -fixed false -x 701 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2_5 -fixed false -x 396 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/N_641_i -fixed false -x 714 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_dataerr_5_u -fixed false -x 535 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[2\] -fixed false -x 294 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1_RNO_0 -fixed false -x 446 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9\[11\] -fixed false -x 316 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_2\[3\] -fixed false -x 890 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[1\] -fixed false -x 384 -y 198
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[2\] -fixed false -x 75 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig\[7\] -fixed false -x 675 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_1\[15\] -fixed false -x 329 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[9\] -fixed false -x 528 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[12\] -fixed false -x 236 -y 180
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1 -fixed false -x 579 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23\[6\] -fixed false -x 261 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[6\] -fixed false -x 430 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[15\] -fixed false -x 104 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[15\] -fixed false -x 416 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_206 -fixed false -x 746 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[2\] -fixed false -x 231 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[25\] -fixed false -x 899 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[10\] -fixed false -x 371 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[22\] -fixed false -x 779 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0\[0\] -fixed false -x 631 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1_2_0 -fixed false -x 307 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[10\] -fixed false -x 352 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel -fixed false -x 709 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[12\] -fixed false -x 407 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_2\[7\] -fixed false -x 101 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_0\[3\] -fixed false -x 42 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat15 -fixed false -x 565 -y 117
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_state18_NE_i_1 -fixed false -x 460 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[34\] -fixed false -x 481 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_14 -fixed false -x 590 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_2_0 -fixed false -x 181 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[21\] -fixed false -x 710 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[38\] -fixed false -x 432 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[7\] -fixed false -x 404 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_fe -fixed false -x 537 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_6 -fixed false -x 694 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff_RNO -fixed false -x 784 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[15\] -fixed false -x 469 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_12 -fixed false -x 723 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_189 -fixed false -x 688 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[8\] -fixed false -x 135 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[16\] -fixed false -x 625 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_13\[9\] -fixed false -x 294 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[28\] -fixed false -x 948 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[2\] -fixed false -x 815 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[5\] -fixed false -x 313 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[0\] -fixed false -x 542 -y 166
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_a2_0\[3\] -fixed false -x 485 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[19\] -fixed false -x 898 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[11\] -fixed false -x 334 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[4\] -fixed false -x 318 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[11\] -fixed false -x 152 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[3\] -fixed false -x 392 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[9\] -fixed false -x 723 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[8\] -fixed false -x 80 -y 205
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[2\] -fixed false -x 74 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[21\] -fixed false -x 884 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_122 -fixed false -x 674 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[6\] -fixed false -x 414 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[21\] -fixed false -x 724 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[13\] -fixed false -x 386 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4\[1\] -fixed false -x 784 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[2\] -fixed false -x 414 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[9\] -fixed false -x 242 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]\[3\] -fixed false -x 781 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIDCBP2\[1\] -fixed false -x 253 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNIBTPAB -fixed false -x 846 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_400 -fixed false -x 651 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[1\] -fixed false -x 284 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_olio1 -fixed false -x 54 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/IilI1 -fixed false -x 359 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_Ioli0_1_0_a2 -fixed false -x 386 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1_0_tz -fixed false -x 103 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un10_i0Oo1 -fixed false -x 312 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[26\] -fixed false -x 626 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_940 -fixed false -x 756 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[12\] -fixed false -x 96 -y 225
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_0_RNI0SQ9T1 -fixed false -x 871 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_0 -fixed false -x 732 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[4\] -fixed false -x 894 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31_1 -fixed false -x 590 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[32\] -fixed false -x 840 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0_RNO\[2\] -fixed false -x 127 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[11\] -fixed false -x 668 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[55\] -fixed false -x 552 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/IilI1 -fixed false -x 227 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[2\] -fixed false -x 283 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_521 -fixed false -x 638 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_9 -fixed false -x 678 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a3_1 -fixed false -x 628 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[30\] -fixed false -x 953 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O0lI1 -fixed false -x 256 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[12\] -fixed false -x 461 -y 196
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_4_u -fixed false -x 449 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[10\] -fixed false -x 229 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOOo1 -fixed false -x 306 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_72 -fixed false -x 662 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[8\] -fixed false -x 853 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[8\] -fixed false -x 797 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17_3_1 -fixed false -x 648 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[5\] -fixed false -x 848 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[1\] -fixed false -x 415 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[28\] -fixed false -x 547 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[7\] -fixed false -x 411 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[30\] -fixed false -x 855 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[1\] -fixed false -x 185 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[3\] -fixed false -x 735 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/fifo_reset_3 -fixed false -x 596 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1_1088_0 -fixed false -x 103 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[12\] -fixed false -x 36 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_4 -fixed false -x 81 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[6\] -fixed false -x 98 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[9\] -fixed false -x 698 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[7\] -fixed false -x 836 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[4\] -fixed false -x 389 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[6\] -fixed false -x 940 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.un3_ex_retr_pipe_sw_csr_wr_op_retr -fixed false -x 728 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[8\] -fixed false -x 154 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_i\[1\] -fixed false -x 211 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_5 -fixed false -x 226 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1_1 -fixed false -x 206 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1\[4\] -fixed false -x 121 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[21\] -fixed false -x 443 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_624 -fixed false -x 794 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[28\] -fixed false -x 951 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_1 -fixed false -x 436 -y 9
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[25\] -fixed false -x 851 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_588 -fixed false -x 736 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[7\] -fixed false -x 644 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[9\] -fixed false -x 69 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oo1o1_i_o2 -fixed false -x 114 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[11\] -fixed false -x 852 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[13\] -fixed false -x 179 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26\[11\] -fixed false -x 281 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_444 -fixed false -x 783 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e -fixed false -x 662 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[7\] -fixed false -x 918 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[25\] -fixed false -x 695 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[3\] -fixed false -x 720 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_o3 -fixed false -x 123 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[10\] -fixed false -x 234 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[33\] -fixed false -x 470 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[3\] -fixed false -x 51 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[14\] -fixed false -x 310 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[23\] -fixed false -x 917 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un141_I1Oi1 -fixed false -x 51 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4953 -fixed false -x 645 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1078 -fixed false -x 675 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[17\] -fixed false -x 895 -y 135
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2\[3\] -fixed false -x 486 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[33\] -fixed false -x 474 -y 210
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state133_RNIINL0C -fixed false -x 510 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg\[2\] -fixed false -x 740 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[13\] -fixed false -x 338 -y 216
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[31\].BUFD_BLK -fixed false -x 542 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0_1_0\[0\] -fixed false -x 340 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[8\] -fixed false -x 138 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[6\] -fixed false -x 846 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[22\] -fixed false -x 590 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[2\] -fixed false -x 564 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_Ilio1 -fixed false -x 53 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un40_i11Io -fixed false -x 409 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[11\] -fixed false -x 855 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01\[22\] -fixed false -x 205 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_sn_m3 -fixed false -x 820 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_2\[0\] -fixed false -x 649 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_2 -fixed false -x 683 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[8\] -fixed false -x 293 -y 180
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b\[0\] -fixed false -x 47 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[18\] -fixed false -x 844 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[10\] -fixed false -x 347 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[13\] -fixed false -x 400 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[20\].BUFD_BLK -fixed false -x 487 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[28\] -fixed false -x 684 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[18\] -fixed false -x 643 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[1\] -fixed false -x 161 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_927 -fixed false -x 699 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_0\[5\] -fixed false -x 187 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4\[2\] -fixed false -x 41 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_6\[13\] -fixed false -x 653 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[26\] -fixed false -x 948 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[11\] -fixed false -x 101 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z\[0\] -fixed false -x 36 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en\[1\] -fixed false -x 719 -y 129
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[4\] -fixed false -x 568 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[8\] -fixed false -x 178 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNIP9IPT -fixed false -x 779 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i -fixed false -x 803 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[3\] -fixed false -x 807 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un55_I1Oi1_1 -fixed false -x 53 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[44\] -fixed false -x 519 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[11\] -fixed false -x 233 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJ9RQ8\[12\] -fixed false -x 616 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2\[0\] -fixed false -x 258 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[24\] -fixed false -x 682 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_4 -fixed false -x 699 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[14\] -fixed false -x 126 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[5\] -fixed false -x 373 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[5\] -fixed false -x 420 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[8\] -fixed false -x 513 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo_RNIV2N4M -fixed false -x 22 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1\[7\] -fixed false -x 100 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_5 -fixed false -x 17 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_llOl1 -fixed false -x 398 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_lIOl1 -fixed false -x 393 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_0\[2\] -fixed false -x 740 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_1 -fixed false -x 544 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[28\] -fixed false -x 388 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo -fixed false -x 30 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel_2_0 -fixed false -x 709 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2 -fixed false -x 652 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_635 -fixed false -x 617 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_1\[4\] -fixed false -x 20 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2\[1\] -fixed false -x 878 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un11_start_div_3_RNIQEVCD -fixed false -x 868 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[17\] -fixed false -x 805 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[21\] -fixed false -x 734 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[17\] -fixed false -x 930 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_659 -fixed false -x 746 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[5\] -fixed false -x 88 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_2_0 -fixed false -x 100 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[9\] -fixed false -x 271 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[25\] -fixed false -x 660 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/i1111_2 -fixed false -x 249 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[1\] -fixed false -x 198 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ii0I1 -fixed false -x 524 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo_RNO -fixed false -x 21 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_262 -fixed false -x 691 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[0\] -fixed false -x 430 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1065 -fixed false -x 782 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[24\] -fixed false -x 382 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[31\] -fixed false -x 703 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1_4 -fixed false -x 700 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[9\] -fixed false -x 187 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2\[1\] -fixed false -x 777 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[3\] -fixed false -x 139 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[3\] -fixed false -x 250 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[10\] -fixed false -x 347 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNIAGET61 -fixed false -x 788 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[16\] -fixed false -x 51 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[1\] -fixed false -x 842 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[20\] -fixed false -x 148 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[2\] -fixed false -x 163 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[1\] -fixed false -x 147 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[17\] -fixed false -x 562 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_7\[9\] -fixed false -x 292 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_16 -fixed false -x 73 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex_0 -fixed false -x 812 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[39\] -fixed false -x 625 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[11\] -fixed false -x 396 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[5\] -fixed false -x 260 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[31\] -fixed false -x 352 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[0\] -fixed false -x 456 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[18\] -fixed false -x 696 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[5\] -fixed false -x 365 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[45\] -fixed false -x 917 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[15\] -fixed false -x 350 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[4\] -fixed false -x 458 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIPJMQS\[5\] -fixed false -x 822 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex_2_0 -fixed false -x 766 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[6\] -fixed false -x 422 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[18\] -fixed false -x 247 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[14\] -fixed false -x 797 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[27\] -fixed false -x 677 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_mem_error_retr -fixed false -x 751 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1\[17\] -fixed false -x 224 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR\[4\] -fixed false -x 565 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[0\] -fixed false -x 690 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[23\] -fixed false -x 853 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[32\] -fixed false -x 629 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[21\] -fixed false -x 729 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_bcu_op_sel_ex7 -fixed false -x 749 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[31\] -fixed false -x 471 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[23\] -fixed false -x 728 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_m1_0_a2_0_5_1 -fixed false -x 781 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_422 -fixed false -x 639 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[21\] -fixed false -x 453 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[14\] -fixed false -x 148 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[29\] -fixed false -x 918 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[16\] -fixed false -x 456 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[23\] -fixed false -x 679 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[5\] -fixed false -x 639 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[38\] -fixed false -x 626 -y 121
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[6\] -fixed false -x 517 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooli1 -fixed false -x 200 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[6\] -fixed false -x 214 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[5\] -fixed false -x 931 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[3\] -fixed false -x 914 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3_0 -fixed false -x 88 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg\[3\] -fixed false -x 575 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[25\] -fixed false -x 219 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_RNO_0 -fixed false -x 269 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[7\] -fixed false -x 759 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[32\] -fixed false -x 627 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[4\] -fixed false -x 37 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_6_2 -fixed false -x 213 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[22\] -fixed false -x 468 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1263 -fixed false -x 661 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[23\] -fixed false -x 556 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un4_cpu_d_resp_valid_rd_s_0 -fixed false -x 797 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[29\] -fixed false -x 917 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo\[7\] -fixed false -x 332 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[4\] -fixed false -x 533 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[3\] -fixed false -x 672 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_1_tz_RNO\[0\] -fixed false -x 832 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[1\].BUFD_BLK -fixed false -x 531 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[17\] -fixed false -x 839 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[25\] -fixed false -x 85 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[11\] -fixed false -x 35 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[2\] -fixed false -x 645 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIQ3FO8 -fixed false -x 322 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[33\] -fixed false -x 501 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[14\] -fixed false -x 192 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[18\] -fixed false -x 967 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001 -fixed false -x 203 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[0\] -fixed false -x 528 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[28\] -fixed false -x 511 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[17\] -fixed false -x 846 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1\[0\] -fixed false -x 70 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[20\] -fixed false -x 929 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1 -fixed false -x 394 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[2\] -fixed false -x 439 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[8\] -fixed false -x 293 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[32\] -fixed false -x 318 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_317 -fixed false -x 618 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[2\] -fixed false -x 438 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[42\] -fixed false -x 922 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[0\] -fixed false -x 255 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[22\] -fixed false -x 422 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[22\] -fixed false -x 913 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_251_i -fixed false -x 160 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[31\] -fixed false -x 390 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/llo11 -fixed false -x 292 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[16\] -fixed false -x 91 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[14\] -fixed false -x 134 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[20\] -fixed false -x 746 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[8\] -fixed false -x 571 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[10\] -fixed false -x 733 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[2\] -fixed false -x 338 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[32\] -fixed false -x 622 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[7\] -fixed false -x 80 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iil11 -fixed false -x 436 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001\[2\] -fixed false -x 40 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_30\[9\] -fixed false -x 217 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/access_valid_i_o3_RNIVONT9 -fixed false -x 778 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_dbreak_retr -fixed false -x 748 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[24\] -fixed false -x 448 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[5\] -fixed false -x 880 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OilOo\[0\] -fixed false -x 135 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[0\] -fixed false -x 190 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[8\] -fixed false -x 592 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[7\] -fixed false -x 356 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_0 -fixed false -x 434 -y 3
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync\[0\] -fixed false -x 12 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[11\] -fixed false -x 268 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE -fixed false -x 495 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[5\] -fixed false -x 280 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[7\] -fixed false -x 157 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un7_next_res_pos_neg_0 -fixed false -x 872 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[17\] -fixed false -x 375 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un2_req_resp_str_req_buff_addr_misalign\[0\] -fixed false -x 804 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[0\] -fixed false -x 624 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[3\] -fixed false -x 436 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[7\] -fixed false -x 77 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel_1 -fixed false -x 713 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[14\] -fixed false -x 709 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un28_il0Oo -fixed false -x 230 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[4\] -fixed false -x 108 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[14\] -fixed false -x 917 -y 144
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[19\].BUFD_BLK -fixed false -x 505 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ooll1 -fixed false -x 495 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[1\] -fixed false -x 141 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[3\] -fixed false -x 168 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0\[3\] -fixed false -x 152 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[9\] -fixed false -x 118 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[0\] -fixed false -x 45 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[4\] -fixed false -x 867 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[2\] -fixed false -x 879 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[18\] -fixed false -x 941 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[16\] -fixed false -x 466 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[7\] -fixed false -x 158 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10 -fixed false -x 507 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[52\] -fixed false -x 555 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[21\] -fixed false -x 882 -y 195
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL -fixed false -x 11 -y 63
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lll11 -fixed false -x 263 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[16\] -fixed false -x 776 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[21\] -fixed false -x 658 -y 118
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q\[0\] -fixed false -x 502 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[51\] -fixed false -x 888 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11\[0\] -fixed false -x 101 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[2\] -fixed false -x 660 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_6\[0\] -fixed false -x 51 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001\[1\] -fixed false -x 159 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4914 -fixed false -x 648 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_2_0 -fixed false -x 52 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_18 -fixed false -x 557 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[12\] -fixed false -x 291 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_4 -fixed false -x 76 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[6\] -fixed false -x 429 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[10\] -fixed false -x 430 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[26\] -fixed false -x 68 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[7\] -fixed false -x 654 -y 124
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[12\] -fixed false -x 562 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oi1o1 -fixed false -x 102 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_or\[0\] -fixed false -x 751 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2\[3\] -fixed false -x 676 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5\[12\] -fixed false -x 124 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0 -fixed false -x 762 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int35 -fixed false -x 810 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llOo1 -fixed false -x 302 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[3\] -fixed false -x 399 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[6\] -fixed false -x 210 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[11\] -fixed false -x 132 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[6\] -fixed false -x 212 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[8\] -fixed false -x 852 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3\[6\] -fixed false -x 99 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[4\] -fixed false -x 130 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[15\] -fixed false -x 460 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.awe1 -fixed false -x 669 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_272 -fixed false -x 639 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_2\[5\] -fixed false -x 533 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[2\] -fixed false -x 511 -y 171
|
|
set_location -inst_name PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0 -fixed false -x 24 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1\[4\] -fixed false -x 945 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[8\] -fixed false -x 55 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[21\] -fixed false -x 846 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[25\] -fixed false -x 140 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[18\] -fixed false -x 462 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[9\] -fixed false -x 813 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[30\] -fixed false -x 78 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o\[0\] -fixed false -x 275 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[1\] -fixed false -x 910 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/req_os_d_src\[7\] -fixed false -x 814 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[5\] -fixed false -x 144 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[3\] -fixed false -x 167 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1\[2\] -fixed false -x 149 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_1_0 -fixed false -x 112 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[24\] -fixed false -x 903 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[0\] -fixed false -x 189 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first_2 -fixed false -x 513 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[28\] -fixed false -x 860 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_321 -fixed false -x 742 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_326 -fixed false -x 652 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[16\] -fixed false -x 853 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4\[12\] -fixed false -x 102 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_2_0 -fixed false -x 687 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[48\] -fixed false -x 531 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un11_IOIl1_1 -fixed false -x 341 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[14\] -fixed false -x 476 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[16\] -fixed false -x 803 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[4\] -fixed false -x 225 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[11\] -fixed false -x 553 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_78 -fixed false -x 762 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[35\] -fixed false -x 378 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[19\] -fixed false -x 862 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IOoo1_i_0 -fixed false -x 100 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[6\] -fixed false -x 296 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset_3 -fixed false -x 591 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[20\] -fixed false -x 835 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[10\] -fixed false -x 269 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[8\] -fixed false -x 100 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[20\] -fixed false -x 528 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[4\] -fixed false -x 295 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_1\[4\] -fixed false -x 845 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[4\] -fixed false -x 942 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[27\] -fixed false -x 844 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[3\] -fixed false -x 281 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24\[12\] -fixed false -x 289 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV_3 -fixed false -x 435 -y 9
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[1\] -fixed false -x 221 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[1\] -fixed false -x 408 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_RNILIQ67 -fixed false -x 774 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_681 -fixed false -x 650 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[8\] -fixed false -x 527 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[6\] -fixed false -x 64 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[24\] -fixed false -x 764 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[17\] -fixed false -x 301 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[22\] -fixed false -x 966 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0 -fixed false -x 615 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[1\] -fixed false -x 483 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111_2 -fixed false -x 229 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_605 -fixed false -x 615 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[40\] -fixed false -x 633 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0\[4\] -fixed false -x 548 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext -fixed false -x 521 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_i\[4\] -fixed false -x 867 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[31\] -fixed false -x 906 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[15\] -fixed false -x 686 -y 123
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr\[1\] -fixed false -x 449 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4\[2\] -fixed false -x 571 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/wfi -fixed false -x 718 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[4\] -fixed false -x 788 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[6\] -fixed false -x 398 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7\[11\] -fixed false -x 283 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[5\] -fixed false -x 282 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11 -fixed false -x 147 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111 -fixed false -x 229 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_s_0 -fixed false -x 713 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[3\] -fixed false -x 229 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[8\] -fixed false -x 863 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[5\] -fixed false -x 888 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[0\] -fixed false -x 781 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_l1i11 -fixed false -x 301 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo\[0\] -fixed false -x 387 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[5\] -fixed false -x 549 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[0\] -fixed false -x 520 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_5 -fixed false -x 97 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[5\] -fixed false -x 503 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[3\] -fixed false -x 865 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIRL98E\[28\] -fixed false -x 630 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[4\] -fixed false -x 397 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_28_RNIEB0E8 -fixed false -x 848 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_timer_enable_0 -fixed false -x 760 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[7\] -fixed false -x 760 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/un1_Ioli0_1_0_0 -fixed false -x 397 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[2\] -fixed false -x 792 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_RNO\[1\] -fixed false -x 625 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow -fixed false -x 464 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[31\] -fixed false -x 283 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[3\] -fixed false -x 689 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_1 -fixed false -x 242 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8\[0\] -fixed false -x 315 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1 -fixed false -x 111 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[15\] -fixed false -x 686 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_13 -fixed false -x 167 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[46\] -fixed false -x 120 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[12\] -fixed false -x 858 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_995 -fixed false -x 639 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[27\] -fixed false -x 793 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[5\] -fixed false -x 73 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_287 -fixed false -x 688 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[8\] -fixed false -x 140 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[7\] -fixed false -x 450 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[24\] -fixed false -x 589 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[12\] -fixed false -x 127 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[3\] -fixed false -x 172 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_lOiOo_i_o3 -fixed false -x 142 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[0\] -fixed false -x 967 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[17\] -fixed false -x 844 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[13\] -fixed false -x 222 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[21\] -fixed false -x 834 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[3\] -fixed false -x 613 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[16\] -fixed false -x 808 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[21\] -fixed false -x 373 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m44 -fixed false -x 268 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_590 -fixed false -x 723 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[14\] -fixed false -x 235 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[8\] -fixed false -x 558 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[18\] -fixed false -x 67 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[19\] -fixed false -x 863 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[3\] -fixed false -x 163 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[0\] -fixed false -x 189 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o3\[6\] -fixed false -x 110 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un2_exception_taken -fixed false -x 787 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[6\] -fixed false -x 413 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[26\] -fixed false -x 400 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_wr_en -fixed false -x 722 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[2\] -fixed false -x 161 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1\[1\] -fixed false -x 778 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[7\] -fixed false -x 115 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[3\] -fixed false -x 189 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[2\] -fixed false -x 697 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel_7 -fixed false -x 690 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[31\] -fixed false -x 671 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy\[21\] -fixed false -x 885 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[10\] -fixed false -x 347 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO\[0\] -fixed false -x 773 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q\[1\] -fixed false -x 570 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[6\] -fixed false -x 716 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[6\] -fixed false -x 818 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[5\] -fixed false -x 365 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_10 -fixed false -x 851 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[14\] -fixed false -x 901 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[12\] -fixed false -x 641 -y 123
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive -fixed false -x 508 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[13\] -fixed false -x 850 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[7\] -fixed false -x 107 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo_RNIHMIO6 -fixed false -x 18 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_233 -fixed false -x 556 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_RNO -fixed false -x 40 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[2\] -fixed false -x 801 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[38\] -fixed false -x 510 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_130 -fixed false -x 603 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_OlIi1 -fixed false -x 123 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l0I01 -fixed false -x 371 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_m7_i_a4_1 -fixed false -x 52 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z\[0\] -fixed false -x 785 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[25\] -fixed false -x 755 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[18\] -fixed false -x 817 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[10\] -fixed false -x 728 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJBTQ8\[21\] -fixed false -x 668 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[14\] -fixed false -x 225 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[3\] -fixed false -x 115 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[4\] -fixed false -x 507 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[14\] -fixed false -x 536 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto9 -fixed false -x 134 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[20\] -fixed false -x 428 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[16\] -fixed false -x 821 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un10_oioOo_1 -fixed false -x 167 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_1_1 -fixed false -x 172 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[2\] -fixed false -x 531 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[20\] -fixed false -x 785 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_348 -fixed false -x 649 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[10\] -fixed false -x 693 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[9\] -fixed false -x 171 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_882 -fixed false -x 720 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow -fixed false -x 562 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[9\] -fixed false -x 589 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[2\] -fixed false -x 399 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/un3_empty_rd_1 -fixed false -x 670 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[20\] -fixed false -x 682 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1\[35\] -fixed false -x 426 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[2\] -fixed false -x 438 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[9\] -fixed false -x 891 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[3\] -fixed false -x 42 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[32\] -fixed false -x 313 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[10\] -fixed false -x 492 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[17\] -fixed false -x 309 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[4\] -fixed false -x 93 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[27\] -fixed false -x 866 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[29\] -fixed false -x 682 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1304 -fixed false -x 687 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIERK9D_0 -fixed false -x 730 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[6\] -fixed false -x 379 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_3 -fixed false -x 726 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[21\] -fixed false -x 916 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m15_1_0 -fixed false -x 78 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[15\] -fixed false -x 209 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[32\].BUFD_BLK -fixed false -x 541 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[26\] -fixed false -x 633 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[20\] -fixed false -x 889 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_841 -fixed false -x 664 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[5\] -fixed false -x 390 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[8\] -fixed false -x 709 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1 -fixed false -x 66 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[6\] -fixed false -x 382 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[11\] -fixed false -x 495 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_15 -fixed false -x 681 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[7\] -fixed false -x 303 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[13\] -fixed false -x 910 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[13\] -fixed false -x 766 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[22\] -fixed false -x 741 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq\[1\].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val\[0\] -fixed false -x 764 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1034 -fixed false -x 731 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2124_i -fixed false -x 869 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[12\] -fixed false -x 725 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[11\] -fixed false -x 919 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_Ioli0_1_0 -fixed false -x 459 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[15\] -fixed false -x 351 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ooli1_0 -fixed false -x 201 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[22\] -fixed false -x 896 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_12_RNI9CUB8 -fixed false -x 832 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[8\] -fixed false -x 155 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[16\] -fixed false -x 929 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[55\] -fixed false -x 940 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[30\] -fixed false -x 918 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[5\] -fixed false -x 897 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n4 -fixed false -x 563 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO\[4\] -fixed false -x 768 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[5\] -fixed false -x 656 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4952_1 -fixed false -x 666 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[8\] -fixed false -x 293 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_s_13_RNO_0 -fixed false -x 373 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2\[29\] -fixed false -x 125 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[23\] -fixed false -x 450 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 368 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[4\] -fixed false -x 405 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[1\] -fixed false -x 894 -y 147
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[0\] -fixed false -x 541 -y 153
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA_0_sqmuxa -fixed false -x 483 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[17\] -fixed false -x 508 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[15\] -fixed false -x 686 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[9\] -fixed false -x 211 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/IilI1 -fixed false -x 182 -y 178
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[7\] -fixed false -x 373 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195 -fixed false -x 848 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[4\] -fixed false -x 520 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[15\] -fixed false -x 595 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_Ii1l1_axb_0_i_0 -fixed false -x 409 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[2\] -fixed false -x 940 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1\[3\] -fixed false -x 120 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[13\] -fixed false -x 833 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[31\] -fixed false -x 147 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[12\] -fixed false -x 766 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4_RNO\[0\] -fixed false -x 719 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_21_RNI9E0D8 -fixed false -x 806 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[1\] -fixed false -x 839 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[10\] -fixed false -x 356 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un34_fifo_mem_d_31_2 -fixed false -x 499 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[23\] -fixed false -x 553 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[2\] -fixed false -x 130 -y 190
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[4\] -fixed false -x 17 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m14 -fixed false -x 51 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[7\] -fixed false -x 203 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_70\[11\] -fixed false -x 304 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5\[4\] -fixed false -x 254 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[27\] -fixed false -x 467 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_0_1\[13\] -fixed false -x 133 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[13\] -fixed false -x 649 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[6\] -fixed false -x 435 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001\[3\] -fixed false -x 51 -y 160
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[28\] -fixed false -x 417 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[14\] -fixed false -x 708 -y 126
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3\[1\] -fixed false -x 492 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00016 -fixed false -x 70 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[2\] -fixed false -x 428 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948 -fixed false -x 688 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lI0i1_0_0_o2 -fixed false -x 160 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[41\] -fixed false -x 334 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_2\[29\] -fixed false -x 930 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[2\] -fixed false -x 773 -y 121
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[0\] -fixed false -x 526 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIQFEQD\[2\] -fixed false -x 80 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[11\] -fixed false -x 553 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[26\] -fixed false -x 855 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un13_IOIOo -fixed false -x 34 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[23\] -fixed false -x 767 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_2 -fixed false -x 171 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[4\] -fixed false -x 464 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[59\] -fixed false -x 929 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2\[24\] -fixed false -x 939 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m46 -fixed false -x 32 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[44\] -fixed false -x 916 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa_1 -fixed false -x 776 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_5 -fixed false -x 12 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[0\] -fixed false -x 427 -y 198
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[7\] -fixed false -x 378 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[36\] -fixed false -x 509 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01_1 -fixed false -x 222 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr\[0\] -fixed false -x 787 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_2_sqmuxa -fixed false -x 506 -y 144
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo12_0_0 -fixed false -x 495 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[1\] -fixed false -x 689 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m78_1_0 -fixed false -x 182 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[8\] -fixed false -x 265 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[19\] -fixed false -x 940 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[1\] -fixed false -x 816 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[25\] -fixed false -x 421 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[27\] -fixed false -x 870 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[12\] -fixed false -x 844 -y 123
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9 -fixed false -x 509 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[6\] -fixed false -x 319 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_10 -fixed false -x 441 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIL72R7_0\[11\] -fixed false -x 95 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[30\] -fixed false -x 885 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[1\] -fixed false -x 451 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[9\] -fixed false -x 296 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_2\[14\] -fixed false -x 621 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[30\] -fixed false -x 810 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_o3_RNIUOLVM_0 -fixed false -x 221 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[15\] -fixed false -x 805 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH9FFD\[2\] -fixed false -x 627 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[8\] -fixed false -x 193 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[25\] -fixed false -x 437 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[6\] -fixed false -x 493 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_334 -fixed false -x 713 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[21\] -fixed false -x 469 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[0\] -fixed false -x 409 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_3 -fixed false -x 749 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[16\] -fixed false -x 451 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/IiO01 -fixed false -x 434 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[1\] -fixed false -x 854 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[8\] -fixed false -x 247 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0\[2\] -fixed false -x 838 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[5\] -fixed false -x 639 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_582 -fixed false -x 687 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1238 -fixed false -x 722 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_o3 -fixed false -x 686 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[26\] -fixed false -x 402 -y 168
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3_1 -fixed false -x 13 -y 164
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0\[2\] -fixed false -x 706 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[2\] -fixed false -x 120 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_1_1_0_RNI2B9BI8 -fixed false -x 802 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[23\] -fixed false -x 804 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[25\] -fixed false -x 653 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0_o2 -fixed false -x 482 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[7\] -fixed false -x 451 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_4 -fixed false -x 508 -y 99
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_11 -fixed false -x 105 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_6 -fixed false -x 213 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[0\] -fixed false -x 315 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[33\] -fixed false -x 377 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 -fixed false -x 49 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7\[10\] -fixed false -x 81 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[27\] -fixed false -x 692 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[24\] -fixed false -x 828 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv\[1\] -fixed false -x 711 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[24\] -fixed false -x 786 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[10\] -fixed false -x 792 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[7\] -fixed false -x 568 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/un1_iOI01_1_i_0 -fixed false -x 218 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[20\] -fixed false -x 336 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[7\] -fixed false -x 761 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[21\] -fixed false -x 470 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_0\[4\] -fixed false -x 771 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_19\[20\] -fixed false -x 135 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[9\] -fixed false -x 729 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[20\] -fixed false -x 459 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st\[1\] -fixed false -x 32 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[23\] -fixed false -x 218 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_4 -fixed false -x 149 -y 195
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state134 -fixed false -x 520 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[18\] -fixed false -x 74 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[9\] -fixed false -x 202 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex_RNI7JLM\[1\] -fixed false -x 765 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[3\] -fixed false -x 233 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[28\] -fixed false -x 902 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13\[4\] -fixed false -x 401 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[19\] -fixed false -x 473 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[17\] -fixed false -x 834 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[21\] -fixed false -x 819 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[23\] -fixed false -x 852 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_5_c2 -fixed false -x 104 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_4 -fixed false -x 778 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv -fixed false -x 722 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[18\] -fixed false -x 445 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[5\] -fixed false -x 67 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01\[1\] -fixed false -x 181 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0\[14\] -fixed false -x 669 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0\[1\] -fixed false -x 145 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[0\] -fixed false -x 60 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[4\] -fixed false -x 398 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOol1 -fixed false -x 407 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[5\] -fixed false -x 714 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[8\] -fixed false -x 78 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[31\] -fixed false -x 838 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_763 -fixed false -x 602 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[9\] -fixed false -x 467 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[1\] -fixed false -x 151 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[16\] -fixed false -x 308 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[30\] -fixed false -x 125 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[2\] -fixed false -x 210 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[27\] -fixed false -x 704 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un310_lIlo1 -fixed false -x 176 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_203 -fixed false -x 616 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[5\] -fixed false -x 567 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_28\[20\] -fixed false -x 134 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[31\] -fixed false -x 908 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter\[1\] -fixed false -x 784 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[13\] -fixed false -x 649 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_100 -fixed false -x 590 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_execute/gen_bit_reset.state_val\[0\] -fixed false -x 795 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[2\] -fixed false -x 867 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[25\] -fixed false -x 63 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_5 -fixed false -x 638 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_error_resp.gen_buff_loop\[0\].buff_entry_error_resp_ram0_\[0\] -fixed false -x 631 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[23\] -fixed false -x 906 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_44\[11\] -fixed false -x 264 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[3\] -fixed false -x 362 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1 -fixed false -x 51 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[26\] -fixed false -x 943 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un26_il0Oo_0_a3 -fixed false -x 135 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[0\] -fixed false -x 220 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[14\] -fixed false -x 417 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[11\] -fixed false -x 659 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_tz\[1\] -fixed false -x 749 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0_1_0\[0\] -fixed false -x 249 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[14\] -fixed false -x 614 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[25\] -fixed false -x 845 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_2_RNO -fixed false -x 802 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un3_i11Io -fixed false -x 408 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en\[0\] -fixed false -x 712 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_186 -fixed false -x 703 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[6\] -fixed false -x 888 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR_2_sqmuxa -fixed false -x 570 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_1_0 -fixed false -x 87 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[23\] -fixed false -x 369 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[6\] -fixed false -x 124 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI3B5AH -fixed false -x 757 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[12\] -fixed false -x 506 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[4\] -fixed false -x 832 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[5\] -fixed false -x 81 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[30\] -fixed false -x 631 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[2\] -fixed false -x 211 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[1\] -fixed false -x 338 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO\[15\] -fixed false -x 149 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[2\] -fixed false -x 531 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[11\] -fixed false -x 300 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[6\] -fixed false -x 795 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_3_1.CO1 -fixed false -x 551 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[1\] -fixed false -x 811 -y 115
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_slave -fixed false -x 532 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[8\] -fixed false -x 324 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_0 -fixed false -x 90 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[14\] -fixed false -x 965 -y 147
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[0\] -fixed false -x 373 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[4\] -fixed false -x 831 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[17\] -fixed false -x 912 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un35_I1Oi1 -fixed false -x 36 -y 177
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_d_1_0 -fixed false -x 536 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[27\] -fixed false -x 929 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_3 -fixed false -x 682 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[4\] -fixed false -x 524 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_8\[0\] -fixed false -x 257 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]_RNICLNUF\[2\] -fixed false -x 780 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[4\] -fixed false -x 770 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr\[1\] -fixed false -x 628 -y 115
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_1 -fixed false -x 519 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oio11_1 -fixed false -x 329 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_O0li1\[0\] -fixed false -x 146 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q2 -fixed false -x 532 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto18_7 -fixed false -x 801 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33\[6\] -fixed false -x 935 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[26\] -fixed false -x 597 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m15_2_0 -fixed false -x 77 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/resp_dest\[0\] -fixed false -x 749 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0 -fixed false -x 843 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1066 -fixed false -x 688 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[4\] -fixed false -x 671 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_2 -fixed false -x 697 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1120 -fixed false -x 629 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex_1\[1\] -fixed false -x 774 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO\[0\] -fixed false -x 192 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo_RNO\[3\] -fixed false -x 328 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[7\] -fixed false -x 400 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid40 -fixed false -x 788 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[2\] -fixed false -x 912 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[9\] -fixed false -x 250 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[9\] -fixed false -x 191 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_36\[9\] -fixed false -x 915 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[1\] -fixed false -x 440 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17 -fixed false -x 570 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[4\] -fixed false -x 379 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oIiOo_1.CO3 -fixed false -x 359 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_sx_0 -fixed false -x 804 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv\[7\] -fixed false -x 752 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[13\] -fixed false -x 135 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[27\] -fixed false -x 923 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc3 -fixed false -x 116 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_RNITOT59\[0\] -fixed false -x 42 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_valid\[0\] -fixed false -x 785 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[58\] -fixed false -x 596 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[25\] -fixed false -x 454 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40_cZ\[6\] -fixed false -x 367 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[15\] -fixed false -x 849 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_27_0_RNO -fixed false -x 832 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_rd_op_retr -fixed false -x 772 -y 130
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[6\] -fixed false -x 497 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc1 -fixed false -x 58 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un423_lIlo1 -fixed false -x 315 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2\[1\] -fixed false -x 764 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[10\] -fixed false -x 877 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_o2_0 -fixed false -x 159 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[8\] -fixed false -x 293 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[19\] -fixed false -x 887 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat\[0\] -fixed false -x 619 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[16\] -fixed false -x 813 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0li1_0_a3 -fixed false -x 181 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un137_OOOI1\[18\] -fixed false -x 438 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_a2 -fixed false -x 638 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[3\] -fixed false -x 49 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[7\] -fixed false -x 135 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_315 -fixed false -x 661 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_16\[1\] -fixed false -x 318 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[6\] -fixed false -x 814 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[4\] -fixed false -x 496 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[28\] -fixed false -x 771 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[20\] -fixed false -x 666 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iOo_1 -fixed false -x 124 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_19 -fixed false -x 137 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[11\] -fixed false -x 508 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0_o3\[1\] -fixed false -x 99 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[26\] -fixed false -x 780 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[8\] -fixed false -x 295 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[11\] -fixed false -x 869 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[1\] -fixed false -x 407 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un17_ool01 -fixed false -x 196 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[17\] -fixed false -x 736 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[22\] -fixed false -x 554 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[5\] -fixed false -x 79 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOo11\[0\] -fixed false -x 96 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_13 -fixed false -x 628 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[30\] -fixed false -x 622 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[4\] -fixed false -x 519 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[12\] -fixed false -x 843 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[48\] -fixed false -x 539 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[10\] -fixed false -x 759 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1iOo_1 -fixed false -x 116 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[5\] -fixed false -x 29 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_6\[29\] -fixed false -x 646 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[16\] -fixed false -x 699 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_14 -fixed false -x 620 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIEA0D6\[0\] -fixed false -x 296 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_3 -fixed false -x 148 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[1\] -fixed false -x 894 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO_0 -fixed false -x 770 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[17\] -fixed false -x 685 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[31\] -fixed false -x 551 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_tick_4 -fixed false -x 510 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[46\] -fixed false -x 505 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_10_0\[22\] -fixed false -x 263 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z\[4\] -fixed false -x 311 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[28\] -fixed false -x 863 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1095 -fixed false -x 699 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_2 -fixed false -x 505 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2118 -fixed false -x 665 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[30\] -fixed false -x 847 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[1\] -fixed false -x 276 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[25\] -fixed false -x 411 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1015 -fixed false -x 614 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_1_sqmuxa -fixed false -x 784 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[26\] -fixed false -x 781 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a3 -fixed false -x 833 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[4\] -fixed false -x 344 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001\[1\] -fixed false -x 95 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[30\] -fixed false -x 413 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_set_wfi_waiting_1 -fixed false -x 764 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[17\] -fixed false -x 455 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[14\] -fixed false -x 926 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iI1i1_0_a2 -fixed false -x 213 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIF83E9\[14\] -fixed false -x 76 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[7\] -fixed false -x 332 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]2_0 -fixed false -x 875 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_773 -fixed false -x 615 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1027 -fixed false -x 630 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[8\] -fixed false -x 446 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_3 -fixed false -x 103 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[1\] -fixed false -x 42 -y 184
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[11\] -fixed false -x 480 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_304 -fixed false -x 746 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2\[2\] -fixed false -x 256 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[38\] -fixed false -x 383 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_44\[10\] -fixed false -x 278 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[7\] -fixed false -x 428 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[1\] -fixed false -x 285 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[20\] -fixed false -x 448 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_1 -fixed false -x 390 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_74 -fixed false -x 603 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[29\] -fixed false -x 738 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[17\] -fixed false -x 740 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[10\] -fixed false -x 316 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[15\] -fixed false -x 307 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0\[15\] -fixed false -x 829 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1_RNI5AAK5 -fixed false -x 734 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Oooi1 -fixed false -x 180 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux -fixed false -x 782 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OlIl1\[0\] -fixed false -x 378 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[3\] -fixed false -x 66 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_2 -fixed false -x 520 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[21\] -fixed false -x 444 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[4\] -fixed false -x 96 -y 214
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_wmux_0_RNITLTG1\[3\] -fixed false -x 82 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2 -fixed false -x 828 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_7_f0 -fixed false -x 775 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/un1_Ioli0_1_0 -fixed false -x 296 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[13\] -fixed false -x 636 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/un1_iOI01_1_i_0 -fixed false -x 328 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[20\] -fixed false -x 770 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_154 -fixed false -x 601 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr\[1\] -fixed false -x 790 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[20\] -fixed false -x 824 -y 126
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[2\].BUFD_BLK -fixed false -x 530 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1293 -fixed false -x 809 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[7\] -fixed false -x 409 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un5_IlIOo_0 -fixed false -x 44 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[29\] -fixed false -x 940 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[49\] -fixed false -x 568 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2\[0\] -fixed false -x 741 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[31\] -fixed false -x 778 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_iv -fixed false -x 486 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[13\] -fixed false -x 748 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1213 -fixed false -x 773 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0\[2\] -fixed false -x 773 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO_1 -fixed false -x 844 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_il0Oo -fixed false -x 157 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1 -fixed false -x 99 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[8\] -fixed false -x 447 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[9\] -fixed false -x 43 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O00i1 -fixed false -x 185 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[4\] -fixed false -x 405 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m24 -fixed false -x 635 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_0 -fixed false -x 705 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_0\[10\] -fixed false -x 848 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNILOR4J -fixed false -x 837 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1 -fixed false -x 231 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_RNO\[4\] -fixed false -x 292 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[0\] -fixed false -x 198 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto8_2 -fixed false -x 133 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z\[0\] -fixed false -x 294 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[16\] -fixed false -x 827 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_992 -fixed false -x 684 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[8\] -fixed false -x 275 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0_1 -fixed false -x 843 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[10\] -fixed false -x 841 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_0_1 -fixed false -x 75 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[28\] -fixed false -x 543 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[5\] -fixed false -x 366 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[4\] -fixed false -x 100 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[1\] -fixed false -x 166 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[11\] -fixed false -x 301 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15 -fixed false -x 87 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[1\] -fixed false -x 146 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[6\] -fixed false -x 964 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[1\] -fixed false -x 634 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O0lI1 -fixed false -x 320 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2\[24\] -fixed false -x 106 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[40\] -fixed false -x 905 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[1\] -fixed false -x 745 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[4\] -fixed false -x 232 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[17\] -fixed false -x 439 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel_2 -fixed false -x 710 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[1\] -fixed false -x 244 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1\[1\] -fixed false -x 70 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_10_0_i -fixed false -x 62 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3 -fixed false -x 829 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[27\] -fixed false -x 783 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[8\] -fixed false -x 363 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[59\] -fixed false -x 951 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_9 -fixed false -x 839 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m3 -fixed false -x 56 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11\[14\] -fixed false -x 32 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_I00Oo -fixed false -x 254 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[8\] -fixed false -x 38 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0\[30\] -fixed false -x 699 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[30\] -fixed false -x 702 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[6\] -fixed false -x 626 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[3\] -fixed false -x 325 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un351_lIlo1 -fixed false -x 175 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_Oooo1_tz_tz_1 -fixed false -x 75 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_90 -fixed false -x 638 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_8 -fixed false -x 737 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6_RNI6DTB8 -fixed false -x 820 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/stage_ready_ex_2_RNO -fixed false -x 737 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[4\] -fixed false -x 179 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[17\] -fixed false -x 651 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[28\] -fixed false -x 246 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001\[3\] -fixed false -x 123 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_a2_1 -fixed false -x 761 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[8\] -fixed false -x 137 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[14\] -fixed false -x 745 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[5\] -fixed false -x 760 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[3\] -fixed false -x 810 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2\[4\] -fixed false -x 253 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1_0\[1\] -fixed false -x 667 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[27\] -fixed false -x 723 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[8\] -fixed false -x 117 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[25\] -fixed false -x 815 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OlIi1_0 -fixed false -x 168 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_1815_fast -fixed false -x 777 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[20\] -fixed false -x 878 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[15\] -fixed false -x 729 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[0\] -fixed false -x 637 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[3\] -fixed false -x 227 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[4\] -fixed false -x 400 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[19\] -fixed false -x 469 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_error_sig_1 -fixed false -x 792 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_8 -fixed false -x 187 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[6\] -fixed false -x 496 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[18\] -fixed false -x 749 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[7\].BUFD_BLK -fixed false -x 529 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[24\] -fixed false -x 867 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un11_ool01 -fixed false -x 195 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[15\] -fixed false -x 818 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[8\] -fixed false -x 358 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[7\] -fixed false -x 439 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_0\[0\] -fixed false -x 966 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[23\] -fixed false -x 357 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[1\] -fixed false -x 833 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.lliOo\[5\] -fixed false -x 340 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[11\] -fixed false -x 480 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_type_1s2 -fixed false -x 733 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m37_1 -fixed false -x 27 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[6\] -fixed false -x 295 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_1_tz -fixed false -x 60 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[7\] -fixed false -x 209 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[12\] -fixed false -x 545 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/un1_iOI01_1_i_0 -fixed false -x 312 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_2 -fixed false -x 151 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[4\] -fixed false -x 434 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/OloIo -fixed false -x 377 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/instr_inhibit_ex -fixed false -x 815 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oii01\[0\] -fixed false -x 36 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q\[3\] -fixed false -x 566 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1\[3\] -fixed false -x 768 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[19\] -fixed false -x 895 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[24\] -fixed false -x 719 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a4_0\[0\] -fixed false -x 42 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[19\] -fixed false -x 884 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0_a3_0 -fixed false -x 481 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[42\] -fixed false -x 285 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1\[1\] -fixed false -x 775 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1_1 -fixed false -x 288 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[7\] -fixed false -x 842 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[0\] -fixed false -x 165 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[10\] -fixed false -x 42 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[11\] -fixed false -x 930 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_980 -fixed false -x 733 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[31\] -fixed false -x 427 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[30\] -fixed false -x 876 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[26\] -fixed false -x 606 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[15\] -fixed false -x 325 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[25\] -fixed false -x 872 -y 132
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA\[5\] -fixed false -x 485 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[19\] -fixed false -x 778 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[3\] -fixed false -x 894 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a0_2 -fixed false -x 782 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_Oo1l1 -fixed false -x 396 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[33\] -fixed false -x 428 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[15\] -fixed false -x 937 -y 141
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[5\] -fixed false -x 388 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg -fixed false -x 802 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[0\] -fixed false -x 424 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo -fixed false -x 242 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig18 -fixed false -x 487 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0\[1\] -fixed false -x 35 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[0\] -fixed false -x 66 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[9\] -fixed false -x 506 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[8\] -fixed false -x 385 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[16\] -fixed false -x 88 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un13_loOo1_0_o4 -fixed false -x 298 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[36\] -fixed false -x 425 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1\[0\] -fixed false -x 137 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo -fixed false -x 15 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux_1 -fixed false -x 736 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[3\] -fixed false -x 55 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[31\] -fixed false -x 928 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3\[5\] -fixed false -x 903 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_7\[24\] -fixed false -x 318 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[6\] -fixed false -x 398 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1045 -fixed false -x 712 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[59\] -fixed false -x 569 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[0\] -fixed false -x 288 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_111 -fixed false -x 771 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[22\] -fixed false -x 427 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_0 -fixed false -x 541 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[5\] -fixed false -x 665 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[2\] -fixed false -x 608 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[11\] -fixed false -x 91 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1074 -fixed false -x 656 -y 186
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc5 -fixed false -x 107 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retrc -fixed false -x 781 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_443 -fixed false -x 638 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[27\] -fixed false -x 326 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[9\] -fixed false -x 128 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[2\] -fixed false -x 716 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[17\] -fixed false -x 667 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[0\] -fixed false -x 408 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_484 -fixed false -x 698 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[10\] -fixed false -x 234 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_2 -fixed false -x 102 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI7HN97\[14\] -fixed false -x 100 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un1_IoI11 -fixed false -x 349 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_9_164_a2 -fixed false -x 436 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[18\] -fixed false -x 460 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[5\] -fixed false -x 707 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[13\] -fixed false -x 873 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[6\] -fixed false -x 830 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_22_RNIBG1D8 -fixed false -x 805 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex_2_u -fixed false -x 764 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[12\] -fixed false -x 721 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[1\] -fixed false -x 637 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n3 -fixed false -x 202 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1\[4\] -fixed false -x 266 -y 213
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM\[2\] -fixed false -x 39 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_312 -fixed false -x 696 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[5\] -fixed false -x 336 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/ii1l1 -fixed false -x 414 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[3\] -fixed false -x 21 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1_0\[8\] -fixed false -x 196 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[2\] -fixed false -x 333 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[14\] -fixed false -x 106 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_24_0_RNO -fixed false -x 817 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_6 -fixed false -x 182 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[9\] -fixed false -x 73 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_RNIQHFRC\[1\] -fixed false -x 122 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[10\] -fixed false -x 42 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[24\] -fixed false -x 680 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[4\] -fixed false -x 458 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[0\] -fixed false -x 841 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[31\] -fixed false -x 746 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr\[2\] -fixed false -x 445 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[7\] -fixed false -x 352 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[1\] -fixed false -x 251 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2116 -fixed false -x 663 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z\[1\] -fixed false -x 295 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[5\] -fixed false -x 862 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[8\] -fixed false -x 90 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[4\] -fixed false -x 939 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[6\] -fixed false -x 610 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_1 -fixed false -x 228 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_23 -fixed false -x 629 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ol0Oo -fixed false -x 282 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[12\] -fixed false -x 239 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[8\] -fixed false -x 348 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[44\] -fixed false -x 912 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_4 -fixed false -x 72 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[1\] -fixed false -x 217 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[20\] -fixed false -x 943 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1243 -fixed false -x 667 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[29\] -fixed false -x 845 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[30\] -fixed false -x 847 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[1\] -fixed false -x 157 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0_a3_1 -fixed false -x 134 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[27\] -fixed false -x 122 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lOl01 -fixed false -x 181 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[34\] -fixed false -x 915 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[15\] -fixed false -x 727 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[18\] -fixed false -x 715 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001_0\[6\] -fixed false -x 80 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[31\] -fixed false -x 945 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_914 -fixed false -x 756 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[12\] -fixed false -x 330 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[1\] -fixed false -x 696 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIAFL4C\[1\] -fixed false -x 642 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11\[11\] -fixed false -x 264 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[19\] -fixed false -x 390 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[0\] -fixed false -x 397 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[22\] -fixed false -x 472 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo -fixed false -x 112 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_1 -fixed false -x 14 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_a8_0 -fixed false -x 627 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[2\] -fixed false -x 493 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_0 -fixed false -x 167 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[7\] -fixed false -x 402 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un263_lIlo1 -fixed false -x 195 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_16\[0\] -fixed false -x 331 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/res_pos_neg -fixed false -x 869 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[34\] -fixed false -x 904 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[14\] -fixed false -x 125 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlOo1 -fixed false -x 306 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1o11 -fixed false -x 347 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[26\] -fixed false -x 648 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_1_RNI03J3J -fixed false -x 732 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val\[0\] -fixed false -x 756 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOii1 -fixed false -x 145 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[20\] -fixed false -x 539 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_2 -fixed false -x 485 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_539 -fixed false -x 806 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[0\] -fixed false -x 703 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i\[1\] -fixed false -x 281 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1001 -fixed false -x 628 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_7 -fixed false -x 188 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[0\] -fixed false -x 254 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[1\] -fixed false -x 424 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[9\] -fixed false -x 434 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex\[2\] -fixed false -x 729 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4_RNILISNE -fixed false -x 742 -y 147
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE_RNO -fixed false -x 24 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv\[9\] -fixed false -x 628 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O00o1_N_3_mux_i -fixed false -x 18 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_0 -fixed false -x 834 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[13\] -fixed false -x 856 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_12\[22\] -fixed false -x 251 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_mem_error_ex -fixed false -x 744 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[19\] -fixed false -x 460 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM_0\[3\] -fixed false -x 205 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m5 -fixed false -x 847 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO -fixed false -x 769 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[17\] -fixed false -x 925 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[8\] -fixed false -x 374 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[7\] -fixed false -x 266 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[0\] -fixed false -x 509 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1278 -fixed false -x 784 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[22\] -fixed false -x 250 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[61\] -fixed false -x 935 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[6\] -fixed false -x 436 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[22\] -fixed false -x 949 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[28\] -fixed false -x 914 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1129 -fixed false -x 688 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[29\] -fixed false -x 804 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO\[1\] -fixed false -x 27 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[31\] -fixed false -x 393 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_25_0_RNO -fixed false -x 846 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo_1 -fixed false -x 362 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[23\] -fixed false -x 686 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[1\] -fixed false -x 473 -y 150
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow_RNO -fixed false -x 533 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO -fixed false -x 193 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[18\] -fixed false -x 426 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4915_3_0 -fixed false -x 613 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[46\] -fixed false -x 903 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[24\] -fixed false -x 673 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[1\] -fixed false -x 256 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[20\] -fixed false -x 808 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0\[0\] -fixed false -x 147 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_llOl1_0 -fixed false -x 397 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_757 -fixed false -x 673 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_0_sqmuxa_0_a3_0 -fixed false -x 197 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un3_ooOOo -fixed false -x 37 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt\[0\] -fixed false -x 30 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx8 -fixed false -x 507 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_43\[8\] -fixed false -x 951 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un19_OIiOo -fixed false -x 148 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[23\] -fixed false -x 835 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[7\] -fixed false -x 404 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1\[36\] -fixed false -x 429 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0\[1\] -fixed false -x 627 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1201 -fixed false -x 662 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[19\] -fixed false -x 121 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJBFFD\[3\] -fixed false -x 637 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l11I1 -fixed false -x 444 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_alu_op_completing_ex -fixed false -x 769 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[4\] -fixed false -x 809 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_accepted_0 -fixed false -x 759 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3\[6\] -fixed false -x 109 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[22\] -fixed false -x 438 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[3\] -fixed false -x 209 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[11\] -fixed false -x 472 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3\[1\] -fixed false -x 125 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_17 -fixed false -x 136 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o0ll1 -fixed false -x 448 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/m23_1_0 -fixed false -x 847 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[4\] -fixed false -x 485 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_69 -fixed false -x 711 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[12\] -fixed false -x 223 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[2\] -fixed false -x 523 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[3\] -fixed false -x 187 -y 202
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[7\].BUFD_BLK -fixed false -x 508 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_749 -fixed false -x 747 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[20\] -fixed false -x 748 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[4\] -fixed false -x 404 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0 -fixed false -x 812 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[0\] -fixed false -x 428 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[9\] -fixed false -x 76 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[10\] -fixed false -x 370 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[5\] -fixed false -x 257 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3_1_0\[1\] -fixed false -x 756 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[1\] -fixed false -x 893 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto2_0 -fixed false -x 819 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[6\] -fixed false -x 530 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[5\] -fixed false -x 109 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[8\] -fixed false -x 929 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[2\] -fixed false -x 590 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_859 -fixed false -x 602 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2\[18\] -fixed false -x 108 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[8\] -fixed false -x 70 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000110 -fixed false -x 78 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01 -fixed false -x 221 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[11\] -fixed false -x 358 -y 201
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state7_0_a2 -fixed false -x 13 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[2\] -fixed false -x 65 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[9\] -fixed false -x 379 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[22\] -fixed false -x 439 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0\[5\] -fixed false -x 89 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex\[2\] -fixed false -x 808 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25\[1\] -fixed false -x 267 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[24\] -fixed false -x 63 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[28\] -fixed false -x 246 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[12\] -fixed false -x 794 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[4\] -fixed false -x 290 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[10\] -fixed false -x 660 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_260 -fixed false -x 673 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[7\] -fixed false -x 785 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[26\] -fixed false -x 246 -y 214
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast\[7\] -fixed false -x 487 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_i_o2\[2\] -fixed false -x 745 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dpc_debugger_wr_sel_1 -fixed false -x 697 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[3\] -fixed false -x 893 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848 -fixed false -x 628 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[4\] -fixed false -x 135 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_735 -fixed false -x 601 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO -fixed false -x 845 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[14\] -fixed false -x 855 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNICICEN -fixed false -x 828 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[29\] -fixed false -x 774 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO -fixed false -x 881 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[0\] -fixed false -x 794 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[1\] -fixed false -x 306 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[9\] -fixed false -x 235 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_7_i_o3\[15\] -fixed false -x 143 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_399 -fixed false -x 662 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[12\] -fixed false -x 372 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI0l1\[0\] -fixed false -x 444 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1 -fixed false -x 28 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[1\].BUFD_BLK -fixed false -x 485 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[1\] -fixed false -x 405 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_327 -fixed false -x 744 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNIP71DG\[11\] -fixed false -x 449 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[13\] -fixed false -x 749 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[2\] -fixed false -x 135 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m253 -fixed false -x 267 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[29\] -fixed false -x 507 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un41_OOOI1\[16\] -fixed false -x 408 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_6 -fixed false -x 672 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[3\] -fixed false -x 394 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state134 -fixed false -x 519 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[27\] -fixed false -x 923 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[2\] -fixed false -x 315 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo_RNIBMSF3\[0\] -fixed false -x 291 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[5\] -fixed false -x 432 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[0\] -fixed false -x 467 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[35\] -fixed false -x 431 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[3\] -fixed false -x 116 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[2\] -fixed false -x 64 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_d_1_sqmuxa_1 -fixed false -x 596 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_shifter_unit_op_sel_ex\[1\] -fixed false -x 818 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_42\[9\] -fixed false -x 280 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[9\] -fixed false -x 175 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[29\] -fixed false -x 798 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_1_0 -fixed false -x 707 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1\[14\] -fixed false -x 856 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[10\] -fixed false -x 729 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[11\] -fixed false -x 496 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[8\] -fixed false -x 187 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001\[4\] -fixed false -x 158 -y 192
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full -fixed false -x 405 -y 235
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_2_sqmuxa_1_RNI3SFHG -fixed false -x 525 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[16\] -fixed false -x 446 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0_a3_0_0\[0\] -fixed false -x 758 -y 141
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code -fixed false -x 3 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_35\[10\] -fixed false -x 293 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OoOl1 -fixed false -x 446 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[0\] -fixed false -x 666 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[30\] -fixed false -x 952 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_5_RNO -fixed false -x 365 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_2\[3\] -fixed false -x 799 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff -fixed false -x 824 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a2_0_N_3L3 -fixed false -x 816 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv\[1\] -fixed false -x 770 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[25\] -fixed false -x 818 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[10\] -fixed false -x 342 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un26_Oo1Io -fixed false -x 399 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10\[1\] -fixed false -x 545 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[16\] -fixed false -x 813 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[2\] -fixed false -x 426 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i0Oi1 -fixed false -x 60 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[23\] -fixed false -x 870 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[27\] -fixed false -x 459 -y 192
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[4\] -fixed false -x 401 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_638 -fixed false -x 674 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_6\[31\] -fixed false -x 658 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[11\] -fixed false -x 772 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_514 -fixed false -x 565 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0\[2\] -fixed false -x 103 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m13 -fixed false -x 52 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2_0 -fixed false -x 823 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_alu_op_completing_ex_RNIDSVU6_0 -fixed false -x 771 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_13 -fixed false -x 686 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[5\] -fixed false -x 162 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_15\[11\] -fixed false -x 307 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[6\] -fixed false -x 541 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[2\] -fixed false -x 48 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[15\] -fixed false -x 687 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[5\] -fixed false -x 491 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[22\] -fixed false -x 453 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa_0 -fixed false -x 561 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_execute/gen_bit_reset.state_val_12_u\[0\] -fixed false -x 795 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[16\] -fixed false -x 221 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[20\] -fixed false -x 848 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_2_sqmuxa_RNIQU23F -fixed false -x 597 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un47_I1Oi1 -fixed false -x 27 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a4_0 -fixed false -x 754 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30\[11\] -fixed false -x 216 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[8\] -fixed false -x 362 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_798 -fixed false -x 627 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[24\] -fixed false -x 734 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[8\] -fixed false -x 885 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[9\] -fixed false -x 614 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_capture_reg4 -fixed false -x 778 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_8 -fixed false -x 230 -y 210
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/full_out -fixed false -x 522 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_4 -fixed false -x 686 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_449 -fixed false -x 759 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[10\] -fixed false -x 871 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2_0 -fixed false -x 76 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[10\] -fixed false -x 176 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[2\] -fixed false -x 399 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[23\] -fixed false -x 928 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un8_loOo1_0_a2 -fixed false -x 290 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[1\] -fixed false -x 161 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[11\] -fixed false -x 126 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[18\] -fixed false -x 460 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_1_sqmuxa_2 -fixed false -x 811 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_941 -fixed false -x 724 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[7\] -fixed false -x 435 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PWRITE_m -fixed false -x 514 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[31\] -fixed false -x 352 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[21\] -fixed false -x 879 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state\[0\] -fixed false -x 472 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0Oo -fixed false -x 279 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[8\] -fixed false -x 636 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[3\] -fixed false -x 209 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_0_146_a2 -fixed false -x 414 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_RNI2O4OH -fixed false -x 708 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[24\] -fixed false -x 939 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[4\] -fixed false -x 462 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[39\] -fixed false -x 442 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[1\] -fixed false -x 758 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1209 -fixed false -x 662 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[6\] -fixed false -x 302 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[1\] -fixed false -x 74 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[9\] -fixed false -x 700 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[0\] -fixed false -x 268 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1OIo -fixed false -x 153 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[3\] -fixed false -x 389 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i -fixed false -x 703 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[1\] -fixed false -x 630 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l1oi1 -fixed false -x 265 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un28_i11Io -fixed false -x 411 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_7 -fixed false -x 145 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[11\] -fixed false -x 354 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1204 -fixed false -x 743 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01\[1\] -fixed false -x 164 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[24\] -fixed false -x 837 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0\[8\] -fixed false -x 120 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[7\] -fixed false -x 230 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[1\] -fixed false -x 115 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[1\] -fixed false -x 74 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[14\] -fixed false -x 879 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[11\] -fixed false -x 603 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_509 -fixed false -x 722 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oo111_2 -fixed false -x 391 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[7\] -fixed false -x 497 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[2\] -fixed false -x 213 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[6\] -fixed false -x 199 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[26\] -fixed false -x 824 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[9\] -fixed false -x 412 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[6\] -fixed false -x 305 -y 187
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO\[3\] -fixed false -x 35 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1167 -fixed false -x 638 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[6\] -fixed false -x 899 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[13\] -fixed false -x 128 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_855 -fixed false -x 603 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[18\] -fixed false -x 439 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[2\] -fixed false -x 495 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O00Oo_RNIAJD3M -fixed false -x 94 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[4\] -fixed false -x 272 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_48\[8\] -fixed false -x 873 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_863 -fixed false -x 650 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[20\] -fixed false -x 649 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_4_0\[1\] -fixed false -x 757 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPJVQ8\[33\] -fixed false -x 642 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1\[28\] -fixed false -x 745 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[8\] -fixed false -x 518 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/IilI1_RNO -fixed false -x 356 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[22\] -fixed false -x 737 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un141_i0lo1\[2\] -fixed false -x 214 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m31 -fixed false -x 54 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1\[0\] -fixed false -x 130 -y 198
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[4\] -fixed false -x 498 -y 97
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out -fixed false -x 575 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places57_RNIJO7A -fixed false -x 856 -y 141
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo12 -fixed false -x 494 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[8\] -fixed false -x 661 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[7\] -fixed false -x 208 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO -fixed false -x 118 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_270 -fixed false -x 757 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[16\] -fixed false -x 682 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[24\] -fixed false -x 843 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[10\] -fixed false -x 568 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[23\] -fixed false -x 905 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m0_i_a2_0\[0\] -fixed false -x 687 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1\[4\] -fixed false -x 870 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[15\] -fixed false -x 374 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ioOl1_1 -fixed false -x 390 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[0\] -fixed false -x 440 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[9\] -fixed false -x 446 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un3_IIO11 -fixed false -x 12 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNI3T88E\[20\] -fixed false -x 651 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_268 -fixed false -x 617 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0\[5\] -fixed false -x 678 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_897 -fixed false -x 728 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[6\] -fixed false -x 420 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[6\] -fixed false -x 41 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1\[0\] -fixed false -x 776 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[17\] -fixed false -x 862 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[5\] -fixed false -x 411 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_OioOo_2 -fixed false -x 97 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[10\] -fixed false -x 208 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_3_sqmuxa -fixed false -x 682 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[31\] -fixed false -x 864 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[25\] -fixed false -x 546 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[15\] -fixed false -x 291 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_1 -fixed false -x 264 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_513 -fixed false -x 710 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_ready_reg_RNIJLJBF -fixed false -x 831 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[0\] -fixed false -x 301 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[1\] -fixed false -x 198 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_0_RNO -fixed false -x 115 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[0\] -fixed false -x 438 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[14\] -fixed false -x 837 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[3\] -fixed false -x 183 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[6\] -fixed false -x 254 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[2\] -fixed false -x 210 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[15\] -fixed false -x 50 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m60 -fixed false -x 62 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_4_sx -fixed false -x 815 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/oo111 -fixed false -x 239 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_RNO -fixed false -x 832 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[35\] -fixed false -x 923 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/un43_lIo11_i_o3 -fixed false -x 112 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[1\].BUFD_BLK -fixed false -x 486 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[11\] -fixed false -x 31 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[2\] -fixed false -x 775 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO -fixed false -x 809 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[29\] -fixed false -x 832 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[23\] -fixed false -x 904 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[6\] -fixed false -x 365 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[6\] -fixed false -x 709 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_l1Oo1\[0\] -fixed false -x 320 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[24\] -fixed false -x 830 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[10\] -fixed false -x 736 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[7\] -fixed false -x 153 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[6\] -fixed false -x 663 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[11\] -fixed false -x 530 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[4\] -fixed false -x 65 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1096 -fixed false -x 630 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/data_rx_q1 -fixed false -x 504 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOII1 -fixed false -x 374 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol1I1 -fixed false -x 454 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2\[3\] -fixed false -x 379 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1016 -fixed false -x 619 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[27\] -fixed false -x 740 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[21\] -fixed false -x 152 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[13\] -fixed false -x 839 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[31\] -fixed false -x 787 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[27\] -fixed false -x 465 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[9\] -fixed false -x 771 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIHK6GO\[16\] -fixed false -x 880 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[3\] -fixed false -x 49 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0_0\[12\] -fixed false -x 857 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_lsu_stall.un14_gpr_rs1_stall_lsu_RNI3J5LE -fixed false -x 784 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[17\] -fixed false -x 438 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[11\] -fixed false -x 128 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[19\] -fixed false -x 398 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_0 -fixed false -x 141 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[24\] -fixed false -x 31 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[2\] -fixed false -x 866 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[6\] -fixed false -x 886 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/illo1 -fixed false -x 333 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_705 -fixed false -x 661 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[1\] -fixed false -x 731 -y 121
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_RNO -fixed false -x 525 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_388 -fixed false -x 628 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_strb\[0\] -fixed false -x 786 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un11_ool01_2 -fixed false -x 194 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[17\] -fixed false -x 844 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[6\] -fixed false -x 169 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[11\] -fixed false -x 131 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[30\] -fixed false -x 420 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2125 -fixed false -x 665 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[28\] -fixed false -x 872 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[28\] -fixed false -x 689 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[33\] -fixed false -x 447 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1\[15\] -fixed false -x 82 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[6\] -fixed false -x 290 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[4\] -fixed false -x 512 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooIi1_0_a2_0_o2 -fixed false -x 170 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[31\] -fixed false -x 937 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[28\] -fixed false -x 768 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_2_i_a2 -fixed false -x 790 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_iIIi1 -fixed false -x 165 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[3\] -fixed false -x 318 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_0_sqmuxa_0 -fixed false -x 193 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[13\] -fixed false -x 689 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[27\] -fixed false -x 86 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.awe2 -fixed false -x 708 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_fence_i_retr -fixed false -x 779 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa -fixed false -x 774 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s -fixed false -x 766 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_1 -fixed false -x 697 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_sn_m2 -fixed false -x 816 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[3\] -fixed false -x 737 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1iO1 -fixed false -x 108 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m4 -fixed false -x 122 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[2\] -fixed false -x 710 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[7\] -fixed false -x 122 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[7\] -fixed false -x 842 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_RNI8IEP7 -fixed false -x 800 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_0_1_0 -fixed false -x 825 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[5\] -fixed false -x 704 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_730 -fixed false -x 663 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[14\] -fixed false -x 803 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_881 -fixed false -x 683 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_5_218_a2 -fixed false -x 313 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[25\] -fixed false -x 867 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI1I18 -fixed false -x 470 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[23\] -fixed false -x 347 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[24\] -fixed false -x 697 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[4\] -fixed false -x 385 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_34\[10\] -fixed false -x 277 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[23\] -fixed false -x 926 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_valid\[1\] -fixed false -x 813 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[28\] -fixed false -x 760 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[3\] -fixed false -x 507 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_N_11_mux_i_N_7L13 -fixed false -x 794 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_5 -fixed false -x 99 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[20\] -fixed false -x 942 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_6 -fixed false -x 146 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_exce\[0\] -fixed false -x 805 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_608 -fixed false -x 637 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[19\] -fixed false -x 700 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[14\] -fixed false -x 83 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[22\] -fixed false -x 857 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_27\[9\] -fixed false -x 279 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[21\] -fixed false -x 456 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[16\] -fixed false -x 385 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.i0li0 -fixed false -x 44 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[4\] -fixed false -x 916 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[2\] -fixed false -x 261 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[0\] -fixed false -x 325 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[2\] -fixed false -x 337 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[9\] -fixed false -x 328 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z\[0\] -fixed false -x 354 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25\[6\] -fixed false -x 263 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[14\] -fixed false -x 83 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_516 -fixed false -x 589 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[7\] -fixed false -x 706 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[12\] -fixed false -x 726 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ooO01 -fixed false -x 372 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_1\[3\] -fixed false -x 712 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_9 -fixed false -x 422 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[5\] -fixed false -x 212 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[2\] -fixed false -x 456 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_1 -fixed false -x 513 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[25\] -fixed false -x 861 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_999 -fixed false -x 661 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[31\] -fixed false -x 739 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[8\] -fixed false -x 416 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[10\] -fixed false -x 837 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_2_0 -fixed false -x 638 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[17\] -fixed false -x 729 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_873 -fixed false -x 772 -y 186
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_3 -fixed false -x 69 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1\[4\] -fixed false -x 143 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2130_RNIJVARA -fixed false -x 650 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_0_0\[0\] -fixed false -x 752 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_41 -fixed false -x 652 -y 186
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/REN_d1_RNI2T40D -fixed false -x 393 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[29\] -fixed false -x 629 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[25\] -fixed false -x 464 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_8 -fixed false -x 27 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/un1_iOI01_1_i -fixed false -x 315 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_4_1 -fixed false -x 647 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[7\] -fixed false -x 415 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[6\] -fixed false -x 914 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[17\] -fixed false -x 261 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[16\] -fixed false -x 821 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_olio1_1 -fixed false -x 51 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_0_i_m2\[0\] -fixed false -x 595 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[12\] -fixed false -x 861 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_I1Ii1 -fixed false -x 276 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel_4 -fixed false -x 694 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_278 -fixed false -x 638 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[5\] -fixed false -x 919 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[8\] -fixed false -x 291 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_18 -fixed false -x 820 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1 -fixed false -x 311 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_457 -fixed false -x 659 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[5\] -fixed false -x 281 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[6\] -fixed false -x 397 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[34\] -fixed false -x 480 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI9HB2R1\[10\] -fixed false -x 75 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1\[12\] -fixed false -x 755 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[11\] -fixed false -x 452 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[21\] -fixed false -x 963 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO -fixed false -x 867 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[31\] -fixed false -x 412 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[7\] -fixed false -x 605 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un22_next_quotient_0_a2_0 -fixed false -x 910 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[11\] -fixed false -x 515 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[10\] -fixed false -x 507 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[26\] -fixed false -x 120 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk1.i1Il1 -fixed false -x 500 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[4\] -fixed false -x 221 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[13\] -fixed false -x 699 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[27\] -fixed false -x 393 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un17_full_wr_NE_RNIC67MH_0 -fixed false -x 629 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1\[0\] -fixed false -x 280 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[2\] -fixed false -x 254 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[10\] -fixed false -x 730 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[21\] -fixed false -x 648 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[30\] -fixed false -x 832 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_4 -fixed false -x 150 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_RNIHPUQD -fixed false -x 507 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ioil1 -fixed false -x 483 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[3\] -fixed false -x 53 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[7\] -fixed false -x 849 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[1\] -fixed false -x 256 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[18\] -fixed false -x 421 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un135_I1Oi1_1 -fixed false -x 63 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[10\] -fixed false -x 691 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux_1_1 -fixed false -x 734 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex\[1\] -fixed false -x 770 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[26\] -fixed false -x 127 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid32 -fixed false -x 855 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[6\] -fixed false -x 186 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[14\] -fixed false -x 556 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[26\] -fixed false -x 942 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[3\] -fixed false -x 794 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[58\] -fixed false -x 835 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_o2_0 -fixed false -x 86 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[26\] -fixed false -x 873 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[6\] -fixed false -x 135 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_1_sqmuxa_1 -fixed false -x 564 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[6\] -fixed false -x 208 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1\[13\] -fixed false -x 160 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_5 -fixed false -x 75 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[14\] -fixed false -x 32 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames\[2\] -fixed false -x 523 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[0\] -fixed false -x 116 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[5\] -fixed false -x 219 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI111 -fixed false -x 180 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI116 -fixed false -x 318 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7\[1\] -fixed false -x 180 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[31\] -fixed false -x 889 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 364 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_860 -fixed false -x 626 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_0_0\[4\] -fixed false -x 844 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[20\] -fixed false -x 928 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[2\] -fixed false -x 657 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m20 -fixed false -x 43 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_iv\[1\] -fixed false -x 741 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_3_1 -fixed false -x 818 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[3\] -fixed false -x 211 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[1\] -fixed false -x 292 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1 -fixed false -x 87 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[3\] -fixed false -x 160 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[26\] -fixed false -x 775 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1046 -fixed false -x 804 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[9\] -fixed false -x 609 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[26\] -fixed false -x 597 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[3\] -fixed false -x 728 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[31\] -fixed false -x 477 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[12\] -fixed false -x 775 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[12\] -fixed false -x 456 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig\[16\] -fixed false -x 677 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[17\] -fixed false -x 754 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OOiI1 -fixed false -x 380 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[5\] -fixed false -x 270 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNITTL4E\[4\] -fixed false -x 517 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oi1I1 -fixed false -x 455 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto2 -fixed false -x 822 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[22\] -fixed false -x 962 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[13\] -fixed false -x 43 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[6\] -fixed false -x 565 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count\[1\] -fixed false -x 784 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[4\] -fixed false -x 698 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_1 -fixed false -x 180 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[20\] -fixed false -x 224 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[20\] -fixed false -x 379 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[39\] -fixed false -x 385 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[2\] -fixed false -x 428 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[0\].BUFD_BLK -fixed false -x 485 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_7 -fixed false -x 192 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[31\] -fixed false -x 905 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_penable_0_a2 -fixed false -x 485 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[25\] -fixed false -x 922 -y 144
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[6\] -fixed false -x 39 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[25\] -fixed false -x 886 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[0\] -fixed false -x 156 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1\[0\] -fixed false -x 359 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[27\] -fixed false -x 849 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr\[0\] -fixed false -x 742 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[2\] -fixed false -x 399 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0\[4\] -fixed false -x 98 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1\[13\] -fixed false -x 146 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[11\] -fixed false -x 540 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/gen_bit_reset.state_val\[0\] -fixed false -x 758 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[0\] -fixed false -x 364 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_3_0 -fixed false -x 701 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[9\] -fixed false -x 640 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[1\] -fixed false -x 25 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_0\[4\] -fixed false -x 769 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[46\] -fixed false -x 962 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[28\] -fixed false -x 397 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[28\] -fixed false -x 871 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[8\] -fixed false -x 81 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_1 -fixed false -x 800 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[19\] -fixed false -x 325 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[10\] -fixed false -x 832 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r -fixed false -x 400 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[29\] -fixed false -x 430 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type\[10\] -fixed false -x 790 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[5\] -fixed false -x 766 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_0_RNO -fixed false -x 55 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_1 -fixed false -x 140 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z\[2\] -fixed false -x 344 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0_RNIAAFA7 -fixed false -x 795 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[1\] -fixed false -x 565 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[1\] -fixed false -x 388 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[2\] -fixed false -x 424 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[10\] -fixed false -x 410 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0ll1 -fixed false -x 211 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[14\] -fixed false -x 498 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[3\] -fixed false -x 255 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[1\] -fixed false -x 285 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_15 -fixed false -x 77 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[16\] -fixed false -x 478 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_496 -fixed false -x 640 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[34\] -fixed false -x 469 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[7\] -fixed false -x 303 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[5\] -fixed false -x 38 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[7\] -fixed false -x 463 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_de -fixed false -x 741 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[6\] -fixed false -x 731 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[6\] -fixed false -x 521 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[23\] -fixed false -x 875 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_gen_apb_byte_shim.apb_st_0_o4_0_0 -fixed false -x 602 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNI4I7JA\[2\] -fixed false -x 763 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[11\] -fixed false -x 363 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[5\] -fixed false -x 139 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first_RNO -fixed false -x 507 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0\[30\] -fixed false -x 132 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO_1 -fixed false -x 855 -y 174
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt\[1\] -fixed false -x 462 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[16\] -fixed false -x 219 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[9\] -fixed false -x 512 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4\[3\] -fixed false -x 56 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1_tz\[0\] -fixed false -x 155 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2\[1\] -fixed false -x 837 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[21\] -fixed false -x 883 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1\[3\] -fixed false -x 293 -y 199
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_code_upd_3_iv_i -fixed false -x 4 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIRI68E\[19\] -fixed false -x 674 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_9 -fixed false -x 229 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_o2 -fixed false -x 50 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[27\] -fixed false -x 862 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_700 -fixed false -x 731 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[9\] -fixed false -x 357 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_m9_1 -fixed false -x 54 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[21\] -fixed false -x 184 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[5\] -fixed false -x 182 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[5\] -fixed false -x 505 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un33_i_a2_2\[1\] -fixed false -x 255 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[5\] -fixed false -x 80 -y 223
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa -fixed false -x 557 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO\[2\] -fixed false -x 612 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un13_lolIo -fixed false -x 13 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[3\] -fixed false -x 153 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff15_0_a3_0 -fixed false -x 781 -y 114
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc2 -fixed false -x 45 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo -fixed false -x 128 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4\[13\] -fixed false -x 138 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m23 -fixed false -x 66 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[18\] -fixed false -x 443 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0_a3_0\[7\] -fixed false -x 318 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[2\] -fixed false -x 530 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNILUBS7\[1\] -fixed false -x 912 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[4\] -fixed false -x 422 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNIHKB4E -fixed false -x 391 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid48_RNI3O089 -fixed false -x 738 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11\[6\] -fixed false -x 264 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[28\] -fixed false -x 843 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[8\] -fixed false -x 420 -y 196
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_valid_RNIBGDFB -fixed false -x 389 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[28\] -fixed false -x 811 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[10\] -fixed false -x 321 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[7\] -fixed false -x 497 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0_1_0\[0\] -fixed false -x 217 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[9\] -fixed false -x 174 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1150 -fixed false -x 637 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[7\] -fixed false -x 278 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O0115 -fixed false -x 484 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[27\] -fixed false -x 783 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[14\] -fixed false -x 793 -y 115
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q\[3\] -fixed false -x 531 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_2\[7\] -fixed false -x 124 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[12\] -fixed false -x 387 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_3 -fixed false -x 434 -y 9
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[55\] -fixed false -x 562 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI75FRQ1_0\[5\] -fixed false -x 825 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[2\] -fixed false -x 267 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[10\] -fixed false -x 669 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[1\] -fixed false -x 261 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01 -fixed false -x 383 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[14\] -fixed false -x 854 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[6\] -fixed false -x 78 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29 -fixed false -x 604 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9_7 -fixed false -x 61 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[10\] -fixed false -x 469 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m18 -fixed false -x 50 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[7\] -fixed false -x 365 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[13\] -fixed false -x 448 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[23\] -fixed false -x 835 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/IilI1 -fixed false -x 220 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0\[4\] -fixed false -x 105 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[4\] -fixed false -x 94 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_945 -fixed false -x 676 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[21\] -fixed false -x 916 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un5_I0i01_0_a3_0_RNIOMILG -fixed false -x 86 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o12_1 -fixed false -x 689 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0\[6\] -fixed false -x 123 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[3\] -fixed false -x 366 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_870 -fixed false -x 721 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_30 -fixed false -x 698 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2_6 -fixed false -x 404 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[31\] -fixed false -x 905 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[14\] -fixed false -x 235 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[4\] -fixed false -x 132 -y 187
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[7\] -fixed false -x 483 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[6\] -fixed false -x 270 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIC698E\[23\] -fixed false -x 682 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0\[1\] -fixed false -x 723 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[23\] -fixed false -x 903 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un171_I1Oi1 -fixed false -x 50 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2123_i -fixed false -x 865 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_325 -fixed false -x 721 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[8\] -fixed false -x 754 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_619 -fixed false -x 638 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_540 -fixed false -x 709 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[11\] -fixed false -x 803 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[11\] -fixed false -x 686 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[15\] -fixed false -x 924 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_46 -fixed false -x 651 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_1 -fixed false -x 532 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[30\] -fixed false -x 866 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[23\] -fixed false -x 651 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[4\] -fixed false -x 278 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[25\] -fixed false -x 890 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_m2_2 -fixed false -x 12 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/liI01 -fixed false -x 37 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI4KONQ4 -fixed false -x 13 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_966 -fixed false -x 640 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[6\] -fixed false -x 399 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].un1_lIII110 -fixed false -x 475 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[9\] -fixed false -x 716 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1\[4\] -fixed false -x 205 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_i_o2 -fixed false -x 687 -y 114
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg\[1\] -fixed false -x 47 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a3 -fixed false -x 353 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[6\] -fixed false -x 155 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[30\] -fixed false -x 599 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[1\] -fixed false -x 683 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo_RNO -fixed false -x 21 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[28\] -fixed false -x 450 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[21\] -fixed false -x 884 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[47\] -fixed false -x 123 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.lliOo\[1\] -fixed false -x 353 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_0_0 -fixed false -x 665 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[20\] -fixed false -x 766 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[0\] -fixed false -x 325 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[10\] -fixed false -x 133 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[11\] -fixed false -x 869 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4954_0_0 -fixed false -x 655 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo -fixed false -x 40 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[19\] -fixed false -x 94 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[3\] -fixed false -x 436 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[3\] -fixed false -x 33 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[34\] -fixed false -x 632 -y 123
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state6 -fixed false -x 517 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv\[2\] -fixed false -x 739 -y 135
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cdr_ready_reg_1_0 -fixed false -x 43 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4_1_0\[0\] -fixed false -x 66 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[11\] -fixed false -x 349 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[4\] -fixed false -x 634 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m11 -fixed false -x 55 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_state\[1\]\[2\] -fixed false -x 786 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0\[20\] -fixed false -x 722 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_58\[11\] -fixed false -x 326 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[11\] -fixed false -x 763 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[11\] -fixed false -x 462 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[5\] -fixed false -x 406 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[25\] -fixed false -x 906 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0 -fixed false -x 158 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi14 -fixed false -x 80 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[9\] -fixed false -x 191 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1_5 -fixed false -x 310 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[50\] -fixed false -x 569 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_8_170_a2 -fixed false -x 435 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_12_134_a2 -fixed false -x 431 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a2_a0 -fixed false -x 771 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[0\] -fixed false -x 219 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[0\] -fixed false -x 334 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooi11 -fixed false -x 309 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[2\] -fixed false -x 768 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1 -fixed false -x 136 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[10\] -fixed false -x 726 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[24\] -fixed false -x 589 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[10\] -fixed false -x 334 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[12\] -fixed false -x 61 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1057 -fixed false -x 673 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[29\] -fixed false -x 164 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1 -fixed false -x 694 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[9\] -fixed false -x 344 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[10\] -fixed false -x 539 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[5\] -fixed false -x 205 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[29\] -fixed false -x 916 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[25\] -fixed false -x 785 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[9\] -fixed false -x 427 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un2_IIil1\[0\] -fixed false -x 418 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[30\] -fixed false -x 546 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[29\] -fixed false -x 589 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[3\] -fixed false -x 181 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[27\] -fixed false -x 227 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27\[1\] -fixed false -x 244 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[21\] -fixed false -x 373 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[15\] -fixed false -x 78 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1_0 -fixed false -x 902 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO0015 -fixed false -x 230 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO_0 -fixed false -x 884 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[21\] -fixed false -x 843 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[31\] -fixed false -x 147 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0\[8\] -fixed false -x 91 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_RNO -fixed false -x 834 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[16\].BUFD_BLK -fixed false -x 507 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[12\] -fixed false -x 319 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_1_0 -fixed false -x 522 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1029 -fixed false -x 654 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO_0\[0\] -fixed false -x 680 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[24\] -fixed false -x 227 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a1 -fixed false -x 823 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo53 -fixed false -x 41 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z\[6\] -fixed false -x 396 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m56 -fixed false -x 61 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_e -fixed false -x 643 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2_1\[28\] -fixed false -x 212 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ol111 -fixed false -x 113 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc3 -fixed false -x 113 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/IilI1 -fixed false -x 299 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO\[3\] -fixed false -x 267 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[8\] -fixed false -x 750 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[10\] -fixed false -x 372 -y 241
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[2\] -fixed false -x 504 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[0\] -fixed false -x 496 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l0Il1 -fixed false -x 461 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[29\] -fixed false -x 427 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_4 -fixed false -x 220 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_N_3L4 -fixed false -x 675 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[3\] -fixed false -x 835 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[17\] -fixed false -x 896 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[6\] -fixed false -x 441 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_0_0 -fixed false -x 100 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[3\] -fixed false -x 496 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6\[1\] -fixed false -x 653 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[16\] -fixed false -x 238 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1085 -fixed false -x 614 -y 132
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[7\] -fixed false -x 488 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[4\] -fixed false -x 868 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[8\] -fixed false -x 180 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_0_RNO_1 -fixed false -x 810 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[31\] -fixed false -x 843 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2\[5\] -fixed false -x 500 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[23\] -fixed false -x 448 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[24\] -fixed false -x 734 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[4\] -fixed false -x 245 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m7 -fixed false -x 53 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01\[3\] -fixed false -x 202 -y 190
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[18\] -fixed false -x 403 -y 241
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[3\] -fixed false -x 400 -y 256
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[29\] -fixed false -x 414 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/gen_bit_reset.state_val\[0\] -fixed false -x 647 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[4\] -fixed false -x 864 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un6_o1ll1 -fixed false -x 456 -y 186
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/load_lane -fixed false -x 8 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]2_0 -fixed false -x 866 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO_2 -fixed false -x 657 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[6\] -fixed false -x 133 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[16\] -fixed false -x 461 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un10_ioOOo -fixed false -x 55 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/dut_tms_int -fixed false -x 480 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_0_1 -fixed false -x 901 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[2\] -fixed false -x 882 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/olI01 -fixed false -x 224 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv\[1\] -fixed false -x 653 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[2\] -fixed false -x 369 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[12\] -fixed false -x 526 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[0\] -fixed false -x 364 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[5\] -fixed false -x 837 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[2\] -fixed false -x 165 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q0_1 -fixed false -x 742 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[1\] -fixed false -x 207 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[0\] -fixed false -x 538 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[22\] -fixed false -x 282 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[8\] -fixed false -x 183 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_953 -fixed false -x 661 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1_6 -fixed false -x 309 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[3\] -fixed false -x 258 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[34\] -fixed false -x 647 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[15\] -fixed false -x 149 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_lsu_op_ex7 -fixed false -x 811 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[5\] -fixed false -x 184 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28\[0\] -fixed false -x 243 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_2 -fixed false -x 433 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[29\] -fixed false -x 739 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[22\] -fixed false -x 718 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1283 -fixed false -x 783 -y 186
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO\[0\] -fixed false -x 491 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[11\] -fixed false -x 928 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_1\[2\] -fixed false -x 796 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[1\] -fixed false -x 224 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[0\] -fixed false -x 60 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[22\] -fixed false -x 961 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0\[6\] -fixed false -x 652 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[3\] -fixed false -x 764 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[4\] -fixed false -x 99 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[7\] -fixed false -x 208 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[11\] -fixed false -x 838 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0_1_0\[0\] -fixed false -x 313 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un215_lIlo1 -fixed false -x 291 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[7\] -fixed false -x 408 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[13\] -fixed false -x 473 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[6\] -fixed false -x 169 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[0\] -fixed false -x 154 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_27 -fixed false -x 771 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iO1 -fixed false -x 131 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[8\] -fixed false -x 373 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[18\] -fixed false -x 446 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_data_gen_buff_loop\[0\].buff_data_0_0_RNO -fixed false -x 783 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4\[3\] -fixed false -x 152 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_i_a2_2\[1\] -fixed false -x 618 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[31\] -fixed false -x 856 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_234 -fixed false -x 687 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_976 -fixed false -x 639 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO_0\[0\] -fixed false -x 616 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[17\] -fixed false -x 439 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[28\] -fixed false -x 453 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i -fixed false -x 746 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[6\] -fixed false -x 426 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[14\] -fixed false -x 769 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_1\[0\] -fixed false -x 50 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[11\] -fixed false -x 846 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_866 -fixed false -x 617 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_1 -fixed false -x 483 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0 -fixed false -x 636 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[30\] -fixed false -x 664 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_coarse_sel_0_sqmuxa -fixed false -x 61 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m19 -fixed false -x 51 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_3 -fixed false -x 234 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[18\] -fixed false -x 865 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[20\] -fixed false -x 704 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[11\] -fixed false -x 411 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV -fixed false -x 530 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_2\[24\] -fixed false -x 379 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[37\] -fixed false -x 923 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_rd_ptr\[0\] -fixed false -x 795 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[25\] -fixed false -x 864 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[23\] -fixed false -x 684 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[27\] -fixed false -x 925 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0 -fixed false -x 190 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1iO1_RNO -fixed false -x 217 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_m11_0_N_4L5 -fixed false -x 803 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[6\] -fixed false -x 370 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[31\] -fixed false -x 474 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[6\] -fixed false -x 566 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un12_l1I01_4 -fixed false -x 249 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_483 -fixed false -x 686 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[39\] -fixed false -x 139 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[2\] -fixed false -x 131 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[8\] -fixed false -x 344 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_1 -fixed false -x 119 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/IilI1 -fixed false -x 345 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[19\] -fixed false -x 252 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[1\] -fixed false -x 336 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_RNO\[9\] -fixed false -x 79 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[8\] -fixed false -x 469 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_hit/gen_bit_reset.state_val_12_iv_i\[0\] -fixed false -x 827 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[31\] -fixed false -x 186 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[0\] -fixed false -x 75 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1_2 -fixed false -x 79 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex\[1\] -fixed false -x 725 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[13\] -fixed false -x 72 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[9\] -fixed false -x 323 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[16\] -fixed false -x 342 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOiOo_0 -fixed false -x 236 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[15\] -fixed false -x 863 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[7\] -fixed false -x 327 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_121 -fixed false -x 689 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[4\] -fixed false -x 149 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIR4CS7\[7\] -fixed false -x 913 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[14\] -fixed false -x 336 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[0\] -fixed false -x 456 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_265 -fixed false -x 770 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff_RNO -fixed false -x 721 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[4\] -fixed false -x 470 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2\[3\] -fixed false -x 214 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[18\] -fixed false -x 792 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1197 -fixed false -x 613 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/un1_iOI01_1_i_0 -fixed false -x 188 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i01i1_4_0_o2 -fixed false -x 204 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m1 -fixed false -x 65 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[4\] -fixed false -x 84 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val\[1\] -fixed false -x 768 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1117 -fixed false -x 663 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[4\] -fixed false -x 171 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO0o1 -fixed false -x 89 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[20\] -fixed false -x 806 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1 -fixed false -x 473 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[35\] -fixed false -x 918 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[11\] -fixed false -x 43 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[18\] -fixed false -x 966 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[26\] -fixed false -x 665 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/read_subsys_hart_soft_reg -fixed false -x 758 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[19\] -fixed false -x 73 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[11\] -fixed false -x 673 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_322 -fixed false -x 628 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILDFFD\[4\] -fixed false -x 670 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILFVQ8\[31\] -fixed false -x 671 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0\[2\] -fixed false -x 336 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1ce_0\[0\] -fixed false -x 128 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/IilI1 -fixed false -x 316 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_o4\[0\] -fixed false -x 664 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2_1 -fixed false -x 52 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m7 -fixed false -x 36 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_0\[2\] -fixed false -x 510 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[4\] -fixed false -x 166 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m48_i_o3 -fixed false -x 43 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[0\] -fixed false -x 195 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op\[1\] -fixed false -x 692 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[3\] -fixed false -x 410 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[0\] -fixed false -x 83 -y 223
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo_4_0_5 -fixed false -x 108 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un5_div_result_3 -fixed false -x 870 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/IilI1 -fixed false -x 251 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o\[1\] -fixed false -x 293 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[23\] -fixed false -x 789 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[0\] -fixed false -x 84 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[5\] -fixed false -x 426 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[13\] -fixed false -x 747 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[5\] -fixed false -x 901 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[61\] -fixed false -x 594 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[5\] -fixed false -x 327 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0 -fixed false -x 85 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[16\] -fixed false -x 332 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_23_RNIDI2D8 -fixed false -x 838 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[37\] -fixed false -x 355 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4927_RNI1GK2F -fixed false -x 696 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_RNIHP2B7 -fixed false -x 49 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i\[0\] -fixed false -x 52 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[17\] -fixed false -x 856 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un5_iili1 -fixed false -x 199 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[12\] -fixed false -x 74 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[7\] -fixed false -x 89 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2\[2\] -fixed false -x 735 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[5\] -fixed false -x 402 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[12\] -fixed false -x 62 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2 -fixed false -x 497 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/ilI01 -fixed false -x 223 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[13\] -fixed false -x 834 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_3_RNO -fixed false -x 371 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_0 -fixed false -x 98 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[22\] -fixed false -x 827 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg_2_0 -fixed false -x 864 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_296 -fixed false -x 662 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_oen_0_sqmuxa -fixed false -x 506 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[22\] -fixed false -x 625 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[17\] -fixed false -x 458 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIi01\[3\] -fixed false -x 107 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_o3\[3\] -fixed false -x 213 -y 204
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3\[2\] -fixed false -x 567 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_924 -fixed false -x 616 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un85_OOOI1\[12\] -fixed false -x 265 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_retr_2_RNIR3BFM -fixed false -x 771 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[52\] -fixed false -x 555 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[10\] -fixed false -x 572 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.un4_ex_retr_pipe_sw_csr_rd_op_retr -fixed false -x 725 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[5\] -fixed false -x 534 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_req_valid_int35_1 -fixed false -x 818 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[15\] -fixed false -x 307 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[8\] -fixed false -x 46 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un12_I1ii1_i_o3 -fixed false -x 150 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[8\] -fixed false -x 479 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_11 -fixed false -x 95 -y 225
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[8\] -fixed false -x 854 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01\[1\] -fixed false -x 162 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[1\] -fixed false -x 136 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[6\] -fixed false -x 304 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[25\] -fixed false -x 867 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[2\] -fixed false -x 299 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[6\] -fixed false -x 215 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[26\] -fixed false -x 394 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[31\] -fixed false -x 871 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i10Oo -fixed false -x 131 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[18\] -fixed false -x 642 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[0\] -fixed false -x 241 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m8 -fixed false -x 41 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_1\[1\] -fixed false -x 121 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[17\] -fixed false -x 739 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[4\] -fixed false -x 460 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[9\] -fixed false -x 313 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_i_1_m2\[0\] -fixed false -x 694 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[14\] -fixed false -x 714 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/IilI1 -fixed false -x 339 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIDKDU8\[10\] -fixed false -x 167 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[13\] -fixed false -x 531 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[22\] -fixed false -x 438 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[3\] -fixed false -x 410 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_OOii1 -fixed false -x 147 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[10\] -fixed false -x 17 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_11 -fixed false -x 732 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[10\] -fixed false -x 500 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[3\] -fixed false -x 765 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011_RNO -fixed false -x 268 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[2\] -fixed false -x 136 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[9\] -fixed false -x 150 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[6\] -fixed false -x 838 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[20\] -fixed false -x 801 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_1 -fixed false -x 60 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[6\] -fixed false -x 289 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_7 -fixed false -x 734 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_59 -fixed false -x 618 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo\[5\] -fixed false -x 344 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_490 -fixed false -x 674 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[12\] -fixed false -x 851 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[11\] -fixed false -x 407 -y 181
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt_RNO\[1\] -fixed false -x 15 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_555 -fixed false -x 710 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[17\] -fixed false -x 457 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[43\] -fixed false -x 351 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[5\] -fixed false -x 336 -y 154
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_0_sqmuxa -fixed false -x 519 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[2\] -fixed false -x 845 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un48_Oo1Io -fixed false -x 398 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q\[4\] -fixed false -x 496 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNIR3S4\[1\] -fixed false -x 168 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[0\] -fixed false -x 194 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1159 -fixed false -x 628 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n2 -fixed false -x 179 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[8\] -fixed false -x 153 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_retr -fixed false -x 767 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_lioIo264_0_1 -fixed false -x 39 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_1\[3\] -fixed false -x 515 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[15\] -fixed false -x 751 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[1\] -fixed false -x 292 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[6\] -fixed false -x 391 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[4\] -fixed false -x 249 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[15\] -fixed false -x 824 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[1\] -fixed false -x 377 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[10\] -fixed false -x 741 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un81_i0lo1\[3\] -fixed false -x 267 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_ioOOo -fixed false -x 57 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_7 -fixed false -x 487 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z\[1\] -fixed false -x 229 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_876 -fixed false -x 685 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[26\] -fixed false -x 784 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_7 -fixed false -x 86 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0\[9\] -fixed false -x 89 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO\[20\] -fixed false -x 941 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[31\] -fixed false -x 673 -y 123
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_27\[2\] -fixed false -x 498 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_789 -fixed false -x 698 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[2\] -fixed false -x 103 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[17\] -fixed false -x 461 -y 214
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_parity_calc -fixed false -x 478 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1125 -fixed false -x 602 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[11\] -fixed false -x 480 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[2\] -fixed false -x 692 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[7\] -fixed false -x 554 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[4\] -fixed false -x 122 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_o1Ii1\[0\] -fixed false -x 281 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[5\] -fixed false -x 62 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[8\] -fixed false -x 61 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[29\] -fixed false -x 903 -y 132
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_3 -fixed false -x 492 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_17 -fixed false -x 404 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[5\] -fixed false -x 201 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNI9AKVB3 -fixed false -x 52 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m25 -fixed false -x 614 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_1\[0\] -fixed false -x 685 -y 138
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m8 -fixed false -x 477 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_0\[1\] -fixed false -x 690 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_0\[13\] -fixed false -x 749 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/un1_iOI01_1_i_0 -fixed false -x 316 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[6\] -fixed false -x 300 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[0\] -fixed false -x 364 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[11\] -fixed false -x 210 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[5\] -fixed false -x 190 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1101 -fixed false -x 725 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[5\] -fixed false -x 567 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2\[2\] -fixed false -x 279 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_write_RNIDQ283 -fixed false -x 738 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[35\] -fixed false -x 316 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_2\[6\] -fixed false -x 951 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/un1_Ioli0_1_0 -fixed false -x 340 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo\[9\] -fixed false -x 357 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[4\] -fixed false -x 686 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto8_1 -fixed false -x 137 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[9\] -fixed false -x 884 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOOIo\[0\] -fixed false -x 131 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_275 -fixed false -x 698 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_a3_2\[3\] -fixed false -x 196 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[13\] -fixed false -x 499 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[12\] -fixed false -x 502 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGP7L31 -fixed false -x 722 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[11\] -fixed false -x 364 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa -fixed false -x 664 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un17_Oi1O1\[23\] -fixed false -x 459 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0\[9\] -fixed false -x 63 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[25\] -fixed false -x 736 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_d_1_sqmuxa -fixed false -x 594 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_ptr\[0\] -fixed false -x 629 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oioo1 -fixed false -x 85 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_25 -fixed false -x 615 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[13\] -fixed false -x 679 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_204 -fixed false -x 650 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_s_5_RNO -fixed false -x 535 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01\[0\] -fixed false -x 195 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[0\] -fixed false -x 386 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1222 -fixed false -x 685 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4\[5\] -fixed false -x 415 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_ioOOo -fixed false -x 50 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5\[1\] -fixed false -x 500 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_halt_req -fixed false -x 773 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[3\] -fixed false -x 161 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr\[1\] -fixed false -x 765 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[29\] -fixed false -x 874 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[6\] -fixed false -x 346 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_pauselow8 -fixed false -x 555 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[6\] -fixed false -x 905 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22\[3\] -fixed false -x 330 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[2\] -fixed false -x 544 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[3\] -fixed false -x 368 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[16\] -fixed false -x 761 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un189_I1Oi1_1 -fixed false -x 46 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo\[0\] -fixed false -x 440 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[32\] -fixed false -x 903 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[28\] -fixed false -x 794 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[25\] -fixed false -x 854 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1147 -fixed false -x 684 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[13\] -fixed false -x 263 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[12\] -fixed false -x 159 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iiOl1 -fixed false -x 528 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[58\] -fixed false -x 930 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[1\] -fixed false -x 689 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_2\[2\] -fixed false -x 793 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[3\] -fixed false -x 291 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[2\] -fixed false -x 965 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1101 -fixed false -x 121 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[7\] -fixed false -x 331 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[9\] -fixed false -x 374 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[23\] -fixed false -x 880 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1\[25\] -fixed false -x 159 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[7\] -fixed false -x 784 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1162 -fixed false -x 636 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1\[35\] -fixed false -x 479 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r\[2\] -fixed false -x 387 -y 229
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_a4_0_a2\[5\] -fixed false -x 623 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO\[4\] -fixed false -x 565 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oiIo1 -fixed false -x 322 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[4\].BUFD_BLK -fixed false -x 484 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lI0i1 -fixed false -x 110 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[7\] -fixed false -x 511 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[8\] -fixed false -x 478 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIOl1 -fixed false -x 448 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[10\] -fixed false -x 189 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[29\] -fixed false -x 598 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_4_4 -fixed false -x 530 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i_o2_RNII5F4H -fixed false -x 690 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_0_RNO\[1\] -fixed false -x 471 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[17\] -fixed false -x 852 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/IilI1 -fixed false -x 312 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[8\] -fixed false -x 182 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[1\] -fixed false -x 898 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[24\] -fixed false -x 289 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_N_5L8 -fixed false -x 707 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[26\] -fixed false -x 885 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand0_mux_sel_ex\[0\] -fixed false -x 771 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[0\] -fixed false -x 889 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[10\] -fixed false -x 608 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[9\] -fixed false -x 345 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlOI1 -fixed false -x 360 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[1\] -fixed false -x 109 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg_2_0_o2 -fixed false -x 868 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI68VTE -fixed false -x 762 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_OlOI1_1 -fixed false -x 204 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[4\] -fixed false -x 306 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[1\] -fixed false -x 340 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_update_result_reg -fixed false -x 852 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[13\] -fixed false -x 291 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[7\] -fixed false -x 486 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_d_1_sqmuxa_1 -fixed false -x 508 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un16_gpr_rd_rs1_completing_ex_1 -fixed false -x 819 -y 138
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr\[0\] -fixed false -x 444 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[22\] -fixed false -x 662 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0OIo_0_a3_0_1 -fixed false -x 117 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01_1 -fixed false -x 239 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[42\] -fixed false -x 921 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[4\] -fixed false -x 376 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[1\] -fixed false -x 500 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data\[3\] -fixed false -x 695 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_942 -fixed false -x 625 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[4\] -fixed false -x 121 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[21\] -fixed false -x 434 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[1\] -fixed false -x 352 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[9\] -fixed false -x 205 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[6\] -fixed false -x 637 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_489 -fixed false -x 690 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un99_I1Oi1 -fixed false -x 13 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[8\] -fixed false -x 468 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[26\] -fixed false -x 658 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11\[0\] -fixed false -x 280 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[11\] -fixed false -x 374 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_524 -fixed false -x 696 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[5\] -fixed false -x 704 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_midbit -fixed false -x 534 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z\[2\] -fixed false -x 290 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[29\] -fixed false -x 463 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_85_u_2\[9\] -fixed false -x 902 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[16\] -fixed false -x 817 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[7\] -fixed false -x 672 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[2\] -fixed false -x 596 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[2\] -fixed false -x 232 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[10\] -fixed false -x 555 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0\[0\] -fixed false -x 133 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[12\] -fixed false -x 31 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[7\] -fixed false -x 516 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2133 -fixed false -x 674 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m5 -fixed false -x 88 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_981 -fixed false -x 768 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_2_RNIR680A -fixed false -x 808 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[9\] -fixed false -x 510 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo263_2_0 -fixed false -x 51 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_a3 -fixed false -x 711 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[9\] -fixed false -x 724 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_1\[1\] -fixed false -x 746 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[17\] -fixed false -x 831 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_1 -fixed false -x 816 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[3\] -fixed false -x 291 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_19 -fixed false -x 689 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000112 -fixed false -x 69 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[9\] -fixed false -x 731 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[29\] -fixed false -x 814 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35\[7\] -fixed false -x 265 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[5\] -fixed false -x 78 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lli11 -fixed false -x 395 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[5\] -fixed false -x 453 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[31\] -fixed false -x 820 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[10\] -fixed false -x 419 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0\[2\] -fixed false -x 757 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_2 -fixed false -x 531 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[4\] -fixed false -x 311 -y 205
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[3\] -fixed false -x 61 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[6\] -fixed false -x 271 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_1_0 -fixed false -x 829 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[3\] -fixed false -x 531 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i_RNIAFAKF13 -fixed false -x 794 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_4 -fixed false -x 701 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[3\] -fixed false -x 446 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_0\[1\] -fixed false -x 783 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDMI_ne_0_3 -fixed false -x 556 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[3\] -fixed false -x 116 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_ready -fixed false -x 799 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[6\] -fixed false -x 362 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[6\] -fixed false -x 163 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[5\] -fixed false -x 512 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1\[13\] -fixed false -x 482 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[8\] -fixed false -x 818 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[4\] -fixed false -x 207 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1\[8\] -fixed false -x 131 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_2 -fixed false -x 518 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[10\] -fixed false -x 106 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.ol1Io -fixed false -x 44 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[8\] -fixed false -x 344 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[15\] -fixed false -x 328 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_0_0_a2\[15\] -fixed false -x 135 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_1 -fixed false -x 96 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[3\] -fixed false -x 845 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3\[3\] -fixed false -x 151 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_a2_3 -fixed false -x 80 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[29\] -fixed false -x 928 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[2\] -fixed false -x 369 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[15\] -fixed false -x 835 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[21\] -fixed false -x 659 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[25\] -fixed false -x 811 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[28\] -fixed false -x 702 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIND0GT\[5\] -fixed false -x 98 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI8EUT5 -fixed false -x 289 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[4\] -fixed false -x 26 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_0_RNO_1 -fixed false -x 110 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[1\] -fixed false -x 770 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[12\] -fixed false -x 132 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[2\] -fixed false -x 409 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[2\] -fixed false -x 487 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_2\[24\] -fixed false -x 158 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0\[7\] -fixed false -x 124 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[12\] -fixed false -x 31 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01\[0\] -fixed false -x 214 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[17\] -fixed false -x 455 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[13\] -fixed false -x 910 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[7\] -fixed false -x 409 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[15\] -fixed false -x 725 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[14\] -fixed false -x 793 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[5\] -fixed false -x 201 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[0\] -fixed false -x 852 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[9\] -fixed false -x 72 -y 166
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO\[6\] -fixed false -x 76 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_0 -fixed false -x 53 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[38\] -fixed false -x 917 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[4\] -fixed false -x 58 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[6\] -fixed false -x 512 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en\[3\] -fixed false -x 800 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1164 -fixed false -x 770 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[21\] -fixed false -x 758 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNIADN2U -fixed false -x 50 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1\[1\] -fixed false -x 96 -y 202
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte\[0\] -fixed false -x 475 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6 -fixed false -x 780 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[15\] -fixed false -x 808 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[4\] -fixed false -x 112 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[2\] -fixed false -x 398 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_RNO\[0\] -fixed false -x 785 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIGK7DS1 -fixed false -x 906 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[0\] -fixed false -x 266 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_29\[4\] -fixed false -x 249 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1\[5\] -fixed false -x 847 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo\[2\] -fixed false -x 248 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m300 -fixed false -x 285 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olOI1 -fixed false -x 245 -y 190
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[5\] -fixed false -x 450 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[3\] -fixed false -x 129 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[2\] -fixed false -x 307 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[13\] -fixed false -x 468 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[7\] -fixed false -x 211 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[24\] -fixed false -x 819 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIll1 -fixed false -x 521 -y 190
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[31\] -fixed false -x 408 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO_1 -fixed false -x 866 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[0\] -fixed false -x 182 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[0\] -fixed false -x 352 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[1\] -fixed false -x 400 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIBE984\[16\] -fixed false -x 908 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IoI11_Z -fixed false -x 355 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIlOo -fixed false -x 25 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_8_RNIOI22J -fixed false -x 627 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[6\] -fixed false -x 809 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata1_mcontrol_execute/gen_bit_reset.state_val\[0\] -fixed false -x 798 -y 184
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[6\] -fixed false -x 19 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[23\] -fixed false -x 791 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[9\] -fixed false -x 538 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[11\] -fixed false -x 326 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_6\[9\] -fixed false -x 290 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_1_tz\[0\] -fixed false -x 831 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_523 -fixed false -x 651 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_9\[10\] -fixed false -x 276 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001\[3\] -fixed false -x 88 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[1\] -fixed false -x 285 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I16 -fixed false -x 391 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[4\] -fixed false -x 649 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[29\] -fixed false -x 421 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oo101 -fixed false -x 136 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[16\] -fixed false -x 402 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[7\] -fixed false -x 206 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_138 -fixed false -x 614 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m5_1_0 -fixed false -x 26 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1_0\[5\] -fixed false -x 282 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[4\] -fixed false -x 412 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_a2_1 -fixed false -x 85 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[1\] -fixed false -x 494 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_0\[0\] -fixed false -x 621 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[6\] -fixed false -x 218 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I11Oo\[0\] -fixed false -x 100 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[11\] -fixed false -x 928 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[22\] -fixed false -x 144 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[5\] -fixed false -x 394 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2\[10\] -fixed false -x 121 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2\[1\] -fixed false -x 130 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[12\] -fixed false -x 790 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_2\[4\] -fixed false -x 755 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m78 -fixed false -x 184 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z\[0\] -fixed false -x 130 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[22\] -fixed false -x 922 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[11\] -fixed false -x 241 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNI63C8E\[30\] -fixed false -x 613 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_1\[1\] -fixed false -x 784 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_drop\[1\] -fixed false -x 822 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un37_ool01\[5\] -fixed false -x 183 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_valid -fixed false -x 744 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[27\] -fixed false -x 767 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[2\] -fixed false -x 894 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un3_loi01 -fixed false -x 41 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[30\] -fixed false -x 411 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[10\] -fixed false -x 252 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[11\] -fixed false -x 242 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_16_0_i -fixed false -x 218 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[8\] -fixed false -x 138 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[20\] -fixed false -x 939 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[1\] -fixed false -x 789 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[5\] -fixed false -x 298 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[39\] -fixed false -x 139 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_o4 -fixed false -x 765 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_accepted_1 -fixed false -x 757 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[3\] -fixed false -x 419 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[5\] -fixed false -x 150 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[9\] -fixed false -x 436 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o11Oo\[0\] -fixed false -x 171 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[11\] -fixed false -x 290 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[3\] -fixed false -x 181 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[9\] -fixed false -x 232 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[10\] -fixed false -x 202 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.debug_resume_req_3 -fixed false -x 793 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[27\] -fixed false -x 547 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[7\] -fixed false -x 401 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[21\] -fixed false -x 887 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[7\] -fixed false -x 178 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[19\] -fixed false -x 885 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ooo11 -fixed false -x 328 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[1\] -fixed false -x 422 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[28\] -fixed false -x 848 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[12\] -fixed false -x 845 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/illOo -fixed false -x 30 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[12\] -fixed false -x 880 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[5\] -fixed false -x 566 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[16\] -fixed false -x 927 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[3\] -fixed false -x 230 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[7\] -fixed false -x 284 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[5\] -fixed false -x 360 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_0\[2\] -fixed false -x 325 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[12\] -fixed false -x 388 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ol101 -fixed false -x 40 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q\[2\] -fixed false -x 493 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_695 -fixed false -x 724 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0\[5\] -fixed false -x 133 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[17\] -fixed false -x 526 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un52_OilI1_0_a2_0_a2 -fixed false -x 282 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[31\] -fixed false -x 384 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38\[4\] -fixed false -x 206 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[20\] -fixed false -x 177 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[1\] -fixed false -x 188 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[38\] -fixed false -x 356 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[23\] -fixed false -x 414 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[4\] -fixed false -x 126 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z\[0\] -fixed false -x 289 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO0110_1 -fixed false -x 344 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[12\] -fixed false -x 538 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[8\] -fixed false -x 953 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[1\] -fixed false -x 388 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[4\] -fixed false -x 639 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[4\] -fixed false -x 287 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[3\] -fixed false -x 408 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24\[5\] -fixed false -x 255 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a2_0_N_2L1 -fixed false -x 817 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[5\] -fixed false -x 518 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_q_1.CO0 -fixed false -x 593 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[29\] -fixed false -x 592 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2\[2\] -fixed false -x 443 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[14\] -fixed false -x 690 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_rd_ptr_0_0\[0\] -fixed false -x 819 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1 -fixed false -x 163 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O0Oo1 -fixed false -x 301 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[6\] -fixed false -x 64 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_29 -fixed false -x 841 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1086 -fixed false -x 781 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[19\] -fixed false -x 538 -y 172
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[3\] -fixed false -x 377 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[9\] -fixed false -x 97 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[6\] -fixed false -x 812 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[5\] -fixed false -x 217 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[14\] -fixed false -x 100 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[7\] -fixed false -x 411 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[18\] -fixed false -x 656 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_4_0 -fixed false -x 805 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[7\] -fixed false -x 238 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[10\] -fixed false -x 814 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[29\] -fixed false -x 697 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[1\] -fixed false -x 41 -y 214
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRCAP -fixed false -x 509 -y 90
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[1\] -fixed false -x 346 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[6\] -fixed false -x 682 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI9C984\[14\] -fixed false -x 929 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[30\] -fixed false -x 468 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_526 -fixed false -x 661 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[22\] -fixed false -x 553 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[27\] -fixed false -x 946 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_9 -fixed false -x 613 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[9\] -fixed false -x 39 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[13\] -fixed false -x 715 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oil11 -fixed false -x 443 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_0_2\[0\] -fixed false -x 64 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_29\[10\] -fixed false -x 242 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[3\] -fixed false -x 927 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch\[0\] -fixed false -x 672 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[16\] -fixed false -x 461 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[29\] -fixed false -x 456 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0 -fixed false -x 179 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[8\] -fixed false -x 429 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[11\] -fixed false -x 193 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/li0I1_RNO -fixed false -x 542 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6_f0\[0\] -fixed false -x 541 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_0_RNI90L7OT -fixed false -x 807 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_114 -fixed false -x 745 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0_1_0\[0\] -fixed false -x 220 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[7\] -fixed false -x 688 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_3 -fixed false -x 170 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIMOR5C\[20\] -fixed false -x 644 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[3\] -fixed false -x 163 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/m23_1 -fixed false -x 870 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[26\] -fixed false -x 873 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_666 -fixed false -x 589 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[4\] -fixed false -x 412 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[5\] -fixed false -x 708 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[24\] -fixed false -x 709 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[4\] -fixed false -x 767 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[29\] -fixed false -x 829 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[2\] -fixed false -x 878 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[33\] -fixed false -x 377 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[8\] -fixed false -x 45 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2\[16\] -fixed false -x 694 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[20\] -fixed false -x 755 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[0\] -fixed false -x 755 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[1\] -fixed false -x 762 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1\[4\] -fixed false -x 222 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[10\] -fixed false -x 552 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[0\] -fixed false -x 387 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[24\] -fixed false -x 425 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[6\] -fixed false -x 435 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[12\] -fixed false -x 129 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[17\] -fixed false -x 224 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[7\] -fixed false -x 183 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[4\] -fixed false -x 364 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lio01 -fixed false -x 96 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_ready_RNIOPSLH -fixed false -x 832 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[5\] -fixed false -x 522 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_2 -fixed false -x 601 -y 144
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[1\] -fixed false -x 45 -y 217
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_0 -fixed false -x 432 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[25\] -fixed false -x 901 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m47 -fixed false -x 74 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00Oo_0 -fixed false -x 160 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[2\] -fixed false -x 138 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/loo01 -fixed false -x 125 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io_3 -fixed false -x 397 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_5_0_a2\[15\] -fixed false -x 123 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_9 -fixed false -x 788 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[5\] -fixed false -x 183 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[6\] -fixed false -x 489 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11_1_0\[0\] -fixed false -x 195 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_0 -fixed false -x 494 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_93 -fixed false -x 614 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0\[9\] -fixed false -x 107 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write\[0\] -fixed false -x 642 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_169 -fixed false -x 614 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[11\] -fixed false -x 170 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43\[11\] -fixed false -x 229 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[15\] -fixed false -x 563 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNI58O7J\[2\] -fixed false -x 654 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[31\] -fixed false -x 633 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io -fixed false -x 398 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_349 -fixed false -x 660 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_112_i -fixed false -x 750 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[32\] -fixed false -x 342 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0\[26\] -fixed false -x 670 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[7\] -fixed false -x 589 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[11\] -fixed false -x 36 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[10\] -fixed false -x 776 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27\[0\] -fixed false -x 241 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.o0li0 -fixed false -x 361 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_1_RNID3EOO1\[2\] -fixed false -x 648 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/o1011 -fixed false -x 264 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_0_0 -fixed false -x 191 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[15\] -fixed false -x 439 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_3\[3\] -fixed false -x 530 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[1\] -fixed false -x 369 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[9\] -fixed false -x 546 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u_2\[2\] -fixed false -x 953 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[26\] -fixed false -x 452 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[11\] -fixed false -x 241 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex\[4\] -fixed false -x 699 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val_1\[0\] -fixed false -x 564 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[3\] -fixed false -x 876 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_8 -fixed false -x 686 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[7\] -fixed false -x 402 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[14\] -fixed false -x 213 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[18\] -fixed false -x 462 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv\[1\] -fixed false -x 602 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[33\] -fixed false -x 488 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0o01_RNO -fixed false -x 66 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[24\] -fixed false -x 105 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_valid_rd_s_0 -fixed false -x 798 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[30\] -fixed false -x 559 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[5\] -fixed false -x 645 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0i1_0_o3 -fixed false -x 102 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1_3 -fixed false -x 47 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01\[7\] -fixed false -x 165 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[12\] -fixed false -x 128 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[0\] -fixed false -x 552 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[38\] -fixed false -x 626 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment15_i_0 -fixed false -x 617 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_reset -fixed false -x 666 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIFI6GO\[15\] -fixed false -x 891 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_4 -fixed false -x 626 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1\[3\] -fixed false -x 410 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001\[9\] -fixed false -x 72 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[4\] -fixed false -x 128 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[14\] -fixed false -x 370 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_1 -fixed false -x 668 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[4\] -fixed false -x 59 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_0_0 -fixed false -x 650 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oio11 -fixed false -x 327 -y 186
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_3 -fixed false -x 10 -y 164
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[21\] -fixed false -x 94 -y 232
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[5\] -fixed false -x 380 -y 243
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_3 -fixed false -x 486 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[22\] -fixed false -x 822 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[28\] -fixed false -x 161 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[31\] -fixed false -x 812 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[4\] -fixed false -x 892 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[16\] -fixed false -x 837 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[14\] -fixed false -x 475 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[13\] -fixed false -x 292 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[17\] -fixed false -x 843 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk1.un4_i1Il1 -fixed false -x 492 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[4\] -fixed false -x 144 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_shifter_unit_op_sel_ex\[0\] -fixed false -x 806 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_568 -fixed false -x 617 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[20\] -fixed false -x 652 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43\[1\] -fixed false -x 279 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[2\] -fixed false -x 739 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[12\] -fixed false -x 845 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[15\] -fixed false -x 128 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1_0 -fixed false -x 65 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q\[4\] -fixed false -x 494 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_108 -fixed false -x 662 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[7\] -fixed false -x 859 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI0O9V9\[7\] -fixed false -x 86 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[12\] -fixed false -x 456 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[8\] -fixed false -x 872 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[24\] -fixed false -x 767 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1 -fixed false -x 236 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/full_out_RNO -fixed false -x 539 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[28\] -fixed false -x 431 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[25\] -fixed false -x 418 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[5\] -fixed false -x 455 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[2\] -fixed false -x 773 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[3\] -fixed false -x 127 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_20_1 -fixed false -x 668 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[24\] -fixed false -x 838 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_43\[9\] -fixed false -x 919 -y 141
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un5_endofshift -fixed false -x 509 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8\[1\] -fixed false -x 314 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[7\] -fixed false -x 280 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[27\] -fixed false -x 387 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_748 -fixed false -x 661 -y 192
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx -fixed false -x 449 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_1\[10\] -fixed false -x 294 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[13\] -fixed false -x 133 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[3\] -fixed false -x 75 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[20\] -fixed false -x 431 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[19\] -fixed false -x 298 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_RNO\[8\] -fixed false -x 78 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo -fixed false -x 115 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_1_0_RNIU7UE0S1 -fixed false -x 808 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[11\] -fixed false -x 459 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[21\] -fixed false -x 404 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[4\] -fixed false -x 195 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO_1 -fixed false -x 853 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[14\] -fixed false -x 751 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13\[2\] -fixed false -x 802 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[18\] -fixed false -x 832 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[0\] -fixed false -x 798 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_retire_mask -fixed false -x 777 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[16\] -fixed false -x 536 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[7\] -fixed false -x 526 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[0\] -fixed false -x 484 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[7\] -fixed false -x 149 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un82_OOOI1\[18\] -fixed false -x 416 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_41\[9\] -fixed false -x 910 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_3\[4\] -fixed false -x 240 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_9 -fixed false -x 680 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[2\] -fixed false -x 881 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[22\] -fixed false -x 457 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[31\] -fixed false -x 293 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[7\] -fixed false -x 382 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un10_Oo1Io_0 -fixed false -x 396 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_d1 -fixed false -x 504 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_OlIi1 -fixed false -x 159 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[7\] -fixed false -x 557 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[14\] -fixed false -x 328 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_d2 -fixed false -x 510 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIEJL4C\[3\] -fixed false -x 646 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr\[1\] -fixed false -x 746 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[2\] -fixed false -x 378 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a3_0_4 -fixed false -x 175 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[25\].BUFD_BLK -fixed false -x 540 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state28 -fixed false -x 767 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_18_0_RNO -fixed false -x 804 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[15\] -fixed false -x 821 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIL7GUI\[9\] -fixed false -x 884 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_strobetx -fixed false -x 533 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1\[6\] -fixed false -x 125 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[11\] -fixed false -x 558 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_1\[28\] -fixed false -x 113 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0Ii1 -fixed false -x 180 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic853 -fixed false -x 600 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[25\] -fixed false -x 900 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_read_RNIIHG39 -fixed false -x 752 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[26\] -fixed false -x 597 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_676 -fixed false -x 747 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_shift_op_complete_ex_RNIKDRC7 -fixed false -x 775 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1\[4\] -fixed false -x 548 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_addr_align\[0\]_3\[0\] -fixed false -x 821 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[1\] -fixed false -x 888 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[26\] -fixed false -x 927 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_i_o2\[4\] -fixed false -x 298 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[17\] -fixed false -x 134 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m10_2_0 -fixed false -x 61 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type\[1\] -fixed false -x 806 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[15\] -fixed false -x 320 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[0\] -fixed false -x 230 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_strb\[1\] -fixed false -x 781 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[29\] -fixed false -x 865 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result194 -fixed false -x 861 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25\[1\] -fixed false -x 277 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[5\] -fixed false -x 63 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[10\] -fixed false -x 36 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[9\] -fixed false -x 723 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[11\] -fixed false -x 497 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[10\] -fixed false -x 402 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0_2\[1\] -fixed false -x 113 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_tz\[0\] -fixed false -x 120 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2123_1_0 -fixed false -x 637 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[3\] -fixed false -x 392 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001\[9\] -fixed false -x 82 -y 160
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[24\] -fixed false -x 417 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[6\] -fixed false -x 636 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/ftrst_1 -fixed false -x 360 -y 193
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_4\[0\] -fixed false -x 747 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[1\] -fixed false -x 46 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[13\] -fixed false -x 938 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[10\] -fixed false -x 229 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oill1 -fixed false -x 451 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_1_0\[1\] -fixed false -x 112 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_40 -fixed false -x 638 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val\[0\] -fixed false -x 724 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftBP_ldmx -fixed false -x 595 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[8\] -fixed false -x 877 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[25\] -fixed false -x 476 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IO0Oo7 -fixed false -x 278 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[10\] -fixed false -x 374 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[10\] -fixed false -x 398 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6 -fixed false -x 788 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[62\] -fixed false -x 593 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[2\] -fixed false -x 883 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[24\] -fixed false -x 786 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOli1_10 -fixed false -x 98 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1lOo -fixed false -x 35 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_en_retr_RNIP5BR6 -fixed false -x 788 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[28\] -fixed false -x 854 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[27\] -fixed false -x 464 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[20\] -fixed false -x 475 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/un7_full_wr_NE -fixed false -x 636 -y 114
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[0\] -fixed false -x 468 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[3\] -fixed false -x 544 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[4\] -fixed false -x 657 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[60\] -fixed false -x 933 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[22\] -fixed false -x 924 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I1i11 -fixed false -x 305 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[20\] -fixed false -x 472 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_985 -fixed false -x 709 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1\[2\] -fixed false -x 501 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2_5 -fixed false -x 699 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[25\] -fixed false -x 402 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_c_0_a0 -fixed false -x 770 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[2\] -fixed false -x 711 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_847 -fixed false -x 769 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01_1_sqmuxa_i_RNO -fixed false -x 386 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_179 -fixed false -x 677 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[9\] -fixed false -x 62 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[31\] -fixed false -x 875 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[10\] -fixed false -x 741 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m10 -fixed false -x 35 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[3\] -fixed false -x 510 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[10\] -fixed false -x 730 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[13\] -fixed false -x 652 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[8\] -fixed false -x 964 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[8\] -fixed false -x 363 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[4\] -fixed false -x 410 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoo1 -fixed false -x 97 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[4\] -fixed false -x 264 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_at_flush20 -fixed false -x 785 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[6\] -fixed false -x 101 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_580 -fixed false -x 794 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read -fixed false -x 455 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[9\] -fixed false -x 703 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[10\] -fixed false -x 489 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[5\] -fixed false -x 412 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/OloIo -fixed false -x 474 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[12\] -fixed false -x 477 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[1\] -fixed false -x 507 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[0\] -fixed false -x 916 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[27\] -fixed false -x 543 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25\[0\] -fixed false -x 268 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[0\] -fixed false -x 843 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en -fixed false -x 768 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[25\] -fixed false -x 673 -y 120
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_9_u_1\[7\] -fixed false -x 480 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0\[2\] -fixed false -x 836 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un314_lIlo1lto15_3_0 -fixed false -x 148 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1_0\[15\] -fixed false -x 60 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[2\] -fixed false -x 217 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_7 -fixed false -x 131 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mtvec_rd_data\[29\] -fixed false -x 724 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOii1_0_a3_0_2 -fixed false -x 151 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iool1 -fixed false -x 354 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[9\] -fixed false -x 881 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[30\] -fixed false -x 850 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[4\] -fixed false -x 461 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I01O1.un1_Ii0O1 -fixed false -x 444 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_630 -fixed false -x 588 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[3\] -fixed false -x 289 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_629 -fixed false -x 564 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[0\] -fixed false -x 386 -y 202
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q\[3\] -fixed false -x 569 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky\[1\] -fixed false -x 519 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[11\] -fixed false -x 858 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_oi1l15_1 -fixed false -x 397 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNI0F56G -fixed false -x 829 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[0\] -fixed false -x 194 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNINTK4B3 -fixed false -x 795 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m6_1_0 -fixed false -x 601 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[1\] -fixed false -x 636 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[8\] -fixed false -x 117 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_293 -fixed false -x 625 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_0 -fixed false -x 147 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[16\] -fixed false -x 461 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_717 -fixed false -x 618 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0\[1\] -fixed false -x 146 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[0\] -fixed false -x 820 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_438 -fixed false -x 688 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_190 -fixed false -x 698 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/IilI1 -fixed false -x 254 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[6\] -fixed false -x 362 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[11\] -fixed false -x 854 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_578 -fixed false -x 637 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[4\] -fixed false -x 203 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ\[10\] -fixed false -x 486 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_m8_i_a5_1_d_0 -fixed false -x 793 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[9\] -fixed false -x 886 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[2\] -fixed false -x 416 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[6\] -fixed false -x 375 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[0\] -fixed false -x 841 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_2 -fixed false -x 656 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[16\] -fixed false -x 762 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[2\] -fixed false -x 519 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[1\] -fixed false -x 211 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[13\] -fixed false -x 693 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_completing_retr -fixed false -x 766 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[1\] -fixed false -x 839 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[30\] -fixed false -x 907 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11\[4\] -fixed false -x 337 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IloOo_2 -fixed false -x 118 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Il0O1 -fixed false -x 389 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[4\] -fixed false -x 692 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[20\] -fixed false -x 468 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z\[4\] -fixed false -x 517 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o0l11 -fixed false -x 351 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_3_RNIJ6ROB -fixed false -x 207 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[29\] -fixed false -x 646 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[4\] -fixed false -x 572 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1_3 -fixed false -x 49 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[16\] -fixed false -x 915 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[10\] -fixed false -x 757 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[7\] -fixed false -x 941 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/un1_Ioli0_1_0 -fixed false -x 283 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_o4 -fixed false -x 266 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1iO1 -fixed false -x 227 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[5\] -fixed false -x 133 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[7\] -fixed false -x 566 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1I1_RNO -fixed false -x 520 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_1_RNIJ418GA -fixed false -x 791 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[22\] -fixed false -x 441 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[7\] -fixed false -x 919 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[1\] -fixed false -x 868 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_3 -fixed false -x 675 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0\[7\] -fixed false -x 460 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01\[1\] -fixed false -x 206 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[9\] -fixed false -x 411 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_819 -fixed false -x 696 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[0\] -fixed false -x 367 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/hipri_req_ptr_RNIHQL2G1\[0\] -fixed false -x 802 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[3\] -fixed false -x 344 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ\[14\] -fixed false -x 341 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr18 -fixed false -x 767 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[11\] -fixed false -x 450 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01\[0\] -fixed false -x 166 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[17\] -fixed false -x 270 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un2_Oo001_4 -fixed false -x 88 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_12 -fixed false -x 572 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[11\] -fixed false -x 838 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIQSR5C\[22\] -fixed false -x 624 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO -fixed false -x 822 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[3\] -fixed false -x 236 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO -fixed false -x 851 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OOil1 -fixed false -x 353 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un2_IOIl1 -fixed false -x 346 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[2\] -fixed false -x 424 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_82 -fixed false -x 761 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[24\] -fixed false -x 350 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/un1_iOI01_1_i_0 -fixed false -x 329 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[15\] -fixed false -x 44 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m35_0 -fixed false -x 705 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[6\] -fixed false -x 136 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1035 -fixed false -x 735 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[0\] -fixed false -x 874 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1059 -fixed false -x 686 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1227 -fixed false -x 687 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset -fixed false -x 591 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[0\] -fixed false -x 843 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[31\] -fixed false -x 784 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_0_sqmuxa_0 -fixed false -x 195 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[22\] -fixed false -x 857 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1\[1\] -fixed false -x 84 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[30\] -fixed false -x 698 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1\[3\] -fixed false -x 396 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[5\] -fixed false -x 416 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[26\] -fixed false -x 453 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m3 -fixed false -x 623 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[32\] -fixed false -x 468 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_5\[0\] -fixed false -x 52 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[0\] -fixed false -x 235 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[4\] -fixed false -x 828 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0o01 -fixed false -x 66 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1\[3\] -fixed false -x 206 -y 196
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[14\].BUFD_BLK -fixed false -x 506 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14\[11\] -fixed false -x 297 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[8\] -fixed false -x 391 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[10\] -fixed false -x 411 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_RNIRNTO -fixed false -x 538 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[9\] -fixed false -x 362 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[22\] -fixed false -x 433 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[16\] -fixed false -x 836 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[31\] -fixed false -x 230 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[29\] -fixed false -x 842 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0 -fixed false -x 715 -y 111
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames\[0\] -fixed false -x 525 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1205 -fixed false -x 770 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_949 -fixed false -x 707 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[23\] -fixed false -x 899 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[10\] -fixed false -x 407 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[6\] -fixed false -x 254 -y 177
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_1 -fixed false -x 481 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[26\] -fixed false -x 399 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[6\] -fixed false -x 433 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_6_1 -fixed false -x 112 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5\[8\] -fixed false -x 170 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a0_2_0 -fixed false -x 788 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[0\] -fixed false -x 766 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_2\[0\] -fixed false -x 661 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[7\] -fixed false -x 658 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1192 -fixed false -x 746 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[26\] -fixed false -x 698 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[25\] -fixed false -x 405 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel7_0_0 -fixed false -x 521 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[39\] -fixed false -x 914 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_IOlOo_12_0 -fixed false -x 38 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[11\] -fixed false -x 111 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42\[11\] -fixed false -x 278 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1112 -fixed false -x 676 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi1o1_i_o2 -fixed false -x 99 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_RNO\[5\] -fixed false -x 541 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI0M7VA\[13\] -fixed false -x 659 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA\[6\] -fixed false -x 484 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1233 -fixed false -x 685 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_i_x4\[10\] -fixed false -x 111 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[4\] -fixed false -x 412 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.lloIo -fixed false -x 389 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ool11 -fixed false -x 242 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_7_3 -fixed false -x 688 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[25\] -fixed false -x 901 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[27\] -fixed false -x 904 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[8\] -fixed false -x 481 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[19\] -fixed false -x 50 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_0\[31\] -fixed false -x 744 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ioli1 -fixed false -x 202 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_152_a2 -fixed false -x 459 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[30\] -fixed false -x 848 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[1\] -fixed false -x 455 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo -fixed false -x 244 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_4 -fixed false -x 307 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO_1 -fixed false -x 895 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[29\] -fixed false -x 829 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[2\] -fixed false -x 436 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[13\] -fixed false -x 23 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[27\] -fixed false -x 409 -y 243
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code_RNO -fixed false -x 3 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[9\] -fixed false -x 434 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[2\] -fixed false -x 359 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1\[3\] -fixed false -x 693 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[6\] -fixed false -x 801 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[5\] -fixed false -x 766 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[18\] -fixed false -x 453 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[3\] -fixed false -x 574 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[10\] -fixed false -x 289 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_0_0\[3\] -fixed false -x 321 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[22\] -fixed false -x 717 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[0\] -fixed false -x 125 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr\[0\] -fixed false -x 627 -y 115
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_RNO\[0\] -fixed false -x 562 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[9\] -fixed false -x 735 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[9\] -fixed false -x 596 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_661 -fixed false -x 604 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_MTIME.un1_T_l_En_0_o2 -fixed false -x 496 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m13 -fixed false -x 63 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv\[2\] -fixed false -x 697 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_m2\[1\] -fixed false -x 299 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_ex_retr_pipe_lsu_op_retr -fixed false -x 771 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11\[6\] -fixed false -x 270 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid -fixed false -x 752 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[26\] -fixed false -x 736 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[19\] -fixed false -x 734 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/o0Oo1 -fixed false -x 310 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[1\] -fixed false -x 409 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[9\] -fixed false -x 506 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi1o1_i_o2_1 -fixed false -x 84 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[10\] -fixed false -x 303 -y 157
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[25\].BUFD_BLK -fixed false -x 507 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_1_sqmuxa_1_0 -fixed false -x 702 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[4\] -fixed false -x 296 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m9 -fixed false -x 73 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[17\] -fixed false -x 650 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un10_iIIi1 -fixed false -x 189 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].un1_lIII110 -fixed false -x 474 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un105_OOOI1\[22\] -fixed false -x 415 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[4\] -fixed false -x 952 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo -fixed false -x 266 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0\[3\] -fixed false -x 258 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_394 -fixed false -x 627 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[24\] -fixed false -x 861 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[13\] -fixed false -x 297 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[21\] -fixed false -x 470 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[9\] -fixed false -x 665 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m25_e -fixed false -x 51 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[11\] -fixed false -x 363 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1\[5\] -fixed false -x 171 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[8\] -fixed false -x 177 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[23\] -fixed false -x 655 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[8\] -fixed false -x 266 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[13\] -fixed false -x 437 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[0\] -fixed false -x 67 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[2\] -fixed false -x 726 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[14\] -fixed false -x 470 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[1\] -fixed false -x 787 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1\[2\] -fixed false -x 770 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_8 -fixed false -x 724 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[27\] -fixed false -x 914 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI69984\[11\] -fixed false -x 856 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[7\] -fixed false -x 834 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u_2\[8\] -fixed false -x 951 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[9\] -fixed false -x 244 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_7_RNO -fixed false -x 372 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iIll1 -fixed false -x 525 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[2\] -fixed false -x 123 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_1_i_m4\[0\] -fixed false -x 791 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[26\] -fixed false -x 870 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[7\] -fixed false -x 296 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5\[1\] -fixed false -x 254 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0ii1 -fixed false -x 139 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[5\] -fixed false -x 772 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_2\[2\] -fixed false -x 61 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un37_ool01\[3\] -fixed false -x 59 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1 -fixed false -x 234 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[14\] -fixed false -x 87 -y 211
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[30\] -fixed false -x 414 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[26\] -fixed false -x 850 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[10\] -fixed false -x 312 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[9\] -fixed false -x 244 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01\[4\] -fixed false -x 196 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[26\] -fixed false -x 836 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO -fixed false -x 829 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[0\] -fixed false -x 123 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[27\] -fixed false -x 113 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iI0o1 -fixed false -x 66 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_a3_0 -fixed false -x 718 -y 111
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel\[1\] -fixed false -x 41 -y 220
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_0_sqmuxa -fixed false -x 524 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[10\] -fixed false -x 479 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[6\] -fixed false -x 376 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liII1 -fixed false -x 315 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2\[0\] -fixed false -x 50 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_267 -fixed false -x 614 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[2\] -fixed false -x 75 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[24\] -fixed false -x 678 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[50\] -fixed false -x 961 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]\[2\] -fixed false -x 789 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[12\] -fixed false -x 606 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2_0_4 -fixed false -x 60 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un11_start_div_3 -fixed false -x 864 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[7\] -fixed false -x 739 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_i_ex -fixed false -x 773 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[24\] -fixed false -x 649 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_815 -fixed false -x 603 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[28\] -fixed false -x 588 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2_i_m3\[31\] -fixed false -x 534 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[23\] -fixed false -x 413 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_1\[15\] -fixed false -x 855 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OiIl1 -fixed false -x 450 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[2\] -fixed false -x 145 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[13\] -fixed false -x 894 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_600 -fixed false -x 661 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[10\] -fixed false -x 69 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[12\] -fixed false -x 541 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_8\[9\] -fixed false -x 162 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[30\] -fixed false -x 637 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[21\] -fixed false -x 727 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[0\] -fixed false -x 888 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[31\] -fixed false -x 953 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[18\] -fixed false -x 56 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_36\[8\] -fixed false -x 923 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I00i1 -fixed false -x 185 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iOiIo -fixed false -x 422 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[1\] -fixed false -x 494 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[3\] -fixed false -x 132 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[4\] -fixed false -x 452 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[1\] -fixed false -x 109 -y 177
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4\[1\] -fixed false -x 462 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[13\] -fixed false -x 700 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1194 -fixed false -x 697 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_408 -fixed false -x 675 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_RNO\[2\] -fixed false -x 542 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u_RNO_0 -fixed false -x 850 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5\[7\] -fixed false -x 483 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2\[1\] -fixed false -x 682 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[8\] -fixed false -x 571 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1114 -fixed false -x 629 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[15\] -fixed false -x 350 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m22_d -fixed false -x 111 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[15\] -fixed false -x 888 -y 148
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[3\] -fixed false -x 452 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_446 -fixed false -x 602 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[1\] -fixed false -x 141 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_d_1_sqmuxa -fixed false -x 556 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[2\] -fixed false -x 306 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o0il1_i -fixed false -x 485 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_3 -fixed false -x 217 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_a3 -fixed false -x 672 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_1_0 -fixed false -x 708 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_20 -fixed false -x 77 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_24\[9\] -fixed false -x 293 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1\[4\] -fixed false -x 216 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[8\] -fixed false -x 516 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[0\] -fixed false -x 384 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ\[15\] -fixed false -x 340 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[19\] -fixed false -x 714 -y 118
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[7\] -fixed false -x 506 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lIoI1 -fixed false -x 410 -y 202
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc1 -fixed false -x 39 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_0\[5\] -fixed false -x 157 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[11\] -fixed false -x 117 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.penable_RNO -fixed false -x 614 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[6\] -fixed false -x 391 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[0\] -fixed false -x 442 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[2\] -fixed false -x 393 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2s2_0_a2 -fixed false -x 747 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[30\] -fixed false -x 215 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[3\] -fixed false -x 240 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[3\] -fixed false -x 389 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_862 -fixed false -x 624 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[2\] -fixed false -x 118 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[0\] -fixed false -x 262 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[10\] -fixed false -x 239 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[20\] -fixed false -x 940 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1\[2\] -fixed false -x 216 -y 193
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[1\] -fixed false -x 42 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5\[0\] -fixed false -x 207 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[11\] -fixed false -x 421 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1\[3\] -fixed false -x 333 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_ioOOo_2 -fixed false -x 52 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[2\] -fixed false -x 792 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3_RNIKE5HR -fixed false -x 756 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2\[6\] -fixed false -x 839 -y 123
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[3\] -fixed false -x 379 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[19\] -fixed false -x 223 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[12\] -fixed false -x 230 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[9\] -fixed false -x 881 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[49\] -fixed false -x 504 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[10\] -fixed false -x 279 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_0_0\[0\] -fixed false -x 49 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0\[1\] -fixed false -x 129 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[7\] -fixed false -x 248 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_4_RNI83504 -fixed false -x 749 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_9_RNO -fixed false -x 363 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state_valid -fixed false -x 795 -y 123
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2\[2\] -fixed false -x 372 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[21\] -fixed false -x 448 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m18 -fixed false -x 50 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[25\] -fixed false -x 832 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1187 -fixed false -x 626 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1142 -fixed false -x 736 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[19\] -fixed false -x 735 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[8\] -fixed false -x 388 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[26\] -fixed false -x 75 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[29\] -fixed false -x 412 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv\[2\] -fixed false -x 19 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch\[1\] -fixed false -x 631 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat12 -fixed false -x 553 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/un1_Ioli0_1_0 -fixed false -x 183 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO\[5\] -fixed false -x 110 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[4\] -fixed false -x 784 -y 106
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[15\] -fixed false -x 416 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[15\] -fixed false -x 830 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[3\] -fixed false -x 175 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[8\] -fixed false -x 363 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0\[0\] -fixed false -x 25 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_instr_is_lsu_op_retr -fixed false -x 810 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un7_I10i1_1 -fixed false -x 162 -y 198
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UTDI -fixed false -x 484 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_3_9_7 -fixed false -x 823 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[19\] -fixed false -x 855 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[16\] -fixed false -x 840 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[10\] -fixed false -x 684 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[9\] -fixed false -x 367 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[30\] -fixed false -x 431 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0\[2\] -fixed false -x 332 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_252 -fixed false -x 627 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[29\] -fixed false -x 917 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[19\] -fixed false -x 432 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[2\] -fixed false -x 263 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[10\] -fixed false -x 428 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[11\] -fixed false -x 262 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_671 -fixed false -x 589 -y 144
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code\[1\] -fixed false -x 10 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[10\] -fixed false -x 854 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[0\] -fixed false -x 781 -y 157
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1_0 -fixed false -x 500 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[7\] -fixed false -x 745 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[18\] -fixed false -x 855 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[1\] -fixed false -x 827 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO\[0\] -fixed false -x 619 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[9\] -fixed false -x 209 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m67 -fixed false -x 29 -y 198
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1\[4\] -fixed false -x 470 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[0\] -fixed false -x 113 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[10\] -fixed false -x 338 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[39\] -fixed false -x 314 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1_RNIRG5AQ -fixed false -x 499 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[5\] -fixed false -x 184 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/un1_iOI01_1_i_0 -fixed false -x 332 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_28\[3\] -fixed false -x 326 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_19 -fixed false -x 651 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[4\] -fixed false -x 388 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[25\] -fixed false -x 321 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[9\] -fixed false -x 367 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[28\] -fixed false -x 388 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[16\] -fixed false -x 679 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[3\] -fixed false -x 381 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[12\] -fixed false -x 778 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_5 -fixed false -x 524 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[18\] -fixed false -x 927 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[4\] -fixed false -x 134 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1iIo -fixed false -x 421 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[25\] -fixed false -x 544 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1\[2\] -fixed false -x 165 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[3\] -fixed false -x 61 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un4_I1Oi1_2_0 -fixed false -x 28 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a2_1\[24\] -fixed false -x 743 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01\[0\] -fixed false -x 198 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[5\] -fixed false -x 198 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[20\] -fixed false -x 879 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[5\] -fixed false -x 276 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[17\] -fixed false -x 650 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z\[1\] -fixed false -x 254 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[4\] -fixed false -x 257 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[14\] -fixed false -x 825 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n3 -fixed false -x 172 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_3_0_a2\[1\] -fixed false -x 200 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o1oo1_i_0 -fixed false -x 86 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[8\] -fixed false -x 177 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1155 -fixed false -x 673 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_lliOo_1.CO3 -fixed false -x 356 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m71 -fixed false -x 28 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11\[13\] -fixed false -x 58 -y 210
|
|
set_location -inst_name PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_98_0 -fixed false -x 0 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_0 -fixed false -x 710 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0\[4\] -fixed false -x 755 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[3\] -fixed false -x 314 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_pos -fixed false -x 511 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[16\] -fixed false -x 473 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[28\] -fixed false -x 938 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_OIOl1_1_0 -fixed false -x 435 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l1ll1 -fixed false -x 488 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo55 -fixed false -x 40 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_2_RNO_0 -fixed false -x 816 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIIo\[0\] -fixed false -x 120 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_a1_2_0 -fixed false -x 789 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_88 -fixed false -x 661 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[17\] -fixed false -x 338 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex\[1\] -fixed false -x 710 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_12 -fixed false -x 724 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_sba_req_rd_byte_en_int_0_a3_0_a3 -fixed false -x 796 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[7\] -fixed false -x 162 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[28\] -fixed false -x 407 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[24\] -fixed false -x 843 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[10\] -fixed false -x 457 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_277 -fixed false -x 672 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[9\] -fixed false -x 867 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_o3_1 -fixed false -x 127 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[2\] -fixed false -x 202 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2125.rv32c_dec_mnemonic2125_3_3 -fixed false -x 699 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI9DA84\[23\] -fixed false -x 946 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[0\] -fixed false -x 297 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OiI11 -fixed false -x 264 -y 193
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_9_iv\[0\] -fixed false -x 30 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_79 -fixed false -x 650 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[3\] -fixed false -x 163 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iO1I1 -fixed false -x 481 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[24\] -fixed false -x 878 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m3_i_o3 -fixed false -x 840 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[11\] -fixed false -x 828 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[20\] -fixed false -x 724 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_busy_cmb_mux.un1_debug_csr_rd_en -fixed false -x 721 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m205 -fixed false -x 256 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01_RNO -fixed false -x 212 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[3\] -fixed false -x 766 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0\[4\] -fixed false -x 318 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmireset_RNO -fixed false -x 592 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[12\] -fixed false -x 403 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIoO1 -fixed false -x 173 -y 190
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_2_sqmuxa_1 -fixed false -x 508 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_curr_fetch_ptr_1_0\[1\] -fixed false -x 890 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[0\] -fixed false -x 483 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[5\] -fixed false -x 376 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1 -fixed false -x 85 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[6\] -fixed false -x 266 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_23 -fixed false -x 85 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i0oi1_i_o2\[0\] -fixed false -x 265 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1252 -fixed false -x 659 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[3\] -fixed false -x 859 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7\[1\] -fixed false -x 417 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oliO1 -fixed false -x 208 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[4\] -fixed false -x 706 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[4\] -fixed false -x 458 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_417 -fixed false -x 708 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[2\] -fixed false -x 136 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[45\] -fixed false -x 339 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid_3_2_RNIE7GVF -fixed false -x 816 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2__RNI07RO5\[15\] -fixed false -x 616 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[27\] -fixed false -x 727 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_8 -fixed false -x 146 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1\[4\] -fixed false -x 305 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIOo1 -fixed false -x 311 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oool1 -fixed false -x 356 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[12\] -fixed false -x 120 -y 207
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_statece\[1\] -fixed false -x 470 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[7\] -fixed false -x 308 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_562 -fixed false -x 723 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[15\] -fixed false -x 191 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_l00o1_1 -fixed false -x 110 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[10\] -fixed false -x 457 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[6\] -fixed false -x 322 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/excpt_ebreak -fixed false -x 764 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[0\] -fixed false -x 409 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI1I1 -fixed false -x 473 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[6\] -fixed false -x 79 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[21\] -fixed false -x 551 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[21\] -fixed false -x 375 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[7\] -fixed false -x 98 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_0_RNO_2 -fixed false -x 165 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_0\[9\] -fixed false -x 851 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo_RNO\[3\] -fixed false -x 297 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[4\] -fixed false -x 214 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1144 -fixed false -x 565 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/olio1 -fixed false -x 49 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[5\] -fixed false -x 940 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[38\] -fixed false -x 634 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[25\] -fixed false -x 488 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_iO1Oo\[0\] -fixed false -x 150 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[5\] -fixed false -x 436 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel -fixed false -x 520 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[3\] -fixed false -x 435 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[4\] -fixed false -x 43 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1 -fixed false -x 784 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m13_1_0 -fixed false -x 770 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_838 -fixed false -x 670 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOi11_1 -fixed false -x 331 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_davailable -fixed false -x 514 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_2_1 -fixed false -x 637 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[14\] -fixed false -x 259 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12\[1\] -fixed false -x 278 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_2 -fixed false -x 219 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[27\] -fixed false -x 706 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_51\[11\] -fixed false -x 269 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[10\] -fixed false -x 238 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q\[1\] -fixed false -x 591 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/soft_reset_pending -fixed false -x 756 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_872 -fixed false -x 660 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_982 -fixed false -x 626 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[5\] -fixed false -x 843 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[13\] -fixed false -x 26 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[50\] -fixed false -x 567 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[13\] -fixed false -x 32 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oi101 -fixed false -x 128 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[31\] -fixed false -x 959 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[6\] -fixed false -x 834 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[11\] -fixed false -x 421 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[4\] -fixed false -x 98 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z\[2\] -fixed false -x 348 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[14\] -fixed false -x 420 -y 154
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[19\].BUFD_BLK -fixed false -x 530 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[7\] -fixed false -x 327 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[7\] -fixed false -x 221 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[15\] -fixed false -x 153 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_0\[5\] -fixed false -x 109 -y 213
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2\[6\] -fixed false -x 74 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[24\] -fixed false -x 545 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1_cZ\[16\] -fixed false -x 263 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[5\] -fixed false -x 337 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[3\] -fixed false -x 186 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[21\] -fixed false -x 439 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[22\] -fixed false -x 66 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[3\] -fixed false -x 329 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m23_1_0 -fixed false -x 731 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m0s2 -fixed false -x 724 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o3_1_0 -fixed false -x 625 -y 135
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[19\] -fixed false -x 397 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[6\] -fixed false -x 758 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_OOOl1_1_0 -fixed false -x 434 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[6\] -fixed false -x 252 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[12\] -fixed false -x 855 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[12\] -fixed false -x 260 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3\[3\] -fixed false -x 499 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[6\] -fixed false -x 787 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[24\] -fixed false -x 279 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0 -fixed false -x 710 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first -fixed false -x 513 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[19\] -fixed false -x 831 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[13\] -fixed false -x 473 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[23\] -fixed false -x 672 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un131_I1Oi1 -fixed false -x 60 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNI9C6GO\[12\] -fixed false -x 879 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ioo11 -fixed false -x 326 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[0\] -fixed false -x 114 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z\[26\] -fixed false -x 158 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lO0Io.m4 -fixed false -x 111 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[8\] -fixed false -x 902 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[3\] -fixed false -x 735 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[3\] -fixed false -x 675 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01 -fixed false -x 212 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[9\] -fixed false -x 788 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_2_1\[6\] -fixed false -x 702 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIO1CS7\[4\] -fixed false -x 907 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_166 -fixed false -x 624 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o0o11 -fixed false -x 390 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0\[0\] -fixed false -x 509 -y 147
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[7\] -fixed false -x 476 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lliO1_1_iv_0_cZ\[0\] -fixed false -x 86 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/il111 -fixed false -x 98 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_2\[2\] -fixed false -x 506 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[10\] -fixed false -x 455 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[0\] -fixed false -x 82 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[20\] -fixed false -x 652 -y 153
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[14\] -fixed false -x 377 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid -fixed false -x 827 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[4\] -fixed false -x 108 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_valid_u_RNII7VGD -fixed false -x 807 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[25\] -fixed false -x 900 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[15\] -fixed false -x 605 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[27\] -fixed false -x 672 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[25\] -fixed false -x 594 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[12\] -fixed false -x 649 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[13\] -fixed false -x 658 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[7\] -fixed false -x 926 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[26\] -fixed false -x 808 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_2_3_0\[7\] -fixed false -x 121 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_7 -fixed false -x 689 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[2\] -fixed false -x 614 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO\[0\] -fixed false -x 320 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[3\] -fixed false -x 312 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[10\] -fixed false -x 848 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[2\] -fixed false -x 62 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[27\] -fixed false -x 385 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[14\].BUFD_BLK -fixed false -x 530 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[15\] -fixed false -x 938 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex\[4\] -fixed false -x 738 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[34\] -fixed false -x 632 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOI11 -fixed false -x 246 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0iO1 -fixed false -x 193 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un17_full_wr_NE -fixed false -x 634 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[5\] -fixed false -x 90 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[19\] -fixed false -x 388 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_1 -fixed false -x 632 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/un1_Ioli0_1_0 -fixed false -x 257 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_looo1 -fixed false -x 49 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[6\] -fixed false -x 413 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001\[2\] -fixed false -x 79 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[3\] -fixed false -x 435 -y 150
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[8\] -fixed false -x 393 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[39\] -fixed false -x 352 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[1\] -fixed false -x 158 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[12\] -fixed false -x 699 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rrex_1 -fixed false -x 31 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_write -fixed false -x 734 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[19\] -fixed false -x 933 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo_5 -fixed false -x 302 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[10\] -fixed false -x 415 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/gen_bit_no_reset.state_val\[0\] -fixed false -x 728 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[7\] -fixed false -x 915 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex\[3\] -fixed false -x 729 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[19\] -fixed false -x 92 -y 211
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_2_sqmuxa -fixed false -x 62 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19_1 -fixed false -x 648 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[28\] -fixed false -x 939 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iO1 -fixed false -x 110 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[25\] -fixed false -x 651 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[30\] -fixed false -x 873 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[11\] -fixed false -x 347 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/wr_en_data_or -fixed false -x 752 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[5\] -fixed false -x 681 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO\[4\] -fixed false -x 617 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[13\] -fixed false -x 154 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_231 -fixed false -x 564 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[43\] -fixed false -x 918 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo\[0\] -fixed false -x 393 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/clr_wfi_waiting_0_RNIG77PK8 -fixed false -x 769 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1075 -fixed false -x 712 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_12 -fixed false -x 705 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI9FM4C\[5\] -fixed false -x 655 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_6 -fixed false -x 661 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0\[12\] -fixed false -x 150 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[2\] -fixed false -x 204 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[5\] -fixed false -x 333 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[8\] -fixed false -x 388 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[0\] -fixed false -x 223 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[13\] -fixed false -x 332 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_data_gen_buff_loop\[0\].buff_data_0_0_RNO_2 -fixed false -x 789 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[31\] -fixed false -x 846 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[3\] -fixed false -x 139 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo\[0\] -fixed false -x 392 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[7\] -fixed false -x 327 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[16\] -fixed false -x 348 -y 199
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[5\] -fixed false -x 402 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un5_I0i01_0_a3_0 -fixed false -x 92 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I0Ol1_1 -fixed false -x 441 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[21\] -fixed false -x 75 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[14\] -fixed false -x 678 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa_1_0_0 -fixed false -x 769 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[7\] -fixed false -x 131 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[11\] -fixed false -x 591 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[7\] -fixed false -x 342 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[4\] -fixed false -x 361 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_572 -fixed false -x 660 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[20\] -fixed false -x 706 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1_RNIHGL6KH2 -fixed false -x 791 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un5_lI0i1 -fixed false -x 108 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[11\] -fixed false -x 426 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_16 -fixed false -x 673 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[16\] -fixed false -x 262 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/stall_retr -fixed false -x 773 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_133 -fixed false -x 686 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[20\] -fixed false -x 650 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo -fixed false -x 99 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_a2_1 -fixed false -x 102 -y 210
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay\[14\] -fixed false -x 553 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[9\] -fixed false -x 232 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[10\] -fixed false -x 466 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[8\] -fixed false -x 452 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0io1 -fixed false -x 86 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m53 -fixed false -x 12 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1_RNO -fixed false -x 99 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[8\] -fixed false -x 446 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[19\] -fixed false -x 451 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[17\] -fixed false -x 322 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[19\] -fixed false -x 44 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3\[7\] -fixed false -x 465 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo_RNO -fixed false -x 32 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[7\] -fixed false -x 85 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[6\] -fixed false -x 965 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[28\] -fixed false -x 871 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[3\] -fixed false -x 374 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2 -fixed false -x 517 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_7_0_RNO -fixed false -x 787 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit\[0\] -fixed false -x 461 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a5_0 -fixed false -x 847 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii0Oo -fixed false -x 127 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1273 -fixed false -x 639 -y 195
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_1 -fixed false -x 474 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type\[6\] -fixed false -x 780 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4\[4\] -fixed false -x 569 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINHVQ8\[32\] -fixed false -x 615 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[16\] -fixed false -x 824 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil15 -fixed false -x 484 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15 -fixed false -x 695 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[18\] -fixed false -x 651 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[1\] -fixed false -x 905 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[4\] -fixed false -x 364 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[35\] -fixed false -x 113 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[12\] -fixed false -x 158 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[7\] -fixed false -x 186 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_OOoo1_0_0 -fixed false -x 98 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_55\[11\] -fixed false -x 302 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/extract_os_i_loop_l0.un3_req_os_i_src\[5\] -fixed false -x 756 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[6\] -fixed false -x 553 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l01o1 -fixed false -x 14 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1 -fixed false -x 184 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[24\] -fixed false -x 963 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_246 -fixed false -x 602 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[6\] -fixed false -x 289 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto3_0_RNITS3HP -fixed false -x 146 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO_0 -fixed false -x 197 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[18\] -fixed false -x 736 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places\[2\] -fixed false -x 866 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[5\] -fixed false -x 812 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[17\] -fixed false -x 693 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OlOI1 -fixed false -x 295 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex\[0\] -fixed false -x 776 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo\[3\] -fixed false -x 126 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[5\] -fixed false -x 729 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo -fixed false -x 153 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3\[3\] -fixed false -x 500 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[0\] -fixed false -x 879 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3 -fixed false -x 744 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[29\] -fixed false -x 733 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_599 -fixed false -x 793 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ilio1 -fixed false -x 48 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNIB64LE\[2\] -fixed false -x 792 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_intce\[64\] -fixed false -x 900 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0\[7\] -fixed false -x 351 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1o01 -fixed false -x 104 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[38\] -fixed false -x 557 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[0\] -fixed false -x 692 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[3\] -fixed false -x 27 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[7\] -fixed false -x 377 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[14\] -fixed false -x 437 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0\[15\] -fixed false -x 218 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_o4\[0\] -fixed false -x 96 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_808 -fixed false -x 616 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un28_lolIo -fixed false -x 12 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1036 -fixed false -x 637 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[1\] -fixed false -x 602 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[4\] -fixed false -x 783 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[5\] -fixed false -x 205 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_176 -fixed false -x 697 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[1\] -fixed false -x 311 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]_3\[0\] -fixed false -x 750 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_m4_0 -fixed false -x 781 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[17\] -fixed false -x 588 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[10\] -fixed false -x 725 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_m1_0_a2_0_5 -fixed false -x 790 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[7\] -fixed false -x 85 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_12_0_RNO -fixed false -x 827 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_0 -fixed false -x 687 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_3_200_a2 -fixed false -x 434 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0\[3\] -fixed false -x 148 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_97 -fixed false -x 650 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m3 -fixed false -x 87 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_RNO -fixed false -x 792 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[9\] -fixed false -x 831 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z\[0\] -fixed false -x 207 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[19\] -fixed false -x 674 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[3\] -fixed false -x 265 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex\[1\] -fixed false -x 809 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[9\] -fixed false -x 173 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_440 -fixed false -x 615 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[10\] -fixed false -x 371 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001\[8\] -fixed false -x 74 -y 166
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[3\] -fixed false -x 490 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2\[1\] -fixed false -x 98 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[5\] -fixed false -x 724 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oi1o1_1 -fixed false -x 98 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[37\] -fixed false -x 655 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[11\] -fixed false -x 704 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[2\] -fixed false -x 361 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[21\] -fixed false -x 701 -y 183
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC_0\[0\] -fixed false -x 7 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_next_buff_resp_wr_ptr_1_sqmuxa -fixed false -x 714 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_9 -fixed false -x 701 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo_RNIF9FU8 -fixed false -x 97 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[10\] -fixed false -x 444 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[7\] -fixed false -x 745 -y 171
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_cnt.xmit_bit_sel_3_a3\[0\] -fixed false -x 425 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[26\] -fixed false -x 403 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001_1 -fixed false -x 91 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmstatus_allany_havereset10_0_a3_RNIIO92L -fixed false -x 796 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_4_iv_i\[0\] -fixed false -x 572 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[7\] -fixed false -x 371 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_1 -fixed false -x 661 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[30\] -fixed false -x 413 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data\[0\] -fixed false -x 696 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[20\] -fixed false -x 554 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[5\] -fixed false -x 646 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[5\] -fixed false -x 203 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_i_o3_RNIR2796U\[31\] -fixed false -x 809 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[26\] -fixed false -x 456 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_3_1_0 -fixed false -x 348 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[11\] -fixed false -x 780 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[20\] -fixed false -x 425 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[2\] -fixed false -x 432 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35_1\[1\] -fixed false -x 913 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_124 -fixed false -x 746 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIO11_1 -fixed false -x 15 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[28\] -fixed false -x 771 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write\[1\] -fixed false -x 634 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[8\] -fixed false -x 350 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[14\] -fixed false -x 678 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[5\] -fixed false -x 336 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[8\] -fixed false -x 298 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_0\[1\] -fixed false -x 478 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[0\] -fixed false -x 387 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_41 -fixed false -x 697 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[7\] -fixed false -x 432 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[13\] -fixed false -x 373 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_9_0_RNO\[0\] -fixed false -x 875 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI1l1 -fixed false -x 506 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_2_RNIC8U2E -fixed false -x 517 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0iO1 -fixed false -x 199 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[6\] -fixed false -x 337 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[9\] -fixed false -x 162 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_2_0\[13\] -fixed false -x 842 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_15 -fixed false -x 710 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[8\] -fixed false -x 228 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl1 -fixed false -x 451 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[20\] -fixed false -x 850 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[0\] -fixed false -x 326 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m63_0 -fixed false -x 284 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNO_0 -fixed false -x 796 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOll1_0 -fixed false -x 385 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1\[1\] -fixed false -x 142 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[9\] -fixed false -x 757 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[32\] -fixed false -x 482 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo54_0_0 -fixed false -x 39 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv\[17\] -fixed false -x 743 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[30\] -fixed false -x 909 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_795 -fixed false -x 733 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_389 -fixed false -x 675 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[0\] -fixed false -x 239 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_0\[3\] -fixed false -x 17 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1002 -fixed false -x 712 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_4\[1\] -fixed false -x 266 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[9\] -fixed false -x 731 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[13\] -fixed false -x 323 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_0\[3\] -fixed false -x 743 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[4\] -fixed false -x 791 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[32\] -fixed false -x 219 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_8 -fixed false -x 692 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_632 -fixed false -x 767 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[1\] -fixed false -x 364 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[5\] -fixed false -x 654 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un3_dmi_rd_0_a2 -fixed false -x 646 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIIi1 -fixed false -x 191 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[21\] -fixed false -x 475 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[12\] -fixed false -x 852 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[12\] -fixed false -x 482 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[7\] -fixed false -x 321 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[47\] -fixed false -x 960 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_537 -fixed false -x 711 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_ac0_5 -fixed false -x 106 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[2\] -fixed false -x 723 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr\[11\] -fixed false -x 757 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[38\] -fixed false -x 912 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_3_1.CO2 -fixed false -x 546 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[10\] -fixed false -x 154 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNO\[0\] -fixed false -x 59 -y 210
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_lcry_RNO -fixed false -x 360 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_m6_0_a2 -fixed false -x 720 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[4\] -fixed false -x 248 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[13\] -fixed false -x 349 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_addr_align\[1\]\[1\] -fixed false -x 823 -y 124
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc1 -fixed false -x 493 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_960 -fixed false -x 626 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_3\[1\] -fixed false -x 619 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un291_rv32i_dec_sw_csr_wr_op_0 -fixed false -x 692 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_1_0 -fixed false -x 74 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[6\] -fixed false -x 837 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[31\] -fixed false -x 456 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_resp_error_2 -fixed false -x 824 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[20\] -fixed false -x 441 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[24\] -fixed false -x 676 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_6 -fixed false -x 167 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_201 -fixed false -x 614 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[4\] -fixed false -x 413 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[5\] -fixed false -x 914 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_913 -fixed false -x 735 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[15\] -fixed false -x 460 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/un1_Ioli0_1_0 -fixed false -x 223 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[29\] -fixed false -x 415 -y 244
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO_0 -fixed false -x 909 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[46\] -fixed false -x 233 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7 -fixed false -x 821 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_alldone -fixed false -x 527 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_3\[10\] -fixed false -x 290 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01\[3\] -fixed false -x 172 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[7\] -fixed false -x 883 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_RNIVVRAO -fixed false -x 686 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[15\] -fixed false -x 818 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[24\] -fixed false -x 220 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[18\] -fixed false -x 605 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[2\] -fixed false -x 438 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[9\] -fixed false -x 378 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[11\] -fixed false -x 332 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIM7072\[4\] -fixed false -x 395 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[0\] -fixed false -x 223 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[24\] -fixed false -x 845 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[9\] -fixed false -x 18 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand1_mux_sel_1_0_iv\[1\] -fixed false -x 770 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[10\] -fixed false -x 919 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0\[13\] -fixed false -x 132 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_gpr_rs2_rd_data_valid_4 -fixed false -x 718 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un9_cpu_d_resp_valid_sig_2 -fixed false -x 804 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_69\[11\] -fixed false -x 352 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_ready -fixed false -x 833 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2\[17\] -fixed false -x 372 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_698 -fixed false -x 649 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[14\] -fixed false -x 901 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[2\] -fixed false -x 135 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5s4 -fixed false -x 735 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state\[1\] -fixed false -x 512 -y 148
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[3\] -fixed false -x 547 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_464 -fixed false -x 736 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[12\] -fixed false -x 844 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[18\] -fixed false -x 964 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0\[30\] -fixed false -x 732 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[2\] -fixed false -x 270 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[19\] -fixed false -x 539 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_103 -fixed false -x 760 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[15\] -fixed false -x 783 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[13\] -fixed false -x 749 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[3\] -fixed false -x 794 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001\[1\] -fixed false -x 47 -y 160
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRCAP -fixed false -x 508 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[6\] -fixed false -x 818 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPFRQ8\[15\] -fixed false -x 648 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[0\] -fixed false -x 428 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_788 -fixed false -x 625 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[1\] -fixed false -x 470 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[7\] -fixed false -x 159 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[0\] -fixed false -x 160 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[18\] -fixed false -x 901 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[4\] -fixed false -x 69 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI1o1_i_0_o2 -fixed false -x 48 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff\[2\] -fixed false -x 698 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[1\] -fixed false -x 46 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[15\] -fixed false -x 360 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0\[6\] -fixed false -x 493 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[28\] -fixed false -x 467 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[11\] -fixed false -x 213 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[4\] -fixed false -x 375 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state133 -fixed false -x 518 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_753 -fixed false -x 627 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[7\] -fixed false -x 528 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[14\] -fixed false -x 860 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_4_tz_1\[0\] -fixed false -x 830 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[10\] -fixed false -x 877 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[7\] -fixed false -x 818 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[13\] -fixed false -x 77 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[9\] -fixed false -x 574 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[11\] -fixed false -x 423 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[10\] -fixed false -x 458 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[29\] -fixed false -x 460 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[15\] -fixed false -x 379 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un4_IoOOo_NE -fixed false -x 51 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[4\] -fixed false -x 774 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[1\] -fixed false -x 530 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I1111 -fixed false -x 105 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2\[0\] -fixed false -x 375 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l11Oo\[0\] -fixed false -x 141 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_N_3L4_RNO_0 -fixed false -x 672 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_1\[30\] -fixed false -x 132 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1\[3\] -fixed false -x 141 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[7\] -fixed false -x 362 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[4\] -fixed false -x 730 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oi0l1\[0\] -fixed false -x 467 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[0\] -fixed false -x 315 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[4\] -fixed false -x 238 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[17\] -fixed false -x 464 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un89_ool01 -fixed false -x 193 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_2_1 -fixed false -x 387 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[11\] -fixed false -x 671 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[31\].BUFD_BLK -fixed false -x 506 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.un1_o1ol1 -fixed false -x 350 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[30\] -fixed false -x 855 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_84 -fixed false -x 615 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[8\] -fixed false -x 238 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[20\] -fixed false -x 703 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[26\] -fixed false -x 941 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_5 -fixed false -x 471 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0 -fixed false -x 99 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[30\] -fixed false -x 623 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i_o3 -fixed false -x 429 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_midbit -fixed false -x 530 -y 151
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[25\] -fixed false -x 415 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[5\] -fixed false -x 637 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[9\] -fixed false -x 771 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[10\] -fixed false -x 730 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[0\] -fixed false -x 825 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[9\] -fixed false -x 726 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un26_il0Oo_0_a2 -fixed false -x 145 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[21\] -fixed false -x 886 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[18\] -fixed false -x 792 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1\[7\] -fixed false -x 371 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6 -fixed false -x 98 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[4\] -fixed false -x 492 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[24\] -fixed false -x 830 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[0\] -fixed false -x 124 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iio11 -fixed false -x 341 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[20\] -fixed false -x 410 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01\[8\] -fixed false -x 193 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid_0 -fixed false -x 805 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1126 -fixed false -x 638 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[9\] -fixed false -x 82 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIiO1 -fixed false -x 225 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01\[6\] -fixed false -x 60 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1\[5\] -fixed false -x 46 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[7\] -fixed false -x 646 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_0_1 -fixed false -x 652 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_95 -fixed false -x 614 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[29\] -fixed false -x 664 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[39\] -fixed false -x 657 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG\[3\] -fixed false -x 60 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[27\] -fixed false -x 803 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[3\] -fixed false -x 59 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[9\] -fixed false -x 126 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1 -fixed false -x 445 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_1 -fixed false -x 236 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_887 -fixed false -x 722 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_40 -fixed false -x 613 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int\[1\] -fixed false -x 769 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[1\] -fixed false -x 147 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[4\] -fixed false -x 52 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_37\[8\] -fixed false -x 937 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[19\] -fixed false -x 748 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].un1_lIII110 -fixed false -x 469 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_1_tz\[1\] -fixed false -x 38 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_bit_reset.state_val\[0\] -fixed false -x 756 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[0\] -fixed false -x 483 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[9\] -fixed false -x 961 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[10\] -fixed false -x 144 -y 205
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[12\] -fixed false -x 383 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_c_1_RNI3BNV01 -fixed false -x 769 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[6\] -fixed false -x 841 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[19\] -fixed false -x 933 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2\[29\] -fixed false -x 915 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_7_206_a2 -fixed false -x 317 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3_RNIEO6GT -fixed false -x 270 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[30\] -fixed false -x 854 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr\[1\] -fixed false -x 625 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[2\] -fixed false -x 782 -y 106
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_strb\[0\] -fixed false -x 808 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo -fixed false -x 264 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[14\] -fixed false -x 259 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIHDI4J\[15\] -fixed false -x 457 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[23\] -fixed false -x 458 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[37\] -fixed false -x 921 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m26 -fixed false -x 109 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1\[6\] -fixed false -x 302 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/un1_Ioli0_1_0 -fixed false -x 182 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[11\] -fixed false -x 231 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_8\[5\] -fixed false -x 186 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_0 -fixed false -x 659 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[16\] -fixed false -x 843 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[13\] -fixed false -x 807 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_970 -fixed false -x 619 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_o2\[22\] -fixed false -x 251 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01 -fixed false -x 100 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[3\] -fixed false -x 572 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[6\] -fixed false -x 195 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_7 -fixed false -x 277 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[5\] -fixed false -x 850 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m8_e_1 -fixed false -x 642 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[4\] -fixed false -x 784 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[0\] -fixed false -x 326 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[19\] -fixed false -x 298 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOi11 -fixed false -x 353 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[12\] -fixed false -x 678 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[20\] -fixed false -x 836 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_valid -fixed false -x 720 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1ll1 -fixed false -x 446 -y 193
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3\[1\] -fixed false -x 73 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[9\] -fixed false -x 405 -y 172
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tmsenb -fixed false -x 481 -y 97
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel_RNO -fixed false -x 505 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1 -fixed false -x 811 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[40\] -fixed false -x 645 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_RNO\[5\] -fixed false -x 314 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[4\] -fixed false -x 543 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[9\] -fixed false -x 874 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a1_0 -fixed false -x 774 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un96_lIlo1_1 -fixed false -x 147 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[11\] -fixed false -x 447 -y 153
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3\[2\] -fixed false -x 110 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un63_i11Io -fixed false -x 409 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a3_0_1\[2\] -fixed false -x 709 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[10\] -fixed false -x 590 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a3_2 -fixed false -x 180 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un9_empty_rd_1 -fixed false -x 631 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[10\] -fixed false -x 34 -y 226
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_515 -fixed false -x 627 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[16\] -fixed false -x 132 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[29\] -fixed false -x 724 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[19\] -fixed false -x 351 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_N_3L4_RNO -fixed false -x 645 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[25\] -fixed false -x 672 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[12\] -fixed false -x 140 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_474 -fixed false -x 688 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[20\] -fixed false -x 666 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1 -fixed false -x 238 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[30\] -fixed false -x 448 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1OOo -fixed false -x 121 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[9\] -fixed false -x 112 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[16\] -fixed false -x 750 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2_3 -fixed false -x 110 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_tick -fixed false -x 510 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[23\] -fixed false -x 181 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[6\] -fixed false -x 173 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[5\] -fixed false -x 176 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_APB_0_Read.prdata18_0_a2 -fixed false -x 488 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_602 -fixed false -x 685 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_reg -fixed false -x 721 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_727 -fixed false -x 710 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35\[8\] -fixed false -x 279 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_0_0\[0\] -fixed false -x 51 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_1\[4\] -fixed false -x 345 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[27\] -fixed false -x 235 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_1 -fixed false -x 109 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[19\] -fixed false -x 925 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_507 -fixed false -x 721 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[1\] -fixed false -x 565 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNO -fixed false -x 795 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[29\] -fixed false -x 697 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[16\] -fixed false -x 467 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lIOl1 -fixed false -x 387 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_ready_reg -fixed false -x 780 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/un1_Ioli0_1_0_0 -fixed false -x 316 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[9\] -fixed false -x 890 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[6\] -fixed false -x 111 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI44EG5\[5\] -fixed false -x 224 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1011 -fixed false -x 240 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1\[19\] -fixed false -x 451 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo\[15\] -fixed false -x 107 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[30\] -fixed false -x 951 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m26 -fixed false -x 72 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[30\] -fixed false -x 431 -y 169
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples\[2\] -fixed false -x 479 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[12\] -fixed false -x 714 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[15\] -fixed false -x 232 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[6\] -fixed false -x 183 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[47\] -fixed false -x 603 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[25\] -fixed false -x 468 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[0\] -fixed false -x 161 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code\[4\] -fixed false -x 42 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[57\] -fixed false -x 941 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO_0 -fixed false -x 864 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[11\] -fixed false -x 925 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_790 -fixed false -x 649 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m150 -fixed false -x 252 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1o11 -fixed false -x 275 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[21\] -fixed false -x 409 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3\[3\] -fixed false -x 240 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[1\] -fixed false -x 57 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[29\] -fixed false -x 130 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25\[9\] -fixed false -x 337 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[22\] -fixed false -x 399 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[8\] -fixed false -x 644 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[18\] -fixed false -x 434 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[1\] -fixed false -x 121 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_645 -fixed false -x 732 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_829 -fixed false -x 637 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOII1_RNO -fixed false -x 374 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_m5_0_a3 -fixed false -x 814 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[17\] -fixed false -x 341 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[50\] -fixed false -x 961 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[29\] -fixed false -x 701 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt\[7\] -fixed false -x 338 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2135_0 -fixed false -x 703 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1II1 -fixed false -x 323 -y 196
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[7\] -fixed false -x 381 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_resp_ready_RNIPEIRM3 -fixed false -x 799 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[19\] -fixed false -x 886 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[9\] -fixed false -x 689 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[15\] -fixed false -x 341 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_dummy_target -fixed false -x 747 -y 150
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc5 -fixed false -x 53 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1_1 -fixed false -x 50 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[6\] -fixed false -x 243 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[13\] -fixed false -x 828 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[18\] -fixed false -x 441 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[22\] -fixed false -x 806 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[17\] -fixed false -x 220 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/endofshift_2 -fixed false -x 486 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0\[2\] -fixed false -x 709 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[0\] -fixed false -x 198 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1257 -fixed false -x 782 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_4 -fixed false -x 420 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[8\] -fixed false -x 913 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[3\] -fixed false -x 737 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oli11 -fixed false -x 394 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_989 -fixed false -x 792 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[12\] -fixed false -x 42 -y 211
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO\[1\] -fixed false -x 480 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_x2\[3\] -fixed false -x 486 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_ld_req_buff_addr_misalign_iv -fixed false -x 736 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[15\] -fixed false -x 48 -y 231
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[28\] -fixed false -x 81 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[13\] -fixed false -x 355 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IlO11 -fixed false -x 18 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/IilI1 -fixed false -x 227 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/un1_Ioli0_1_0 -fixed false -x 318 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[55\] -fixed false -x 574 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[14\] -fixed false -x 589 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[37\] -fixed false -x 283 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[20\] -fixed false -x 939 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO_0 -fixed false -x 779 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[2\] -fixed false -x 844 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un63_I1Oi1_1 -fixed false -x 61 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[19\] -fixed false -x 775 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt\[2\] -fixed false -x 309 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[0\] -fixed false -x 446 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[39\] -fixed false -x 657 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25\[5\] -fixed false -x 254 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[11\] -fixed false -x 182 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[38\] -fixed false -x 358 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4\[1\] -fixed false -x 123 -y 210
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[18\] -fixed false -x 403 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[10\] -fixed false -x 253 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[14\] -fixed false -x 296 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_6 -fixed false -x 250 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[17\] -fixed false -x 315 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01\[0\] -fixed false -x 171 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3\[3\] -fixed false -x 566 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[11\] -fixed false -x 554 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[10\] -fixed false -x 407 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[19\] -fixed false -x 854 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_0_iv\[0\] -fixed false -x 742 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[4\] -fixed false -x 866 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0Ii1 -fixed false -x 173 -y 160
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state140_2 -fixed false -x 517 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0_1_0\[0\] -fixed false -x 249 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[7\] -fixed false -x 286 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/data_out_d\[16\] -fixed false -x 523 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[7\] -fixed false -x 210 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[4\] -fixed false -x 876 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[0\] -fixed false -x 162 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[1\] -fixed false -x 395 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[26\] -fixed false -x 926 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[7\] -fixed false -x 48 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iO0o1 -fixed false -x 93 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiOIo -fixed false -x 139 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[3\] -fixed false -x 90 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_2 -fixed false -x 89 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_next_buff_resp_wr_ptr -fixed false -x 716 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_2\[2\] -fixed false -x 734 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[4\] -fixed false -x 327 -y 154
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4\[2\] -fixed false -x 464 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[4\] -fixed false -x 255 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_ii1i1\[0\] -fixed false -x 185 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[3\] -fixed false -x 188 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4912 -fixed false -x 773 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[62\] -fixed false -x 598 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[15\] -fixed false -x 82 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_1_1 -fixed false -x 792 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoo1_i_0 -fixed false -x 111 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[2\] -fixed false -x 836 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[0\] -fixed false -x 522 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[22\] -fixed false -x 541 -y 172
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_rx_bit_cnt_1.CO1 -fixed false -x 467 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_87\[11\] -fixed false -x 274 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[7\] -fixed false -x 399 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_i_req_ready -fixed false -x 797 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb7_i_o3_RNIFL5ND -fixed false -x 685 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[8\] -fixed false -x 719 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[2\] -fixed false -x 169 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_2\[15\] -fixed false -x 943 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_33\[9\] -fixed false -x 297 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[8\] -fixed false -x 65 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[7\] -fixed false -x 939 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[4\] -fixed false -x 180 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[26\] -fixed false -x 596 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_apb -fixed false -x 802 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[15\] -fixed false -x 140 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[18\] -fixed false -x 962 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1iOo -fixed false -x 108 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0\[18\] -fixed false -x 97 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0\[1\] -fixed false -x 290 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1_RNO -fixed false -x 475 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[29\] -fixed false -x 909 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[30\] -fixed false -x 868 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_3\[7\] -fixed false -x 131 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op\[2\] -fixed false -x 812 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[31\] -fixed false -x 941 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1\[3\] -fixed false -x 138 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[7\] -fixed false -x 862 -y 130
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO\[3\] -fixed false -x 483 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[27\] -fixed false -x 842 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[7\] -fixed false -x 500 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[23\] -fixed false -x 764 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[7\] -fixed false -x 149 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/wr_data -fixed false -x 784 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_RNO -fixed false -x 379 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[14\] -fixed false -x 81 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[57\] -fixed false -x 547 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[3\] -fixed false -x 432 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[2\] -fixed false -x 493 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIP2FO8 -fixed false -x 312 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[30\] -fixed false -x 476 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[21\] -fixed false -x 656 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[9\] -fixed false -x 127 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2\[31\] -fixed false -x 746 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[3\] -fixed false -x 157 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[43\] -fixed false -x 321 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOi11 -fixed false -x 289 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[12\] -fixed false -x 71 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[2\] -fixed false -x 340 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_3_0_a2\[15\] -fixed false -x 134 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[10\] -fixed false -x 765 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[12\] -fixed false -x 47 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[25\] -fixed false -x 488 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1076 -fixed false -x 613 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[0\] -fixed false -x 621 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[0\] -fixed false -x 766 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[11\] -fixed false -x 201 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[17\] -fixed false -x 435 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_1 -fixed false -x 218 -y 192
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r -fixed false -x 392 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[25\] -fixed false -x 925 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[17\] -fixed false -x 845 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[7\] -fixed false -x 345 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[8\] -fixed false -x 162 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_apb_RNIGPOAJ9 -fixed false -x 793 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1182 -fixed false -x 617 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[15\] -fixed false -x 153 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/IilI1 -fixed false -x 286 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01\[7\] -fixed false -x 226 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1\[0\].machine_sw_wr_tdata1_mcontrol_execute_wr_en_1 -fixed false -x 686 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNI404DC2 -fixed false -x 49 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/o0iI1 -fixed false -x 324 -y 199
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[26\] -fixed false -x 410 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[3\] -fixed false -x 380 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[10\] -fixed false -x 553 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1_2 -fixed false -x 687 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_18_3_0 -fixed false -x 855 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[5\] -fixed false -x 137 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[1\] -fixed false -x 40 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oiIl18 -fixed false -x 465 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int\[2\] -fixed false -x 802 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[11\] -fixed false -x 109 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[8\] -fixed false -x 719 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oo0o1 -fixed false -x 97 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2 -fixed false -x 60 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[17\] -fixed false -x 742 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[20\] -fixed false -x 206 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex -fixed false -x 766 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_0_RNO_0 -fixed false -x 156 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[4\] -fixed false -x 760 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[47\] -fixed false -x 604 -y 175
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync\[1\] -fixed false -x 17 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[18\] -fixed false -x 780 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[13\] -fixed false -x 534 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_ndmreset -fixed false -x 760 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[21\] -fixed false -x 711 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[28\] -fixed false -x 937 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1_0_a2_0\[22\] -fixed false -x 319 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[7\] -fixed false -x 658 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[11\] -fixed false -x 343 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[6\] -fixed false -x 701 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0_RNIM211D -fixed false -x 757 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_825 -fixed false -x 710 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[4\] -fixed false -x 306 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_Olii1lto4_0 -fixed false -x 135 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]_RNILPGP9\[0\] -fixed false -x 884 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[3\] -fixed false -x 183 -y 202
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[3\] -fixed false -x 44 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[10\] -fixed false -x 404 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_o01O1_0 -fixed false -x 432 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[7\] -fixed false -x 106 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_1\[25\] -fixed false -x 111 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[8\] -fixed false -x 552 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[24\] -fixed false -x 751 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.lloIo -fixed false -x 259 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[19\] -fixed false -x 882 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_486 -fixed false -x 685 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[17\] -fixed false -x 740 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo_RNO_0 -fixed false -x 124 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[30\] -fixed false -x 950 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[0\] -fixed false -x 872 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_0 -fixed false -x 676 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m1 -fixed false -x 50 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/io0I1 -fixed false -x 403 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[22\] -fixed false -x 775 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0\[0\] -fixed false -x 550 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_o1i11_0_a2_3 -fixed false -x 344 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/toggle_hart_soft_reset -fixed false -x 568 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_lsu_op_complete_ex_RNII7SF8E2 -fixed false -x 779 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z\[1\] -fixed false -x 101 -y 208
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1\[0\] -fixed false -x 475 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[3\] -fixed false -x 452 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[0\] -fixed false -x 707 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_23_RNI7FA6M5 -fixed false -x 37 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[10\] -fixed false -x 401 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liI11 -fixed false -x 328 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[16\] -fixed false -x 876 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_368 -fixed false -x 673 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/II111 -fixed false -x 183 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[4\] -fixed false -x 157 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[7\] -fixed false -x 451 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[5\] -fixed false -x 758 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[1\] -fixed false -x 755 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_4 -fixed false -x 233 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[3\] -fixed false -x 892 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[17\] -fixed false -x 439 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[25\] -fixed false -x 849 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[1\] -fixed false -x 134 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv\[8\] -fixed false -x 626 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_str_amo_addr_misalign_0 -fixed false -x 798 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_9_0_RNO_0\[0\] -fixed false -x 792 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[5\] -fixed false -x 277 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[8\] -fixed false -x 469 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i -fixed false -x 286 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.OlIo1_0 -fixed false -x 299 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Olo11 -fixed false -x 407 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[5\] -fixed false -x 755 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_write_mux -fixed false -x 711 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1137 -fixed false -x 648 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[28\] -fixed false -x 486 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[1\] -fixed false -x 101 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_s_32_RNO -fixed false -x 807 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[15\] -fixed false -x 468 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[11\] -fixed false -x 86 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2\[11\] -fixed false -x 466 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[9\] -fixed false -x 894 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I1iOo -fixed false -x 110 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_861 -fixed false -x 648 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[13\] -fixed false -x 127 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[3\] -fixed false -x 229 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[30\] -fixed false -x 787 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.rx_filtered_2_i_o2 -fixed false -x 479 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[18\] -fixed false -x 478 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[10\] -fixed false -x 313 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[23\] -fixed false -x 468 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_30\[2\] -fixed false -x 344 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[0\] -fixed false -x 783 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[8\] -fixed false -x 593 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_0 -fixed false -x 681 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0\[5\] -fixed false -x 312 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[2\] -fixed false -x 164 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[2\] -fixed false -x 742 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[4\] -fixed false -x 529 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[15\] -fixed false -x 589 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1\[6\] -fixed false -x 535 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[14\] -fixed false -x 89 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un6_I0io1_1\[0\] -fixed false -x 54 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[23\] -fixed false -x 652 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[4\] -fixed false -x 385 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2 -fixed false -x 845 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[10\] -fixed false -x 294 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1\[3\] -fixed false -x 111 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[13\] -fixed false -x 503 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic1725 -fixed false -x 678 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0_RNICPD96 -fixed false -x 804 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1184 -fixed false -x 769 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[1\] -fixed false -x 651 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[15\] -fixed false -x 826 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[3\] -fixed false -x 337 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[20\] -fixed false -x 428 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/liIo1 -fixed false -x 319 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[0\] -fixed false -x 131 -y 178
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc_2 -fixed false -x 469 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[24\] -fixed false -x 243 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_m_1\[4\] -fixed false -x 640 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[6\] -fixed false -x 248 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m20 -fixed false -x 623 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1 -fixed false -x 63 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_RNO -fixed false -x 624 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[6\] -fixed false -x 317 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[11\] -fixed false -x 726 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m28 -fixed false -x 49 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[17\].BUFD_BLK -fixed false -x 486 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_i_retr -fixed false -x 758 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[3\] -fixed false -x 708 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[10\] -fixed false -x 711 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[28\] -fixed false -x 938 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[9\] -fixed false -x 886 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[29\] -fixed false -x 675 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_a2_3\[4\] -fixed false -x 730 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[17\] -fixed false -x 534 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[6\] -fixed false -x 72 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt\[9\] -fixed false -x 412 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[3\] -fixed false -x 132 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[16\] -fixed false -x 457 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[17\] -fixed false -x 892 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[4\] -fixed false -x 735 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[15\] -fixed false -x 380 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/un1_Ioli0_1_0 -fixed false -x 467 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[0\] -fixed false -x 219 -y 178
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_d_2_0 -fixed false -x 563 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/force_debug_nop_de_1 -fixed false -x 778 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2\[19\] -fixed false -x 38 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state134_1 -fixed false -x 516 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0_RNIUARJC1 -fixed false -x 817 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2s2_0_a2_0 -fixed false -x 761 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO\[13\] -fixed false -x 419 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/un1_oOo11_1_i -fixed false -x 107 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en\[2\] -fixed false -x 737 -y 126
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[8\] -fixed false -x 514 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[6\] -fixed false -x 227 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[7\] -fixed false -x 85 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[11\] -fixed false -x 305 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[3\] -fixed false -x 712 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[6\] -fixed false -x 938 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_4 -fixed false -x 652 -y 138
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_lcry_RNO_0 -fixed false -x 399 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[29\] -fixed false -x 836 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[9\] -fixed false -x 889 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i0o11 -fixed false -x 271 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[1\] -fixed false -x 128 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1\[5\] -fixed false -x 462 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_d -fixed false -x 775 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[15\] -fixed false -x 904 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z\[3\] -fixed false -x 291 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4\[0\] -fixed false -x 709 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01\[3\] -fixed false -x 205 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[15\] -fixed false -x 708 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_243 -fixed false -x 684 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[15\] -fixed false -x 74 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[40\] -fixed false -x 905 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[23\] -fixed false -x 852 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2 -fixed false -x 677 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_140 -fixed false -x 769 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[2\] -fixed false -x 75 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_250 -fixed false -x 625 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[27\] -fixed false -x 543 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[2\] -fixed false -x 773 -y 171
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[7\] -fixed false -x 392 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[6\] -fixed false -x 92 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[9\] -fixed false -x 433 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[17\] -fixed false -x 99 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io\[0\] -fixed false -x 476 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1_4 -fixed false -x 699 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[15\] -fixed false -x 378 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_0_sqmuxa_i_o3_0_RNIO97HQ -fixed false -x 220 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un2_O1Il1\[0\] -fixed false -x 461 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101\[1\] -fixed false -x 51 -y 199
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[11\].BUFD_BLK -fixed false -x 505 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[14\] -fixed false -x 803 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[15\] -fixed false -x 828 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14\[10\] -fixed false -x 936 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0_RNO\[3\] -fixed false -x 124 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo\[3\] -fixed false -x 273 -y 154
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/reset_lane -fixed false -x 19 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.awe0 -fixed false -x 661 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[21\] -fixed false -x 434 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[10\] -fixed false -x 229 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[9\] -fixed false -x 41 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[5\] -fixed false -x 785 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[3\] -fixed false -x 60 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5_1\[6\] -fixed false -x 729 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[7\] -fixed false -x 364 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[0\] -fixed false -x 438 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[13\] -fixed false -x 466 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[24\] -fixed false -x 355 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Ii1l1\[0\] -fixed false -x 411 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56 -fixed false -x 85 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_130_i -fixed false -x 681 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01\[0\] -fixed false -x 161 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[14\] -fixed false -x 496 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un62_o1Oi1 -fixed false -x 84 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2114_2 -fixed false -x 673 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[6\] -fixed false -x 673 -y 183
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3\[0\] -fixed false -x 505 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[12\] -fixed false -x 813 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[1\] -fixed false -x 478 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[9\] -fixed false -x 46 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[9\] -fixed false -x 773 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[0\] -fixed false -x 697 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_a3_1_1 -fixed false -x 100 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr\[4\] -fixed false -x 728 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[9\] -fixed false -x 849 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[7\] -fixed false -x 39 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[30\] -fixed false -x 125 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[9\] -fixed false -x 574 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_427 -fixed false -x 760 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_378 -fixed false -x 613 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[21\] -fixed false -x 474 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0\[3\] -fixed false -x 763 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[6\] -fixed false -x 30 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un95_ool01 -fixed false -x 192 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un3_Oll01_3 -fixed false -x 162 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[3\] -fixed false -x 763 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNIH4K4P3 -fixed false -x 827 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt\[8\] -fixed false -x 288 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[25\] -fixed false -x 320 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[26\] -fixed false -x 768 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[2\] -fixed false -x 364 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[19\] -fixed false -x 427 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[4\] -fixed false -x 670 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_2\[2\] -fixed false -x 952 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[11\] -fixed false -x 632 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[63\] -fixed false -x 594 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[24\] -fixed false -x 850 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[17\] -fixed false -x 704 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[18\] -fixed false -x 845 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[20\] -fixed false -x 808 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_3_0_1_0_RNIE6SVP -fixed false -x 773 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0 -fixed false -x 470 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iiol1 -fixed false -x 334 -y 208
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[2\] -fixed false -x 514 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[54\] -fixed false -x 556 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40\[2\] -fixed false -x 363 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[2\] -fixed false -x 68 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1\[0\] -fixed false -x 851 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[23\] -fixed false -x 375 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0\[8\] -fixed false -x 861 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[7\] -fixed false -x 235 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_14_1 -fixed false -x 638 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[29\] -fixed false -x 461 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_871 -fixed false -x 616 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_3 -fixed false -x 218 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[4\] -fixed false -x 521 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_5_1 -fixed false -x 647 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[19\] -fixed false -x 695 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[14\] -fixed false -x 148 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[1\] -fixed false -x 156 -y 205
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[4\] -fixed false -x 73 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0_RNIM211D_0 -fixed false -x 761 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[35\] -fixed false -x 641 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[0\] -fixed false -x 432 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[23\].BUFD_BLK -fixed false -x 504 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[5\] -fixed false -x 217 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[14\] -fixed false -x 397 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[1\] -fixed false -x 687 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001\[7\] -fixed false -x 57 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[18\] -fixed false -x 74 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRSH -fixed false -x 507 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[18\] -fixed false -x 531 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo\[0\] -fixed false -x 124 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0Oo -fixed false -x 156 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ii0l1\[0\] -fixed false -x 463 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[29\] -fixed false -x 418 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNIUU5SR -fixed false -x 749 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Ioi11 -fixed false -x 303 -y 207
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[7\] -fixed false -x 55 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[2\] -fixed false -x 897 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[1\] -fixed false -x 504 -y 94
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_11_RNIM2LRM -fixed false -x 26 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[3\] -fixed false -x 153 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_3_1 -fixed false -x 808 -y 144
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[22\].BUFD_BLK -fixed false -x 485 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel -fixed false -x 685 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[7\] -fixed false -x 589 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[15\] -fixed false -x 820 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0\[2\] -fixed false -x 257 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26\[0\] -fixed false -x 260 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2\[7\] -fixed false -x 58 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913_2 -fixed false -x 670 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[1\] -fixed false -x 64 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[29\] -fixed false -x 703 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_0_sqmuxa_i -fixed false -x 431 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_41\[8\] -fixed false -x 950 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_6 -fixed false -x 230 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIOQR5C\[21\] -fixed false -x 659 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[19\] -fixed false -x 691 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1160 -fixed false -x 720 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0oOo -fixed false -x 120 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ilIi1 -fixed false -x 172 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[2\] -fixed false -x 496 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO\[2\] -fixed false -x 594 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[7\] -fixed false -x 406 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[5\] -fixed false -x 144 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0_a2_0_2\[0\] -fixed false -x 625 -y 144
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_1 -fixed false -x 433 -y 9
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[16\] -fixed false -x 729 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2 -fixed false -x 98 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_o3\[1\] -fixed false -x 659 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[19\] -fixed false -x 600 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[1\] -fixed false -x 311 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[7\] -fixed false -x 711 -y 180
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_9\[0\] -fixed false -x 746 -y 43
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_11_tz_tz\[0\] -fixed false -x 864 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_67\[11\] -fixed false -x 300 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[23\] -fixed false -x 830 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0\[3\] -fixed false -x 142 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state136_RNI6PQT9 -fixed false -x 518 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[17\] -fixed false -x 777 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[0\] -fixed false -x 192 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[18\] -fixed false -x 449 -y 157
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[22\] -fixed false -x 380 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io\[5\] -fixed false -x 54 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[12\] -fixed false -x 231 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[15\] -fixed false -x 135 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01 -fixed false -x 217 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[5\] -fixed false -x 62 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_294 -fixed false -x 612 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/tx_alldone -fixed false -x 522 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_TCM_byte_shim.un7_cpu_d_req_wr_byte_en_sel -fixed false -x 693 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o2\[0\] -fixed false -x 123 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[34\] -fixed false -x 510 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo\[7\] -fixed false -x 300 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[21\] -fixed false -x 709 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1\[19\] -fixed false -x 468 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[18\] -fixed false -x 742 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_RNII5V8F\[2\] -fixed false -x 175 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_853 -fixed false -x 673 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[11\] -fixed false -x 730 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_110_i -fixed false -x 711 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_9\[0\] -fixed false -x 266 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[30\] -fixed false -x 738 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[17\] -fixed false -x 667 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[5\] -fixed false -x 143 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_344 -fixed false -x 697 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z\[1\] -fixed false -x 437 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[5\] -fixed false -x 497 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_RNO\[0\] -fixed false -x 651 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m69 -fixed false -x 27 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_23_0_RNO -fixed false -x 815 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_431 -fixed false -x 672 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[11\] -fixed false -x 494 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[1\] -fixed false -x 493 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[39\] -fixed false -x 908 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[17\] -fixed false -x 749 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_732 -fixed false -x 615 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[1\] -fixed false -x 398 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[28\] -fixed false -x 379 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001_RNIP0F2N\[0\] -fixed false -x 95 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe -fixed false -x 531 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[1\] -fixed false -x 186 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0_1_0\[0\] -fixed false -x 342 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[3\] -fixed false -x 396 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un30_OIoO1 -fixed false -x 51 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[34\] -fixed false -x 112 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/iOIl1 -fixed false -x 403 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[12\] -fixed false -x 143 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_mode -fixed false -x 771 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo\[4\] -fixed false -x 93 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[12\] -fixed false -x 35 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[35\] -fixed false -x 492 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[25\] -fixed false -x 504 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_258 -fixed false -x 722 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i0l11 -fixed false -x 286 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01_RNO -fixed false -x 83 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_6 -fixed false -x 734 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[1\] -fixed false -x 139 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[31\] -fixed false -x 630 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[6\] -fixed false -x 208 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un171_I1Oi1_0 -fixed false -x 42 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[1\] -fixed false -x 789 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[10\] -fixed false -x 830 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[2\] -fixed false -x 361 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[20\] -fixed false -x 841 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[26\] -fixed false -x 548 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un13_oI0i1_1 -fixed false -x 111 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead -fixed false -x 537 -y 145
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[7\] -fixed false -x 54 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[29\] -fixed false -x 694 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[14\] -fixed false -x 535 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto4_1 -fixed false -x 136 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[10\] -fixed false -x 241 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO -fixed false -x 900 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[19\] -fixed false -x 351 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_3_RNO\[0\] -fixed false -x 48 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[9\] -fixed false -x 913 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un23_next_buff_resp_wr_ptr_1_sqmuxa -fixed false -x 713 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[19\] -fixed false -x 91 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_5\[0\] -fixed false -x 626 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/hipri_req_ptr_RNO\[0\] -fixed false -x 721 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIOA2JA -fixed false -x 764 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[22\] -fixed false -x 932 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0_1_0\[0\] -fixed false -x 330 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/o11l1 -fixed false -x 401 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1067 -fixed false -x 601 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[3\] -fixed false -x 442 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2\[5\] -fixed false -x 115 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_OOii1_0_a2 -fixed false -x 132 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2_1\[4\] -fixed false -x 104 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un41_ool01 -fixed false -x 49 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]\[2\] -fixed false -x 750 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[28\] -fixed false -x 667 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[31\] -fixed false -x 926 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[13\] -fixed false -x 774 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[0\] -fixed false -x 256 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00015 -fixed false -x 63 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[5\] -fixed false -x 427 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[10\] -fixed false -x 279 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_16_0_RNO -fixed false -x 833 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[9\] -fixed false -x 498 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/emi_resp_head_uncompressed_full_0_a2 -fixed false -x 656 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[31\] -fixed false -x 423 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[1\] -fixed false -x 506 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[14\] -fixed false -x 928 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted\[5\] -fixed false -x 841 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[17\] -fixed false -x 691 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE -fixed false -x 304 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un1_ex_retr_pipe_curr_pc_retr -fixed false -x 775 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4\[17\] -fixed false -x 72 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o0111 -fixed false -x 130 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m31 -fixed false -x 618 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[7\] -fixed false -x 744 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[30\] -fixed false -x 841 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[3\] -fixed false -x 384 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_RNO\[0\] -fixed false -x 761 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z\[4\] -fixed false -x 426 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[14\] -fixed false -x 620 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[36\] -fixed false -x 624 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO\[13\] -fixed false -x 147 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[18\] -fixed false -x 809 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[30\] -fixed false -x 737 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0\[4\] -fixed false -x 83 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[18\] -fixed false -x 876 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_sn_m4 -fixed false -x 766 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[8\] -fixed false -x 266 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0\[7\] -fixed false -x 722 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo\[11\] -fixed false -x 103 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 490 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_286 -fixed false -x 687 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01\[7\] -fixed false -x 145 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2_2\[4\] -fixed false -x 121 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q\[3\] -fixed false -x 495 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[6\] -fixed false -x 849 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_exce\[0\] -fixed false -x 758 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un5_l1ll1 -fixed false -x 479 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[18\] -fixed false -x 85 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[13\] -fixed false -x 934 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3\[11\] -fixed false -x 291 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[3\] -fixed false -x 178 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[5\] -fixed false -x 745 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1O11 -fixed false -x 84 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[1\] -fixed false -x 412 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2s2_0_a3_0 -fixed false -x 752 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iOo -fixed false -x 128 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9\[3\] -fixed false -x 732 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[31\] -fixed false -x 783 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[31\] -fixed false -x 406 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[12\] -fixed false -x 35 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[17\] -fixed false -x 847 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr\[0\] -fixed false -x 782 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[16\] -fixed false -x 445 -y 213
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[18\] -fixed false -x 409 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m209 -fixed false -x 254 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[12\] -fixed false -x 842 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1200 -fixed false -x 684 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_1\[6\] -fixed false -x 950 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_i_RNO\[4\] -fixed false -x 870 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICPK9D -fixed false -x 722 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOl11 -fixed false -x 250 -y 190
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[1\] -fixed false -x 480 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[5\] -fixed false -x 171 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[12\] -fixed false -x 244 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_24 -fixed false -x 709 -y 150
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_fifo_rd_en_0 -fixed false -x 387 -y 237
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[29\] -fixed false -x 685 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[24\] -fixed false -x 67 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[10\] -fixed false -x 351 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[56\] -fixed false -x 936 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[7\] -fixed false -x 419 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1_0\[1\] -fixed false -x 713 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo_i_o2_0\[3\] -fixed false -x 296 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_a2\[31\] -fixed false -x 780 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[26\] -fixed false -x 359 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0_iv\[0\] -fixed false -x 721 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[5\] -fixed false -x 901 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[7\] -fixed false -x 351 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1 -fixed false -x 309 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_480 -fixed false -x 628 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[26\] -fixed false -x 854 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[11\] -fixed false -x 830 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[25\] -fixed false -x 476 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_o3 -fixed false -x 90 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z\[39\] -fixed false -x 447 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[2\] -fixed false -x 111 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[0\] -fixed false -x 767 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[2\] -fixed false -x 309 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001\[2\] -fixed false -x 82 -y 157
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[10\] -fixed false -x 19 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO_1 -fixed false -x 840 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[9\] -fixed false -x 742 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[1\] -fixed false -x 231 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data\[14\] -fixed false -x 723 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[23\] -fixed false -x 563 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_0_tz\[20\] -fixed false -x 149 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lio11 -fixed false -x 325 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr_0\[0\] -fixed false -x 827 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[12\] -fixed false -x 792 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[20\] -fixed false -x 469 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[15\] -fixed false -x 287 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto5 -fixed false -x 135 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/empty_rd -fixed false -x 635 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[4\] -fixed false -x 112 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_0\[0\] -fixed false -x 636 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI8LK9D -fixed false -x 824 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiiOo\[0\] -fixed false -x 127 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIOl1 -fixed false -x 451 -y 192
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[7\] -fixed false -x 455 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv\[1\] -fixed false -x 758 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[30\] -fixed false -x 468 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 253 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[8\] -fixed false -x 673 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_3 -fixed false -x 385 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[15\] -fixed false -x 843 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[26\] -fixed false -x 776 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[9\] -fixed false -x 457 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_1\[29\] -fixed false -x 927 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[0\] -fixed false -x 213 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[25\] -fixed false -x 736 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0\[6\] -fixed false -x 645 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[3\] -fixed false -x 116 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[16\] -fixed false -x 936 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[9\] -fixed false -x 301 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[2\] -fixed false -x 196 -y 211
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_q_1.CO1 -fixed false -x 555 -y 156
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_s3_i -fixed false -x 60 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[22\] -fixed false -x 859 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNIVTR8H -fixed false -x 760 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[48\] -fixed false -x 567 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[0\] -fixed false -x 90 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[25\] -fixed false -x 670 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_0\[4\] -fixed false -x 637 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[4\] -fixed false -x 396 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0\[7\] -fixed false -x 507 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un8_l00o1 -fixed false -x 110 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[13\] -fixed false -x 860 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[15\] -fixed false -x 88 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNIFJ3KL -fixed false -x 717 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913_2_0 -fixed false -x 618 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr\[1\] -fixed false -x 671 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loli1 -fixed false -x 203 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lil11 -fixed false -x 432 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO0Oo -fixed false -x 165 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[7\] -fixed false -x 539 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRUPD -fixed false -x 506 -y 90
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv\[5\] -fixed false -x 747 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0\[4\] -fixed false -x 244 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO_0\[1\] -fixed false -x 768 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[31\] -fixed false -x 756 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0\[7\] -fixed false -x 443 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo\[3\] -fixed false -x 227 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[29\] -fixed false -x 633 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[9\] -fixed false -x 559 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[30\] -fixed false -x 549 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid_RNI9OFR8 -fixed false -x 729 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[4\] -fixed false -x 27 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[12\] -fixed false -x 436 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7\[5\] -fixed false -x 276 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[16\] -fixed false -x 84 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_1\[3\] -fixed false -x 726 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[15\] -fixed false -x 878 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_data_valid_ex_0 -fixed false -x 809 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[0\] -fixed false -x 426 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv_RNO\[10\] -fixed false -x 640 -y 126
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[11\] -fixed false -x 554 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[3\] -fixed false -x 759 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0\[8\] -fixed false -x 247 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[5\] -fixed false -x 601 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[28\] -fixed false -x 386 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un27_I1Oi1_2 -fixed false -x 47 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[22\] -fixed false -x 385 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2_\[7\] -fixed false -x 707 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1_5 -fixed false -x 706 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1103 -fixed false -x 756 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[7\] -fixed false -x 70 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_2_0 -fixed false -x 794 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_ex -fixed false -x 817 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1_RNIN92R7\[2\] -fixed false -x 42 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[1\] -fixed false -x 373 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[16\] -fixed false -x 717 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24\[1\] -fixed false -x 265 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[0\] -fixed false -x 193 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[12\] -fixed false -x 823 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[22\] -fixed false -x 557 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[16\] -fixed false -x 477 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex\[1\] -fixed false -x 758 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_401 -fixed false -x 711 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1177 -fixed false -x 589 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oiII1 -fixed false -x 320 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[16\] -fixed false -x 840 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_702 -fixed false -x 759 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[9\] -fixed false -x 231 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_850 -fixed false -x 758 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt\[2\] -fixed false -x 309 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OOi11 -fixed false -x 337 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[19\] -fixed false -x 938 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_10_iv_i\[0\] -fixed false -x 523 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[6\] -fixed false -x 679 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[30\] -fixed false -x 432 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_o12 -fixed false -x 686 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[9\] -fixed false -x 791 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[2\] -fixed false -x 281 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[19\] -fixed false -x 858 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[17\] -fixed false -x 452 -y 213
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_RNIS69MA -fixed false -x 529 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_5 -fixed false -x 697 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m101 -fixed false -x 176 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[21\] -fixed false -x 571 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[10\] -fixed false -x 509 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_5 -fixed false -x 33 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z\[7\] -fixed false -x 309 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOoI1 -fixed false -x 409 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001_RNO -fixed false -x 93 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[3\] -fixed false -x 230 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[7\] -fixed false -x 130 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo\[2\] -fixed false -x 121 -y 172
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_RNILMIFJ -fixed false -x 505 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un25_I1oo1 -fixed false -x 72 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[6\] -fixed false -x 635 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[12\] -fixed false -x 132 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOOIo\[0\] -fixed false -x 99 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[3\] -fixed false -x 204 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[25\] -fixed false -x 839 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[14\] -fixed false -x 288 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_923 -fixed false -x 626 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_463 -fixed false -x 649 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_7\[13\] -fixed false -x 678 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[9\] -fixed false -x 297 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[11\] -fixed false -x 697 -y 129
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/un1_tx_parity_1_sqmuxa_0 -fixed false -x 448 -y 147
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_tckgo_2_sqmuxa_0_tz -fixed false -x 504 -y 99
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[7\] -fixed false -x 141 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_o2\[4\] -fixed false -x 194 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[20\] -fixed false -x 886 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[4\] -fixed false -x 385 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1\[1\] -fixed false -x 94 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[21\] -fixed false -x 669 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[8\] -fixed false -x 151 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[11\] -fixed false -x 343 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oioOo_1 -fixed false -x 100 -y 159
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[2\].BUFD_BLK -fixed false -x 483 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[32\] -fixed false -x 624 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_1 -fixed false -x 806 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[26\] -fixed false -x 68 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0\[4\] -fixed false -x 203 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/IilI1_RNO -fixed false -x 286 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[29\] -fixed false -x 887 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[9\] -fixed false -x 204 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lioi1 -fixed false -x 148 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[31\] -fixed false -x 895 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[11\] -fixed false -x 84 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m50 -fixed false -x 26 -y 189
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_2\[0\] -fixed false -x 744 -y 4
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[1\].buff_valid\[1\] -fixed false -x 780 -y 136
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[29\] -fixed false -x 417 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[1\] -fixed false -x 878 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0\[14\] -fixed false -x 679 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_2 -fixed false -x 668 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0\[3\] -fixed false -x 706 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[9\] -fixed false -x 484 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[22\] -fixed false -x 806 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[30\] -fixed false -x 833 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto3 -fixed false -x 132 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[5\] -fixed false -x 194 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[2\] -fixed false -x 125 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[4\] -fixed false -x 767 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[2\] -fixed false -x 136 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[1\] -fixed false -x 47 -y 184
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[15\] -fixed false -x 553 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[1\] -fixed false -x 64 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25_1\[10\] -fixed false -x 336 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[20\] -fixed false -x 184 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m9 -fixed false -x 120 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa -fixed false -x 480 -y 159
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[3\] -fixed false -x 41 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[8\] -fixed false -x 205 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[26\] -fixed false -x 874 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[19\] -fixed false -x 839 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001 -fixed false -x 89 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[5\] -fixed false -x 231 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[11\] -fixed false -x 837 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[18\] -fixed false -x 861 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_46\[11\] -fixed false -x 332 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1_2 -fixed false -x 133 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[25\] -fixed false -x 865 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[7\] -fixed false -x 517 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[8\] -fixed false -x 143 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_5\[0\] -fixed false -x 627 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[52\] -fixed false -x 571 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt\[2\] -fixed false -x 190 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[8\] -fixed false -x 432 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg\[1\] -fixed false -x 703 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[7\] -fixed false -x 850 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[13\] -fixed false -x 135 -y 192
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[25\] -fixed false -x 412 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/li1l1\[2\] -fixed false -x 422 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIoOo -fixed false -x 124 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[30\] -fixed false -x 466 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lo0l1\[0\] -fixed false -x 447 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0\[15\] -fixed false -x 161 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1169 -fixed false -x 672 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftIR_ne_0_3 -fixed false -x 557 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff\[0\] -fixed false -x 723 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6\[6\] -fixed false -x 434 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[6\] -fixed false -x 867 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[14\] -fixed false -x 255 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[4\] -fixed false -x 840 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[28\] -fixed false -x 679 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[27\] -fixed false -x 846 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[5\] -fixed false -x 589 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[11\] -fixed false -x 909 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[30\] -fixed false -x 850 -y 139
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01\[4\] -fixed false -x 176 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[5\] -fixed false -x 160 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex\[1\] -fixed false -x 770 -y 154
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[18\].BUFD_BLK -fixed false -x 484 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[10\] -fixed false -x 495 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[10\] -fixed false -x 681 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_status_mpie_wr_en -fixed false -x 727 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[18\] -fixed false -x 844 -y 145
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[3\] -fixed false -x 446 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[22\] -fixed false -x 741 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u_RNO -fixed false -x 867 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_0\[23\] -fixed false -x 181 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[5\] -fixed false -x 121 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[5\] -fixed false -x 572 -y 139
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[10\] -fixed false -x 725 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a2_1 -fixed false -x 193 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[6\] -fixed false -x 566 -y 117
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out -fixed false -x 523 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRJFFD\[7\] -fixed false -x 646 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z\[7\] -fixed false -x 234 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt\[8\] -fixed false -x 361 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[26\] -fixed false -x 403 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[9\] -fixed false -x 91 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[8\] -fixed false -x 638 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[2\] -fixed false -x 316 -y 186
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/reset_lane_RNIJDIL7 -fixed false -x 17 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[2\] -fixed false -x 723 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_1 -fixed false -x 495 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[0\] -fixed false -x 540 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_28 -fixed false -x 80 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[11\] -fixed false -x 290 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_2\[2\] -fixed false -x 141 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1156 -fixed false -x 555 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[16\] -fixed false -x 741 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111 -fixed false -x 390 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[1\] -fixed false -x 438 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un189_I1Oi1 -fixed false -x 36 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_2\[9\] -fixed false -x 292 -y 156
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[2\] -fixed false -x 491 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ii0i1_RNO -fixed false -x 183 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[16\] -fixed false -x 699 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[4\] -fixed false -x 290 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[19\] -fixed false -x 762 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[18\] -fixed false -x 822 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[13\] -fixed false -x 408 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/III11 -fixed false -x 342 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_instr_is_lsu_op_retr_0_tz -fixed false -x 811 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[44\] -fixed false -x 916 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[6\] -fixed false -x 812 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un31_trap_val -fixed false -x 725 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0\[6\] -fixed false -x 186 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[10\] -fixed false -x 921 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[24\] -fixed false -x 852 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[13\] -fixed false -x 274 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1\[9\] -fixed false -x 377 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[8\] -fixed false -x 372 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3\[1\] -fixed false -x 511 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIoO1_RNIBVKRO -fixed false -x 170 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[19\] -fixed false -x 695 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[7\] -fixed false -x 343 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[23\] -fixed false -x 463 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2_4 -fixed false -x 273 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[3\] -fixed false -x 315 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_count_0_sqmuxa -fixed false -x 507 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[21\] -fixed false -x 640 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlIo1 -fixed false -x 299 -y 211
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state\[4\] -fixed false -x 518 -y 100
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1_2 -fixed false -x 554 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[28\] -fixed false -x 904 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[16\] -fixed false -x 936 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[5\] -fixed false -x 890 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_769 -fixed false -x 614 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0\[5\] -fixed false -x 210 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_1 -fixed false -x 797 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a2\[0\] -fixed false -x 331 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[6\] -fixed false -x 361 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un83_I1Oi1 -fixed false -x 25 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1\[1\] -fixed false -x 809 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_2\[0\] -fixed false -x 645 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[24\] -fixed false -x 542 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl15 -fixed false -x 464 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[12\] -fixed false -x 758 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[10\] -fixed false -x 411 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_a2_0\[1\] -fixed false -x 293 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[21\] -fixed false -x 713 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[19\] -fixed false -x 891 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_I1iIo_1 -fixed false -x 458 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[6\] -fixed false -x 441 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO\[0\] -fixed false -x 127 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[10\] -fixed false -x 572 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_loOo1_0_a2 -fixed false -x 297 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ\[23\] -fixed false -x 705 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[5\] -fixed false -x 639 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_473 -fixed false -x 588 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0_a3\[15\] -fixed false -x 222 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1_RNO -fixed false -x 23 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[19\] -fixed false -x 888 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_956 -fixed false -x 721 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[21\] -fixed false -x 800 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_198 -fixed false -x 696 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_212 -fixed false -x 613 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[11\] -fixed false -x 228 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[9\] -fixed false -x 143 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[2\] -fixed false -x 172 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3\[4\] -fixed false -x 853 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[14\] -fixed false -x 857 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[12\] -fixed false -x 524 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_RNI3TSFL -fixed false -x 736 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/un1_Ioli0_1_0 -fixed false -x 314 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13\[11\] -fixed false -x 291 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 481 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/un1_iOI01_1_i_0 -fixed false -x 197 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_O0oi1_0_a2 -fixed false -x 222 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[8\] -fixed false -x 783 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2 -fixed false -x 838 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_525 -fixed false -x 650 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1000 -fixed false -x 671 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[13\] -fixed false -x 474 -y 207
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[2\].BUFD_BLK -fixed false -x 483 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4\[12\] -fixed false -x 353 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[29\] -fixed false -x 473 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[3\] -fixed false -x 895 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[13\] -fixed false -x 466 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic537 -fixed false -x 825 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[10\] -fixed false -x 73 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[20\] -fixed false -x 716 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt\[2\] -fixed false -x 185 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[15\] -fixed false -x 638 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIHNUT5 -fixed false -x 391 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[5\] -fixed false -x 373 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[1\] -fixed false -x 417 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo\[0\] -fixed false -x 127 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[5\] -fixed false -x 426 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[7\] -fixed false -x 737 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_q2 -fixed false -x 530 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[11\] -fixed false -x 828 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[2\] -fixed false -x 716 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[14\] -fixed false -x 943 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[8\] -fixed false -x 721 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[16\] -fixed false -x 406 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo54 -fixed false -x 84 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_o2 -fixed false -x 63 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[8\] -fixed false -x 278 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[2\] -fixed false -x 75 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loi01\[3\] -fixed false -x 47 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv\[0\] -fixed false -x 667 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OlOOo_0_a3_1 -fixed false -x 139 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47 -fixed false -x 734 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[28\] -fixed false -x 264 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1\[14\] -fixed false -x 213 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_o3_RNIUOLVM -fixed false -x 219 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_1\[5\] -fixed false -x 726 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[43\] -fixed false -x 286 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv\[0\] -fixed false -x 31 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[29\] -fixed false -x 872 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[6\] -fixed false -x 271 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand0_mux_sel_1_iv_2\[0\] -fixed false -x 746 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_61 -fixed false -x 710 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1\[3\] -fixed false -x 357 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[30\] -fixed false -x 927 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[22\] -fixed false -x 904 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_685 -fixed false -x 613 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3\[0\] -fixed false -x 597 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[33\] -fixed false -x 638 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Iiil1 -fixed false -x 527 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[20\] -fixed false -x 853 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[0\] -fixed false -x 695 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_33 -fixed false -x 664 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_7 -fixed false -x 680 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[13\] -fixed false -x 221 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_549 -fixed false -x 644 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0\[1\] -fixed false -x 110 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12_1\[0\] -fixed false -x 156 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo_5 -fixed false -x 264 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/illi1 -fixed false -x 188 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[5\] -fixed false -x 505 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1I1 -fixed false -x 520 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[7\] -fixed false -x 673 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[11\] -fixed false -x 128 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_cmd_transfer_ff -fixed false -x 766 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[6\] -fixed false -x 156 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1\[1\] -fixed false -x 404 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[10\] -fixed false -x 207 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[26\] -fixed false -x 940 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[3\] -fixed false -x 756 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01\[0\] -fixed false -x 168 -y 190
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[14\] -fixed false -x 384 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr\[0\] -fixed false -x 827 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1\[6\] -fixed false -x 330 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1206 -fixed false -x 626 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[4\] -fixed false -x 437 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[26\] -fixed false -x 471 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_operand_sel_1_iv\[1\] -fixed false -x 721 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[17\] -fixed false -x 839 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[9\] -fixed false -x 865 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ioi01 -fixed false -x 70 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/IilI1 -fixed false -x 391 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[12\] -fixed false -x 320 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[5\] -fixed false -x 119 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z\[0\] -fixed false -x 787 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo\[0\] -fixed false -x 215 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[17\] -fixed false -x 700 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_4 -fixed false -x 216 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[7\] -fixed false -x 637 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3\[1\] -fixed false -x 735 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[23\] -fixed false -x 681 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[20\] -fixed false -x 742 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_2_3 -fixed false -x 129 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_49\[8\] -fixed false -x 938 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[29\] -fixed false -x 353 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1\[1\] -fixed false -x 159 -y 193
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_ac0_3 -fixed false -x 56 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[1\] -fixed false -x 139 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[5\] -fixed false -x 658 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_469 -fixed false -x 680 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_6_182_a2 -fixed false -x 433 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[5\] -fixed false -x 126 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt\[11\] -fixed false -x 363 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[17\] -fixed false -x 926 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[24\] -fixed false -x 451 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_iv_0 -fixed false -x 745 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[4\] -fixed false -x 856 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01 -fixed false -x 83 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[56\] -fixed false -x 545 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig\[3\] -fixed false -x 668 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[31\] -fixed false -x 753 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_1\[8\] -fixed false -x 122 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[18\] -fixed false -x 248 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_961 -fixed false -x 735 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un19_IoOi1_i -fixed false -x 169 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[7\] -fixed false -x 913 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[9\] -fixed false -x 84 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[25\] -fixed false -x 818 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3_RNI420PL -fixed false -x 269 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2\[28\] -fixed false -x 133 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[11\] -fixed false -x 413 -y 217
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UTDI -fixed false -x 482 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[17\] -fixed false -x 767 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[10\] -fixed false -x 434 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[32\] -fixed false -x 615 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[14\] -fixed false -x 49 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic852_2 -fixed false -x 603 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO -fixed false -x 828 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[4\] -fixed false -x 778 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_2 -fixed false -x 672 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[19\] -fixed false -x 645 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[3\] -fixed false -x 425 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un6_I0io1\[0\] -fixed false -x 51 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[27\] -fixed false -x 228 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1\[2\] -fixed false -x 151 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOOIo\[0\] -fixed false -x 97 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3\[1\] -fixed false -x 685 -y 117
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc_4_u -fixed false -x 478 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ilo11 -fixed false -x 405 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_1 -fixed false -x 829 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3 -fixed false -x 256 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO0i1 -fixed false -x 152 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_N_4L6_RNIUQTG44 -fixed false -x 796 -y 138
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv\[7\] -fixed false -x 573 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[9\] -fixed false -x 394 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132 -fixed false -x 681 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[10\] -fixed false -x 759 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[21\] -fixed false -x 592 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_6_1 -fixed false -x 794 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel_0 -fixed false -x 699 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_0_sqmuxa_0_a2 -fixed false -x 458 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z\[2\] -fixed false -x 41 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[3\] -fixed false -x 250 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/oio01 -fixed false -x 77 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_779 -fixed false -x 709 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[7\] -fixed false -x 162 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[5\] -fixed false -x 374 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[24\] -fixed false -x 375 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[1\] -fixed false -x 230 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_a2\[3\] -fixed false -x 288 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[6\] -fixed false -x 492 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[4\] -fixed false -x 108 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNILL54U -fixed false -x 886 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[29\] -fixed false -x 472 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[11\] -fixed false -x 542 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ooo01 -fixed false -x 129 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[5\] -fixed false -x 785 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[10\] -fixed false -x 861 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[15\] -fixed false -x 135 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[9\] -fixed false -x 465 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[4\] -fixed false -x 76 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[5\] -fixed false -x 529 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00018 -fixed false -x 65 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[10\] -fixed false -x 722 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0\[2\] -fixed false -x 192 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[9\] -fixed false -x 245 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[18\] -fixed false -x 925 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_2 -fixed false -x 660 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_745 -fixed false -x 697 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ooil1 -fixed false -x 519 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIGU4M11 -fixed false -x 907 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[8\] -fixed false -x 920 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[5\] -fixed false -x 296 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1\[2\] -fixed false -x 143 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_2_3\[7\] -fixed false -x 123 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001\[1\] -fixed false -x 77 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNID84LE\[3\] -fixed false -x 794 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_18 -fixed false -x 660 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[9\] -fixed false -x 698 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olo11_1 -fixed false -x 359 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[17\] -fixed false -x 705 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_0_2 -fixed false -x 813 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[13\] -fixed false -x 759 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[2\] -fixed false -x 206 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_7 -fixed false -x 145 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l15 -fixed false -x 401 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[27\] -fixed false -x 918 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val\[9\] -fixed false -x 764 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[1\] -fixed false -x 234 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[28\] -fixed false -x 961 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[48\] -fixed false -x 965 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_856 -fixed false -x 625 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_rxbusy -fixed false -x 499 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2\[25\] -fixed false -x 688 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[13\] -fixed false -x 254 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[16\] -fixed false -x 880 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1132 -fixed false -x 612 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[18\] -fixed false -x 537 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[4\] -fixed false -x 339 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1i01 -fixed false -x 126 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_i0lo1\[14\] -fixed false -x 352 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[23\] -fixed false -x 679 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[15\] -fixed false -x 826 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0\[0\] -fixed false -x 414 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOOIo\[0\] -fixed false -x 98 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO\[3\] -fixed false -x 729 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[8\] -fixed false -x 189 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_2\[2\] -fixed false -x 746 -y 126
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[5\] -fixed false -x 18 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[9\] -fixed false -x 794 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_6 -fixed false -x 216 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z\[14\] -fixed false -x 136 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[4\] -fixed false -x 41 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[3\] -fixed false -x 115 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1I11 -fixed false -x 127 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[4\] -fixed false -x 28 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[5\] -fixed false -x 37 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1190 -fixed false -x 745 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/un1_Ioli0_1_0 -fixed false -x 243 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[11\] -fixed false -x 591 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0\[12\] -fixed false -x 127 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ooli1 -fixed false -x 200 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3\[25\] -fixed false -x 705 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1110 -fixed false -x 626 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul -fixed false -x 793 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[16\] -fixed false -x 949 -y 138
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc5 -fixed false -x 50 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[9\] -fixed false -x 453 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt\[10\] -fixed false -x 253 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[6\] -fixed false -x 499 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[26\] -fixed false -x 127 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[20\] -fixed false -x 408 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un16_OOOI1\[9\] -fixed false -x 348 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[22\] -fixed false -x 815 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[17\] -fixed false -x 443 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[9\] -fixed false -x 397 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001\[1\] -fixed false -x 64 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[30\] -fixed false -x 840 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1\[8\] -fixed false -x 515 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo_RNI8G024_0 -fixed false -x 35 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[2\] -fixed false -x 135 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[22\] -fixed false -x 458 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1\[9\] -fixed false -x 175 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo -fixed false -x 23 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_648 -fixed false -x 695 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[31\] -fixed false -x 820 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[2\] -fixed false -x 451 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIOF68E\[18\] -fixed false -x 642 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_255 -fixed false -x 638 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[1\] -fixed false -x 384 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo\[1\] -fixed false -x 288 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Oo1l1 -fixed false -x 396 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[15\] -fixed false -x 826 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o10Oo_3 -fixed false -x 147 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_compressed -fixed false -x 626 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51\[9\] -fixed false -x 908 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[19\] -fixed false -x 890 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[23\] -fixed false -x 786 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_o7_0\[4\] -fixed false -x 23 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_7 -fixed false -x 692 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15\[20\] -fixed false -x 349 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_4_RNO -fixed false -x 380 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[1\] -fixed false -x 425 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[6\] -fixed false -x 123 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_\[36\] -fixed false -x 632 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[30\] -fixed false -x 667 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[22\] -fixed false -x 396 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1 -fixed false -x 576 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff -fixed false -x 673 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.lloIo -fixed false -x 323 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[1\] -fixed false -x 181 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_alu_op_completing_ex_s -fixed false -x 773 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[16\] -fixed false -x 456 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lOiO1 -fixed false -x 326 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[9\] -fixed false -x 178 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[27\] -fixed false -x 676 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[8\] -fixed false -x 370 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[29\] -fixed false -x 824 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_0_0\[3\] -fixed false -x 744 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[1\] -fixed false -x 77 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[38\] -fixed false -x 510 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[11\] -fixed false -x 840 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_q_1.CO0 -fixed false -x 498 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001\[9\] -fixed false -x 73 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[6\] -fixed false -x 454 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[5\] -fixed false -x 890 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0\[2\] -fixed false -x 240 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[20\] -fixed false -x 817 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[10\] -fixed false -x 430 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[14\] -fixed false -x 192 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[8\] -fixed false -x 490 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m34_e -fixed false -x 75 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_2\[1\] -fixed false -x 716 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[29\] -fixed false -x 353 -y 201
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[13\] -fixed false -x 390 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[1\] -fixed false -x 271 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[6\] -fixed false -x 216 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[6\] -fixed false -x 134 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[0\] -fixed false -x 350 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data\[2\] -fixed false -x 663 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_479 -fixed false -x 651 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_1_0 -fixed false -x 400 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[11\] -fixed false -x 274 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m16 -fixed false -x 74 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_25_RNIHM4D8 -fixed false -x 835 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[4\] -fixed false -x 157 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioOo1_1 -fixed false -x 303 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_next_dividend_0_sqmuxa -fixed false -x 871 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[9\] -fixed false -x 612 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i0ll1 -fixed false -x 454 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_1_0 -fixed false -x 27 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_54\[11\] -fixed false -x 323 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[0\] -fixed false -x 286 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[30\] -fixed false -x 743 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[16\] -fixed false -x 860 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i\[9\] -fixed false -x 712 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO\[18\] -fixed false -x 590 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_Tc0_l_En_0_a2 -fixed false -x 494 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1\[6\] -fixed false -x 156 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[17\] -fixed false -x 383 -y 186
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/un1_PLL_POWERDOWN_B_i -fixed false -x 744 -y 3
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_971 -fixed false -x 734 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_333 -fixed false -x 744 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[3\] -fixed false -x 735 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0\[7\] -fixed false -x 97 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[12\] -fixed false -x 853 -y 123
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[3\] -fixed false -x 433 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data\[5\] -fixed false -x 840 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM\[2\] -fixed false -x 234 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un22_il0Oo_0_a2 -fixed false -x 154 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_h_En_0_a2_RNI88OH8 -fixed false -x 524 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IoOI1 -fixed false -x 296 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1097 -fixed false -x 686 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[3\].BUFD_BLK -fixed false -x 481 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[2\] -fixed false -x 346 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1\[3\] -fixed false -x 267 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_RNO\[1\] -fixed false -x 688 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[12\] -fixed false -x 244 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_66 -fixed false -x 704 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val\[1\] -fixed false -x 721 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1017 -fixed false -x 636 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[1\] -fixed false -x 231 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[4\] -fixed false -x 350 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[4\] -fixed false -x 361 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNISH7VA\[11\] -fixed false -x 662 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_m6_0_a2_3_1 -fixed false -x 748 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[43\] -fixed false -x 508 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[7\] -fixed false -x 349 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_3_1 -fixed false -x 646 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[21\] -fixed false -x 908 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1134 -fixed false -x 625 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[11\] -fixed false -x 864 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1\[1\] -fixed false -x 372 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[4\] -fixed false -x 186 -y 207
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15_0 -fixed false -x 458 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[5\] -fixed false -x 434 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[10\] -fixed false -x 28 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[1\] -fixed false -x 134 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[5\] -fixed false -x 515 -y 160
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt\[3\] -fixed false -x 35 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[4\] -fixed false -x 108 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[29\] -fixed false -x 951 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[6\] -fixed false -x 439 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[6\] -fixed false -x 91 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[23\] -fixed false -x 847 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[13\] -fixed false -x 465 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO_1 -fixed false -x 812 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[24\] -fixed false -x 468 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8\[12\] -fixed false -x 795 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un29_ool01 -fixed false -x 180 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1\[6\] -fixed false -x 68 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[9\] -fixed false -x 266 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_1 -fixed false -x 707 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[22\] -fixed false -x 423 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12\[11\] -fixed false -x 290 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[2\] -fixed false -x 242 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[19\] -fixed false -x 674 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[18\] -fixed false -x 854 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0io1 -fixed false -x 91 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[27\] -fixed false -x 680 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNI724LE\[0\] -fixed false -x 807 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[18\] -fixed false -x 453 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2__RNIS1727\[2\] -fixed false -x 639 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[20\] -fixed false -x 451 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[2\] -fixed false -x 404 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[34\] -fixed false -x 639 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[15\] -fixed false -x 128 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1 -fixed false -x 126 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ilIO1\[0\] -fixed false -x 168 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1\[3\] -fixed false -x 228 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[14\] -fixed false -x 89 -y 193
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_q_1.CO2 -fixed false -x 503 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[2\] -fixed false -x 508 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.implicit_wr_dpc_pc_en -fixed false -x 808 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[11\] -fixed false -x 841 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_4 -fixed false -x 706 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[8\] -fixed false -x 726 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIG7GR22\[0\] -fixed false -x 31 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[1\] -fixed false -x 696 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[7\] -fixed false -x 884 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata\[12\] -fixed false -x 538 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0\[0\] -fixed false -x 312 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[6\] -fixed false -x 498 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o0Oi1 -fixed false -x 77 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[1\] -fixed false -x 231 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[20\] -fixed false -x 881 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1\[9\] -fixed false -x 193 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[31\] -fixed false -x 267 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[9\] -fixed false -x 313 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un55_I1Oi1 -fixed false -x 49 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[6\] -fixed false -x 660 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[3\] -fixed false -x 236 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_3 -fixed false -x 552 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOi01 -fixed false -x 44 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[3\] -fixed false -x 243 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1021 -fixed false -x 805 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_is_subsys_hart_soft_reg_2 -fixed false -x 820 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_14 -fixed false -x 626 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_690 -fixed false -x 684 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_oI0i1 -fixed false -x 117 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[25\] -fixed false -x 861 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_i_o4\[4\] -fixed false -x 287 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[10\] -fixed false -x 131 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_283 -fixed false -x 685 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[16\] -fixed false -x 247 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_8_sx -fixed false -x 836 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_7_1 -fixed false -x 679 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_180 -fixed false -x 636 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_N_4L6 -fixed false -x 704 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[5\] -fixed false -x 293 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIIi1 -fixed false -x 181 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1\[1\] -fixed false -x 541 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/PRDDATA\[3\] -fixed false -x 548 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0_1_0\[0\] -fixed false -x 323 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[11\] -fixed false -x 40 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_498 -fixed false -x 768 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un72_o1Oi1 -fixed false -x 74 -y 180
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[15\].BUFD_BLK -fixed false -x 483 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1140 -fixed false -x 721 -y 198
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/un1_read_rx_byte -fixed false -x 464 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/wr_en_data -fixed false -x 726 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5\[19\] -fixed false -x 687 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0\[3\] -fixed false -x 360 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_1 -fixed false -x 754 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[3\] -fixed false -x 754 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1\[11\] -fixed false -x 504 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[27\] -fixed false -x 796 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[10\] -fixed false -x 138 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[22\] -fixed false -x 816 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed\[15\] -fixed false -x 642 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[15\] -fixed false -x 782 -y 180
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[4\] -fixed false -x 482 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31\[7\] -fixed false -x 360 -y 174
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM\[0\] -fixed false -x 444 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIF1U1J\[10\] -fixed false -x 73 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[10\] -fixed false -x 458 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[9\] -fixed false -x 710 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_alu_op_complete_ex_0_a3_2 -fixed false -x 789 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI99L88\[5\] -fixed false -x 216 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[10\] -fixed false -x 837 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex\[1\] -fixed false -x 721 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[6\] -fixed false -x 441 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un27_I1Oi1_1 -fixed false -x 42 -y 183
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[5\].BUFD_BLK -fixed false -x 482 -y 108
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo\[0\] -fixed false -x 128 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8\[31\] -fixed false -x 234 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Iio01 -fixed false -x 78 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1221 -fixed false -x 672 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[28\] -fixed false -x 867 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a2_1 -fixed false -x 695 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[3\] -fixed false -x 57 -y 211
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_4_u_1_0 -fixed false -x 454 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[24\] -fixed false -x 919 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[35\] -fixed false -x 641 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO\[2\] -fixed false -x 79 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00019 -fixed false -x 74 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state\[0\] -fixed false -x 782 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_1_0\[0\] -fixed false -x 50 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01\[6\] -fixed false -x 205 -y 199
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[7\] -fixed false -x 501 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[31\] -fixed false -x 396 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioo01 -fixed false -x 123 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[3\] -fixed false -x 314 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oiOOo -fixed false -x 49 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0\[7\] -fixed false -x 123 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[1\] -fixed false -x 502 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[17\] -fixed false -x 840 -y 144
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first6 -fixed false -x 528 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[6\] -fixed false -x 264 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_c_0_a0_RNIVB5TM -fixed false -x 783 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[13\] -fixed false -x 913 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg\[0\] -fixed false -x 722 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/data_rd\[0\] -fixed false -x 624 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_11 -fixed false -x 205 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[11\] -fixed false -x 374 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[30\] -fixed false -x 690 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb\[2\] -fixed false -x 594 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[22\] -fixed false -x 455 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[23\] -fixed false -x 752 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_740 -fixed false -x 660 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNIQ5RRG\[6\] -fixed false -x 651 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0_7 -fixed false -x 469 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un31_ool01\[9\] -fixed false -x 67 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[11\] -fixed false -x 738 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m11 -fixed false -x 85 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_RNO -fixed false -x 801 -y 156
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1\[2\] -fixed false -x 494 -y 96
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state -fixed false -x 546 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/un1_Ioli0_1_0 -fixed false -x 394 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[10\] -fixed false -x 403 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[7\] -fixed false -x 448 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_11_0_RNO -fixed false -x 784 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2\[24\] -fixed false -x 739 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIVTT4D -fixed false -x 788 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OiOi1 -fixed false -x 184 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[1\] -fixed false -x 136 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[20\] -fixed false -x 947 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_6_RNIF137D -fixed false -x 838 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[5\] -fixed false -x 492 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960 -fixed false -x 675 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[12\] -fixed false -x 715 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNI29J25 -fixed false -x 195 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_RNI13T1N -fixed false -x 671 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[8\] -fixed false -x 40 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[4\] -fixed false -x 92 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[4\] -fixed false -x 630 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1\[10\] -fixed false -x 395 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2_4 -fixed false -x 158 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[6\] -fixed false -x 69 -y 166
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[5\] -fixed false -x 499 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[27\] -fixed false -x 950 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[18\] -fixed false -x 716 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io\[0\] -fixed false -x 209 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[10\] -fixed false -x 705 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[19\] -fixed false -x 889 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un13_lolIo_1 -fixed false -x 110 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3\[4\] -fixed false -x 494 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_m8_i_a5_1_2 -fixed false -x 807 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_435 -fixed false -x 757 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1\[29\] -fixed false -x 480 -y 187
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_lcry_RNO_1 -fixed false -x 402 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1\[25\] -fixed false -x 545 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_1\[1\] -fixed false -x 734 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[17\] -fixed false -x 425 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0\[14\] -fixed false -x 220 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I019 -fixed false -x 183 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[10\] -fixed false -x 147 -y 180
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[10\] -fixed false -x 395 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[18\] -fixed false -x 462 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_rx_1 -fixed false -x 46 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[5\] -fixed false -x 230 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[25\] -fixed false -x 468 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3\[2\] -fixed false -x 841 -y 120
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[6\] -fixed false -x 50 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[11\] -fixed false -x 744 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1 -fixed false -x 233 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4912_0 -fixed false -x 639 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1047 -fixed false -x 613 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[22\] -fixed false -x 560 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2\[1\] -fixed false -x 218 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_ss6 -fixed false -x 741 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[16\] -fixed false -x 829 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[4\] -fixed false -x 114 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[3\] -fixed false -x 756 -y 120
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[16\].BUFD_BLK -fixed false -x 482 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNI38GU61 -fixed false -x 771 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/un1_Ioli0_1_0 -fixed false -x 386 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid43 -fixed false -x 732 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4\[7\] -fixed false -x 97 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[11\] -fixed false -x 552 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0Ii1 -fixed false -x 168 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[18\].BUFD_BLK -fixed false -x 529 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[2\] -fixed false -x 230 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[18\] -fixed false -x 873 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata2_sw_rd_sel -fixed false -x 684 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[5\] -fixed false -x 420 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[5\] -fixed false -x 190 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int\[3\] -fixed false -x 792 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1\[26\] -fixed false -x 65 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0\[0\] -fixed false -x 730 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff_4 -fixed false -x 785 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lO011 -fixed false -x 234 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOI11 -fixed false -x 142 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[18\] -fixed false -x 60 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOO11 -fixed false -x 42 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[0\] -fixed false -x 120 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_5_0\[3\] -fixed false -x 41 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[41\] -fixed false -x 914 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI0l1\[0\] -fixed false -x 454 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1\[0\] -fixed false -x 137 -y 220
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_1_1\[4\] -fixed false -x 15 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNO -fixed false -x 406 -y 234
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m18_2_0 -fixed false -x 600 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[8\] -fixed false -x 117 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[26\] -fixed false -x 481 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1\[10\] -fixed false -x 236 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[7\] -fixed false -x 745 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1\[2\] -fixed false -x 361 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1\[14\] -fixed false -x 82 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[9\] -fixed false -x 175 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_1_0 -fixed false -x 642 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[18\] -fixed false -x 255 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2\[1\] -fixed false -x 641 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[22\] -fixed false -x 759 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[18\] -fixed false -x 702 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001\[0\] -fixed false -x 39 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[21\] -fixed false -x 915 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_303 -fixed false -x 734 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[30\] -fixed false -x 446 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2_0 -fixed false -x 26 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[32\] -fixed false -x 372 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_resp_ready -fixed false -x 760 -y 138
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4\[0\] -fixed false -x 508 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un16_valid_sba_0_a3_RNIKKCRJ -fixed false -x 721 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2\[22\] -fixed false -x 874 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2\[3\] -fixed false -x 48 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oil01_RNIC3T3J -fixed false -x 180 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850 -fixed false -x 602 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01\[5\] -fixed false -x 181 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNIU0S5C\[24\] -fixed false -x 676 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[1\] -fixed false -x 844 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_5 -fixed false -x 228 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[25\] -fixed false -x 914 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1\[7\] -fixed false -x 94 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[21\] -fixed false -x 723 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1\[12\] -fixed false -x 858 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_713 -fixed false -x 759 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0\[28\] -fixed false -x 696 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lii01 -fixed false -x 40 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[5\] -fixed false -x 500 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[27\] -fixed false -x 909 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[18\] -fixed false -x 446 -y 214
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_valid -fixed false -x 389 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[32\] -fixed false -x 616 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_384 -fixed false -x 757 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m31_1 -fixed false -x 49 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0\[1\] -fixed false -x 300 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[20\] -fixed false -x 961 -y 168
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[23\] -fixed false -x 416 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4\[35\] -fixed false -x 460 -y 198
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_RNO -fixed false -x 446 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[8\] -fixed false -x 242 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_23\[0\] -fixed false -x 330 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0\[1\] -fixed false -x 717 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m21 -fixed false -x 49 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[22\] -fixed false -x 748 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[11\] -fixed false -x 663 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo55_1 -fixed false -x 37 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/status_byte\[1\] -fixed false -x 526 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[6\] -fixed false -x 176 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1\[0\] -fixed false -x 164 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo_0 -fixed false -x 147 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[21\] -fixed false -x 433 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[22\] -fixed false -x 353 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[22\] -fixed false -x 450 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[10\] -fixed false -x 769 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[12\] -fixed false -x 862 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[25\] -fixed false -x 489 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_2 -fixed false -x 659 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[7\] -fixed false -x 43 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[16\] -fixed false -x 926 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_2_N_2L1 -fixed false -x 807 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[23\] -fixed false -x 767 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_834 -fixed false -x 737 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_flush_i -fixed false -x 754 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[8\] -fixed false -x 235 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[6\] -fixed false -x 443 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[1\] -fixed false -x 384 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_965 -fixed false -x 698 -y 186
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4\[0\] -fixed false -x 459 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_79\[11\] -fixed false -x 277 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11\[5\] -fixed false -x 80 -y 222
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3\[1\] -fixed false -x 591 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2119_1 -fixed false -x 655 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO -fixed false -x 759 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int\[2\] -fixed false -x 881 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[18\] -fixed false -x 804 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[0\] -fixed false -x 199 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[23\] -fixed false -x 447 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1199 -fixed false -x 720 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2_\[25\] -fixed false -x 681 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1229 -fixed false -x 697 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[15\] -fixed false -x 229 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un9_IOIOo_1 -fixed false -x 29 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[9\] -fixed false -x 213 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[8\] -fixed false -x 852 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1119 -fixed false -x 554 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo\[3\] -fixed false -x 18 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[1\].buff_data\[1\]_RNIAKDAI\[10\] -fixed false -x 810 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNICF984\[17\] -fixed false -x 926 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[3\] -fixed false -x 743 -y 139
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31 -fixed false -x 495 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[12\] -fixed false -x 496 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1224 -fixed false -x 612 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_8 -fixed false -x 597 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un6_OoI01_2 -fixed false -x 182 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OIil1 -fixed false -x 417 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_560 -fixed false -x 709 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[17\] -fixed false -x 842 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11\[0\] -fixed false -x 382 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[18\] -fixed false -x 295 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_12 -fixed false -x 134 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_RNIERC8F -fixed false -x 601 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[21\] -fixed false -x 758 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[7\] -fixed false -x 520 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_0_sqmuxa_0_o3 -fixed false -x 217 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_43 -fixed false -x 653 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[24\] -fixed false -x 860 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Io0I1_RNO -fixed false -x 390 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[12\] -fixed false -x 524 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1\[8\] -fixed false -x 296 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[24\] -fixed false -x 962 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_0_0\[0\] -fixed false -x 615 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[11\] -fixed false -x 918 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[5\] -fixed false -x 497 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[25\] -fixed false -x 444 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[12\] -fixed false -x 548 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[4\] -fixed false -x 77 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[9\] -fixed false -x 358 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[0\] -fixed false -x 765 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1\[6\] -fixed false -x 142 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[8\] -fixed false -x 395 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o0Ol1 -fixed false -x 434 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1_0 -fixed false -x 493 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3\[12\] -fixed false -x 938 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[21\] -fixed false -x 59 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i_a2_0 -fixed false -x 76 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[3\] -fixed false -x 177 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1\[14\] -fixed false -x 337 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un37_ool01\[0\] -fixed false -x 60 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1101_2_iv_0_0 -fixed false -x 122 -y 213
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[6\] -fixed false -x 58 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_RNIDBOQT -fixed false -x 860 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[1\] -fixed false -x 416 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0Ol1_1 -fixed false -x 442 -y 195
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/iPSELS\[0\] -fixed false -x 468 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv\[4\] -fixed false -x 57 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[5\] -fixed false -x 259 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1\[12\] -fixed false -x 156 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[15\] -fixed false -x 469 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0_a3_0\[0\] -fixed false -x 736 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[20\] -fixed false -x 438 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_1\[11\] -fixed false -x 289 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[6\] -fixed false -x 265 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_a3_1 -fixed false -x 96 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[8\] -fixed false -x 686 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[2\] -fixed false -x 284 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1069 -fixed false -x 708 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_error_resp.gen_buff_loop\[0\].buff_entry_error_resp_ram3_\[0\] -fixed false -x 634 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[1\] -fixed false -x 650 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[15\] -fixed false -x 416 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOii1_0_0 -fixed false -x 144 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1\[5\] -fixed false -x 452 -y 202
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[3\] -fixed false -x 451 -y 151
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[5\] -fixed false -x 446 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29\[2\] -fixed false -x 348 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2 -fixed false -x 493 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIND15R1\[0\] -fixed false -x 25 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[31\] -fixed false -x 844 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[12\] -fixed false -x 697 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[11\] -fixed false -x 320 -y 178
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state7 -fixed false -x 505 -y 90
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel\[0\] -fixed false -x 425 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2\[6\] -fixed false -x 294 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[22\] -fixed false -x 676 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1\[12\] -fixed false -x 563 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_genblk1.O0Il1_2_i_m3_RNI41E5E -fixed false -x 488 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_938 -fixed false -x 624 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[23\] -fixed false -x 654 -y 127
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNO\[1\] -fixed false -x 5 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_could_commit_0 -fixed false -x 785 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_0_sqmuxa -fixed false -x 788 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[3\] -fixed false -x 205 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[9\] -fixed false -x 722 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[23\] -fixed false -x 542 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[11\] -fixed false -x 762 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[3\] -fixed false -x 794 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[2\] -fixed false -x 378 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[2\] -fixed false -x 338 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_6\[15\] -fixed false -x 87 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[20\] -fixed false -x 754 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[6\] -fixed false -x 833 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26\[17\] -fixed false -x 889 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[3\] -fixed false -x 97 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[21\] -fixed false -x 936 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO\[2\] -fixed false -x 779 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[22\] -fixed false -x 826 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0\[15\] -fixed false -x 858 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[11\] -fixed false -x 301 -y 195
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[6\].BUFD_BLK -fixed false -x 481 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNI9HAHG -fixed false -x 758 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[3\] -fixed false -x 539 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un10_o1ii1_3 -fixed false -x 153 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmcontrol_ndmreset13_4_0_o2_0_RNI620SL1 -fixed false -x 697 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[4\] -fixed false -x 250 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo -fixed false -x 36 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[8\] -fixed false -x 382 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un219_I1Oi1 -fixed false -x 46 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO\[3\] -fixed false -x 613 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNI1ORQ8\[19\] -fixed false -x 630 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[15\] -fixed false -x 350 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[6\] -fixed false -x 236 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1172 -fixed false -x 613 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_1 -fixed false -x 588 -y 186
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1\[5\] -fixed false -x 445 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_ready_reg -fixed false -x 795 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram2__RNIU4RO5\[14\] -fixed false -x 614 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0\[3\] -fixed false -x 705 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO_3 -fixed false -x 734 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNINVNHP -fixed false -x 791 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_0_sqmuxa_0 -fixed false -x 194 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err -fixed false -x 777 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_21\[20\] -fixed false -x 128 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[6\] -fixed false -x 169 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[28\] -fixed false -x 807 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un37_ool01\[7\] -fixed false -x 57 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[8\] -fixed false -x 833 -y 133
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic538_m1_e -fixed false -x 715 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[4\] -fixed false -x 129 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_405 -fixed false -x 627 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt\[2\] -fixed false -x 192 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2\[6\] -fixed false -x 964 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[4\] -fixed false -x 249 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[18\] -fixed false -x 86 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[11\] -fixed false -x 401 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0\[7\] -fixed false -x 126 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[2\] -fixed false -x 628 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOli1_2_i_o3 -fixed false -x 157 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_731 -fixed false -x 769 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_4 -fixed false -x 733 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/IilI1 -fixed false -x 463 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01\[8\] -fixed false -x 170 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[7\] -fixed false -x 508 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[3\] -fixed false -x 388 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[6\] -fixed false -x 105 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0\[7\] -fixed false -x 96 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control1\[1\] -fixed false -x 525 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[24\] -fixed false -x 674 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_23\[20\] -fixed false -x 110 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3 -fixed false -x 156 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.N_50_i_i -fixed false -x 208 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/state_val_14\[0\] -fixed false -x 728 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_en_ex -fixed false -x 703 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_637 -fixed false -x 793 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m16_1_0 -fixed false -x 40 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[19\] -fixed false -x 65 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[12\] -fixed false -x 937 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_736 -fixed false -x 656 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIOo1 -fixed false -x 308 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115 -fixed false -x 667 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_strb\[0\] -fixed false -x 766 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3\[7\] -fixed false -x 717 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_OIiIo -fixed false -x 433 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[29\] -fixed false -x 914 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[64\] -fixed false -x 957 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12\[0\] -fixed false -x 459 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[4\] -fixed false -x 386 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2\[8\] -fixed false -x 661 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[34\] -fixed false -x 510 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[15\] -fixed false -x 471 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[21\] -fixed false -x 282 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOio1 -fixed false -x 76 -y 202
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[6\] -fixed false -x 380 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3\[12\] -fixed false -x 722 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111_2 -fixed false -x 264 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[8\] -fixed false -x 79 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_iiiI1_1_0 -fixed false -x 441 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[13\] -fixed false -x 776 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[16\] -fixed false -x 397 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_656 -fixed false -x 756 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0\[11\] -fixed false -x 340 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo\[1\] -fixed false -x 22 -y 166
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[6\] -fixed false -x 483 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_975 -fixed false -x 672 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[15\] -fixed false -x 89 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[15\] -fixed false -x 279 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[18\] -fixed false -x 745 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo_RNI4E64A -fixed false -x 20 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata\[7\] -fixed false -x 492 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un52_Oi1O1\[21\] -fixed false -x 440 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_valid_retr -fixed false -x 772 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_m3\[1\] -fixed false -x 835 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_RNO\[9\] -fixed false -x 76 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt\[7\] -fixed false -x 203 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto2 -fixed false -x 85 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[8\] -fixed false -x 882 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/un1_iOI01_1_i_0 -fixed false -x 288 -y 174
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0\[0\] -fixed false -x 72 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_a8_0_1 -fixed false -x 635 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[16\] -fixed false -x 529 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_570 -fixed false -x 625 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[26\] -fixed false -x 246 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[8\] -fixed false -x 468 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_3 -fixed false -x 247 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_1\[24\] -fixed false -x 420 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo -fixed false -x 35 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[4\] -fixed false -x 638 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ioOl1 -fixed false -x 386 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[4\] -fixed false -x 960 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_d_1_sqmuxa_2 -fixed false -x 554 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[7\] -fixed false -x 230 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[1\] -fixed false -x 395 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1149 -fixed false -x 725 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[26\] -fixed false -x 167 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un59_OOOI1\[18\] -fixed false -x 424 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a2\[1\] -fixed false -x 745 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0\[41\] -fixed false -x 325 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z\[5\] -fixed false -x 461 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[20\] -fixed false -x 742 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[0\] -fixed false -x 426 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_10 -fixed false -x 84 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ioO01 -fixed false -x 468 -y 175
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_2\[4\] -fixed false -x 506 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_4 -fixed false -x 696 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[35\] -fixed false -x 923 -y 169
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/cdr_start5_0_a2 -fixed false -x 13 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_159 -fixed false -x 627 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_10 -fixed false -x 814 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_0\[0\] -fixed false -x 624 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[28\] -fixed false -x 386 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_31_RNO_0 -fixed false -x 838 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr\[8\] -fixed false -x 703 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[9\] -fixed false -x 292 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[36\] -fixed false -x 632 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[5\] -fixed false -x 589 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[4\] -fixed false -x 376 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data\[16\] -fixed false -x 829 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[6\] -fixed false -x 442 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_s_5_RNO -fixed false -x 526 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0\[30\] -fixed false -x 950 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiOOo -fixed false -x 59 -y 166
|
|
set_location -inst_name CFG0_GND_INST -fixed false -x 329 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt\[2\] -fixed false -x 240 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1_RNIC4PVC -fixed false -x 804 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[10\] -fixed false -x 938 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[9\] -fixed false -x 432 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[22\] -fixed false -x 337 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0O11_i_o2 -fixed false -x 98 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_804 -fixed false -x 711 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0\[27\] -fixed false -x 132 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[2\] -fixed false -x 810 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[24\] -fixed false -x 820 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z\[29\] -fixed false -x 793 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_1\[0\] -fixed false -x 613 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[12\] -fixed false -x 347 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IIiO1 -fixed false -x 246 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m43 -fixed false -x 19 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1174 -fixed false -x 700 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[40\] -fixed false -x 559 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[1\] -fixed false -x 910 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI71FGI\[1\] -fixed false -x 483 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_898 -fixed false -x 732 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR_1_sqmuxa -fixed false -x 565 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[5\] -fixed false -x 368 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[34\] -fixed false -x 474 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[23\] -fixed false -x 866 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[4\] -fixed false -x 376 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNIHM8GO\[25\] -fixed false -x 900 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[49\] -fixed false -x 930 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_5 -fixed false -x 649 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[21\] -fixed false -x 444 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[4\] -fixed false -x 42 -y 187
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_1_sqmuxa_0 -fixed false -x 534 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1\[4\] -fixed false -x 502 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un5_l1ll1_0 -fixed false -x 455 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt\[3\] -fixed false -x 555 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un7_i_0_RNIGL1VH -fixed false -x 484 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4\[5\] -fixed false -x 912 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[21\] -fixed false -x 459 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr\[10\] -fixed false -x 855 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[20\] -fixed false -x 823 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[40\] -fixed false -x 523 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I015 -fixed false -x 206 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_fence -fixed false -x 704 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m67 -fixed false -x 48 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn -fixed false -x 798 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt\[11\] -fixed false -x 214 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO\[5\] -fixed false -x 176 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[7\] -fixed false -x 405 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[1\] -fixed false -x 292 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01\[5\] -fixed false -x 186 -y 211
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[6\] -fixed false -x 403 -y 256
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[16\] -fixed false -x 51 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[0\] -fixed false -x 278 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[26\] -fixed false -x 648 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[5\] -fixed false -x 433 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4954 -fixed false -x 654 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5\[12\] -fixed false -x 153 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m111 -fixed false -x 161 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain\[10\] -fixed false -x 504 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_558 -fixed false -x 745 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[20\] -fixed false -x 529 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros -fixed false -x 534 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[22\] -fixed false -x 914 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[4\] -fixed false -x 511 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[23\] -fixed false -x 847 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/empty_rd -fixed false -x 660 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[8\] -fixed false -x 160 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2\[7\] -fixed false -x 494 -y 153
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_RNO -fixed false -x 517 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0 -fixed false -x 767 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt\[0\] -fixed false -x 259 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[47\] -fixed false -x 910 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1 -fixed false -x 637 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_error_resp.gen_buff_loop\[0\].buff_entry_error_resp_ram1_\[0\] -fixed false -x 624 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_4_RNI1SNO9 -fixed false -x 173 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[7\] -fixed false -x 833 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/access_valid_i_o3 -fixed false -x 768 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo\[2\] -fixed false -x 217 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[12\] -fixed false -x 321 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[7\] -fixed false -x 829 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/looOolto2 -fixed false -x 84 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2\[4\] -fixed false -x 824 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[6\] -fixed false -x 943 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[11\] -fixed false -x 190 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[56\] -fixed false -x 877 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_first_3_f0 -fixed false -x 543 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt\[3\] -fixed false -x 237 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0\[3\] -fixed false -x 295 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[2\] -fixed false -x 217 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_9 -fixed false -x 657 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[16\] -fixed false -x 294 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1\[0\] -fixed false -x 806 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0\[5\] -fixed false -x 138 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_23 -fixed false -x 848 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_m2\[1\] -fixed false -x 126 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo\[6\] -fixed false -x 305 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[22\] -fixed false -x 842 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg\[8\] -fixed false -x 818 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[3\] -fixed false -x 267 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1\[11\] -fixed false -x 544 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIN0CS7\[3\] -fixed false -x 913 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[28\] -fixed false -x 733 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2_0 -fixed false -x 121 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_prescale_counter_1.CO1 -fixed false -x 781 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[16\] -fixed false -x 286 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state\[0\] -fixed false -x 782 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[25\] -fixed false -x 444 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_6_RNO -fixed false -x 378 -y 219
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[2\] -fixed false -x 399 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_908 -fixed false -x 624 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[2\] -fixed false -x 382 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[10\] -fixed false -x 720 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[24\] -fixed false -x 835 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns\[0\] -fixed false -x 489 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z\[36\] -fixed false -x 428 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_11 -fixed false -x 23 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[11\] -fixed false -x 786 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lloI1 -fixed false -x 450 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_2 -fixed false -x 742 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_m1_e -fixed false -x 808 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO\[24\] -fixed false -x 114 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[2\] -fixed false -x 151 -y 216
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m11 -fixed false -x 508 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[17\] -fixed false -x 754 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_26\[9\] -fixed false -x 282 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[15\] -fixed false -x 758 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[8\] -fixed false -x 229 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[21\] -fixed false -x 152 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0oo1 -fixed false -x 72 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[28\] -fixed false -x 949 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid -fixed false -x 600 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[4\] -fixed false -x 927 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[9\] -fixed false -x 354 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/un1_o0IO1\[0\] -fixed false -x 184 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m4_0_1 -fixed false -x 684 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un4_lolIo -fixed false -x 109 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ilo11 -fixed false -x 290 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[27\] -fixed false -x 546 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6\[11\] -fixed false -x 291 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[1\] -fixed false -x 67 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_havereset -fixed false -x 796 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1\[13\] -fixed false -x 216 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[15\] -fixed false -x 797 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr\[0\] -fixed false -x 776 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_244 -fixed false -x 648 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[16\] -fixed false -x 322 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[4\] -fixed false -x 272 -y 214
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[4\] -fixed false -x 438 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex\[2\] -fixed false -x 739 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[19\] -fixed false -x 927 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[8\] -fixed false -x 851 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1165 -fixed false -x 708 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[1\] -fixed false -x 900 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok_2 -fixed false -x 520 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[7\] -fixed false -x 499 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[3\] -fixed false -x 564 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0\[5\] -fixed false -x 853 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0\[26\] -fixed false -x 939 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[4\] -fixed false -x 87 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_239 -fixed false -x 709 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[28\] -fixed false -x 794 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[14\] -fixed false -x 705 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[6\] -fixed false -x 288 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2\[30\] -fixed false -x 712 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1 -fixed false -x 386 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[3\] -fixed false -x 421 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[5\] -fixed false -x 420 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_701 -fixed false -x 804 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i\[4\] -fixed false -x 600 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[10\] -fixed false -x 133 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1\[7\] -fixed false -x 406 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO_1 -fixed false -x 828 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[0\] -fixed false -x 860 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_291 -fixed false -x 602 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_core_reset_1 -fixed false -x 818 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[3\] -fixed false -x 78 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[7\] -fixed false -x 229 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z\[1\] -fixed false -x 70 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[12\] -fixed false -x 801 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[8\] -fixed false -x 516 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i01l1\[0\] -fixed false -x 392 -y 217
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_pktend -fixed false -x 527 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_8 -fixed false -x 817 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_2_1 -fixed false -x 802 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un13_mul_mc_3_0 -fixed false -x 809 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_O1Oo1_3 -fixed false -x 293 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[2\] -fixed false -x 391 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[1\].lIII1_44\[13\] -fixed false -x 482 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[7\] -fixed false -x 404 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_607 -fixed false -x 695 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101ce\[10\] -fixed false -x 40 -y 204
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[26\] -fixed false -x 408 -y 240
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_706 -fixed false -x 673 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[14\] -fixed false -x 33 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[23\] -fixed false -x 55 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_4_tz\[0\] -fixed false -x 828 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[3\].lIII1_62\[29\] -fixed false -x 480 -y 186
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO2 -fixed false -x 548 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[60\] -fixed false -x 595 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01\[2\] -fixed false -x 204 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[15\] -fixed false -x 460 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_rd_ptr_0_0\[0\] -fixed false -x 747 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/IilI1 -fixed false -x 260 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo_1 -fixed false -x 121 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[16\] -fixed false -x 358 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[58\] -fixed false -x 931 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt\[7\] -fixed false -x 418 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[0\] -fixed false -x 409 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[1\] -fixed false -x 146 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_2 -fixed false -x 783 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1262 -fixed false -x 612 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[13\] -fixed false -x 349 -y 199
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[28\] -fixed false -x 408 -y 237
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[7\] -fixed false -x 141 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1\[16\] -fixed false -x 887 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51_RNIF2FDB1\[9\] -fixed false -x 900 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0\[9\] -fixed false -x 339 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_1\[0\] -fixed false -x 255 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_193 -fixed false -x 792 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[15\] -fixed false -x 373 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[8\] -fixed false -x 774 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[33\] -fixed false -x 849 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[1\] -fixed false -x 217 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg\[2\] -fixed false -x 696 -y 181
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/control2\[1\] -fixed false -x 514 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lOlOo -fixed false -x 33 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0_5 -fixed false -x 107 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[0\] -fixed false -x 325 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_a2_3 -fixed false -x 271 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[20\] -fixed false -x 465 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo -fixed false -x 43 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2\[25\] -fixed false -x 911 -y 135
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE\[0\] -fixed false -x 46 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[11\] -fixed false -x 507 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[10\] -fixed false -x 25 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[19\] -fixed false -x 250 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto15_4_0 -fixed false -x 133 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[4\] -fixed false -x 327 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[38\] -fixed false -x 151 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z\[31\] -fixed false -x 213 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_3 -fixed false -x 504 -y 144
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[4\] -fixed false -x 472 -y 150
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_0\[3\] -fixed false -x 538 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2\[0\] -fixed false -x 637 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[6\] -fixed false -x 416 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[10\] -fixed false -x 229 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_51 -fixed false -x 661 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0\[26\] -fixed false -x 868 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_222 -fixed false -x 720 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[6\] -fixed false -x 302 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_valid_reg -fixed false -x 742 -y 142
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state\[1\] -fixed false -x 0 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO\[1\] -fixed false -x 420 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/llio1 -fixed false -x 81 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[9\] -fixed false -x 425 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int -fixed false -x 805 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0Ii1 -fixed false -x 163 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1\[1\] -fixed false -x 62 -y 204
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0\[1\] -fixed false -x 519 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data\[23\] -fixed false -x 694 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[31\] -fixed false -x 387 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1 -fixed false -x 50 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[21\] -fixed false -x 653 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0\[1\] -fixed false -x 408 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_1_a2\[15\] -fixed false -x 133 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0\[24\] -fixed false -x 787 -y 117
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[24\] -fixed false -x 419 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_1811 -fixed false -x 745 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_0 -fixed false -x 399 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2\[4\] -fixed false -x 732 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[23\] -fixed false -x 901 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[15\] -fixed false -x 383 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1\[3\] -fixed false -x 495 -y 202
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_3 -fixed false -x 438 -y 9
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[11\] -fixed false -x 744 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO\[8\] -fixed false -x 636 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001\[2\] -fixed false -x 62 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[14\] -fixed false -x 33 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1\[21\] -fixed false -x 711 -y 126
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxs_txready -fixed false -x 539 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z\[7\] -fixed false -x 271 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[3\] -fixed false -x 912 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_330 -fixed false -x 649 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9\[1\] -fixed false -x 313 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[9\] -fixed false -x 449 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIO11\[1\] -fixed false -x 13 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt\[0\] -fixed false -x 733 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30\[6\] -fixed false -x 313 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[27\] -fixed false -x 692 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_4_1 -fixed false -x 924 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_5\[12\] -fixed false -x 109 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[0\] -fixed false -x 325 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[31\] -fixed false -x 114 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_0_1\[2\] -fixed false -x 840 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_589 -fixed false -x 636 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[0\] -fixed false -x 505 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Oii11 -fixed false -x 297 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[4\] -fixed false -x 275 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[15\] -fixed false -x 622 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a2_1 -fixed false -x 814 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[6\] -fixed false -x 361 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO\[3\] -fixed false -x 727 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNII66EB -fixed false -x 765 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[21\] -fixed false -x 841 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m13 -fixed false -x 39 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_0\[3\] -fixed false -x 26 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51_RNIE1FDB1\[8\] -fixed false -x 968 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff -fixed false -x 785 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[28\] -fixed false -x 431 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[11\] -fixed false -x 402 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[20\] -fixed false -x 424 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[3\] -fixed false -x 502 -y 97
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o1o01 -fixed false -x 100 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo\[1\] -fixed false -x 288 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[8\] -fixed false -x 367 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[6\] -fixed false -x 169 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[4\] -fixed false -x 37 -y 232
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ioOOo -fixed false -x 53 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[17\] -fixed false -x 396 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_0_sqmuxa_i_o2 -fixed false -x 729 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[2\] -fixed false -x 65 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z\[10\] -fixed false -x 528 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0\[3\] -fixed false -x 152 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_0\[0\] -fixed false -x 254 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2\[22\] -fixed false -x 891 -y 195
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte\[1\] -fixed false -x 432 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[5\] -fixed false -x 402 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[11\] -fixed false -x 835 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[8\] -fixed false -x 445 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[3\] -fixed false -x 783 -y 106
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_210 -fixed false -x 780 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un112_OOOI1\[3\] -fixed false -x 345 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11\[9\] -fixed false -x 155 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1\[7\] -fixed false -x 280 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[22\] -fixed false -x 960 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO_1 -fixed false -x 834 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/SPISS\[0\] -fixed false -x 524 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18\[18\] -fixed false -x 261 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1\[6\] -fixed false -x 528 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3\[4\] -fixed false -x 565 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[5\] -fixed false -x 420 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_962 -fixed false -x 745 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[42\] -fixed false -x 493 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[8\] -fixed false -x 225 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram0_\[7\] -fixed false -x 702 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_44\[9\] -fixed false -x 913 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt\[9\] -fixed false -x 242 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[16\] -fixed false -x 787 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[12\] -fixed false -x 913 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0\[2\] -fixed false -x 723 -y 147
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa_0 -fixed false -x 506 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[29\] -fixed false -x 828 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[33\] -fixed false -x 902 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[5\] -fixed false -x 373 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[9\] -fixed false -x 723 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[3\] -fixed false -x 427 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[2\] -fixed false -x 650 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[15\] -fixed false -x 597 -y 156
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[2\] -fixed false -x 492 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10\[5\] -fixed false -x 262 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[6\] -fixed false -x 308 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_135 -fixed false -x 649 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[7\] -fixed false -x 157 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[7\] -fixed false -x 123 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[31\] -fixed false -x 889 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[25\] -fixed false -x 594 -y 166
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[8\] -fixed false -x 381 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_debug_exit -fixed false -x 817 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0iIo -fixed false -x 436 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1\[4\] -fixed false -x 222 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_2\[1\] -fixed false -x 715 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[21\] -fixed false -x 648 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1\[1\] -fixed false -x 275 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iOo_0 -fixed false -x 140 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[3\] -fixed false -x 183 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3\[2\] -fixed false -x 501 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0_0\[16\] -fixed false -x 112 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo\[7\] -fixed false -x 65 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[3\] -fixed false -x 501 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[5\] -fixed false -x 727 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[5\] -fixed false -x 192 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[3\] -fixed false -x 175 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1\[5\] -fixed false -x 134 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_2_0_1 -fixed false -x 96 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[53\] -fixed false -x 566 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold_RNO_0 -fixed false -x 787 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[15\] -fixed false -x 124 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01\[1\] -fixed false -x 145 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt\[2\] -fixed false -x 320 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[27\] -fixed false -x 811 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_sn_N_8_mux_i_i_o2_RNI3OI13 -fixed false -x 526 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[31\] -fixed false -x 450 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[4\] -fixed false -x 233 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4\[12\] -fixed false -x 277 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1\[2\] -fixed false -x 250 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1\[21\] -fixed false -x 840 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un7_liii1 -fixed false -x 120 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_12_1\[0\] -fixed false -x 818 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[17\] -fixed false -x 891 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0\[11\] -fixed false -x 396 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count\[8\] -fixed false -x 588 -y 142
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/IIIl1 -fixed false -x 543 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0\[28\] -fixed false -x 217 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[0\] -fixed false -x 625 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[12\] -fixed false -x 462 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0\[9\] -fixed false -x 38 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[5\] -fixed false -x 914 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[1\] -fixed false -x 784 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111\[1\] -fixed false -x 157 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0\[7\] -fixed false -x 702 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_8 -fixed false -x 402 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_785 -fixed false -x 601 -y 189
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out_RNICU0A6 -fixed false -x 514 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m28 -fixed false -x 237 -y 192
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky\[0\] -fixed false -x 523 -y 154
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[8\] -fixed false -x 405 -y 238
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[25\] -fixed false -x 844 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31\[0\] -fixed false -x 192 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01\[0\] -fixed false -x 162 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[1\] -fixed false -x 786 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIDJM4C\[7\] -fixed false -x 719 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[3\] -fixed false -x 49 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z\[2\] -fixed false -x 494 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[12\] -fixed false -x 885 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_4 -fixed false -x 223 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[10\] -fixed false -x 120 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg\[0\] -fixed false -x 804 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_651 -fixed false -x 684 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[7\] -fixed false -x 262 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_14 -fixed false -x 839 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[8\] -fixed false -x 734 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIEH984\[19\] -fixed false -x 920 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[4\] -fixed false -x 728 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_692 -fixed false -x 600 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[11\] -fixed false -x 714 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1\[2\] -fixed false -x 279 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[8\] -fixed false -x 721 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[33\] -fixed false -x 428 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_597 -fixed false -x 602 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[20\] -fixed false -x 909 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[14\] -fixed false -x 253 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0\[3\] -fixed false -x 666 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[32\] -fixed false -x 491 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[31\] -fixed false -x 811 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un331_lIlo1_2 -fixed false -x 172 -y 177
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_2_sqmuxa -fixed false -x 68 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[14\] -fixed false -x 913 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOoo1 -fixed false -x 97 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[31\] -fixed false -x 747 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_209 -fixed false -x 768 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1\[3\] -fixed false -x 360 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[12\] -fixed false -x 960 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[5\] -fixed false -x 358 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_hit/gen_bit_reset.state_val_RNO\[0\] -fixed false -x 817 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[0\] -fixed false -x 319 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[10\] -fixed false -x 342 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oI1I18_1 -fixed false -x 478 -y 189
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout\[4\] -fixed false -x 378 -y 244
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[4\] -fixed false -x 243 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[11\] -fixed false -x 435 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[5\] -fixed false -x 781 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_11 -fixed false -x 672 -y 174
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_3 -fixed false -x 529 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[29\] -fixed false -x 881 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[20\] -fixed false -x 715 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19\[13\] -fixed false -x 265 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_1\[2\] -fixed false -x 643 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo\[6\] -fixed false -x 127 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_8 -fixed false -x 76 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0_a3_0\[0\] -fixed false -x 96 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_62\[0\] -fixed false -x 963 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[8\] -fixed false -x 276 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[10\] -fixed false -x 764 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[2\] -fixed false -x 362 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3_1\[12\] -fixed false -x 119 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[36\] -fixed false -x 915 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1\[28\] -fixed false -x 356 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[10\] -fixed false -x 92 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1\[11\] -fixed false -x 268 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[4\] -fixed false -x 289 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_O1I019_1 -fixed false -x 181 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1_RNIT40LK2 -fixed false -x 772 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[4\] -fixed false -x 38 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_5 -fixed false -x 734 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1_35\[1\] -fixed false -x 393 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[33\] -fixed false -x 479 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_688 -fixed false -x 612 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2_2\[0\] -fixed false -x 637 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[8\] -fixed false -x 43 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[22\] -fixed false -x 180 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5\[8\] -fixed false -x 297 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[0\] -fixed false -x 152 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[10\] -fixed false -x 832 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[14\] -fixed false -x 241 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_257 -fixed false -x 672 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1\[10\] -fixed false -x 516 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand0_mux_sel_1_iv_2_RNIT2VUG\[0\] -fixed false -x 781 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI9FUT5 -fixed false -x 294 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[8\] -fixed false -x 416 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[10\] -fixed false -x 92 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2127_0 -fixed false -x 648 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor\[48\] -fixed false -x 934 -y 181
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_813 -fixed false -x 612 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un17_iIlo1lto10_fc_1 -fixed false -x 154 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[8\] -fixed false -x 91 -y 169
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1 -fixed false -x 536 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_0 -fixed false -x 193 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[21\] -fixed false -x 275 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11\[24\] -fixed false -x 449 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO\[10\] -fixed false -x 316 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[11\] -fixed false -x 744 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[16\] -fixed false -x 711 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[23\] -fixed false -x 655 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[26\] -fixed false -x 627 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_early\[1\] -fixed false -x 711 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io\[15\] -fixed false -x 48 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[30\] -fixed false -x 619 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[23\] -fixed false -x 757 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO_0 -fixed false -x 847 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[19\].BUFD_BLK -fixed false -x 481 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_ss0 -fixed false -x 744 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo\[0\] -fixed false -x 292 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[15\] -fixed false -x 133 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[2\] -fixed false -x 376 -y 235
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_RNO_0\[0\] -fixed false -x 96 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_218 -fixed false -x 601 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram0_\[22\] -fixed false -x 632 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_89 -fixed false -x 732 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_a2_0\[1\] -fixed false -x 823 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[33\] -fixed false -x 488 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOI11_0_a3 -fixed false -x 132 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_972 -fixed false -x 699 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_0\[8\] -fixed false -x 685 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3_RNI81TOD -fixed false -x 97 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[6\] -fixed false -x 69 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m154 -fixed false -x 283 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1OIo -fixed false -x 146 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_1\[1\] -fixed false -x 109 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_56 -fixed false -x 745 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0\[17\] -fixed false -x 684 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m15 -fixed false -x 271 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3\[23\] -fixed false -x 459 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[24\] -fixed false -x 408 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[35\] -fixed false -x 937 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001\[3\] -fixed false -x 54 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write\[1\] -fixed false -x 636 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[10\] -fixed false -x 355 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[26\] -fixed false -x 949 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_300 -fixed false -x 709 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[7\] -fixed false -x 937 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[3\] -fixed false -x 378 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1\[10\] -fixed false -x 398 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6\[3\] -fixed false -x 312 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01\[4\] -fixed false -x 171 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_i_req_valid_3 -fixed false -x 765 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[7\] -fixed false -x 512 -y 190
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames\[1\] -fixed false -x 516 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0\[2\] -fixed false -x 648 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_77\[11\] -fixed false -x 342 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1\[9\] -fixed false -x 141 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1180 -fixed false -x 600 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_IioOo -fixed false -x 114 -y 177
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_state18_NE_i -fixed false -x 465 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20\[8\] -fixed false -x 238 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_852 -fixed false -x 686 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_0_0_0 -fixed false -x 97 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI12M4E\[6\] -fixed false -x 519 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[10\] -fixed false -x 375 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[7\] -fixed false -x 227 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[14\] -fixed false -x 346 -y 192
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[1\] -fixed false -x 482 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_RNO\[2\] -fixed false -x 187 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[15\] -fixed false -x 314 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17\[25\] -fixed false -x 829 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg\[5\] -fixed false -x 759 -y 136
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1_2_f0 -fixed false -x 298 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[10\] -fixed false -x 675 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10\[0\] -fixed false -x 319 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[5\] -fixed false -x 77 -y 205
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO\[3\] -fixed false -x 523 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_1\[1\] -fixed false -x 619 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_o8\[3\] -fixed false -x 24 -y 174
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_int_1_sqmuxa_i -fixed false -x 477 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0\[10\] -fixed false -x 252 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_3\[27\] -fixed false -x 132 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[0\] -fixed false -x 434 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[3\] -fixed false -x 455 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_6 -fixed false -x 72 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[5\] -fixed false -x 322 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[8\] -fixed false -x 373 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[30\] -fixed false -x 618 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_o0iIo -fixed false -x 392 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011\[9\] -fixed false -x 283 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[0\] -fixed false -x 862 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[13\] -fixed false -x 368 -y 199
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_2_sqmuxa_1 -fixed false -x 69 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI75FRQ1_1\[5\] -fixed false -x 872 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_4 -fixed false -x 739 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3\[0\] -fixed false -x 691 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr\[23\] -fixed false -x 751 -y 157
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4\[5\] -fixed false -x 68 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 386 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt\[16\] -fixed false -x 382 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1\[3\] -fixed false -x 513 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[28\] -fixed false -x 858 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3\[2\] -fixed false -x 210 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_csr_complete_retr_RNIIF5MG2 -fixed false -x 800 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[3\] -fixed false -x 291 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/i1o01 -fixed false -x 105 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0\[10\] -fixed false -x 360 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[5\] -fixed false -x 374 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ooll1 -fixed false -x 488 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14\[22\] -fixed false -x 384 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_18_RNIC7TC8 -fixed false -x 846 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[11\] -fixed false -x 340 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1_RNIJ52R7\[0\] -fixed false -x 46 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1099 -fixed false -x 733 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOOo1 -fixed false -x 305 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001\[1\] -fixed false -x 77 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m1 -fixed false -x 41 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_complete_qual_0_1_RNI263MP13 -fixed false -x 785 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3\[5\] -fixed false -x 924 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[15\] -fixed false -x 781 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_13\[10\] -fixed false -x 289 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv\[26\] -fixed false -x 158 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01\[1\] -fixed false -x 170 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1019 -fixed false -x 661 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0\[8\] -fixed false -x 228 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[25\] -fixed false -x 399 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_0\[2\] -fixed false -x 731 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[16\] -fixed false -x 924 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[14\] -fixed false -x 323 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2_1 -fixed false -x 822 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_2\[0\] -fixed false -x 47 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[24\] -fixed false -x 943 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[12\] -fixed false -x 29 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel_2_0 -fixed false -x 708 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0\[0\] -fixed false -x 347 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_105 -fixed false -x 710 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z\[27\] -fixed false -x 727 -y 124
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt\[4\] -fixed false -x 563 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[9\] -fixed false -x 304 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[8\] -fixed false -x 407 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr\[24\] -fixed false -x 813 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_5 -fixed false -x 668 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2\[25\] -fixed false -x 849 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_8 -fixed false -x 691 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_2 -fixed false -x 238 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3\[11\] -fixed false -x 911 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/un1_Ioli0_1_0 -fixed false -x 321 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_6 -fixed false -x 453 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[23\] -fixed false -x 74 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[1\].req_buff_resp_fault\[1\]\[2\] -fixed false -x 806 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[31\] -fixed false -x 887 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1\[21\] -fixed false -x 380 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[1\] -fixed false -x 409 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[30\] -fixed false -x 715 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_m3_1 -fixed false -x 840 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[3\] -fixed false -x 25 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[23\] -fixed false -x 244 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiOIo_1 -fixed false -x 136 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1\[19\] -fixed false -x 690 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[15\] -fixed false -x 325 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_5 -fixed false -x 138 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[1\] -fixed false -x 519 -y 193
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[23\].BUFD_BLK -fixed false -x 480 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[18\] -fixed false -x 537 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[17\] -fixed false -x 890 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_o2 -fixed false -x 106 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[17\] -fixed false -x 754 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_41\[1\] -fixed false -x 264 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_0 -fixed false -x 233 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0\[8\] -fixed false -x 572 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un50_OOOI1\[17\] -fixed false -x 448 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_148 -fixed false -x 696 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1087 -fixed false -x 741 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1051 -fixed false -x 674 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_8 -fixed false -x 831 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[25\] -fixed false -x 685 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_\[13\] -fixed false -x 658 -y 127
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/i_access_misalign_error_retr -fixed false -x 712 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[3\] -fixed false -x 71 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c_RNIF2MQ4P -fixed false -x 824 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_0 -fixed false -x 91 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1\[9\] -fixed false -x 451 -y 196
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state93_1 -fixed false -x 485 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo\[8\] -fixed false -x 71 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[5\] -fixed false -x 429 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1l1_u_2_0 -fixed false -x 463 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1\[3\] -fixed false -x 78 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo_RNO -fixed false -x 244 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[7\] -fixed false -x 211 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_dmactive -fixed false -x 762 -y 112
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[53\] -fixed false -x 572 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/full_out_RNO -fixed false -x 522 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOoI1 -fixed false -x 374 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un19_ool01\[6\] -fixed false -x 213 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1_cZ\[18\] -fixed false -x 262 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.debug_active_retr5 -fixed false -x 774 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_7 -fixed false -x 683 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_369 -fixed false -x 624 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[5\] -fixed false -x 774 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[11\] -fixed false -x 357 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_buff_resp_head_compressed_RNIF0SPP -fixed false -x 625 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[10\] -fixed false -x 936 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z\[3\] -fixed false -x 413 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[15\] -fixed false -x 140 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_2_0 -fixed false -x 807 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[15\] -fixed false -x 288 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[23\] -fixed false -x 902 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[28\] -fixed false -x 769 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0 -fixed false -x 104 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11\[27\] -fixed false -x 912 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_3_0\[2\] -fixed false -x 252 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_780 -fixed false -x 696 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[31\] -fixed false -x 852 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0\[14\] -fixed false -x 712 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave2_PRDATA_m\[9\] -fixed false -x 468 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_4\[1\] -fixed false -x 782 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un314_lIlo1lto15_3_0_4 -fixed false -x 145 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_2 -fixed false -x 45 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[5\] -fixed false -x 329 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1251 -fixed false -x 684 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_o2\[3\] -fixed false -x 708 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5\[4\] -fixed false -x 398 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo\[0\] -fixed false -x 471 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO\[0\] -fixed false -x 680 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[4\] -fixed false -x 410 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_6\[29\] -fixed false -x 312 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[1\] -fixed false -x 650 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_1\[15\] -fixed false -x 139 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1_2_0 -fixed false -x 60 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1\[3\] -fixed false -x 333 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO0018 -fixed false -x 38 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO\[26\] -fixed false -x 788 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_552 -fixed false -x 626 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[30\] -fixed false -x 599 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/un1_iOI01_1_i_0 -fixed false -x 336 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[7\] -fixed false -x 126 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_sw_csr_rd_op_cnst_1 -fixed false -x 657 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[19\] -fixed false -x 463 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0\[6\] -fixed false -x 124 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[12\] -fixed false -x 674 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNI42K8A_0 -fixed false -x 99 -y 213
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/ram_w_addr\[7\] -fixed false -x 404 -y 256
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/T_l_En_0_a2 -fixed false -x 492 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z\[3\] -fixed false -x 332 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_OIOl1_2_0 -fixed false -x 384 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oo101_RNO -fixed false -x 103 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_16 -fixed false -x 679 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10\[8\] -fixed false -x 380 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo56_1 -fixed false -x 36 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_36\[2\] -fixed false -x 495 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3 -fixed false -x 106 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1_2 -fixed false -x 12 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u\[26\] -fixed false -x 925 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0\[30\] -fixed false -x 748 -y 120
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel\[0\] -fixed false -x 37 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_16 -fixed false -x 648 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[2\] -fixed false -x 862 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27\[8\] -fixed false -x 277 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un9_IlIi1 -fixed false -x 169 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex_1\[0\] -fixed false -x 769 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[5\] -fixed false -x 373 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1\[2\] -fixed false -x 60 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1121 -fixed false -x 781 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[8\] -fixed false -x 361 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4953_5 -fixed false -x 647 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[43\] -fixed false -x 508 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[23\] -fixed false -x 268 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_4\[0\] -fixed false -x 49 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_3_9_0 -fixed false -x 755 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[8\] -fixed false -x 242 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[20\].BUFD_BLK -fixed false -x 528 -y 105
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[21\] -fixed false -x 765 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[2\] -fixed false -x 501 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[15\] -fixed false -x 394 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr\[0\] -fixed false -x 709 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0\[2\] -fixed false -x 228 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3 -fixed false -x 192 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[11\] -fixed false -x 801 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/un1_Ioli0_1_0_0 -fixed false -x 343 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un18_OilI1_0_a2_0 -fixed false -x 344 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01\[7\] -fixed false -x 207 -y 208
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4\[12\] -fixed false -x 388 -y 243
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_10_0_RNO -fixed false -x 800 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0_i_m3\[31\] -fixed false -x 552 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1io1 -fixed false -x 75 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex\[26\] -fixed false -x 798 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0OIo -fixed false -x 132 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[4\] -fixed false -x 403 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[4\] -fixed false -x 271 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/un1_Ioli0_1_0 -fixed false -x 319 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_m9 -fixed false -x 48 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6\[12\] -fixed false -x 952 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_768 -fixed false -x 601 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_810 -fixed false -x 780 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_s_RNIDHQ0AM -fixed false -x 825 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un4_l1I01 -fixed false -x 205 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_RNO\[0\] -fixed false -x 36 -y 219
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros_4_f0 -fixed false -x 534 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[20\] -fixed false -x 924 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[0\].lIII1\[3\] -fixed false -x 389 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1_1109_0 -fixed false -x 96 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_IlIi1_3 -fixed false -x 157 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[24\] -fixed false -x 719 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[5\] -fixed false -x 212 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[12\] -fixed false -x 132 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_10 -fixed false -x 696 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[17\] -fixed false -x 862 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[4\] -fixed false -x 719 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25\[10\] -fixed false -x 294 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt\[1\] -fixed false -x 168 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11\[17\] -fixed false -x 90 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_4_1_RNIO0MNI -fixed false -x 505 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2\[12\] -fixed false -x 849 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m17 -fixed false -x 42 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/next_buff_valid\[1\] -fixed false -x 764 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[2\] -fixed false -x 835 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78\[18\] -fixed false -x 959 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_addr_req\[0\]\[3\] -fixed false -x 869 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_reset_reg -fixed false -x 790 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO\[28\] -fixed false -x 900 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[18\] -fixed false -x 963 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[5\] -fixed false -x 95 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[32\] -fixed false -x 181 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[7\] -fixed false -x 93 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_1 -fixed false -x 779 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z\[2\] -fixed false -x 394 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[30\] -fixed false -x 950 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_156 -fixed false -x 672 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[12\] -fixed false -x 362 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29\[11\] -fixed false -x 228 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en\[2\] -fixed false -x 708 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io_RNIMTGD1 -fixed false -x 70 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[16\] -fixed false -x 683 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_47 -fixed false -x 601 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1049 -fixed false -x 744 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20\[9\] -fixed false -x 295 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_2_2 -fixed false -x 790 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[48\] -fixed false -x 935 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[12\] -fixed false -x 355 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[1\] -fixed false -x 556 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[12\] -fixed false -x 290 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un5_oIIi1 -fixed false -x 156 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oo0i1 -fixed false -x 227 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_valid -fixed false -x 815 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIDG984\[18\] -fixed false -x 927 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_2 -fixed false -x 728 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO\[2\] -fixed false -x 242 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/oo1Io_1 -fixed false -x 410 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient\[24\] -fixed false -x 892 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[14\] -fixed false -x 736 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state\[2\] -fixed false -x 709 -y 112
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2 -fixed false -x 60 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1\[1\] -fixed false -x 252 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp.gen_buff_loop\[0\].buff_entry_data_resp_ram1_\[8\] -fixed false -x 701 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z\[3\] -fixed false -x 343 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_2 -fixed false -x 144 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z\[0\] -fixed false -x 244 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_0_tz\[3\] -fixed false -x 696 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1\[2\].lIII1_53\[19\] -fixed false -x 468 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[21\] -fixed false -x 565 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_13 -fixed false -x 96 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_0_sqmuxa_i_o3_0 -fixed false -x 216 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr\[0\] -fixed false -x 791 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z\[5\] -fixed false -x 381 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[0\] -fixed false -x 259 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_1\[8\] -fixed false -x 144 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_723 -fixed false -x 758 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[7\] -fixed false -x 253 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[9\] -fixed false -x 281 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[0\] -fixed false -x 442 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[27\] -fixed false -x 183 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[7\] -fixed false -x 207 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2_0\[0\] -fixed false -x 108 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_137 -fixed false -x 614 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2\[16\] -fixed false -x 739 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2\[21\] -fixed false -x 343 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[32\] -fixed false -x 372 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[12\] -fixed false -x 137 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15\[21\] -fixed false -x 926 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_6 -fixed false -x 700 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo_RNO -fixed false -x 128 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO\[1\] -fixed false -x 145 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata1_mcontrol_hit/gen_bit_reset.state_val\[0\] -fixed false -x 827 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z\[1\] -fixed false -x 44 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[8\] -fixed false -x 362 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u\[0\] -fixed false -x 948 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_867 -fixed false -x 684 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1\[4\] -fixed false -x 529 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[3\] -fixed false -x 870 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_1_1_1 -fixed false -x 793 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO -fixed false -x 177 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1\[10\] -fixed false -x 34 -y 184
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[10\] -fixed false -x 289 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01 -fixed false -x 246 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_379 -fixed false -x 612 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITLTQ8\[26\] -fixed false -x 632 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_slow_mul_RNO_1 -fixed false -x 824 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0_0_0\[6\] -fixed false -x 268 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0\[14\] -fixed false -x 160 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[11\] -fixed false -x 721 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[49\] -fixed false -x 966 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_O1oOo\[1\] -fixed false -x 125 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[27\] -fixed false -x 467 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[5\] -fixed false -x 517 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[27\] -fixed false -x 385 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1\[29\] -fixed false -x 443 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[6\] -fixed false -x 765 -y 169
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_lsu_stall.un14_gpr_rs1_stall_lsu_RNIJCLR98 -fixed false -x 801 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[0\] -fixed false -x 542 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIB5FGI\[3\] -fixed false -x 462 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[31\] -fixed false -x 925 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1259 -fixed false -x 612 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[41\] -fixed false -x 916 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2_1 -fixed false -x 25 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0\[0\] -fixed false -x 761 -y 141
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[20\] -fixed false -x 406 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[17\] -fixed false -x 888 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1254 -fixed false -x 732 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_3 -fixed false -x 528 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err -fixed false -x 768 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM_0_a2\[2\] -fixed false -x 193 -y 213
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[11\].BUFD_BLK -fixed false -x 529 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_734 -fixed false -x 625 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[2\] -fixed false -x 350 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2\[19\] -fixed false -x 252 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io\[0\] -fixed false -x 374 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[8\] -fixed false -x 757 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[4\] -fixed false -x 245 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2123.rv32c_dec_mnemonic2123_1 -fixed false -x 645 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2121.rv32c_dec_mnemonic2121 -fixed false -x 636 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_1\[2\] -fixed false -x 753 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata\[1\] -fixed false -x 521 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1195 -fixed false -x 662 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIOI1 -fixed false -x 298 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m64_0 -fixed false -x 282 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[4\] -fixed false -x 891 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[15\] -fixed false -x 545 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/IilI1_RNO -fixed false -x 396 -y 168
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg\[13\] -fixed false -x 497 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12 -fixed false -x 805 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[21\] -fixed false -x 559 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1115 -fixed false -x 600 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[5\] -fixed false -x 840 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z\[9\] -fixed false -x 127 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1\[29\] -fixed false -x 414 -y 160
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[19\] -fixed false -x 391 -y 241
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[3\] -fixed false -x 83 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1\[1\] -fixed false -x 24 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23_1 -fixed false -x 796 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[21\] -fixed false -x 855 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oII11 -fixed false -x 128 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01\[2\] -fixed false -x 63 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m4 -fixed false -x 38 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[6\] -fixed false -x 81 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo\[0\] -fixed false -x 374 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[19\] -fixed false -x 833 -y 132
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[7\] -fixed false -x 378 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[8\] -fixed false -x 215 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111 -fixed false -x 264 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1_cZ\[8\] -fixed false -x 349 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1\[8\] -fixed false -x 534 -y 193
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r\[8\] -fixed false -x 382 -y 235
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9_2 -fixed false -x 510 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0\[9\] -fixed false -x 691 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_778 -fixed false -x 625 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[5\] -fixed false -x 397 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[21\] -fixed false -x 440 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO\[0\] -fixed false -x 781 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1267 -fixed false -x 685 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[34\] -fixed false -x 281 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01\[7\] -fixed false -x 170 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel\[11\] -fixed false -x 713 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[57\] -fixed false -x 551 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count\[2\] -fixed false -x 497 -y 97
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[12\] -fixed false -x 753 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[21\] -fixed false -x 434 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[0\] -fixed false -x 168 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA\[8\] -fixed false -x 637 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0\[4\] -fixed false -x 332 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNI6QHQ6\[8\] -fixed false -x 647 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io\[9\] -fixed false -x 33 -y 226
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[1\] -fixed false -x 275 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0_a2 -fixed false -x 192 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2\[2\] -fixed false -x 834 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1292 -fixed false -x 626 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1189 -fixed false -x 650 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt\[4\] -fixed false -x 339 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z\[0\] -fixed false -x 414 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/un1_Ioli0_1_0 -fixed false -x 333 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[11\] -fixed false -x 358 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_resumereq -fixed false -x 751 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_916 -fixed false -x 708 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[16\] -fixed false -x 611 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1212 -fixed false -x 665 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux\[25\] -fixed false -x 734 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[55\] -fixed false -x 552 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[4\] -fixed false -x 375 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i\[21\] -fixed false -x 256 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[1\] -fixed false -x 358 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3\[3\] -fixed false -x 199 -y 189
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[32\].BUFD_BLK -fixed false -x 505 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[2\].buff_entry_addr_req\[2\]\[1\] -fixed false -x 893 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_d\[0\]_0_sqmuxa -fixed false -x 493 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_10_RNI818323 -fixed false -x 25 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z\[5\] -fixed false -x 295 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un5_llOo1_1 -fixed false -x 301 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0\[8\] -fixed false -x 372 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[7\] -fixed false -x 364 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[4\] -fixed false -x 390 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7\[23\] -fixed false -x 441 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0_a2 -fixed false -x 112 -y 159
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15 -fixed false -x 462 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[10\] -fixed false -x 780 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[4\] -fixed false -x 149 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[29\] -fixed false -x 815 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[9\] -fixed false -x 663 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m231 -fixed false -x 242 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_4 -fixed false -x 230 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_RNO\[0\] -fixed false -x 105 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[48\] -fixed false -x 539 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1\[19\] -fixed false -x 438 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[6\] -fixed false -x 936 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[30\] -fixed false -x 115 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[3\] -fixed false -x 450 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[31\] -fixed false -x 627 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0\[3\] -fixed false -x 109 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[17\] -fixed false -x 454 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[7\] -fixed false -x 758 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO\[14\] -fixed false -x 144 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1\[6\] -fixed false -x 277 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1311 -fixed false -x 708 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_969 -fixed false -x 768 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1\[5\] -fixed false -x 901 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0__RNI944LE\[1\] -fixed false -x 809 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m24_1_0 -fixed false -x 30 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5\[22\] -fixed false -x 816 -y 126
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt\[0\] -fixed false -x 20 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1\[2\] -fixed false -x 542 -y 190
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB -fixed false -x 1155 -y 162
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[0\] -fixed false -x 159 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[21\] -fixed false -x 432 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmireset -fixed false -x 592 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_4_1\[0\] -fixed false -x 830 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1\[17\] -fixed false -x 339 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_24\[10\] -fixed false -x 288 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0\[6\] -fixed false -x 180 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iiOI1_2 -fixed false -x 522 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val\[11\] -fixed false -x 743 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[18\] -fixed false -x 932 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0\[0\] -fixed false -x 295 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_633 -fixed false -x 601 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r\[21\] -fixed false -x 387 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2\[1\] -fixed false -x 756 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb\[0\].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9\[8\] -fixed false -x 755 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_877 -fixed false -x 696 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4_0_0 -fixed false -x 456 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI34M4E\[7\] -fixed false -x 527 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1\[25\] -fixed false -x 925 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[1\] -fixed false -x 102 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[1\] -fixed false -x 556 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30\[18\] -fixed false -x 962 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_2 -fixed false -x 794 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState\[7\] -fixed false -x 573 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[1\] -fixed false -x 211 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[4\] -fixed false -x 179 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_22 -fixed false -x 673 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO\[0\] -fixed false -x 259 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1\[6\] -fixed false -x 429 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2\[29\] -fixed false -x 799 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[26\] -fixed false -x 315 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_5_188_a2 -fixed false -x 432 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[15\] -fixed false -x 324 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i1il1 -fixed false -x 518 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[6\] -fixed false -x 236 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_640 -fixed false -x 708 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_3 -fixed false -x 96 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_3_1_0 -fixed false -x 705 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_45 -fixed false -x 636 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[17\] -fixed false -x 438 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_1 -fixed false -x 225 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[37\] -fixed false -x 355 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1 -fixed false -x 516 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[0\] -fixed false -x 268 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_1\[6\] -fixed false -x 270 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un85_OOOI1\[2\] -fixed false -x 266 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_0_0 -fixed false -x 180 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[6\] -fixed false -x 795 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[25\] -fixed false -x 733 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m26 -fixed false -x 48 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q\[0\] -fixed false -x 516 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oi1Oo -fixed false -x 144 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1\[21\] -fixed false -x 474 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_448 -fixed false -x 744 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[2\] -fixed false -x 738 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_addr_align\[0\] -fixed false -x 817 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_1 -fixed false -x 636 -y 135
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRUPD -fixed false -x 504 -y 90
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[0\] -fixed false -x 408 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_sel_1_iv_0\[1\] -fixed false -x 731 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[20\] -fixed false -x 608 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[25\] -fixed false -x 411 -y 202
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr\[9\] -fixed false -x 478 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[9\] -fixed false -x 333 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8\[2\] -fixed false -x 364 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[24\] -fixed false -x 950 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2\[3\] -fixed false -x 768 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1\[3\] -fixed false -x 21 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[13\] -fixed false -x 25 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27\[3\] -fixed false -x 393 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[1\] -fixed false -x 391 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_11 -fixed false -x 228 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8\[29\] -fixed false -x 473 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1\[13\] -fixed false -x 133 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1\[0\] -fixed false -x 130 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_107 -fixed false -x 720 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[9\] -fixed false -x 596 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI8CA84\[22\] -fixed false -x 914 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo\[5\] -fixed false -x 71 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[25\] -fixed false -x 863 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_19 -fixed false -x 834 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z\[3\] -fixed false -x 407 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1\[3\] -fixed false -x 172 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[29\] -fixed false -x 948 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_950 -fixed false -x 612 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIi11 -fixed false -x 349 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0\[6\] -fixed false -x 73 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0\[9\] -fixed false -x 38 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0_a3_0_0 -fixed false -x 168 -y 198
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_2_sqmuxa_i -fixed false -x 517 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13 -fixed false -x 810 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[14\] -fixed false -x 401 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[13\] -fixed false -x 866 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[3\] -fixed false -x 673 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0\[3\] -fixed false -x 331 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[9\] -fixed false -x 852 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]_3\[2\] -fixed false -x 755 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1145 -fixed false -x 684 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter\[6\] -fixed false -x 786 -y 106
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_10_RNIHL8GT -fixed false -x 24 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[6\] -fixed false -x 145 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg\[19\] -fixed false -x 707 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[16\] -fixed false -x 653 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_o2 -fixed false -x 650 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0\[1\] -fixed false -x 168 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2\[1\] -fixed false -x 483 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2\[1\] -fixed false -x 253 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[27\] -fixed false -x 825 -y 157
|
|
set_location -inst_name CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ\[5\] -fixed false -x 481 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd\[31\] -fixed false -x 633 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0 -fixed false -x 94 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[35\] -fixed false -x 554 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01\[2\] -fixed false -x 183 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[13\] -fixed false -x 731 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO_1 -fixed false -x 851 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[25\] -fixed false -x 789 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[6\] -fixed false -x 719 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n4 -fixed false -x 196 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0Oo -fixed false -x 282 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un13_lolIo -fixed false -x 109 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[6\] -fixed false -x 627 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17\[5\] -fixed false -x 274 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_Ol1I18 -fixed false -x 450 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13\[1\] -fixed false -x 277 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state\[0\]\[0\] -fixed false -x 783 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[24\] -fixed false -x 948 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_RNICRUMP\[2\] -fixed false -x 116 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_4\[4\] -fixed false -x 120 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]_RNINQ6GO\[19\] -fixed false -x 880 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_4 -fixed false -x 744 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[11\] -fixed false -x 318 -y 172
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw\[0\] -fixed false -x 520 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z\[5\] -fixed false -x 270 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[10\] -fixed false -x 804 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.N_571_i -fixed false -x 209 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un34_l1I01 -fixed false -x 204 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_454 -fixed false -x 600 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data\[31\] -fixed false -x 704 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val\[22\] -fixed false -x 822 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z\[14\] -fixed false -x 143 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO\[0\] -fixed false -x 739 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_704 -fixed false -x 672 -y 189
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_12\[0\] -fixed false -x 745 -y 43
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41_cZ\[8\] -fixed false -x 205 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_816 -fixed false -x 709 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1\[13\] -fixed false -x 25 -y 205
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51\[8\] -fixed false -x 936 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1_3 -fixed false -x 35 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[27\] -fixed false -x 847 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex\[7\] -fixed false -x 702 -y 136
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1\[5\] -fixed false -x 799 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt\[3\] -fixed false -x 211 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[23\] -fixed false -x 924 -y 177
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/parity_err -fixed false -x 468 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0\[6\] -fixed false -x 237 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_4_3 -fixed false -x 698 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg\[13\] -fixed false -x 852 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOoOo -fixed false -x 237 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA\[0\] -fixed false -x 486 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_RNO\[1\] -fixed false -x 96 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.N_2_i_i -fixed false -x 62 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m\[11\] -fixed false -x 935 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[19\] -fixed false -x 446 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0\[4\] -fixed false -x 740 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1242 -fixed false -x 553 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_0_sqmuxa_2 -fixed false -x 684 -y 111
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[6\] -fixed false -x 81 -y 229
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIO11 -fixed false -x 46 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.set_step_debug_enter_pending_0 -fixed false -x 756 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_18 -fixed false -x 872 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_rd_en -fixed false -x 726 -y 127
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4_2\[1\] -fixed false -x 527 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[23\] -fixed false -x 689 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[2\] -fixed false -x 61 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/IilI1_RNO -fixed false -x 401 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_466 -fixed false -x 731 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[1\].buff_valid\[1\] -fixed false -x 764 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4952_5 -fixed false -x 639 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_6 -fixed false -x 132 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24\[8\] -fixed false -x 715 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_0_1 -fixed false -x 69 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDR_ne_0_3 -fixed false -x 554 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg\[25\] -fixed false -x 484 -y 169
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout\[17\] -fixed false -x 407 -y 241
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_iv_RNO\[1\] -fixed false -x 740 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_6 -fixed false -x 80 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1oO1\[0\] -fixed false -x 156 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28\[3\] -fixed false -x 370 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_5\[1\] -fixed false -x 789 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m202 -fixed false -x 253 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[9\] -fixed false -x 440 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[21\] -fixed false -x 894 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un59_Oi1O1\[4\] -fixed false -x 402 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[3\] -fixed false -x 437 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_0\[10\] -fixed false -x 332 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_1_1_0 -fixed false -x 630 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[4\] -fixed false -x 349 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo\[10\] -fixed false -x 106 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo\[5\] -fixed false -x 113 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[18\] -fixed false -x 733 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_979 -fixed false -x 734 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_m2 -fixed false -x 674 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1\[7\] -fixed false -x 73 -y 205
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count\[7\] -fixed false -x 500 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[14\] -fixed false -x 761 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend\[23\] -fixed false -x 855 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_10 -fixed false -x 571 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[8\] -fixed false -x 229 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3\[6\] -fixed false -x 295 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[5\] -fixed false -x 756 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2\[1\] -fixed false -x 655 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m7 -fixed false -x 41 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1\[11\] -fixed false -x 132 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1 -fixed false -x 830 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4\[4\] -fixed false -x 780 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr\[1\] -fixed false -x 764 -y 136
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[4\] -fixed false -x 498 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_\[11\] -fixed false -x 665 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_ioIO1_NE -fixed false -x 123 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_215 -fixed false -x 683 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooOi1_RNO -fixed false -x 187 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1\[19\] -fixed false -x 73 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m59 -fixed false -x 26 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0\[3\] -fixed false -x 753 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_retr_2_RNITV316 -fixed false -x 770 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z\[5\] -fixed false -x 109 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1\[59\] -fixed false -x 926 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_284 -fixed false -x 760 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[22\] -fixed false -x 450 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4\[1\] -fixed false -x 630 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_drop\[0\] -fixed false -x 816 -y 124
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_IIiO1_1 -fixed false -x 355 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0\[8\] -fixed false -x 30 -y 207
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft\[9\] -fixed false -x 394 -y 235
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp\[26\] -fixed false -x 545 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[3\] -fixed false -x 318 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt\[22\] -fixed false -x 414 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m10 -fixed false -x 108 -y 189
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_c2 -fixed false -x 41 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l1iIo -fixed false -x 435 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt\[2\] -fixed false -x 836 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[11\] -fixed false -x 136 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[26\] -fixed false -x 416 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0\[3\] -fixed false -x 360 -y 168
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt\[3\] -fixed false -x 16 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[9\] -fixed false -x 344 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_0\[2\] -fixed false -x 698 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1_RNIO9H6E -fixed false -x 19 -y 159
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[26\] -fixed false -x 410 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1li1 -fixed false -x 190 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo\[3\] -fixed false -x 341 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi1 -fixed false -x 113 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[28\] -fixed false -x 756 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo -fixed false -x 129 -y 166
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2 -fixed false -x 560 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_132 -fixed false -x 613 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_491 -fixed false -x 600 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[6\] -fixed false -x 238 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/un1_iOI01_1_i_0 -fixed false -x 247 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[18\] -fixed false -x 113 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_792 -fixed false -x 600 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff_6_iv_i -fixed false -x 769 -y 114
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q\[1\] -fixed false -x 511 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0\[7\] -fixed false -x 737 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE\[5\] -fixed false -x 40 -y 217
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNI6NV62\[0\] -fixed false -x 372 -y 228
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[36\] -fixed false -x 277 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3_m\[2\] -fixed false -x 733 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2\[14\] -fixed false -x 433 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3\[10\] -fixed false -x 836 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2\[5\] -fixed false -x 717 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un35_I1Oi1_1 -fixed false -x 38 -y 177
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_4 -fixed false -x 504 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[2\] -fixed false -x 799 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1\[1\] -fixed false -x 167 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state\[3\] -fixed false -x 777 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1_2 -fixed false -x 48 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt\[1\] -fixed false -x 247 -y 187
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[4\].BUFD_BLK -fixed false -x 480 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[8\] -fixed false -x 263 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1\[7\] -fixed false -x 156 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_531 -fixed false -x 744 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z\[1\] -fixed false -x 143 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel_1_1 -fixed false -x 693 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1\[2\] -fixed false -x 666 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0\[6\] -fixed false -x 300 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0\[24\] -fixed false -x 193 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_RNO\[2\] -fixed false -x 492 -y 93
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0\[11\] -fixed false -x 228 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff\[26\] -fixed false -x 721 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2\[3\] -fixed false -x 720 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO_1 -fixed false -x 827 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_1_sqmuxa -fixed false -x 789 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex\[6\] -fixed false -x 729 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt\[3\] -fixed false -x 306 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1\[3\] -fixed false -x 108 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_603 -fixed false -x 637 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m24 -fixed false -x 108 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0\[10\] -fixed false -x 500 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioI11 -fixed false -x 274 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6\[12\] -fixed false -x 424 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[8\] -fixed false -x 206 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35\[18\] -fixed false -x 954 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[4\] -fixed false -x 725 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[13\] -fixed false -x 442 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[0\] -fixed false -x 420 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[13\] -fixed false -x 668 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_retr_d_1 -fixed false -x 797 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4\[5\] -fixed false -x 416 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.IloIo -fixed false -x 252 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_634 -fixed false -x 717 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[15\] -fixed false -x 545 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0\[8\] -fixed false -x 204 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[6\] -fixed false -x 295 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[1\] -fixed false -x 613 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata\[21\] -fixed false -x 559 -y 154
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re -fixed false -x 530 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_il0Oo_0 -fixed false -x 156 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1\[0\] -fixed false -x 44 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val\[13\] -fixed false -x 755 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12\[1\] -fixed false -x 406 -y 201
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4\[1\] -fixed false -x 516 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1\[9\] -fixed false -x 139 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1\[4\] -fixed false -x 83 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11\[15\] -fixed false -x 24 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_1_0_0 -fixed false -x 811 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[6\] -fixed false -x 836 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt\[13\] -fixed false -x 239 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[14\] -fixed false -x 451 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_0_2 -fixed false -x 803 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1\[3\] -fixed false -x 508 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[13\] -fixed false -x 474 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2\[3\] -fixed false -x 674 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[11\] -fixed false -x 241 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[4\] -fixed false -x 357 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1\[2\] -fixed false -x 77 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_OOoo1_0_a3_1_1 -fixed false -x 108 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[23\] -fixed false -x 853 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0\[1\] -fixed false -x 768 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_o2_0\[1\] -fixed false -x 822 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_c_1 -fixed false -x 778 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_0_m3\[1\] -fixed false -x 684 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1\[18\] -fixed false -x 446 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO\[30\] -fixed false -x 958 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1003 -fixed false -x 613 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01\[8\] -fixed false -x 201 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0\[2\] -fixed false -x 240 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0_4\[0\] -fixed false -x 701 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[46\] -fixed false -x 962 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment -fixed false -x 803 -y 145
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1\[0\] -fixed false -x 345 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z\[4\] -fixed false -x 400 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/IilIo -fixed false -x 48 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_1_1_0 -fixed false -x 785 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[57\] -fixed false -x 843 -y 172
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_2\[1\] -fixed false -x 732 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0\[30\] -fixed false -x 949 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1\[21\] -fixed false -x 690 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io\[17\] -fixed false -x 76 -y 232
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[10\] -fixed false -x 632 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_937 -fixed false -x 657 -y 174
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO -fixed false -x 560 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/alloc_resp_qual -fixed false -x 769 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2_3\[15\] -fixed false -x 612 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2\[9\] -fixed false -x 44 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[1\] -fixed false -x 365 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un91_OOOI1_cZ\[14\] -fixed false -x 276 -y 189
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/un1_NxtPrdata23_0 -fixed false -x 460 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_11 -fixed false -x 624 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7\[8\] -fixed false -x 742 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1\[1\] -fixed false -x 276 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1\[15\] -fixed false -x 291 -y 190
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNIMTARA -fixed false -x 699 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1__RNI03S5C\[25\] -fixed false -x 676 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[10\] -fixed false -x 938 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux\[31\] -fixed false -x 741 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.un2_o1ol1_0 -fixed false -x 359 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_476 -fixed false -x 588 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_3\[24\] -fixed false -x 429 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[31\] -fixed false -x 873 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1\[0\] -fixed false -x 475 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNIDP5VF\[15\] -fixed false -x 660 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3\[9\] -fixed false -x 113 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[24\] -fixed false -x 851 -y 160
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_q_1.CO2 -fixed false -x 553 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_0 -fixed false -x 177 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[61\] -fixed false -x 593 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[9\] -fixed false -x 514 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO\[12\] -fixed false -x 495 -y 192
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[12\].BUFD_BLK -fixed false -x 528 -y 102
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1303 -fixed false -x 552 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[2\] -fixed false -x 888 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI\[35\] -fixed false -x 628 -y 121
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96\[20\] -fixed false -x 938 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[26\] -fixed false -x 868 -y 133
|
|
set_location -inst_name Core_reset_pf_0/Core_reset_pf_0/dff_8\[0\] -fixed false -x 744 -y 43
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[29\] -fixed false -x 740 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_28 -fixed false -x 659 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1\[2\] -fixed false -x 147 -y 199
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.BNC1 -fixed false -x 442 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1 -fixed false -x 503 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0\[9\] -fixed false -x 165 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i -fixed false -x 384 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[2\] -fixed false -x 429 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg\[5\] -fixed false -x 712 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1\[9\] -fixed false -x 229 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11\[10\] -fixed false -x 53 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg\[3\] -fixed false -x 731 -y 130
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2\[18\] -fixed false -x 604 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO\[4\] -fixed false -x 100 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_o01O1 -fixed false -x 439 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0\[2\] -fixed false -x 720 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[3\] -fixed false -x 839 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0\[2\] -fixed false -x 85 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16\[10\] -fixed false -x 343 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[6\] -fixed false -x 769 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3\[9\] -fixed false -x 399 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[23\] -fixed false -x 375 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data\[0\]\[9\] -fixed false -x 814 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m\[10\] -fixed false -x 349 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val\[22\] -fixed false -x 764 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1\[19\] -fixed false -x 190 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram1_\[21\] -fixed false -x 659 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_71 -fixed false -x 648 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[17\] -fixed false -x 889 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[25\] -fixed false -x 888 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m0_i_a2_0_RNI6A7CTT\[0\] -fixed false -x 735 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt\[8\] -fixed false -x 304 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_220 -fixed false -x 759 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11\[1\] -fixed false -x 285 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/ram_init_soft_debug_reset -fixed false -x 756 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_21 -fixed false -x 91 -y 231
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNINHMQS\[5\] -fixed false -x 853 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[34\] -fixed false -x 513 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2\[2\] -fixed false -x 845 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22\[4\] -fixed false -x 204 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[13\] -fixed false -x 564 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_27_2 -fixed false -x 660 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[10\] -fixed false -x 83 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0\[2\] -fixed false -x 720 -y 135
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel\[0\] -fixed false -x 540 -y 145
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[29\] -fixed false -x 908 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_c_0 -fixed false -x 762 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[22\] -fixed false -x 412 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[22\] -fixed false -x 840 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6\[23\] -fixed false -x 782 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[8\] -fixed false -x 372 -y 208
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag\[0\] -fixed false -x 68 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0\[2\] -fixed false -x 766 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0\[31\] -fixed false -x 924 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram0_\[4\] -fixed false -x 798 -y 142
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIANK9D -fixed false -x 823 -y 129
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_19_0_RNO -fixed false -x 824 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[19\] -fixed false -x 85 -y 186
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_7 -fixed false -x 528 -y 99
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg\[2\] -fixed false -x 571 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5\[7\] -fixed false -x 397 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_6\[26\] -fixed false -x 944 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2\[1\] -fixed false -x 793 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[0\].u_tdata2_match_data/gen_bit_reset.state_val_33\[18\] -fixed false -x 825 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2\[5\] -fixed false -x 346 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt\[11\] -fixed false -x 380 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo\[2\] -fixed false -x 341 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[3\] -fixed false -x 318 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[17\] -fixed false -x 588 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_1 -fixed false -x 221 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_432 -fixed false -x 625 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0\[0\] -fixed false -x 372 -y 165
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_2 -fixed false -x 516 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2\[12\] -fixed false -x 766 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1\[0\] -fixed false -x 60 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1\[7\] -fixed false -x 93 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ\[3\] -fixed false -x 513 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ll111 -fixed false -x 94 -y 223
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel -fixed false -x 547 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3\[4\] -fixed false -x 357 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01\[4\] -fixed false -x 197 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z\[1\] -fixed false -x 788 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_1\[3\] -fixed false -x 873 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32\[1\] -fixed false -x 285 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr_RNI5NJ77\[0\] -fixed false -x 667 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv\[26\] -fixed false -x 888 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt\[13\] -fixed false -x 415 -y 175
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m180 -fixed false -x 252 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV\[2\] -fixed false -x 507 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2\[5\] -fixed false -x 504 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8\[26\] -fixed false -x 591 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[17\] -fixed false -x 461 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[26\] -fixed false -x 769 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[19\] -fixed false -x 591 -y 121
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1\[9\] -fixed false -x 422 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1_0 -fixed false -x 826 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oi1l1\[2\] -fixed false -x 418 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4\[2\] -fixed false -x 252 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3\[12\] -fixed false -x 72 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_valid\[0\] -fixed false -x 760 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex\[21\] -fixed false -x 742 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data\[23\] -fixed false -x 871 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O1lIo_1_0_.m11 -fixed false -x 34 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_12 -fixed false -x 677 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/un1_iOI01_1_0_a3_i -fixed false -x 327 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1\[27\] -fixed false -x 428 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_0_o2_1\[3\] -fixed false -x 708 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt\[8\] -fixed false -x 257 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[16\] -fixed false -x 697 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1\[11\] -fixed false -x 499 -y 196
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2\[0\].BUFD_TRST/bufd_gen\[0\].BUFD_BLK -fixed false -x 528 -y 96
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1\[0\] -fixed false -x 397 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt\[8\] -fixed false -x 356 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3\[4\] -fixed false -x 97 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2123_1 -fixed false -x 653 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1\[4\] -fixed false -x 269 -y 151
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt\[11\] -fixed false -x 326 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_17\[20\] -fixed false -x 109 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0\[1\] -fixed false -x 833 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_cZ\[15\] -fixed false -x 358 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce\[6\] -fixed false -x 912 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2\[17\] -fixed false -x 851 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex\[3\] -fixed false -x 773 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid41 -fixed false -x 852 -y 126
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[33\] -fixed false -x 119 -y 178
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11\[6\] -fixed false -x 214 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_ptr_RNI6QHQ6\[0\] -fixed false -x 640 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4920_1 -fixed false -x 612 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[15\] -fixed false -x 560 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[6\] -fixed false -x 540 -y 196
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel_RNIB5HSE -fixed false -x 520 -y 147
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state\[0\] -fixed false -x 521 -y 100
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_102 -fixed false -x 648 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo -fixed false -x 169 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1225 -fixed false -x 696 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01\[5\] -fixed false -x 173 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt\[9\] -fixed false -x 237 -y 178
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0\[2\] -fixed false -x 648 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0\[20\] -fixed false -x 861 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[15\] -fixed false -x 843 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ioo01 -fixed false -x 106 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int\[32\] -fixed false -x 840 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a2_0_0_2 -fixed false -x 708 -y 114
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[12\].BUFD_BLK -fixed false -x 504 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z\[10\] -fixed false -x 452 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oIll1 -fixed false -x 519 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_iIio1 -fixed false -x 83 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21\[5\] -fixed false -x 242 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ\[26\] -fixed false -x 852 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo\[0\] -fixed false -x 301 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt\[0\] -fixed false -x 243 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_501 -fixed false -x 624 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_i0lo1\[17\] -fixed false -x 380 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Iioi0 -fixed false -x 402 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1\[17\] -fixed false -x 452 -y 214
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg\[4\] -fixed false -x 568 -y 148
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg\[3\] -fixed false -x 497 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop\[0\].req_buff_resp_state_valid\[0\] -fixed false -x 796 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4\[61\] -fixed false -x 950 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13\[1\] -fixed false -x 339 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_1_a2_yy\[28\] -fixed false -x 838 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[7\] -fixed false -x 694 -y 127
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[13\] -fixed false -x 468 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1\[22\] -fixed false -x 345 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1\[10\] -fixed false -x 130 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_848 -fixed false -x 660 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_6 -fixed false -x 600 -y 168
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen\[29\].BUFD_BLK -fixed false -x 504 -y 111
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2\[25\] -fixed false -x 546 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4\[18\] -fixed false -x 463 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[10\] -fixed false -x 205 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0\[25\] -fixed false -x 736 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27\[11\] -fixed false -x 276 -y 168
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1\[7\] -fixed false -x 489 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/stage_ready_ex_2 -fixed false -x 735 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_604 -fixed false -x 708 -y 201
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen\[10\].BUFD_BLK -fixed false -x 480 -y 108
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat13 -fixed false -x 568 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo\[2\] -fixed false -x 105 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0_1\[1\] -fixed false -x 551 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1\[26\] -fixed false -x 668 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[38\] -fixed false -x 634 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42\[0\] -fixed false -x 240 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3\[7\] -fixed false -x 833 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[3\] -fixed false -x 625 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo\[2\] -fixed false -x 299 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9\[8\] -fixed false -x 194 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend\[11\] -fixed false -x 854 -y 190
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1\[15\] -fixed false -x 382 -y 196
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u -fixed false -x 884 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0_RNO -fixed false -x 684 -y 114
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_2\[1\] -fixed false -x 794 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z\[27\] -fixed false -x 323 -y 160
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_1_0 -fixed false -x 654 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2 -fixed false -x 33 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0\[8\] -fixed false -x 396 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oii11 -fixed false -x 348 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11\[8\] -fixed false -x 250 -y 214
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_823 -fixed false -x 636 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO\[1\] -fixed false -x 272 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12\[6\] -fixed false -x 144 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1\[1\].u_tdata2_match_data/gen_bit_reset.state_val\[14\] -fixed false -x 802 -y 184
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ\[2\] -fixed false -x 713 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO\[13\] -fixed false -x 555 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2\[18\] -fixed false -x 398 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/valid_out -fixed false -x 780 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net\[25\] -fixed false -x 484 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt\[11\] -fixed false -x 231 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1\[15\] -fixed false -x 466 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_2 -fixed false -x 684 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOi11_2_0 -fixed false -x 355 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_0 -fixed false -x 869 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1\[3\] -fixed false -x 268 -y 187
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01\[0\] -fixed false -x 73 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0\[0\] -fixed false -x 612 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_read_gpr_rs1_ex.gen_rs1_exu_stall.un7_gpr_rs1_stall_exu_NE_2 -fixed false -x 738 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_60 -fixed false -x 636 -y 195
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9 -fixed false -x 515 -y 93
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_shifter_unit_op_sel_ex7 -fixed false -x 768 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0\[11\] -fixed false -x 264 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23\[5\] -fixed false -x 193 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_907 -fixed false -x 708 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m22_d_1_1 -fixed false -x 108 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_8\[0\] -fixed false -x 790 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1130 -fixed false -x 636 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_228 -fixed false -x 624 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_csr_complete_retr_RNIFPA2C -fixed false -x 792 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1\[7\] -fixed false -x 431 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_RNI5NT6D -fixed false -x 835 -y 150
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc4 -fixed false -x 484 -y 96
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_358 -fixed false -x 624 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_266 -fixed false -x 720 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1 -fixed false -x 108 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO -fixed false -x 819 -y 135
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag\[0\] -fixed false -x 34 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_331 -fixed false -x 636 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1\[2\] -fixed false -x 359 -y 217
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_336 -fixed false -x 612 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0\[59\] -fixed false -x 569 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0\[5\] -fixed false -x 322 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[3\] -fixed false -x 121 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_247_i -fixed false -x 217 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr\[0\] -fixed false -x 667 -y 115
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO\[2\] -fixed false -x 514 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5\[16\] -fixed false -x 833 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[8\] -fixed false -x 196 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1\[0\] -fixed false -x 283 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_subsys_cfg_0_a2 -fixed false -x 743 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2\[6\] -fixed false -x 360 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[17\] -fixed false -x 432 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto3_0_RNI8GP9F -fixed false -x 144 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l01I1 -fixed false -x 462 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop\[0\].buff_valid\[0\] -fixed false -x 811 -y 133
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo\[3\] -fixed false -x 341 -y 154
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlIo1 -fixed false -x 295 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_16 -fixed false -x 600 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oo0I1_Z\[10\] -fixed false -x 389 -y 220
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places\[0\] -fixed false -x 866 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_3 -fixed false -x 444 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1\[2\] -fixed false -x 134 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO\[1\] -fixed false -x 102 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z\[17\] -fixed false -x 289 -y 154
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r\[0\] -fixed false -x 397 -y 238
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNISGOVC -fixed false -x 23 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIIC98E\[25\] -fixed false -x 681 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_851 -fixed false -x 757 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11\[10\] -fixed false -x 123 -y 157
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z\[31\] -fixed false -x 549 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1\[9\] -fixed false -x 139 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1\[6\] -fixed false -x 227 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0\[2\] -fixed false -x 409 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_0_sqmuxa_i_o2_RNIPF1OD -fixed false -x 615 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1\[24\] -fixed false -x 433 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO\[4\] -fixed false -x 536 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_2\[31\] -fixed false -x 924 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt\[1\] -fixed false -x 230 -y 187
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.ramout_1\[15\] -fixed false -x 618 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_1_N_4L5 -fixed false -x 803 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg\[0\] -fixed false -x 443 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0\[8\] -fixed false -x 288 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate\[7\] -fixed false -x 743 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1\[27\] -fixed false -x 948 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp\[16\] -fixed false -x 873 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0\[6\] -fixed false -x 348 -y 168
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z\[7\] -fixed false -x 133 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u\[2\] -fixed false -x 949 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01\[8\] -fixed false -x 40 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/un1_Ioli0_1 -fixed false -x 320 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0\[26\] -fixed false -x 661 -y 159
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel\[3\] -fixed false -x 515 -y 151
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_460 -fixed false -x 600 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex\[0\] -fixed false -x 835 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data\[3\] -fixed false -x 757 -y 123
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31\[6\] -fixed false -x 962 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo -fixed false -x 389 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO\[7\] -fixed false -x 126 -y 153
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state\[2\] -fixed false -x 426 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt\[2\] -fixed false -x 361 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt\[8\] -fixed false -x 270 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[30\] -fixed false -x 936 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0\[16\] -fixed false -x 768 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01\[4\] -fixed false -x 190 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1\[3\] -fixed false -x 209 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m\[8\] -fixed false -x 624 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[13\] -fixed false -x 856 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1_0_tz -fixed false -x 168 -y 195
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1\[23\] -fixed false -x 414 -y 240
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns\[4\] -fixed false -x 485 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z\[1\] -fixed false -x 130 -y 211
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_241 -fixed false -x 696 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z\[12\] -fixed false -x 365 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_76 -fixed false -x 624 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0\[11\] -fixed false -x 691 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state\[1\] -fixed false -x 787 -y 115
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data_cZ\[13\] -fixed false -x 653 -y 120
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_2_0 -fixed false -x 536 -y 147
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un16_i11Io -fixed false -x 408 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[13\] -fixed false -x 473 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11\[19\] -fixed false -x 90 -y 223
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1297 -fixed false -x 672 -y 186
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2\[21\] -fixed false -x 685 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1\[15\] -fixed false -x 367 -y 195
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata\[5\] -fixed false -x 494 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4\[36\] -fixed false -x 357 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o3_0\[0\] -fixed false -x 48 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1217 -fixed false -x 612 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt\[2\] -fixed false -x 320 -y 181
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_3 -fixed false -x 96 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr\[11\] -fixed false -x 766 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z\[16\] -fixed false -x 461 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0\[10\] -fixed false -x 116 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31 -fixed false -x 552 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_402 -fixed false -x 648 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIIo\[0\] -fixed false -x 108 -y 166
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n2 -fixed false -x 203 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1\[3\] -fixed false -x 362 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop\[0\].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\].buff_data_ram1_\[0\] -fixed false -x 761 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1\[6\] -fixed false -x 90 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2\[9\] -fixed false -x 852 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO\[21\] -fixed false -x 960 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1037 -fixed false -x 612 -y 135
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt\[13\] -fixed false -x 323 -y 175
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1\[29\] -fixed false -x 850 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0\[22\] -fixed false -x 664 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0I11 -fixed false -x 127 -y 199
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_188 -fixed false -x 660 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR\[2\] -fixed false -x 607 -y 118
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv_RNO\[28\] -fixed false -x 663 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_29\[20\] -fixed false -x 113 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47\[2\] -fixed false -x 948 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_143 -fixed false -x 705 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_2\[26\] -fixed false -x 724 -y 123
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01\[3\] -fixed false -x 121 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2\[14\] -fixed false -x 902 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1\[7\] -fixed false -x 349 -y 217
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un37_ool01\[9\] -fixed false -x 158 -y 213
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_axbxc4 -fixed false -x 309 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m\[18\] -fixed false -x 925 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_alu_op_completing_ex_s_RNIDE0BB -fixed false -x 778 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_22 -fixed false -x 840 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux\[4\] -fixed false -x 603 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14\[0\] -fixed false -x 276 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_2 -fixed false -x 189 -y 177
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1\[11\] -fixed false -x 854 -y 129
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOol1_2\[3\] -fixed false -x 416 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_6_0 -fixed false -x 703 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01\[9\] -fixed false -x 159 -y 214
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/un1_Ioli0_1_0 -fixed false -x 246 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0_1_0\[0\] -fixed false -x 319 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z\[1\] -fixed false -x 120 -y 208
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1\[7\] -fixed false -x 343 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_ready_1_RNIQ3P59 -fixed false -x 756 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo\[7\] -fixed false -x 71 -y 172
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un5_llOo1_2 -fixed false -x 308 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z\[3\] -fixed false -x 432 -y 151
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_pktsel -fixed false -x 519 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1\[2\] -fixed false -x 72 -y 169
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt\[8\] -fixed false -x 324 -y 166
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[1\].buff_entry_addr_req\[1\]\[23\] -fixed false -x 857 -y 148
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1\[24\] -fixed false -x 912 -y 141
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift\[5\] -fixed false -x 482 -y 148
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1\[6\] -fixed false -x 51 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1\[23\] -fixed false -x 244 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_\[26\] -fixed false -x 633 -y 118
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[17\] -fixed false -x 447 -y 214
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns\[4\] -fixed false -x 450 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0_1\[0\] -fixed false -x 636 -y 120
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loO11_0_a2 -fixed false -x 87 -y 213
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/valid_out -fixed false -x 805 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop\[0\].buff_entry_data_resp_1.gen_buff_loop\[0\].buff_entry_data_resp_1_ram2__RNIUO98E\[29\] -fixed false -x 630 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21\[5\] -fixed false -x 192 -y 177
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_8 -fixed false -x 18 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg\[17\] -fixed false -x 847 -y 130
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_0_sqmuxa_0_a3_0 -fixed false -x 192 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff\[25\] -fixed false -x 681 -y 124
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st\[1\] -fixed false -x 622 -y 154
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_2 -fixed false -x 648 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1089 -fixed false -x 683 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3\[5\] -fixed false -x 150 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3\[14\] -fixed false -x 134 -y 204
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1\[9\] -fixed false -x 84 -y 193
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0\[2\] -fixed false -x 204 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_ptr\[0\] -fixed false -x 633 -y 115
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_14\[9\] -fixed false -x 288 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loi11 -fixed false -x 303 -y 208
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_valid_RNI8T9MP -fixed false -x 820 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13\[5\] -fixed false -x 276 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1\[5\] -fixed false -x 520 -y 193
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_616 -fixed false -x 756 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0\[3\] -fixed false -x 228 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1\[17\] -fixed false -x 374 -y 202
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_91_u\[3\] -fixed false -x 900 -y 138
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z\[30\] -fixed false -x 417 -y 160
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1\[11\] -fixed false -x 428 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_m3\[2\] -fixed false -x 830 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val\[2\] -fixed false -x 723 -y 157
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo\[14\] -fixed false -x 123 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9\[30\] -fixed false -x 440 -y 186
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1_Z\[12\] -fixed false -x 434 -y 196
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0\[5\] -fixed false -x 109 -y 183
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_276 -fixed false -x 636 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_i_m2\[0\] -fixed false -x 725 -y 114
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIO11 -fixed false -x 14 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1_6\[29\] -fixed false -x 463 -y 207
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i -fixed false -x 710 -y 144
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1\[27\] -fixed false -x 728 -y 117
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_5\[31\] -fixed false -x 628 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0\[10\] -fixed false -x 696 -y 126
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_RNIVF55H -fixed false -x 574 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1\[9\] -fixed false -x 454 -y 211
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0\[1\] -fixed false -x 204 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.IlIl1\[13\] -fixed false -x 479 -y 202
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1\[0\] -fixed false -x 114 -y 169
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync\[0\] -fixed false -x 1 -y 205
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3\[5\] -fixed false -x 176 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0\[15\] -fixed false -x 124 -y 180
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA\[1\] -fixed false -x 480 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_0 -fixed false -x 360 -y 206
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0 -fixed false -x 660 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_5 -fixed false -x 504 -y 206
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0 -fixed false -x 804 -y 206
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0 -fixed false -x 504 -y 170
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0 -fixed false -x 816 -y 170
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0 -fixed false -x 696 -y 206
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 -fixed false -x 360 -y 233
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0 -fixed false -x 804 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0 -fixed false -x 504 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0 -fixed false -x 828 -y 170
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0 -fixed false -x 768 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_3 -fixed false -x 324 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop\[0\].buff_data_gen_buff_loop\[0\].buff_data_0_0/RAM64x12_PHYS_0 -fixed false -x 744 -y 140
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0 -fixed false -x 552 -y 170
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 -fixed false -x 396 -y 233
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0 -fixed false -x 540 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0 -fixed false -x 840 -y 170
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0 -fixed false -x 876 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0 -fixed false -x 900 -y 170
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0 -fixed false -x 492 -y 170
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0 -fixed false -x 696 -y 179
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_6 -fixed false -x 468 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0 -fixed false -x 624 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_7 -fixed false -x 396 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0 -fixed false -x 840 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0 -fixed false -x 588 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0 -fixed false -x 588 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_3 -fixed false -x 468 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_0 -fixed false -x 396 -y 206
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0 -fixed false -x 732 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_1 -fixed false -x 432 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_2 -fixed false -x 324 -y 206
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0 -fixed false -x 792 -y 170
|
|
set_location -inst_name PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 -fixed false -x 360 -y 260
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0 -fixed false -x 768 -y 179
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_2 -fixed false -x 540 -y 206
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_1 -fixed false -x 360 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0 -fixed false -x 660 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0 -fixed false -x 732 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0 -fixed false -x 624 -y 179
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0 -fixed false -x 864 -y 170
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_4 -fixed false -x 432 -y 179
|
|
set_location -inst_name PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 -fixed false -x 396 -y 260
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0 -fixed false -x 564 -y 170
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_3800 -fixed false -x 360 -y 153
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full6_5_RNI2RB6G -fixed false -x 396 -y 255
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_3807 -fixed false -x 228 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_3797 -fixed false -x 324 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_4_cry_0 -fixed false -x 492 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0 -fixed false -x 366 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_3798 -fixed false -x 341 -y 165
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT -fixed false -x 468 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0 -fixed false -x 39 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioi01_0_I_1 -fixed false -x 36 -y 210
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNICBJKF\[1\] -fixed false -x 876 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_cry_0 -fixed false -x 72 -y 219
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC\[0\] -fixed false -x 12 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_3818 -fixed false -x 204 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0 -fixed false -x 801 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_3840 -fixed false -x 156 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_3817 -fixed false -x 228 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_3816 -fixed false -x 240 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_3802 -fixed false -x 300 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un60_iloOo_cry_0 -fixed false -x 240 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_3811 -fixed false -x 360 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0 -fixed false -x 519 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_3825 -fixed false -x 252 -y 174
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0 -fixed false -x 94 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M -fixed false -x 492 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_3809 -fixed false -x 300 -y 165
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6 -fixed false -x 396 -y 237
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_0 -fixed false -x 49 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D -fixed false -x 144 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_3791 -fixed false -x 504 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_s_3795 -fixed false -x 828 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_3834 -fixed false -x 296 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0 -fixed false -x 420 -y 180
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_cry_0 -fixed false -x 93 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0 -fixed false -x 876 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_3806 -fixed false -x 180 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0 -fixed false -x 504 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_i0oi1_1_s_1_3842 -fixed false -x 264 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_IOIl1_cry_0 -fixed false -x 480 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0 -fixed false -x 792 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_3827 -fixed false -x 240 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0 -fixed false -x 72 -y 225
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNID1KK4 -fixed false -x 528 -y 201
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_cry_0 -fixed false -x 84 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_cry_0 -fixed false -x 540 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_3839 -fixed false -x 108 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1 -fixed false -x 855 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1_RNO_4 -fixed false -x 507 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1_cry_cy\[0\] -fixed false -x 384 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_3836 -fixed false -x 24 -y 225
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0 -fixed false -x 856 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0 -fixed false -x 144 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0 -fixed false -x 862 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIS9C3J -fixed false -x 192 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793 -fixed false -x 516 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_0 -fixed false -x 300 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_3832 -fixed false -x 300 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0 -fixed false -x 504 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_I0iOo_1_s_1_3838 -fixed false -x 300 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_s_3794 -fixed false -x 780 -y 105
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_cry_cy\[0\] -fixed false -x 168 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1 -fixed false -x 915 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0 -fixed false -x 195 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL -fixed false -x 423 -y 207
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s_3792 -fixed false -x 492 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_3803 -fixed false -x 204 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy -fixed false -x 567 -y 141
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_3835 -fixed false -x 36 -y 228
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[0\] -fixed false -x 771 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6 -fixed false -x 141 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_3796 -fixed false -x 325 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0 -fixed false -x 528 -y 153
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_3789 -fixed false -x 842 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_3819 -fixed false -x 168 -y 174
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIT8GH5\[8\] -fixed false -x 384 -y 228
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_0 -fixed false -x 384 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_3801 -fixed false -x 372 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNIDL29J -fixed false -x 348 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_3833 -fixed false -x 391 -y 183
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_5_cry_0 -fixed false -x 84 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0 -fixed false -x 139 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0 -fixed false -x 318 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0 -fixed false -x 913 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un42_i0oi1_cry_0 -fixed false -x 249 -y 150
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/iOol1_RNIHSQ7J -fixed false -x 396 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_3829 -fixed false -x 335 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0 -fixed false -x 526 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_3828 -fixed false -x 322 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_3820 -fixed false -x 300 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0 -fixed false -x 358 -y 210
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un90_fine_sel_cry_0 -fixed false -x 58 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_3813 -fixed false -x 168 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_3824 -fixed false -x 360 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_3790 -fixed false -x 72 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_3799 -fixed false -x 384 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_0_I_1 -fixed false -x 384 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1\[0\] -fixed false -x 480 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0 -fixed false -x 357 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6 -fixed false -x 165 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0 -fixed false -x 456 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_3805 -fixed false -x 258 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0 -fixed false -x 695 -y 117
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0 -fixed false -x 219 -y 183
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sc_r_fwft_cry_0 -fixed false -x 408 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_3837 -fixed false -x 84 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_li1l1_cry_0 -fixed false -x 420 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_3812 -fixed false -x 228 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_Ii1l1_cry_0 -fixed false -x 421 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0 -fixed false -x 204 -y 216
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0 -fixed false -x 432 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNIM931E\[1\] -fixed false -x 48 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_3808 -fixed false -x 276 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un7_il0Oo_cry_0 -fixed false -x 264 -y 153
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_Oo1I1_cry_0 -fixed false -x 408 -y 210
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_3830 -fixed false -x 396 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_3826 -fixed false -x 252 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0 -fixed false -x 342 -y 216
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0 -fixed false -x 853 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy -fixed false -x 876 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_3823 -fixed false -x 242 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_o1Ii1_cry_0 -fixed false -x 300 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[1\] -fixed false -x 795 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_3815 -fixed false -x 168 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_3821 -fixed false -x 300 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_RNI6F57F\[0\] -fixed false -x 20 -y 210
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_lcry_cy -fixed false -x 372 -y 234
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_3810 -fixed false -x 288 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1 -fixed false -x 538 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_3804 -fixed false -x 414 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_I1Ii1_s_1_3841 -fixed false -x 288 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_3831 -fixed false -x 216 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_3814 -fixed false -x 204 -y 171
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_3822 -fixed false -x 264 -y 180
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy -fixed false -x 876 -y 153
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0 -fixed false -x 516 -y 150
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_2_u_2_1_0_wmux -fixed false -x 432 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted_2_1_0_wmux\[2\] -fixed false -x 831 -y 120
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[28\] -fixed false -x 753 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[23\] -fixed false -x 780 -y 171
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[16\] -fixed false -x 750 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m96_1_0_wmux -fixed false -x 219 -y 204
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[24\] -fixed false -x 822 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m71_1_0_wmux -fixed false -x 234 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[4\] -fixed false -x 774 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m34_1_0_wmux -fixed false -x 72 -y 192
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux\[6\] -fixed false -x 57 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m160_1_0_wmux -fixed false -x 273 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m263_1_1_wmux -fixed false -x 264 -y 195
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux\[3\] -fixed false -x 114 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[22\] -fixed false -x 777 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m192_1_0_wmux -fixed false -x 243 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[17\] -fixed false -x 750 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[3\] -fixed false -x 342 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[5\] -fixed false -x 789 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[8\] -fixed false -x 960 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[14\] -fixed false -x 948 -y 147
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[21\] -fixed false -x 798 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m69_1_0_wmux -fixed false -x 279 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m65_1_0_wmux -fixed false -x 24 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m175_1_1_wmux -fixed false -x 282 -y 198
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux\[2\] -fixed false -x 111 -y 219
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m214_1_0_wmux -fixed false -x 255 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[19\] -fixed false -x 744 -y 165
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux\[3\] -fixed false -x 108 -y 219
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[25\] -fixed false -x 756 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[13\] -fixed false -x 912 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[8\] -fixed false -x 762 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[1\] -fixed false -x 330 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[9\] -fixed false -x 888 -y 132
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[5\] -fixed false -x 912 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[1\] -fixed false -x 888 -y 135
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[6\] -fixed false -x 960 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[10\] -fixed false -x 759 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m21_1_0_wmux -fixed false -x 36 -y 171
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_9_1_0_wmux -fixed false -x 573 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[7\] -fixed false -x 900 -y 141
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted_2_1_0_wmux\[1\] -fixed false -x 828 -y 120
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux\[4\] -fixed false -x 36 -y 222
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[2\] -fixed false -x 960 -y 144
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m297_1_0_wmux -fixed false -x 280 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[30\] -fixed false -x 821 -y 180
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m17_2_1_0_wmux -fixed false -x 36 -y 192
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m7_1_0_wmux -fixed false -x 60 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[26\] -fixed false -x 816 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m51_1_0_wmux -fixed false -x 252 -y 156
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[10\] -fixed false -x 936 -y 150
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[12\] -fixed false -x 936 -y 132
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[7\] -fixed false -x 339 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_1_0_wmux -fixed false -x 120 -y 192
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[11\] -fixed false -x 912 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[6\] -fixed false -x 759 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[27\] -fixed false -x 806 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[18\] -fixed false -x 816 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[9\] -fixed false -x 780 -y 168
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[13\] -fixed false -x 762 -y 165
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_11_1_0_wmux -fixed false -x 570 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[6\] -fixed false -x 339 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[14\] -fixed false -x 756 -y 159
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m164_1_0_wmux -fixed false -x 278 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[3\] -fixed false -x 888 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux\[4\] -fixed false -x 936 -y 138
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[12\] -fixed false -x 795 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[29\] -fixed false -x 810 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m41_2_1_0_wmux -fixed false -x 27 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m312_1_0_wmux -fixed false -x 279 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[5\] -fixed false -x 327 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_1_0_0_wmux -fixed false -x 48 -y 189
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[7\] -fixed false -x 771 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m27_1_0_wmux -fixed false -x 231 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_32_1_0_wmux -fixed false -x 888 -y 183
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m10_1_0_wmux -fixed false -x 36 -y 174
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[20\] -fixed false -x 744 -y 168
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux\[5\] -fixed false -x 54 -y 222
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_wmux -fixed false -x 564 -y 159
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[11\] -fixed false -x 746 -y 165
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_i_m4_1_0_wmux\[2\] -fixed false -x 768 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m187_1_0_wmux -fixed false -x 276 -y 195
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m280_1_0_wmux -fixed false -x 252 -y 198
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[3\] -fixed false -x 756 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m55_1_0_wmux -fixed false -x 24 -y 189
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m44_1_0_wmux -fixed false -x 238 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m330_1_0_wmux -fixed false -x 254 -y 201
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux\[15\] -fixed false -x 792 -y 165
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[4\] -fixed false -x 336 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m302_1_0_wmux -fixed false -x 276 -y 198
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m60_0_1_0_wmux -fixed false -x 276 -y 156
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[0\] -fixed false -x 336 -y 207
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m13_2_1_0_wmux -fixed false -x 36 -y 198
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux\[6\] -fixed false -x 51 -y 222
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m236_1_0_wmux -fixed false -x 240 -y 195
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_i_m4_1_0_wmux\[31\] -fixed false -x 792 -y 174
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux\[2\] -fixed false -x 324 -y 201
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m18_1_0_wmux -fixed false -x 216 -y 204
|
|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux\[5\] -fixed false -x 48 -y 222
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0 -fixed false -x 586 -y 122
|
|
set_location -inst_name COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1_RGB0 -fixed false -x 576 -y 93
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB0 -fixed false -x 577 -y 233
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1 -fixed false -x 577 -y 206
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB10 -fixed false -x 583 -y 14
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB2 -fixed false -x 583 -y 206
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB3 -fixed false -x 577 -y 179
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4 -fixed false -x 583 -y 179
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5 -fixed false -x 577 -y 149
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6 -fixed false -x 583 -y 149
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB7 -fixed false -x 583 -y 122
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB8 -fixed false -x 583 -y 95
|
|
set_location -inst_name PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB9 -fixed false -x 583 -y 41
|
|
set_location -inst_name PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB0 -fixed false -x 580 -y 205
|
|
set_location -inst_name PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB1 -fixed false -x 580 -y 178
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1_RGB0 -fixed false -x 579 -y 204
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1_RGB1 -fixed false -x 579 -y 177
|
|
set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1_RGB2 -fixed false -x 579 -y 147
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_0_CC_0 -fixed false -x 384 -y 236
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_CC_0 -fixed false -x 396 -y 239
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIT8GH5\[8\]_CC_0 -fixed false -x 384 -y 230
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_lcry_cy_CC_0 -fixed false -x 372 -y 236
|
|
set_location -inst_name COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sc_r_fwft_cry_0_CC_0 -fixed false -x 408 -y 236
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s_3792_CC_0 -fixed false -x 492 -y 146
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_CC_0 -fixed false -x 528 -y 155
|
|
set_location -inst_name CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_CC_0 -fixed false -x 516 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_cry_cy\[0\]_CC_0 -fixed false -x 168 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioi01_0_I_1_CC_0 -fixed false -x 36 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNIM931E\[1\]_CC_0 -fixed false -x 48 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_3790_CC_0 -fixed false -x 72 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_3790_CC_1 -fixed false -x 84 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_RNI6F57F\[0\]_CC_0 -fixed false -x 20 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_RNI6F57F\[0\]_CC_1 -fixed false -x 24 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0_CC_0 -fixed false -x 72 -y 227
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0_CC_1 -fixed false -x 84 -y 227
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIS9C3J_CC_0 -fixed false -x 192 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_IOIl1_cry_0_CC_0 -fixed false -x 480 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1_CC_0 -fixed false -x 538 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1_CC_1 -fixed false -x 540 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNID1KK4_CC_0 -fixed false -x 528 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNID1KK4_CC_1 -fixed false -x 540 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_3791_CC_0 -fixed false -x 504 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_3791_CC_1 -fixed false -x 516 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_CC_0 -fixed false -x 492 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_CC_1 -fixed false -x 504 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1\[0\]_CC_0 -fixed false -x 480 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1\[0\]_CC_1 -fixed false -x 492 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1_RNO_4_CC_0 -fixed false -x 507 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0_CC_0 -fixed false -x 456 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0_CC_1 -fixed false -x 468 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1_cry_cy\[0\]_CC_0 -fixed false -x 384 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1_cry_cy\[0\]_CC_1 -fixed false -x 396 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/iOol1_RNIHSQ7J_CC_0 -fixed false -x 396 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/iOol1_RNIHSQ7J_CC_1 -fixed false -x 408 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_Oo1I1_cry_0_CC_0 -fixed false -x 408 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un1_Oo1I1_cry_0_CC_1 -fixed false -x 420 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_Ii1l1_cry_0_CC_0 -fixed false -x 421 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un2_li1l1_cry_0_CC_0 -fixed false -x 420 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0_CC_0 -fixed false -x 342 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0_CC_1 -fixed false -x 348 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0_CC_0 -fixed false -x 357 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0_CC_1 -fixed false -x 360 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNIDL29J_CC_0 -fixed false -x 348 -y 221
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNIDL29J_CC_1 -fixed false -x 360 -y 221
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_0_I_1_CC_0 -fixed false -x 384 -y 221
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_CC_0 -fixed false -x 366 -y 221
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_CC_1 -fixed false -x 372 -y 221
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0_CC_0 -fixed false -x 358 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0_CC_1 -fixed false -x 360 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0_CC_0 -fixed false -x 504 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0_CC_1 -fixed false -x 516 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0_CC_0 -fixed false -x 504 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0_CC_1 -fixed false -x 516 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL_CC_0 -fixed false -x 423 -y 209
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL_CC_1 -fixed false -x 432 -y 209
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_4_cry_0_CC_0 -fixed false -x 492 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_cry_0_CC_0 -fixed false -x 540 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0_CC_0 -fixed false -x 526 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0_CC_1 -fixed false -x 528 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D_CC_0 -fixed false -x 144 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D_CC_1 -fixed false -x 156 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0_CC_0 -fixed false -x 219 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0_CC_1 -fixed false -x 228 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_0_CC_0 -fixed false -x 300 -y 200
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0_CC_0 -fixed false -x 139 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0_CC_1 -fixed false -x 144 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6_CC_0 -fixed false -x 141 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6_CC_1 -fixed false -x 144 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_o1Ii1_cry_0_CC_0 -fixed false -x 300 -y 203
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_I1Ii1_s_1_3841_CC_0 -fixed false -x 288 -y 209
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_3840_CC_0 -fixed false -x 156 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_3840_CC_1 -fixed false -x 168 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0_CC_0 -fixed false -x 195 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0_CC_1 -fixed false -x 204 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0_CC_0 -fixed false -x 144 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0_CC_1 -fixed false -x 156 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0_CC_0 -fixed false -x 204 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0_CC_1 -fixed false -x 216 -y 218
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_i0oi1_1_s_1_3842_CC_0 -fixed false -x 264 -y 212
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6_CC_0 -fixed false -x 165 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6_CC_1 -fixed false -x 168 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un42_i0oi1_cry_0_CC_0 -fixed false -x 249 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un42_i0oi1_cry_0_CC_1 -fixed false -x 252 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_I0iOo_1_s_1_3838_CC_0 -fixed false -x 300 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un60_iloOo_cry_0_CC_0 -fixed false -x 240 -y 155
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_3837_CC_0 -fixed false -x 84 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_3837_CC_1 -fixed false -x 96 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_3839_CC_0 -fixed false -x 108 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_3839_CC_1 -fixed false -x 120 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un7_il0Oo_cry_0_CC_0 -fixed false -x 264 -y 155
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_0 -fixed false -x 432 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_1 -fixed false -x 444 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_2 -fixed false -x 456 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_0 -fixed false -x 420 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_1 -fixed false -x 432 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_2 -fixed false -x 444 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_3834_CC_0 -fixed false -x 296 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_3834_CC_1 -fixed false -x 300 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_3834_CC_2 -fixed false -x 312 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_3833_CC_0 -fixed false -x 391 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_3833_CC_1 -fixed false -x 396 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_3833_CC_2 -fixed false -x 408 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_3832_CC_0 -fixed false -x 300 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_3832_CC_1 -fixed false -x 312 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_3831_CC_0 -fixed false -x 216 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_3831_CC_1 -fixed false -x 228 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_3830_CC_0 -fixed false -x 396 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_3830_CC_1 -fixed false -x 408 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_3829_CC_0 -fixed false -x 335 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_3829_CC_1 -fixed false -x 336 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_3829_CC_2 -fixed false -x 348 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_3828_CC_0 -fixed false -x 322 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_3828_CC_1 -fixed false -x 324 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_3828_CC_2 -fixed false -x 336 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_3827_CC_0 -fixed false -x 240 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_3827_CC_1 -fixed false -x 252 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_3825_CC_0 -fixed false -x 252 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_3825_CC_1 -fixed false -x 264 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_3824_CC_0 -fixed false -x 360 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_3824_CC_1 -fixed false -x 372 -y 185
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_3811_CC_0 -fixed false -x 360 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_3811_CC_1 -fixed false -x 372 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_3810_CC_0 -fixed false -x 288 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_3810_CC_1 -fixed false -x 300 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_3809_CC_0 -fixed false -x 300 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_3809_CC_1 -fixed false -x 312 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0_CC_0 -fixed false -x 318 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0_CC_1 -fixed false -x 324 -y 152
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_3807_CC_0 -fixed false -x 228 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_3807_CC_1 -fixed false -x 240 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_3806_CC_0 -fixed false -x 180 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_3806_CC_1 -fixed false -x 192 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_3805_CC_0 -fixed false -x 258 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_3805_CC_1 -fixed false -x 264 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_3804_CC_0 -fixed false -x 414 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_3804_CC_1 -fixed false -x 420 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_3803_CC_0 -fixed false -x 204 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_3803_CC_1 -fixed false -x 216 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_3802_CC_0 -fixed false -x 300 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_3802_CC_1 -fixed false -x 312 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_3801_CC_0 -fixed false -x 372 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_3801_CC_1 -fixed false -x 384 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_3800_CC_0 -fixed false -x 360 -y 155
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_3800_CC_1 -fixed false -x 372 -y 155
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_3799_CC_0 -fixed false -x 384 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_3799_CC_1 -fixed false -x 396 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_3798_CC_0 -fixed false -x 341 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_3798_CC_1 -fixed false -x 348 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_3797_CC_0 -fixed false -x 324 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_3797_CC_1 -fixed false -x 336 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_3796_CC_0 -fixed false -x 325 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_3796_CC_1 -fixed false -x 336 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_3826_CC_0 -fixed false -x 252 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_3826_CC_1 -fixed false -x 264 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_3823_CC_0 -fixed false -x 242 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_3823_CC_1 -fixed false -x 252 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_3822_CC_0 -fixed false -x 264 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_3822_CC_1 -fixed false -x 276 -y 182
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_3821_CC_0 -fixed false -x 300 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_3821_CC_1 -fixed false -x 312 -y 194
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_3820_CC_0 -fixed false -x 300 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_3820_CC_1 -fixed false -x 312 -y 191
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_3819_CC_0 -fixed false -x 168 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_3819_CC_1 -fixed false -x 180 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_3818_CC_0 -fixed false -x 204 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_3818_CC_1 -fixed false -x 216 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_3817_CC_0 -fixed false -x 228 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_3817_CC_1 -fixed false -x 240 -y 161
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_3816_CC_0 -fixed false -x 240 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_3816_CC_1 -fixed false -x 252 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_3815_CC_0 -fixed false -x 168 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_3815_CC_1 -fixed false -x 180 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_3814_CC_0 -fixed false -x 204 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_3814_CC_1 -fixed false -x 216 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_3813_CC_0 -fixed false -x 168 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_3813_CC_1 -fixed false -x 180 -y 173
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_3812_CC_0 -fixed false -x 228 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_3812_CC_1 -fixed false -x 240 -y 176
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_3808_CC_0 -fixed false -x 276 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_3808_CC_1 -fixed false -x 288 -y 167
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_3835_CC_0 -fixed false -x 36 -y 230
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_3835_CC_1 -fixed false -x 48 -y 230
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_3835_CC_2 -fixed false -x 60 -y 230
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_0 -fixed false -x 39 -y 236
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_1 -fixed false -x 48 -y 236
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_2 -fixed false -x 60 -y 236
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_3836_CC_0 -fixed false -x 24 -y 227
|
|
set_location -inst_name CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_3836_CC_1 -fixed false -x 36 -y 227
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT_CC_0 -fixed false -x 468 -y 155
|
|
set_location -inst_name CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT_CC_1 -fixed false -x 480 -y 155
|
|
set_location -inst_name fifo_to_tpsram_bridge_0/buffer_full6_5_RNI2RB6G_CC_0 -fixed false -x 396 -y 257
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_0 -fixed false -x 516 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_1 -fixed false -x 528 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_2 -fixed false -x 540 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_3 -fixed false -x 552 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_4 -fixed false -x 564 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_3793_CC_5 -fixed false -x 588 -y 176
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy_CC_0 -fixed false -x 567 -y 143
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy_CC_1 -fixed false -x 588 -y 143
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_0 -fixed false -x 519 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_1 -fixed false -x 528 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_2 -fixed false -x 540 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_3 -fixed false -x 552 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_4 -fixed false -x 564 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_5 -fixed false -x 588 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_s_3794_CC_0 -fixed false -x 780 -y 107
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_0 -fixed false -x 695 -y 119
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_1 -fixed false -x 696 -y 119
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_2 -fixed false -x 708 -y 119
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_3 -fixed false -x 720 -y 119
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_0 -fixed false -x 792 -y 161
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_1 -fixed false -x 804 -y 161
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_2 -fixed false -x 816 -y 161
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[0\]_CC_0 -fixed false -x 771 -y 185
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[0\]_CC_1 -fixed false -x 780 -y 185
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[1\]_CC_0 -fixed false -x 795 -y 185
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14\[1\]_CC_1 -fixed false -x 804 -y 185
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_0 -fixed false -x 801 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_1 -fixed false -x 804 -y 173
|
|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_2 -fixed false -x 816 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_3 -fixed false -x 828 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_s_3795_CC_0 -fixed false -x 828 -y 194
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_3789_CC_0 -fixed false -x 842 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_3789_CC_1 -fixed false -x 852 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_3789_CC_2 -fixed false -x 864 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNICBJKF\[1\]_CC_0 -fixed false -x 876 -y 194
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNICBJKF\[1\]_CC_1 -fixed false -x 888 -y 194
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNICBJKF\[1\]_CC_2 -fixed false -x 900 -y 194
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_0 -fixed false -x 853 -y 167
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_1 -fixed false -x 864 -y 167
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_2 -fixed false -x 876 -y 167
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_0 -fixed false -x 862 -y 161
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_1 -fixed false -x 864 -y 161
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_2 -fixed false -x 876 -y 161
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_3 -fixed false -x 888 -y 161
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1_CC_0 -fixed false -x 855 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1_CC_1 -fixed false -x 864 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_0 -fixed false -x 856 -y 182
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_1 -fixed false -x 864 -y 182
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_2 -fixed false -x 876 -y 182
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_0 -fixed false -x 876 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_1 -fixed false -x 888 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_2 -fixed false -x 900 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_3 -fixed false -x 912 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_4 -fixed false -x 924 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_5 -fixed false -x 936 -y 191
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_0 -fixed false -x 876 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_1 -fixed false -x 888 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_2 -fixed false -x 900 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_0 -fixed false -x 915 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_1 -fixed false -x 924 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_2 -fixed false -x 936 -y 173
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_0 -fixed false -x 913 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_1 -fixed false -x 924 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_2 -fixed false -x 936 -y 176
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_0 -fixed false -x 876 -y 155
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set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_1 -fixed false -x 888 -y 155
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|
set_location -inst_name MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_2 -fixed false -x 900 -y 155
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|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_0_CC_0 -fixed false -x 49 -y 221
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_5_cry_0_CC_0 -fixed false -x 84 -y 221
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0_CC_0 -fixed false -x 94 -y 221
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|
set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0_CC_1 -fixed false -x 96 -y 221
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_cry_0_CC_0 -fixed false -x 72 -y 221
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_cry_0_CC_0 -fixed false -x 93 -y 218
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_cry_0_CC_1 -fixed false -x 96 -y 218
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_cry_0_CC_0 -fixed false -x 84 -y 218
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un90_fine_sel_cry_0_CC_0 -fixed false -x 58 -y 221
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set_location -inst_name PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un90_fine_sel_cry_0_CC_1 -fixed false -x 60 -y 221
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set_location -inst_name PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC\[0\]_CC_0 -fixed false -x 12 -y 209
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