47 lines
2.0 KiB
Plaintext
47 lines
2.0 KiB
Plaintext
top.ddc
|
||
2.0
|
||
Wed Apr 15 22:32:15 2026
|
||
false
|
||
false
|
||
false
|
||
DDC_VERSION 12.5
|
||
SOFTWARE_VERSION 2025.1
|
||
|
||
38
|
||
<H<<<<<<<<<<<<<<
|
||
XML|false|false|1838
|
||
<M<<<<<<<<<<<<<<
|
||
|
||
<ddc_export>
|
||
<debugDevice>
|
||
<deviceUserName>MPF300TS</deviceUserName>
|
||
<deviceFamily>PA5M</deviceFamily>
|
||
<deviceDie>PA5M300TS</deviceDie>
|
||
<devicePackage>fcg1152</devicePackage>
|
||
<partNumber>MPF300TS-1FCG1152I</partNumber>
|
||
<deviceChecksum>852D</deviceChecksum>
|
||
</debugDevice>
|
||
<deviceProgFileMap>
|
||
</deviceProgFileMap>
|
||
<probe_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_probe.db</probe_file>
|
||
<inst_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_inst.db</inst_file>
|
||
<live_probe_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_live_probe_status.txt</live_probe_file>
|
||
<fcb_block_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fcb_block.db</fcb_block_file>
|
||
<pkg_pin_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_pkg_pin.db</pkg_pin_file>
|
||
<pro_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.pro</pro_file>
|
||
<spm_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.spm</spm_file>
|
||
<serdes_file></serdes_file>
|
||
<tvs_file></tvs_file>
|
||
<fhb_inst_file></fhb_inst_file>
|
||
<ddr_inst_file></ddr_inst_file>
|
||
<iod_inst_file></iod_inst_file>
|
||
<iod_cdr_inst_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_iod_cdr_inst.txt</iod_cdr_inst_file>
|
||
<init_lock_file></init_lock_file>
|
||
<uprom_file></uprom_file>
|
||
<snvm_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\SNVM.cfg</snvm_file>
|
||
<uic_init_file>E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_SD_DFE.txt</uic_init_file>
|
||
<plot_eye_file>E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer\data\PlotEye.serdes</plot_eye_file>
|
||
<dfe_ss_file>E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer\data\DfeSs.tcl</dfe_ss_file>
|
||
<ddr_training_file>E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer\data\runDdrTraining.tcl</ddr_training_file>
|
||
</ddc_export>
|
||
|