88 lines
9.8 KiB
Tcl
88 lines
9.8 KiB
Tcl
# Microchip Technology Inc.
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# Date: 2026-Apr-15 22:52:43
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# This file was generated based on the following SDC source files:
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# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
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# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc
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#
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create_clock -name {REF_CLK_0} -period 20 [ get_ports { REF_CLK_0 } ]
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create_clock -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} -period 8 -waveform {0 3.2 } [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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create_clock -name {REFCLK_P} -period 8 [ get_ports { REFCLK_P } ]
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create_clock -name {TCK} -period 100 -waveform {0 50 } [ get_ports { TCK } ]
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create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by 8 -divide_by 5 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
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create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
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create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 90 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
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create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 180 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
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create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 270 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
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create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A } ] [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
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create_generated_clock -name {PHY_MDC_CLOCK} -divide_by 28 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -phase 0 [ get_ports { PHY_MDC } ]
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set_input_delay 0 -min -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
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set_input_delay 20 -max -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
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set_input_delay 0 -min -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
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set_input_delay 20 -max -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
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set_output_delay 10 -max -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
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set_output_delay -10 -min -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/RESET } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK_PAUSE } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/SWITCH } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code*[*] } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag*[1] } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag*[1] } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag*[1] } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/ARST_N } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/ARST_N } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/ARST_N } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/RX_SYNC_RST } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/RX_SYNC_RST } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/RX_SYNC_RST } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/TX_SYNC_RST } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/TX_SYNC_RST } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/TX_SYNC_RST } ]
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set_false_path -from [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } ] -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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set_false_path -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CDR_CLK } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync*[1] } ]
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set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync*[1] } ]
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set_false_path -to [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0/CODE_UPDATE } ]
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set_false_path -from [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane* } ]
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set_clock_uncertainty 0.135 [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty 0.000992228 [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -rise_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -fall_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
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set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
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set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { PHY_MDC_CLOCK } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PHY_MDC_CLOCK } ] -rise_to [ get_clocks { PHY_MDC_CLOCK } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PHY_MDC_CLOCK } ] -fall_to [ get_clocks { PHY_MDC_CLOCK } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { REFCLK_P } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REFCLK_P } ] -rise_to [ get_clocks { REFCLK_P } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REFCLK_P } ] -fall_to [ get_clocks { REFCLK_P } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { REF_CLK_0 } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REF_CLK_0 } ] -rise_to [ get_clocks { REF_CLK_0 } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REF_CLK_0 } ] -fall_to [ get_clocks { REF_CLK_0 } ]
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set_clock_uncertainty 0.00483062 [ get_clocks { TCK } ]
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set_clock_uncertainty -hold 0 -rise_from [ get_clocks { TCK } ] -rise_to [ get_clocks { TCK } ]
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set_clock_uncertainty -hold 0 -fall_from [ get_clocks { TCK } ] -fall_to [ get_clocks { TCK } ]
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set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
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set_clock_groups -name {Y_DIV_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
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set_clock_groups -name {NWC_PLL_OUT0_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
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set_clock_groups -name {NWC_PLL_OUT1_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
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set_clock_groups -name {NWC_PLL_OUT2_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
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set_clock_groups -name {NWC_PLL_OUT3_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
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set_clock_groups -name {PF_CCC_0_OUT0_GRP} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
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set_clock_groups -name {JTAG_Async} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -group [ get_clocks { TCK } ]
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