70 lines
11 KiB
Tcl
70 lines
11 KiB
Tcl
set_device -family {PolarFire} -die {MPF300TS} -speed {-1} -range {IND}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CORESPI_0\CORESPI_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CORETSE_0\CORETSE_0.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreAPB3_0\CoreAPB3_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\Core_reset_pf\Core_reset_pf.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\hdl\SSDetect.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\top\top.v}
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set_top_level {top}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.sdc}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.sdc}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.sdc}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.sdc}
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read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.sdc}
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derive_constraints
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write_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.sdc}
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write_ndc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.ndc}
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write_pdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\fp\top_derived_constraints.pdc}
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