# probeTable

name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[6]_inst_19:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIIi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_addr_align_1_[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_addr_align[1][1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[46]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[46]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[7]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I1111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I1111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l11Oo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l11Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oi0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oi0l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_30:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIiO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIiO1_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_39:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[39]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_step:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[37]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_Z_net_5:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_valid:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1ll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[9]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tmsenb_Z:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tmsenb:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oo011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1OOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_reg_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_reg:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_ready_reg:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/I1011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1011:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[30]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_4_inst:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[22]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_8:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[50]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[50]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i1II1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1II1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[7]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[12]_inst_17:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IlO11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IlO11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/o0Io1_net_1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[55]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[55]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iioO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[0]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[10]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0Ii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[4]_inst_21:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lliO1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[62]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[62]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Iiol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Iiol1_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[27]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/ram0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[17]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/EMPTY1:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/o0Io1_net_1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/l0oI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/o0iI1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[26]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs3_rd_valid_ex:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[47]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[47]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sys_reset:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_ndmreset:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OOil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OOil1_inst_3:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01_Z_net_6[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[3]_inst_62:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/lloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.lloIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/toggle_hart_soft_reset_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/toggle_hart_soft_reset:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OOo01[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/liI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liI11_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/II111:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/II111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/ram1_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_sel_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[23]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_sel_retr[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[4]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/NN_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/liIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/liIo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[0]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[9]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I0Io1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_Z_net_7[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[3]_inst_40:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[15]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[7]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/IiI01[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[3]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/PF_COREDELAYCODE_TIP_0_reset_lane:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/reset_lane:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[9]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01_Z_net_6[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[0]_inst_39:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/Ol1Io10_a_4:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[30]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[9]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[63]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[63]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iiol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iiol1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[2]_inst_12:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_35:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[7]_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/CO0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ii0l1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ii0l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_7_inst:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_Z[1]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[3]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ilIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ilIi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[0]_inst_14:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[15]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIl11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[39]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[39]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[1]_inst_3:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/trace_priv_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_mode:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0l11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i0l11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_31:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/i_trx_resp_pkd[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_28:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o0111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o0111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_14:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/iloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[7]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1O11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1O11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iOl11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOl11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1_1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1_i_10:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001_Z_net_4[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiiOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiiOo[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/iloIo_net_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[2]_inst_51:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[48]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[48]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_25:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loli1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loli1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lil11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lil11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO0Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_11_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[12]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_3_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_ex:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[0]_inst_53:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiII1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oiII1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IOoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOoI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ANB2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOo11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOOIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIl11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_1_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/buff_valid[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[1].buff_valid[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[52]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[52]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIoOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIoOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lo0l1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lo0l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[27]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[5]_inst_54:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_10:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[18]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lliO1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIl11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/III11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/III11_inst_5:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[44]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[44]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_19:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlIo1:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_Z[4]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[6]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Iiil1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Iiil1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1_i_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/illi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oO1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1I1_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_cmd_transfer_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_cmd_transfer_ff:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ioi01_Z_net_13:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ioi01_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/resp_count[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[56]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[56]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_32:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[14]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOOIo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOOIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oO001[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt13[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oio01_net_19:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/oio01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/NN_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[4]:Q


name:
CORETSE_0_MRXDAT[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooo01_net_20:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ooo01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ooil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ooil1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oI001[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[48]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[48]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1i01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1i01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOOIo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOOIo[0]_inst_11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[9]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[5]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/NN_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i1_i_12:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1I11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[5]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[1]_inst_6:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo_Z_net_14:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo_inst_3:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Oo1l1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Oo1l1:Q


name:
CORETSE_0_MRXDAT[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_36:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[36]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/dmi_resp_data[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/lloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.lloIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lOiO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lOiO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i0ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i0ll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[7]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IoOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IoOI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_cause_excpt_code[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0io1_Z_net_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0io1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Ii0i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ilIO1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o0Oi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o0Oi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIIi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[22]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/shifter_operand_sel[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Iio01_net_14:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Iio01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioo01_net_16:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioo01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oiOOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oiOOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/R_DATA_7_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pstrb[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OiOi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OiOi1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[8]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[17]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[10]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst_rx_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_rx_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_11_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0Ii1:Q


name:
CORETSE_0_MRXDAT[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[26]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lO011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lO011:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOI11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOI11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOO11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOO11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[41]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[41]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI0l1[0]_inst_12:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[10]_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[9]_inst_5:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[7]:Q


name:
CORETSE_0_MRXDAT[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[18]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_valid_Z:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_valid:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_32:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/o1li1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[22]:Q


name:
CORETSE_0_MRXDAT[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[0]_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_25:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_sel_retr[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[3]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[5]:Q


name:
CORETSE_0_MRXDAT[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/i_trx_resp_pkd[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[3]_inst_11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram3_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram3_[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[5]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[3]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[11]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/CO0:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_23:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_6_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[6]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_os_buff_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_ready_reg:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_24:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_en_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_en_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIOo1_inst_9:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[64]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[64]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[34]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOio1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOio1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[6]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ioO01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ioO01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[35]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiOOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiOOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IIiO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IIiO1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[40]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[40]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/o01I1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[34]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[40]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[40]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[5]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_in[10]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[47]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[47]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state[0]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[2]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1_1[36]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[36]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lloI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lloI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ilo11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ilo11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[1]_inst_23:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_havereset_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_havereset:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[4]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oo0I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[8]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[7]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oOl01[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[33]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_valid_reg_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_valid_reg:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/llio1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/llio1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_resp_ready_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0Ii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_6_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[14]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxs_txready_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxs_txready:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/NN_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Oii11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Oii11_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_15:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_5_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[28]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_Z[3]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1o01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o1o01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[10]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_10_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt13[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[9]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[31]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/IIIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/IIIl1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[12]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[8]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[0]_inst_59:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/OoI11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[4]_inst_11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_2_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CORETSE_0_MRXBYTEVALID[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[48]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[48]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_30:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[15]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[2]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1OIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1OIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[4]_inst_49:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[7]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_10:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/iloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1o01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/i1o01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ooll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ooll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOOo1_inst_4:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/req_buff_resp_fault_1_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_fault[1][2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_13:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[7]_inst_17:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/N_81_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_dmactive:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[53]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[53]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lOoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOoI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iol11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[43]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[43]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1io1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1io1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sticky_reset_reg:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_reset_reg:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oo0i1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oo0i1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_8:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lol11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o1l11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIl11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata1_mcontrol_hit:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oO001[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[49]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[49]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[6]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[20]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_11_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIOI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[15]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[14]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[29]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[19]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/oII11_net_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oII11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/iloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/iO111:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[8]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[8]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[7]_inst_7:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[57]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[57]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_Z[2]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_resumereq_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_resumereq:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/NN_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[48]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[48]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_10_inst:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/CO0:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtmcs_dmireset:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmireset:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i1il1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i1il1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram1_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oi1Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oi1Oo_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[21]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[25]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[9]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1_Z_net_1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[0]_inst_6:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/o1li1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIi11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIi11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[19]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[35]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_state_0_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[3]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/PARITY_ERR:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/parity_err:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_rd_en_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_rd_en:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/i_trx_resp_valid_pkd[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_valid[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[25]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[17]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[7]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/i_trx_resp_pkd[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_sel_retr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_drop[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_drop[0]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[9]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/cnt07[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[26]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[3]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1li1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1li1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[18]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oioO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[36]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_7_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/IIoO1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ioI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioI11_inst_13:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/IloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.IloIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[1]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[46]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[46]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[57]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[57]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[17]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/UTDOInt[0]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[35]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[35]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram0_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/irReg[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ll111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ll111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/resp_count[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/i_trx_resp_valid_pkd[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_valid[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/NN_4:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[6]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_Z[0]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ioo01_net_17:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ioo01_inst_8:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[32]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oIll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oIll1_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[17]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/req_buff_resp_state_valid[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state_valid[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[7]:Q


name:
CORETSE_0_MRXDAT[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oii11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oii11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[8]_inst_16:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/N_1418_i:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l01I1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l01I1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_valid_pkd[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_valid[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[3]_inst_22:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlIo1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[17]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[0]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[8]_inst_7:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_5_inst:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[4]_inst_20:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIIo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIIo[0]_inst_9:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/ram1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/O0I11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0I11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[3]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_pktsel_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_pktsel:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][23]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[26]:Q


name:
CORETSE_0_MRXDAT[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/rd_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loi11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loi11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[2]:Q


name:
CORETSE_0_MRXDAT[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[0]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync_Z[0]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync[0]:Q


name:
COREJTAGDEBUG_C0_0_COREJTAGDEBUG_C0_0_genblk2_genblk2_0__BUFD_TRST_delay_sel[34]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[33].BUFD_BLK/U0:Y


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[15]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[4]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[14]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[3]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[13]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[2]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[12]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[1]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[11]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[0]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[10]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[11]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[9]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[10]


name:
CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[8]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[9]


name:
R_DATA_c[31]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[7]


name:
R_DATA_c[30]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[6]


name:
R_DATA_c[29]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[5]


name:
R_DATA_c[28]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[4]


name:
R_DATA_c[27]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[3]


name:
R_DATA_c[26]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[2]


name:
R_DATA_c[25]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[1]


name:
R_DATA_c[24]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3/INST_RAM1K20_IP:A_DOUT[0]


name:
R_DATA_c[23]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[7]


name:
R_DATA_c[22]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[6]


name:
R_DATA_c[21]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[5]


name:
R_DATA_c[20]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[4]


name:
R_DATA_c[19]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[3]


name:
R_DATA_c[18]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[2]


name:
R_DATA_c[17]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[1]


name:
R_DATA_c[16]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2/INST_RAM1K20_IP:A_DOUT[0]


name:
R_DATA_c[15]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[7]


name:
R_DATA_c[14]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[6]


name:
R_DATA_c[13]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[5]


name:
R_DATA_c[12]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[4]


name:
R_DATA_c[11]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[3]


name:
R_DATA_c[10]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[2]


name:
R_DATA_c[9]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[1]


name:
R_DATA_c[8]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP:A_DOUT[0]


name:
R_DATA_c[7]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[7]


name:
R_DATA_c[6]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[6]


name:
R_DATA_c[5]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[5]


name:
R_DATA_c[4]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[4]


name:
R_DATA_c[3]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[3]


name:
R_DATA_c[2]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[2]


name:
R_DATA_c[1]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[1]


name:
R_DATA_c[0]:PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[0]


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[31]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[30]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[29]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[28]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[27]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[26]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[25]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[24]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[23]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[22]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[21]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[20]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[19]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[18]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[17]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[16]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI1G1DG[15]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIFBI4J[14]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNID9I4J[13]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIB7I4J[12]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNI95I4J[11]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNI73I4J[10]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI78M4E[9]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNILFFGI[8]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIJDFGI[7]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIHBFGI[6]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIF9FGI[5]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNID7FGI[4]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIB5FGI[3]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI93FGI[2]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI71FGI[1]:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_io0O1_m[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI5VEGI[0]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[15]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[14]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[13]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[12]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[11]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[10]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[9]:Y


name:
CoreAPB3_0_0_APBmslave2_PRDATA_m[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[8]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[7]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[7]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[6]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[6]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[5]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[5]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[4]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[4]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[3]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[3]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[2]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[2]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[1]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[1]:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_PRDATA_0_iv_0[0]:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[0]:Y


name:
COREJTAGDEBUG_C0_0_TGT_TDI_0:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[33].BUFD_BLK/U0:Y


name:
COREJTAGDEBUG_C0_0_TGT_TMS_0:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[33].BUFD_BLK/U0:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_apb_pslverr_net:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA_0_sqmuxa_RNI3FK6K:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_subsys_debug_u_subsys_debug_unit_0_MIV_subsys_debug_transport_module_jtag_0_gen_shift_register_active_high_gen_shift_register_active_low_shiftDR21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR21:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_subsys_debug_u_subsys_debug_unit_0_MIV_subsys_debug_transport_module_jtag_0_gen_shift_register_active_high_gen_shift_register_active_low_un1_shiftDR20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.un1_shiftDR20:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_mtime_un3_apb_int_sel:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0:Y


name:
CoreAPB3_0_0_APBmslave0_PWRITE_s0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave0_PWRITE_s0:Y


name:
CORESPI_0_0_CORESPI_0_0_USPI_UCON_tx_fifo_write_sig_0_sqmuxa_i_1:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_0:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_N_1214:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_I1iIo_1:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_iPRDATA28:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA28:Y


name:
CORESPI_0_0_CORESPI_0_0_USPI_UCON_tx_fifo_write_sig14_i_2:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_2:Y


name:
CORESPI_0_0_CORESPI_0_0_USPI_UCON_tx_fifo_write_sig14_i_1:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_1:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_N_1206:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO019_4:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_Oi0O1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Il0O1:Y


name:
MIV_RV32_C0_0_APB_INITIATOR_PSELx:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_psel_0_a2:Y


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_apb_hst_cnv_I01O1_un1_Ii0O1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I01O1.un1_Ii0O1:Y


name:
CoreAPB3_0_0_APBmslave0_PENABLE:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_penable_0_a2:Y


name:
CoreAPB3_0_0_CoreAPB3_0_0_u_mux_p_to_b3_iPRDATA_0_sqmuxa:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA_0_sqmuxa:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_N_974:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/tdo_0:Y


name:
Core_reset_pf_0_Core_reset_pf_0_un1_PLL_POWERDOWN_B_i:Core_reset_pf_0/Core_reset_pf_0/un1_PLL_POWERDOWN_B_i:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_u_hart_0_u_expipe_0_N_8_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_8_i:Y


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_u_hart_0_u_expipe_0_N_10_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_10_i:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[8]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[6]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[7]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[6]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[5]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[4]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[3]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[2]


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_out_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[1]


name:
CORESPI_0_0/CORESPI_0_0/USPI/fifo_mem_q[16]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[0]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[15]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[4]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[14]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[3]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[13]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[2]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[12]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[1]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[11]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[0]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[10]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[11]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[9]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[10]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[8]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[9]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[7]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[8]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[6]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[7]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[5]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[6]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[4]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[5]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[4]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[3]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[2]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[0]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[1]


name:
CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_write_sig14:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[7]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[6]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[5]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[4]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[3]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[2]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[1]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_cry[0]:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0[5]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[15]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[15]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[14]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[14]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[13]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[12]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[12]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[11]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[10]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[10]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[9]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[9]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[8]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[8]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[7]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[6]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[5]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_RNO[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6_f0[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_2_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_2[5]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_1_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_1[5]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_2_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_2[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_0_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_0[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_3_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_3[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[15]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[15]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[14]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[14]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[13]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[12]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[12]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[11]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[10]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[10]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[9]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[9]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[8]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[8]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[7]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[6]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[5]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe_1_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe_1_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_4_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_4:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastbit_3:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_oen_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_oen_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_u:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros_4:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros_4_f0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_5_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_5:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx_5:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx_5_iv:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_7_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_7:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_alldone_2_sqmuxa_1_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first_RNO_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_alldone_2_sqmuxa_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel_RNO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_5_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_5:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_txfifo_read_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_RNO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_3_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_3:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_msrxs_datain_1_sqmuxa_1_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_RNO_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_0_sqmuxa_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_holdsel_RNO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_5:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_5_u:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_1_sqmuxa_i_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_1_sqmuxa_i:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_2_i_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_2_i:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_2_sqmuxa_i_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_2_sqmuxa_i:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_1_sqmuxa_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_RNIS69MA:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_4_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_4:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/N_364:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_9_1_wmux_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_9_1_0_y0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_9_1_0_wmux:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/N_366:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_11_1_wmux_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_11_1_0_y0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_11_1_0_wmux:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/N_368:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_wmux_3:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_y1:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_wmux_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_y3:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_wmux_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_y0_0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_wmux_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_y0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_wmux:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_0_sqmuxa_4_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_0_sqmuxa_4:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_7_0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_1_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_1_sqmuxa_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_1_sqmuxa_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_0_sqmuxa:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/N_205_i_0:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_3_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_3:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg6:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_1[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_sn_N_3:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_2_0_RNO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel_RNIB5HSE_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel_RNIB5HSE:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_slave_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_slave:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_3_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_3:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone_2_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone_2_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_next_1_sqmuxa:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_2_1:CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_1_RNO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitcnt_1_i:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitcnt_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd5:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_2_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_2_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_datareg_3_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_datareg_3_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_3_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_3:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead_2_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead_2_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d[4]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_4_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_3_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_2_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_1_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[16]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[0]


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d[31]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx[31]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_Y_0:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_d_0__0_sqmuxa:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_d[0]_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_d_1_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_d_1_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_d_1_sqmuxa_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_d_1_sqmuxa_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_d_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_d_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_d_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_d_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/m4_e_2:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_RNI1GLK5:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_4_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_3_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d[2]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_2_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_1_0:S


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[4]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[3]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[2]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx[31]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_Y:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_0:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_d_0__0_sqmuxa:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_d[0]_0_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_d_1_sqmuxa_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_d_1_sqmuxa_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/un34_fifo_mem_d_31_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/un34_fifo_mem_d_31_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_d_1_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_d_1_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_d_1_sqmuxa_0:CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_d_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_d_1_sqmuxa_0:CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_d_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/m4_e_2:CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_RNIRNTO:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_13_iv_i_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_13_iv_i[1]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_10_iv_i_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_10_iv_i[0]:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_i:CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_i:CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_i:CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1_RNI6B1NA:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_N_20_mux:CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa_0:CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa_0_0:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_0_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_1:Y


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa:Y


name:
CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA27_Z:CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA27:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_branch_cond_ex[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_branch_cond_ex[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/req_masked[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_cZ[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/req_masked[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNIG3V3L71:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_u[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un19_cpu_d_resp_rd_data_sig[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un19_cpu_d_resp_rd_data_sig[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_resp_rd_data_0[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_expipe_req_op_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_expipe_req_op_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un2_req_resp_str_req_buff_addr_misalign[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un2_req_resp_str_req_buff_addr_misalign[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_emi_req_rd_byte_en_2[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid48_RNI3O089:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_byte_en_net_1[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_emi_req_rd_byte_en_iv_0[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_0[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_emi_req_rd_byte_en_3_m[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3_m[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_rd_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_rd_byte_en_net_1[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_1[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_byte_en_net_2[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_2[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_wr_byte_en_net_2[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_2[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/next_req_fetch_ptr_yy[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/next_req_fetch_ptr_yy[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_rd_data_sel[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_s_31:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_30_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_29_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_28_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_27_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_26_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_25_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_24_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_23_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_22_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_21_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_20_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_19_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_18_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_17_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_16_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_15_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_14_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_13_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_12_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_11_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_10_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_9_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_8_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_7_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_6_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_5_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_4_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_3_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_2_0:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_addr_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_1:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_s_29_RNI7ST9PO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_28_RNIA1R0FO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_27_RNIHG10FO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_26_RNIFE00FO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_25_RNIDCVVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_24_RNIBAUVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_23_RNI98TVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_22_RNI76SVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_21_RNI54RVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNID5KKIO3[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNIB2JKIO3[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_18_RNI8TNVEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_17_RNIQM1QJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_16_RNIDATUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_15_RNIB8SUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_14_RNI96RUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_13_RNI74QUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_12_RNI52PUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_11_RNI30OUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_10_RNI1UMUEO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_9_RNIO9Q5HO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_8_RNIM7P5HO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_7_RNIDPUPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_6_RNIBNTPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_5_RNI9LSPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_4_RNI7JRPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_3_RNI5HQPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_2_RNI3FPPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_RNI1DOPJO3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_addr_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_wr_byte_en_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_wr_byte_en_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_wr_byte_en_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_wr_byte_en_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_rd_byte_en_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_rd_byte_en_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_rd_byte_en_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_rd_byte_en_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_byte_en_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_byte_en_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_byte_en_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_wr_byte_en_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[30]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[29]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[28]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[27]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[26]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[25]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[24]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[23]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[22]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[21]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[20]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[19]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[18]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[17]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[16]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[15]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[14]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[13]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[12]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[11]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[10]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[9]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[8]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[6]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[5]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[4]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[3]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_addr_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[31]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[30]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[29]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[28]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[27]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[26]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[25]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[24]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[23]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[22]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[21]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[20]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[19]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[18]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[17]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[16]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[15]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[14]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[13]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[12]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[11]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[10]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[9]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[8]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[7]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[6]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[5]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[4]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[3]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[2]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[1]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_resp_rd_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[0]/U0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/req_os_d_src[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/req_os_d_src[7]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un2_cpu_i_req_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_i_req_ready:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_req_is_tcm0_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_m1_e_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1_sx_RNI6H24CH3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un8_cpu_i_req_is_tcm0lt19_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_req_is_tcm0_4_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_m3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cmp_cond:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_8[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/exu_result_valid_ex:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_is_apb:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un8_cpu_i_req_is_tcm0lt18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_m1_e:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_exit_retr:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_exit:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_instr_inhibit_ex:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_ready_net_tz:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0_tz[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_i_req_ready_net_tz:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_0_tz[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_i_req_valid_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1_RNIKGARAL1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_lsu_resp_valid_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_valid_d:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_d:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_i_req_ready_x:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_req_ready_x:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_req_is_apb:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_apb:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un2_cpu_i_req_ready_x:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_i_req_ready_x:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_cpu_i_req_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un3_cpu_i_req_ready:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_req_is_dummy_target:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_m8_0_a3_0_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_req_is_tcm0_5_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_m8_0_a3_0_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI75KT83:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un8_cpu_i_req_is_tcm0lto18_12_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_N_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI65U5Q:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gpr_rs2_rd_data_valid_sig:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_halt_ack_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_halt_ack:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_rd_data_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un5_m_timer_irq_cry_63:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_63_FCINST1:CO


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un5_m_timer_irq_cry_63_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_63_RNIH51Q7:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/init_wr_dcsr_step_en:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/bcu_result_cry_0_Y:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_emi_req_valid49:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47_2:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/lsu_emi_req_valid47:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_lsu_emi_req_valid46_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid46_1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_90:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_0_a2[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_lsu_emi_req_valid46:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid46:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_84:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_i[0]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_lsu_expipe_req_op_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_4:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un5_lsu_emi_req_rd_byte_en:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un5_lsu_emi_req_rd_byte_en:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un24_lsu_emi_req_rd_byte_en:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un24_lsu_emi_req_rd_byte_en:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_145:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1[1]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_error_sig:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_sig:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_lsu_resp_valid:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_0_RNI6PJI7:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_ready_sig:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_0_RNIC3CB5C1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_15_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_15:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_16_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_16:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_18_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_18:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_21_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_21:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_22_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_22:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_23_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_23:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_25_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_25:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_26_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_26:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_cry_27_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_27:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un3_next_req_fetch_ptr_s_29_S:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_s_29:S


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un5_N_4_0_i:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/ifu_expipe_req_branch_excpt_req_valid_1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_1_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/ifu_emi_req_valid_i_o2_1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/ifu_N_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0_RNIO1BB7S1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_764:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_2:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/ifu_expipe_req_branch_excpt_req_fenci_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_fenci:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_valid_sel:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/ifu_emi_req_valid_i_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_accepted_0_o2_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_i_resp_error_sel:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_error:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_i_req_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_req_ready:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_d_req_ready_sig_0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c_RNI9BM3B4:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_resp_valid_sig:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_resp_error_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_error:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_807:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_i_o3[31]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_trx_os_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_trx_os:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_1_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_N_14_mux:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_RNI62P334:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_d_req_ready_sig_d_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_d_req_ready_sig_c:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_i_req_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_valid_mux_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_valid_mux_1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_d_req_accepted_1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_TCM_byte_shim.un7_cpu_d_req_wr_byte_en_sel:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un24_cpu_i_req_is_apb_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_12:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_req_valid_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid_2:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_1154:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1]_RNICLNUF[2]:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un24_cpu_i_req_is_apb_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_17:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_1157:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_2_i:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_i_req_valid_net_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_i_req_valid_3:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_req_valid_3_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_3_0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_ready_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_ready_1:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_req_is_tcm0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_d_req_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un4_cpu_i_req_is_apb:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un4_cpu_i_req_is_apb:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un16_cpu_i_req_is_apb:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un24_cpu_i_req_is_apb_19_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_11:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/un1_cpu_d_req_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/un1_cpu_d_req_ready:Y


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/N_88:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0_a3_0:Y


