# probeTable

name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lol11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[2]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[0]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1111:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/exu_result_mux_sel[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iii11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iii11_inst_3:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oo001_net_1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[3]_inst_14:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/o1li1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[36]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[36]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/lI001:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Oio01_net_18:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Oio01_inst_6:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oili1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oili1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[32]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[32]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[8]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_resumeack_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_resumeack:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[17]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[56]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[56]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/ll101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l1oo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/wtrst_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/wtrst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[7]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[2]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[9]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_rd_op_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_rd_op_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OI1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OI1I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/oo011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiO1_inst_6:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg_Z[9]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[9]:Q


name:
CORETSE_0_MRXDAT[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liOOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liOOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iolOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iolOo[0]_inst_8:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/R_DATA_6_inst:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[9]_inst_34:Q


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_subsys_debug_u_subsys_debug_unit_0_MIV_subsys_debug_transport_module_jtag_0_genblk3_shift_active_high_shift_active_low_shiftIR_ne_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftIR_ne_0:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_0_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[45]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[45]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_trigger_ex[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[12]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/IIoO1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Ii011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oliO1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/ie_mextsysie[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[0].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oOl01[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/IloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.IloIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[43]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[43]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[20]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pstrb[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_resume_req_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_resume_req:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I0I01_Z_net_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I0I01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[3]_inst_50:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOo11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOo11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lI1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lI1I1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI1Oo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI1Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I0l11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_19:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[4]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loOOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loOOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/o0oI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O0iI1_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/dtm_resp_ready:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtm_resp_ready:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0IIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0IIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/fifo_reset:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.fifo_reset:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/I01I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_trigger_ex[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_req_rd_ptr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_10_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs2_rd_sel_ex[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0l11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1OOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1OOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_34:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oOl01[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIIo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I11l1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I11l1_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O11l1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O11l1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/ram1_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1io1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1io1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o1l11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/iII01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/iII01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Olio1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Olio1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_stoptime:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/gen_bit_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_33:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[49]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[49]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[33]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1_Z_net_5:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[17]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[15]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rst_synch_reg[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/genblk1.rst_synch_reg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[7]:Q


name:
CoreAPB3_0_0_APBmslave0_PWRITE:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/lloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.lloIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/iloIo_net_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[57]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[57]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txready_at_ssel_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txready_at_ssel:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[23]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIi11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIi11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oiil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oiil1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliO1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliO1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oIol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oIol1_inst_4:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i1iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_sel_ex[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_30:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIo11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[27]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[11]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[5]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/I0lo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/I0lo1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[8]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/wr_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[6]_inst_37:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/o01I1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[29]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_pktsel_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_pktsel:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[4]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_15:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/IIoO1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[3]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_in[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_9:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[40]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[40]:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE[6]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[26]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/SYNC3_stxp_dataerr:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_dataerr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_sel_ex[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[8]_inst_17:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_dbreak_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_dbreak_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Io0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Io0l1[0]_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[42]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[11]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[2]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iOoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOoI1_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_31:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/loI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loI11_Z:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[5]_inst_19:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[11]:Q


name:
CORETSE_0_MRXDAT[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[2]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1_Z_net_12:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0oo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0oo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oill1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oill1_inst_6:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs2_rd_sel_ex[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[12]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[8]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_halted_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_halted:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_32:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[6]:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE[4]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01_Z_net_2[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oo0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oo0l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[55]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[55]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[12]_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[47]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[47]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1IIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1IIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_19:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ilo01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/illi0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.illi0:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_misalign_error_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_misalign_error_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/i_trx_resp_pkd[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/NN_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rst_synch_reg[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/genblk1.rst_synch_reg[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[12]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[22]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[6]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrx_async_reset_ok_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrx_async_reset_ok:Q


name:
PHY_MDC_c:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/mdc_Z:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[45]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[45]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/i_trx_resp_pkd[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[1]_inst_52:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[53]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[53]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IIl11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0l11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[1]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[31]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/llol1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.llol1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o0ii1_Z_net_6:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o0ii1_inst_3:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[13]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[17]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/xmit_clock:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_clock:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[33]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_34:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[2]_inst_57:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[51]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[51]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[0]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol1Oo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol1Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01_Z_net_1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01[0]_inst_22:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[18]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt13[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/lo011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIiO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[16]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/cnt07[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_strobe_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_strobe:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iOil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iOil1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_23:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Ilii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Ilii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oIIOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oIIOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_stopcount:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[4]:Q


name:
CORETSE_0_MDO:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OiIO1_Z:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[21]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[2]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[2]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/stop_strobe:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/stop_strobe:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[5]_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1_Z_net_8:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[16]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/req_buff_resp_state_1_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OioI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_d_wr_rd_state[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_wr_rd_state_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[37]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOo11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOo11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[20]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/io0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/io0l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[4]_inst_55:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[26]:Q


name:
CORETSE_0_MRXDAT[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/liOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/liOo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_addr_align_0_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_addr_align[0][0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol0l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_31:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO1Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO1Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OI0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OI0Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I0o01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IiIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IiIo1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/buff_rd_ptr_1[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_error_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pslverr_reg:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I0Io1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/I0Il1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/I0Il1:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/data_out[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oioi1_Z_net_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oioi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_8:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oIoI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IlOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IlOo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lOll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lOll1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[9]_inst_44:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[4]_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_resp_rd_ptr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[7]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[12]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IoIO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IoIO1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_1_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[44]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[44]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_14:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[19]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_23:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[4]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMRADDR[0]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[8]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[27]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[1]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_9_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_mux_sel_retr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_5_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/i0iI1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/i0iI1_inst_2:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_30:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[29]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[16]:Q


name:
CORETSE_0_MRXDAT[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un7_iab_readylt1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[35]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_28:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[53]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[53]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_Z[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iOi11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOi11_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i1Oi1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[50]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[50]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[44]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[44]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ilio1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ilio1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/N_1_i:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIO11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[16]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[6]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Ilol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Ilol1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OO1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO1I1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/III11_net_9:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/III11_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[56]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[56]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0il1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Il0l1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Il0l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOIo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIII1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[60]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[60]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1I11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1I11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/irReg[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Il1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Il1I1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[1]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1o01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/ie_mtie:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_mtie/gen_bit_no_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mcause_interrupt:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_27:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[61]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[61]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_35:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001_Z_net_4[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[0]_inst_22:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[43]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[43]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[7]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_in[12]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1l11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1l11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iooo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iooo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[52]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[52]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ioll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ioll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/loil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/loil1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lOlo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lOlo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[44]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[44]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/OlI01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/OlI01_inst_2:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oll11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_sel_ex[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOiI1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[36]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[36]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[5]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOIOo_Z_net_6:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOIOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO0Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loIOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loIOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[11]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iiOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iiOI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[47]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[47]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_13:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/o01I1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[32]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/buff_rd_ptr_2[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_rd_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_valid_ex:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1_Z_net_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[14]_inst_3:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1_Z_net_1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_rd_en_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_rd_en:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[53]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[53]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[2]_inst_13:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iIIl1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iIIl1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/ii011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0iO1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/li1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOiI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O0111_Z_net_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O0111_inst_3:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/io001_net_6:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/io001:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[0]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[3]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0il1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[15]_inst_2:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo_inst_14:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/iOI11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIl11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/IloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.IloIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oO0o1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oO0o1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/is_locked:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[58]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[58]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[3]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[8]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[39]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[39]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/ram0_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_sel_retr[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111_Z_net_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[9]_inst_19:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[22]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/middle_valid:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_valid:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/req_buff_resp_state_1_[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_25:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOo11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOo11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_8:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[20]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0Ii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/stage_state_ex:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_ex:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_7_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOIi1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt13[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_Z_net_7[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[2]_inst_41:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_8_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_valid_retr:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/o01I1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lioO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[35]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIll1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst_ft_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_ft_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[17]:Q


name:
CORETSE_0_inst_0_CORETSE_0_0_CoreTSE_TOP_INST_tsmac_top_U0_amcxfif_U0_CTSE_AMCXRFIF_FAB_1_genblk1_O0Il1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iloi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iloi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_27:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/IloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.IloIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[2]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[24]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[5]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[0]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[29]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/ram0_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_31:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CO0_2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IIl11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[4]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_parity_Z:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_parity:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/oO0i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/oIli0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.l0li0:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[22]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOii1_Z_net_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/lOo01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOo01_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs2_rd_sel_ex[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lOl11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOl11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_m_env_call_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_m_env_call_retr:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/OoI11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand0_mux_sel_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand0_mux_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[38]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[1]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[27]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i11l1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i11l1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0iOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0iOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIlIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIlIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_cause[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[46]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[46]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOIi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIl11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioi11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioi11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O0oIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[3]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[0]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_ebreakm:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OO1i1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OO1i1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_trigger_retr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_ex_retr.ex_retr_pipe_trigger_retr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_Z[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[34]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[40]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[40]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_sel_ex[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[2]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_19:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/req_buff_resp_state_1_[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/hart_soft_reset_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_9:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1oo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1oo1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_inst_3:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iO0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iO0l1[0]_inst_9:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[36]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[36]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iol11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[54]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[54]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/buff_rd_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_rd_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oo001_net_1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIl11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIl11:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[9]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[10]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[10]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[9]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[4]_inst_13:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[9]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0_dll_code_upd:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_code_upd:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_24:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIl11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i10l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i10l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i1l11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1l11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_27:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[4]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/ram0_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o11I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o11I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[60]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[60]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftIR[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_7_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[44]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[44]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[41]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[41]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[0]:Q


name:
CORETSE_0_MRXDAT[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/OI011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/i1111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[0]_inst_14:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_28:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIl11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_state_0_[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oOl01[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ooo01_net_15:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ooo01_inst_9:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/irReg[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01_Z_net_6:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Ol1i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1l11_inst_11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[32]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[38]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Oi011[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oOl11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOl11_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IIl11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOi01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOi01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_33:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_25:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/IilI1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[2]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[3]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un7_iab_readylto1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[5]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[4]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[5]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[0]_inst_28:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[28]:Q


name:
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg_Z[2]:PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[17]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[14]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[51]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[51]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_Z_net_4[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[6]_inst_8:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[11]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_strobetx_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_strobetx:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[3]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1_Z[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[11]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_in[13]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/oO011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/havereset_skip_pwrup_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/havereset_skip_pwrup:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIol1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/iiO11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iiO11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/OOlo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/OOlo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[9]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/FRAMING_ERR:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_14:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[36]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[36]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOol1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram0_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IiI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IiI11_inst_9:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[6]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pstrb[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_13:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_fault_0_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_fault[0][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/baud_clock:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_clock_int:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_addr_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/lIli0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.I0li0_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[42]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_9:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_cause[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[13]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oll11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[63]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[63]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/i_trx_resp_pkd[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[8]_inst_16:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[32]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[37]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0Ii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001_Z_net_4[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[1]_inst_21:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oo001_net_1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[43]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[43]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[41]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[41]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1_Z_net_1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[7]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/shifter_operand_sel[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01_Z_net_2[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[35]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[2]_inst_15:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oi0i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[5]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lii11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lii11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[9]_inst_15:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_addr_net[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[10]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[3]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[1]_inst_27:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/step_debug_enter_pending:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.step_debug_enter_pending:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[24]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_19:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[55]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[55]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O0oIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1_i_0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/O0lo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/O0lo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_15:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOiO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_Z[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[32]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[1]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[25]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0ll1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[22]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/IiI01[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101[0]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i0ol1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oo001_net_1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoiO1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_39:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[32]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[25]:Q


