# probeTable

name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/llIIo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/llIIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[0]_inst_24:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01_Z_net_6[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[5]_inst_60:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_11_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[21]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[40]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[40]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[2]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IliO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/R_DATA_4_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr[0]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/olOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/olOo1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_strobe_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_strobe:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OO011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OO011:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0Ii1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l1l11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1l11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/O0oI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0oI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_15:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[17]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_Z[0]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lIIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lIIl1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_1_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][0]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[14]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[8]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_10:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1OIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1OIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[4]_inst_3:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_int_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_int[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CORETSE_0_MRXEOF:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/i10I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i10I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oOOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oOOo1_inst_7:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[7]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMRADDR[3]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[42]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[31]:Q


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_apb_penable_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.penable:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[13]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_5_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[58]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[58]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Oi0I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Oi0I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1oI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Olol1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oOoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOoI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[32]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[32]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i1Oi1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[13]:Q


name:
CORETSE_0_MRXDAT[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iol11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/ram1_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[8]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0o01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_2_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ii001[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1o01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O0oIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[2]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[4]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIl11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[2]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[0]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_15:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo_Z_net_13:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[5]_inst_2:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[1]:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE[3]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/llOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOil1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOIIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOIIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1_Z_net_1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[45]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[45]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[19]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[28]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ill11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ill11_inst_8:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[9]:Q


name:
RD_BC_ERROR_c:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oioo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I0Oo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I0Oo1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[10]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs2_rd_sel_ex[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[6]_inst_8:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[4]:Q


name:
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg_Z[3]:PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[7]_inst_8:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_PAUSE:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_13:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/frrst_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/frrst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_cause_excpt_code[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[7]_inst_46:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/NN_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l0iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt28[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iiIi1lt2:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ii1o1_Z_net_8:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ii1o1_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[26]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i1Oi1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[11]_inst_18:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[43]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[43]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[32]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_40:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[40]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/trigger_debug_enter_pending:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.trigger_debug_enter_pending:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_trap_ret_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_trap_ret_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_wfi_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_wfi_ex:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[6]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1OIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1OIo_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[37]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[2]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/TXRDY:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/txrdy_int:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iil01_Z_net_10:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iil01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[41]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[41]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiOIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiOIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/interrupt_captured_timer:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iliO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iliO1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram1_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[19]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o0Il1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o0Il1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/ii1Io[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii1Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii1Oo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_Z_net_8[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[5]_inst_48:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst_tx_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tx_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/debug_reset_pending:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_reset_pending:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01_Z_net_6[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[2]_inst_63:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IoO11_Z_net_12:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IoO11_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0l11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[61]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[61]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_28:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0o01_inst_3:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[12]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/o1101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o1101:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[5]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/rx_fifo_data_in[15]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[23]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/debug_sysbus_req_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OOo01[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[43]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[43]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iol11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[14]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[0]_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/NN_4:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[6]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[16]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[18]:Q


name:
CORETSE_0_MRXDAT[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[14]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_strobetx_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_strobetx:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioOIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioOIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[3]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[54]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[54]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/oo101_net_8:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oo101:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/ll1I1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_Z_net_1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[7]_inst_17:Q


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_subsys_debug_u_subsys_debug_unit_0_MIV_subsys_debug_transport_module_jtag_0_gen_current_state_register_active_high_gen_current_state_register_active_low_currTapState[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Iioi1_Z_net_7:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Iioi1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_addr_net[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1_i_8:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[3]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/SYNC2_stxp_dataerr:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_dataerr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[0]_inst_15:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oIIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oIIl1_inst_1:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_Z[0]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/O0Il1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i1_i_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OI111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram0_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pstrb[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOoOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOoOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt13[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[27]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOl11[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_12:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_3_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_debug_enter_req_retr:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_debug_enter_req_retr:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI0l1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI0l1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Io101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Io101:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram1_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_busy_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_busy:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[39]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoiO1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O0oIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[7]_inst_36:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[9]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O1ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O1ll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/ii101_net_7:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii101:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioO11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioO11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[12]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[60]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[60]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_active_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/clk_en_dm:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_22:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_16:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIl11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_state_0_[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram2_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[55]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[55]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOOo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01_Z[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01[22]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b_Z[0]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[1]_inst_32:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oO001[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram1_25:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/ii0I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ii0I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[39]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iIl11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[45]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[45]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_mem_error_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_mem_error_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftIR[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[32]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[32]:Q


name:
CORETSE_0_MRXDAT[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/shiftDMI[38]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooli1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooli1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/irReg[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[33]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_Z[42]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iil11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iil11_inst_12:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_dbreak_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_dbreak_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OilOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OilOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[0]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync_Z[0]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12lto14:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_net_1[6]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lll11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lll11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[21]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[7]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[12]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ooIO1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lliO1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[35]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[6]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_40:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[40]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/R_DATA_5_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[31]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_9_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/iO0i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_pkd[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_0_inst:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/OVERFLOW:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[31]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[46]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[46]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[13]_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_st[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[3]_inst_25:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_wr_en_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_wr_en:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/o1li1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[2]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[5]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[38]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l0I01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l0I01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_resp_rd_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OII11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_0_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[9]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow_Z:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[6]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMRADDR[5]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/ie_mextsysie[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[1].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_1_inst:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/IilI1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[2]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[4]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[4]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte_Z[6]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oo001_net_1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[3]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[28]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[59]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[59]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[7]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/IiO01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/IiO01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ii0i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_6_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[33]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt17[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_10_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOol1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOol1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[5]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_13:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata1_mcontrol_execute:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/gen_bit_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_14:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[1]_inst_24:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/tcm0_i_resp_valid_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/resp_dest[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_4:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt12[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/buff_valid[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_valid[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[58]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[58]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_rd_op_retr:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_rd_op_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtmcs_dmistat[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOo11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOo11[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_30:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[46]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[46]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lol11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[11]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OlIl1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OlIl1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_gpr_wr_mux_sel_retr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[49]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[49]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iol11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[1]_inst_58:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[40]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[40]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/ram0_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[4]_inst_29:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_0:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[42]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg:Q


name:
CORETSE_0_MRXDAT[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[36]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[36]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[59]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[59]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_17:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i1Oi1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[0]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr_Z[2]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I0l11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ol0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ol0Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[1]_inst_16:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/lOl01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lOl01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/res_pos_neg_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/res_pos_neg:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[34]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOo01[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/status_mie:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOii1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/exu_result_mux_sel[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_mem_error_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_mem_error_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[22]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[61]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[61]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l11I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l11I1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_2_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[3]:Q


name:
CORETSE_0_MRXDAT[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o0ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o0ll1:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01_Z_net_9[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[3]_inst_56:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[24]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI0l1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI0l1[0]_inst_13:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt02[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[29]:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_VALID_CODE:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/ilI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i0Oi1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][23]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[4]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram1_9:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[31]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0Oo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[39]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[1]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1OIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1OIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l1oi1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l1oi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt23[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[6]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lO1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[4]:Q


name:
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_Z[4]:COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_8:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[15]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iO011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/oo111_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_addr_retr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_6:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_3_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O00i0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOII1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Ol1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol1I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[3]_inst_4:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/illo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/illo1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_fence_i_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_fence_i_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1iO1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[23]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/d_trx_resp_valid_pkd[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_valid[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/Olli0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.i0li0:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oll11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram1_7:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ooO01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ooO01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_wr_data_int[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[4]_inst_7:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_29:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoiO1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_Z[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram0_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ioil1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ioil1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[3]_inst_11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Iolo1[18]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram1_3:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[14]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/lI111:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Ii1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OOiI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oi1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oi1I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[13]_inst_16:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/num_emi_req_os[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o00i0[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[39]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/IIoO1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/hipri_req_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_stepie:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[19]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/full_r:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lol11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0ll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0ll1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[15]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[34]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_de_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_de:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[5]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_Z[1]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IIl11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O11I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/sba_req_addr_int[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/liI01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/liI01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[4]:Q


name:
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg_Z[1]:PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/R_DATA_2_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[47]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[47]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/OI1i0[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/req_buff_resp_state_1_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[50]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[50]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[9]_inst_16:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt07_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lo0I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ol111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ol111_inst_5:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/o0Io1_net_1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/IilI1:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[10]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_Z[0]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l0Il1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l0Il1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[6]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt03[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[16]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/data_out[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_hart_gpr_ded_reset_reg:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/gen_bit_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[4]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0_load_lane:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/load_lane:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/olI01_Z_net_4:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/olI01:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt38[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/il101[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OiO11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[17]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[37]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[37]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/buff_rd_ptr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_rd_ptr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[42]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/l1Oi1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/shifter_unit_places_sel[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[4]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/data_out[4]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/dcsr_cause[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO0o1_Z_net_14:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO0o1_inst_4:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[11]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ram0_11:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/o0Io1_net_1[23]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ooIO1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[23]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[37]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[37]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/ilI01_Z_net_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/ilI01_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[52]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[52]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/mscratch_scratch[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01_Z_net_1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01[1]_inst_21:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O0l11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i10Oo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i10Oo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_18:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/o0Io1_net_1[43]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/IilI1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[11]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/l0101[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt01[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[5]_inst_20:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[2]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_retr_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_retr:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[15]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMRADDR[6]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/i0011[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oiI01_net_3[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[17]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_parity_calc_Z:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_parity_calc:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt14[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOo11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOOIo[0]_inst_12:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/R_DATA_1_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IoIl1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_ptr[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_halt_req_net:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_halt_req:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_sw_csr_wr_op_retr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O0oIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iiOl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iiOl1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I1101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1101_inst_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_Z[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[35]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMRADDR[2]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oiIo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oiIo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oiio1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand0_mux_sel_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand0_mux_sel_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IlOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlOI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1_i_11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[7]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[42]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[42]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l1Io1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_26:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[26]:Q


name:
CoreAPB3_0_0_APBmslave0_PADDR[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I0Io1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[16]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt00[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oo1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/Ii0I1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Oo0i0[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/ol1Io_net_2:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.ol1Io:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oolo1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_21:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_pc_retr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/ioI01[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_Z_net_7[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[0]_inst_43:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[38]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[4]_inst_10:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain_5[7]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1[1]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/data_out[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/olOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olOI1:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg_Z[5]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[0]_inst_15:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/IoI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IoI11_Z:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIlOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIlOo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute/gen_bit_reset.state_val[0]:Q


name:
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt_Z[6]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001_Z_net_4[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Oo101_net_4:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oo101:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I11Oo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I11Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/iOI11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_drop[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_drop[1]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[30]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iol11[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o11Oo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o11Oo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoiO1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt20[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[21]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/illOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/illOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oiI11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/OO101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ol101:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_Z[2]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[31]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[38]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[38]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout_Z[23]:COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I0l11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O0Oo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O0Oo1_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[19]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/fifo_MEMWADDR[3]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[5]_inst_12:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt29[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O1Io1_net_2[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[1]:Q


name:
CORETSE_0_MRXDAT[30]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oil11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oil11_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[20]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/R_DATA_4_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lio01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lio01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loo01_net_21:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/loo01:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[6]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/currTapState[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_31:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[31]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i1ol1[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/iIli0:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.o0li0:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/o1011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/o1011:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OOIl1[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt31[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_rs1_rd_sel_ex[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[33]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[33]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[30]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/ram0_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iloI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[28]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/i0101[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_20:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[12]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_Z[4]:CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oIoI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[24]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i11I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[16]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[18]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data_1[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[7]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/N_110:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/i0Io1_net_3[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[2]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_strobetx_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_strobetx:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[6]:Q


name:
MIV_RV32_C0_0_MIV_RV32_C0_0_u_ipcore_0_gen_subsys_debug_u_subsys_debug_unit_0_MIV_subsys_debug_transport_module_jtag_0_gen_current_state_register_active_high_gen_current_state_register_active_low_currTapState[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0Ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0Ii1_inst_2:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lliO1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001_Z_net_2[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[5]_inst_9:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_Z[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i01I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/ftrst_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/ftrst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[1]_inst_14:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt18[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_cause_excpt_code[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/llIl1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1_Z[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[62]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[62]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1lOo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1lOo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1OI1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I1i11_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I1i11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I01I1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[25]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_2_[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoo1_Z_net_10:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoo1_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/NN_5:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OI1O1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_int[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[0]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][11]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_9_inst:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_1:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/li101[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0Io1[41]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/IilI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt16[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[13]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gpr_rs1_rd_data_sig[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/R_DATA_0_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[20]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/oi0I1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0l11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o0l11:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o1iO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_Z_net_7[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[1]_inst_42:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/l00i0[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_Z_net_5[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[0]_inst_33:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01_Z_net_1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[15]_inst_4:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtmcs_dmihardreset:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex_Z[31]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[31]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[22]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIoI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0OI1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Io0i0[32]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[32]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii001[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0o01_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lo1I1[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I11I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[22]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[22]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/Ii101[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/lloIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.lloIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Ool11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ool11:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift_Z[8]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[13]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_epc_retr[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[5]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[3]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr[0]:Q


name:
CoreAPB3_0_0_APBmslave0_PWDATA[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iol11[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/o0Oo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/o0Oo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0_Z[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt26[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_23:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[23]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/NN_1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_Z_net_3[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt09[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iIll1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iIll1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0ii1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0ii1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_mtvec_excpt_vec_retr[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_Z[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[27]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iI0o1_Z_net_4:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iI0o1:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[10]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/liII1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liII1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/ram2_24:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[24]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_resp_state_0_[2]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[12]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_i_ex_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_i_ex:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OiIl1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OiIl1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IiO11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1_Z[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/i.OI/il1Io_1[18]:CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[18]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I00i1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I00i1:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[1]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_Z[8]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt05[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_0_[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][15]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_Z[3]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt15[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[2]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_Z[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIoI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lIoI1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo_Z[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/ll1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIl11[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIoI1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oo1I1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/ram1_2:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[19]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_op_wr_data_net[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/I1Io1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[21]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_paddr[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/i0OI1[29]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[29]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt04[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoI11[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[9]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_Z[29]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[29]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt10[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt24[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[11]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[11]:Q


name:
PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE[1]:PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/csr_priv_dpc_retr[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[39]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[39]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt22[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/O10i0[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[25]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[25]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OoiO1[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[17]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Oll11[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[16]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIIo:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIIo[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0OI1[28]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_Z_net_3[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[2]_inst_2:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/O0Io1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OiI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OiI11_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/iO1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iO1I1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/csr_priv_mtval[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/oIoO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIoO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IloI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/IOOi1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oliO1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oliO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1_Z[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[45]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[45]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIOo1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIOo1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oool1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oool1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt34[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[15]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[15]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt35[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oI1I1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI1I1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt33[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_38:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[25]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[25]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iO1O1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_Z[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[4]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_davailable_Z:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_davailable:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_Z[27]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[27]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[10]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_Z[1]:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/soft_reset_pending_Z:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/soft_reset_pending:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/oi101:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oi101:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/l0l11[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1_Z[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[7]_inst_10:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0Io1[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOlI1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[6]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend_Z[12]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/NN_3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[18]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_csr_op_addr_net[6]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oIOI1[24]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[24]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OIo11[26]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[26]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex_Z[9]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[9]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/baud_cntr[7]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/il111_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/il111:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/olIl1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/mtime_count_out[15]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[15]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_27:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[27]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/tdata2_match_data[26]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[26]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/iIl11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_exu_result_retr[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[10]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex_Z[4]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[4]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI[34]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[34]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/IOI11:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOI11:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/oi011:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0iO1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt32[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oI001[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001[2]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft_Z[8]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[8]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01_Z_net_6[1]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[1]_inst_64:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rrex_1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rrex_1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/status_mpie:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/gen_bit_no_reset.state_val[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex_Z[3]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[3]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_Z[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iO1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iO1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_entry_addr_req_1_[30]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][30]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[13]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[13]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt21[2]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[2]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1_Z[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[0]_inst_1:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IOoIo[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt06[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/il1I1[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[16]:Q


name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_Z[5]:COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1_Z[21]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[21]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt08[16]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[16]:Q


name:
CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay_Z[14]:CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt19[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Io1I1[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0io1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0io1:Q


name:
CORETSE_0_MRXDAT[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_d_resp_rd_data_net[19]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt27[17]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[17]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1_Z_net_1[19]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[19]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i1Oi1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg_Z[28]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[28]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lIl11[3]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[3]:Q


name:
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit_Z[0]:CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[7]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_7_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt25[4]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[4]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/O1iO1[35]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[35]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o0iO1[12]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[12]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt30[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IO1I1[6]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[6]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_Z:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr_Z[5]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/cpu_debug_gpr_op_rd_data_net[8]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/R_DATA_8_inst:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OlOI1:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OlOI1_inst_3:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_Z[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ANB3:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[3]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/buff_entry_addr_req_0_[0]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][0]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1o01:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1o01:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp_Z[38]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[38]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt11[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[7]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/I1OI1[14]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[14]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[1]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg_Z[10]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/oiI01_net_3[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[0]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/OO111[9]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[9]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/cnt39[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_rs1_rd_hzd_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram1_37:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[37]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[11]:Q


name:
CORETSE_0_MRXDAT[10]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[10]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/o01I1[7]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[7]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/ram0_5:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[5]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_Z[5]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[5]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_pc_ex[11]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[11]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/oloI1[20]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[20]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write_Z[1]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write[1]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo_Z[8]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[8]:Q


name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_Z[14]:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[14]:Q


name:
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/IIoI1[0]:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[0]:Q


