# fcbBlockTable

PortAPins: [11]:[10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP

LogicalBlockName:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0_R_DATA0to0[0:11]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0]%32%32%SPEED%0%0%MICRO_RAM


LogicalBlockName: COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe
PortA: COREFIFO_C0_0/COREFIFO_C0_0/RDATA_int[16:31]
PortAPins: nc:nc:[31]:[30]:[29]:[28]:[27]:[26]:[25]:[24]:nc:nc:[23]:[22]:[21]:[20]:[19]:[18]:[17]:[16]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
Name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1/INST_RAM1K20_IP

RAMINDEX:
PF__COMPILE__GEN__:COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_6/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[30:34]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[34]:[33]:[32]:[31]:[30]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%6%DUAL-PORT%ECC_EN-0


PortAPins: [11]:[10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP

LogicalBlockName:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0_R_DATA0to0[0:11]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0]%32%32%SPEED%0%1%MICRO_RAM


Name: CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP
LogicalBlockName: CORESPI_0_0/CORESPI_0_0/USPI/UTXF
PortA: CORESPI_0_0/CORESPI_0_0/USPI/tx_fifo_data_out[11:15]
PortAPins: nc:nc:nc:nc:nc:nc:nc:[15]:[14]:[13]:[12]:[11]
RAMINDEX:
PF__COMPILE__GEN__:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0],fifo_mem_q[16]%32%17%SPEED%0%1%MICRO_RAM


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%10%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%13%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%8%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/I10i0[10:19]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[19]:[18]:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]%2048-2048%40-40%SPEED%0%1%DUAL-PORT%ECC_EN-0


PortAPins: nc:nc:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP

LogicalBlockName:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0_R_DATA0to0[0:7]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0]%32%32%SPEED%0%2%MICRO_RAM


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%1%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_5/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[25:29]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[29]:[28]:[27]:[26]:[25]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%5%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%14%0%TWO-PORT%ECC_EN-0


Name: CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP
LogicalBlockName: CORESPI_0_0/CORESPI_0_0/USPI/UTXF
PortA: CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[0:10,16]
PortAPins: [10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]:[16]
RAMINDEX:
PF__COMPILE__GEN__:CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0],fifo_mem_q[16]%32%17%SPEED%0%0%MICRO_RAM


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_7/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/o01I1[35]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[35]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%7%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%0%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/I10i0[30:39]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[39]:[38]:[37]:[36]:[35]:[34]:[33]:[32]:[31]:[30]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]%2048-2048%40-40%SPEED%0%3%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%6%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%15%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%12%0%TWO-PORT%ECC_EN-0


Name: CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP
LogicalBlockName: CORESPI_0_0/CORESPI_0_0/USPI/URXF
PortA: CORESPI_0_0/CORESPI_0_0/USPI/fifo_mem_q[0:10,16]
PortAPins: [10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]:[16]
RAMINDEX:
PF__COMPILE__GEN__:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0],fifo_mem_q[16]%32%17%SPEED%0%0%MICRO_RAM


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%3%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%4%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[5:9]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[9]:[8]:[7]:[6]:[5]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%1%DUAL-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/I10i0[0:9]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]%2048-2048%40-40%SPEED%0%0%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%11%0%TWO-PORT%ECC_EN-0


PortAPins: [11]:[10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0_R_DATA0to0[0:11]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0]%32%32%SPEED%0%1%MICRO_RAM


Name: CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP
LogicalBlockName: CORESPI_0_0/CORESPI_0_0/USPI/URXF
PortA: CORESPI_0_0_CORESPI_0_0_USPI_rx_fifo_data_out[11:15]
PortAPins: nc:nc:nc:nc:nc:nc:nc:[15]:[14]:[13]:[12]:[11]
RAMINDEX:
PF__COMPILE__GEN__:CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0],fifo_mem_q[16]%32%17%SPEED%0%1%MICRO_RAM


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[15:19]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[19]:[18]:[17]:[16]:[15]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%3%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%5%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%7%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[10:14]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[14]:[13]:[12]:[11]:[10]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%2%DUAL-PORT%ECC_EN-0


PortAPins: [11]:[10]:[9]:[8]:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0_R_DATA0to0[0:11]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0]%32%32%SPEED%0%0%MICRO_RAM


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/I10i0[20:29]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[29]:[28]:[27]:[26]:[25]:[24]:[23]:[22]:[21]:[20]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]%2048-2048%40-40%SPEED%0%2%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%16%0%TWO-PORT%ECC_EN-0


PortAPins: nc:nc:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0_R_DATA0to0[0:7]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0]%32%32%SPEED%0%2%MICRO_RAM


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%9%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_4/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[20:24]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[24]:[23]:[22]:[21]:[20]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%4%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%2%0%TWO-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer
PortA: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/req_buffer_resp_sel[0:5]
PortAPins: nc:nc:nc:nc:nc:nc:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0]%2%6%SPEED%0%0%MICRO_RAM


LogicalBlockName: COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe
PortA: COREFIFO_C0_0/COREFIFO_C0_0/RDATA_int[0:15]
PortAPins: nc:nc:[15]:[14]:[13]:[12]:[11]:[10]:[9]:[8]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
Name:
COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0/INST_RAM1K20_IP

RAMINDEX:
PF__COMPILE__GEN__:COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0


Name: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP
LogicalBlockName: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1
PortA: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/io0i0[0:4]
PortAPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc:nc
RAMINDEX:
PF__COMPILE__GEN__:CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]%4096-4096%36-36%SPEED%0%0%DUAL-PORT%ECC_EN-0


LogicalBlockName: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0
PortAPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
PortBPins: nc:nc:[17]:[16]:[15]:[14]:[13]:[12]:[11]:[10]:nc:nc:[7]:[6]:[5]:[4]:[3]:[2]:[1]:[0]
Name:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0/INST_RAM1K20_IP

PortA:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0_A_DOUT[0:7,10:17]

PortB:
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0_B_DOUT[0:7,10:17]

RAMINDEX:
PF__COMPILE__GEN__:MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0%9216-9216%32-32%POWER%17%0%TWO-PORT%ECC_EN-0


