<?xml version="1.0" encoding="UTF-8" standalone="no" ?><SdModel xmlns="http://actel.com/sweng/afi" name="top" xmlns:actel-cc="http://www.actel.com/XMLSchema/CoreConsole" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.1"><module_list><topmodule class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="top::work" reset_layout="false" type="6"><configuration/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADN" attribute="0" constant="" direction="IN" export="true" exposed="false" inverted="false" isUserNamed="false" name="REFCLK_N" open="false" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADP" attribute="0" constant="" direction="IN" export="true" exposed="false" inverted="false" isUserNamed="false" name="REFCLK_P" open="false" pad="true" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="REF_CLK_0" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="RESET_N" open="false" pad="false" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADN" attribute="0" constant="" direction="IN" export="true" exposed="false" inverted="false" isUserNamed="false" name="RX_N" open="false" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADP" attribute="0" constant="" direction="IN" export="true" exposed="false" inverted="false" isUserNamed="false" name="RX_P" open="false" pad="true" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="RX" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="SPISDI" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="TCK" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="TDI" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="TMS" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="IN" export="false" exposed="false" inverted="false" isUserNamed="false" name="TRSTB" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="LINK_OK" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="PHY_MDC" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="PHY_RST" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="RD_BC_ERROR" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="REF_CLK_SEL" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="SPISCLKO" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="SPISDO" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="SPISS" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="TDO" open="false" pad="false" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="OUTBUF_DIFF" PROPERTY_PADMACROPIN="PADN" attribute="0" constant="" direction="OUT" export="true" exposed="false" inverted="false" isUserNamed="false" name="TX_N" open="false" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="OUTBUF_DIFF" PROPERTY_PADMACROPIN="PADP" attribute="0" constant="" direction="OUT" export="true" exposed="false" inverted="false" isUserNamed="false" name="TX_P" open="false" pad="true" type="std_logic" used="true"/><scalar_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" name="TX" open="false" pad="false" type="std_logic" used="true"/><scalar_port attribute="4" constant="" direction="OUT" export="false" exposed="false" inverted="true" isUserNamed="false" name="coma_mode" open="false" pad="false" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="BIBUF" PROPERTY_PADMACROPIN="PAD" attribute="0" constant="" direction="INOUT" export="true" exposed="false" inverted="false" isUserNamed="false" name="PHY_MDIO" open="false" pad="true" type="std_logic" used="true"/><bus_port attribute="0" constant="" direction="OUT" export="false" exposed="false" inverted="false" isUserNamed="false" left="31" name="R_DATA" open="false" pad="false" right="0" type="std_logic" used="true"/></topmodule><module class_type="Regular" module_class="AdlibModule" name="AND2" type="9"><scalar_port direction="IN" export="false" isUserNamed="false" name="A" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="B" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="Y" pad="false" type="std_logic" used="true"/></module><module class_type="Regular" module_class="AdlibModule" name="BIBUF" type="9"><scalar_port direction="IN" export="false" isUserNamed="false" name="D" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="E" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="Y" pad="false" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="BIBUF" PROPERTY_PADMACROPIN="PAD" direction="INOUT" export="true" isUserNamed="false" name="PAD" pad="true" type="std_logic" used="true"/></module><module class_type="Bus" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="CoreAPB3_0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="PSEL" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PENABLE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PWRITE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PREADY" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSLVERR" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSELS0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PENABLES" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PWRITES" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="1" direction="IN" export="false" isUserNamed="false" name="PREADYS0" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" direction="IN" export="false" isUserNamed="false" name="PSLVERRS0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSELS1" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="1" direction="IN" export="false" isUserNamed="false" name="PREADYS1" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" direction="IN" export="false" isUserNamed="false" name="PSLVERRS1" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSELS2" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="1" direction="IN" export="false" isUserNamed="false" name="PREADYS2" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" direction="IN" export="false" isUserNamed="false" name="PSLVERRS2" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="PRDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PWDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="PADDRS" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PRDATAS0" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="PWDATAS" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PRDATAS1" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PRDATAS2" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APB3mmaster" role="mirroredMaster" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDR"/><signal definition_name="PSELx" port_name="PSEL"/><signal definition_name="PENABLE" port_name="PENABLE"/><signal definition_name="PWRITE" port_name="PWRITE"/><signal definition_name="PRDATA" port_name="PRDATA"/><signal definition_name="PWDATA" port_name="PWDATA"/><signal definition_name="PREADY" port_name="PREADY"/><signal definition_name="PSLVERR" port_name="PSLVERR"/></signal_map><parameter_list/></bus_ifc_port><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APBmslave0" role="mirroredSlave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDRS"/><signal definition_name="PSELx" port_name="PSELS0"/><signal definition_name="PENABLE" port_name="PENABLES"/><signal definition_name="PWRITE" port_name="PWRITES"/><signal definition_name="PRDATA" port_name="PRDATAS0"/><signal definition_name="PWDATA" port_name="PWDATAS"/><signal definition_name="PREADY" port_name="PREADYS0"/><signal definition_name="PSLVERR" port_name="PSLVERRS0"/></signal_map><parameter_list/></bus_ifc_port><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APBmslave1" role="mirroredSlave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDRS"/><signal definition_name="PSELx" port_name="PSELS1"/><signal definition_name="PENABLE" port_name="PENABLES"/><signal definition_name="PWRITE" port_name="PWRITES"/><signal definition_name="PRDATA" port_name="PRDATAS1"/><signal definition_name="PWDATA" port_name="PWDATAS"/><signal definition_name="PREADY" port_name="PREADYS1"/><signal definition_name="PSLVERR" port_name="PSLVERRS1"/></signal_map><parameter_list/></bus_ifc_port><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APBmslave2" role="mirroredSlave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDRS"/><signal definition_name="PSELx" port_name="PSELS2"/><signal definition_name="PENABLE" port_name="PENABLES"/><signal definition_name="PWRITE" port_name="PWRITES"/><signal definition_name="PRDATA" port_name="PRDATAS2"/><signal definition_name="PWDATA" port_name="PWDATAS"/><signal definition_name="PREADY" port_name="PREADYS2"/><signal definition_name="PSLVERR" port_name="PSLVERRS2"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="COREFIFO_C0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="CLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="RESET_N" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="WE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="RE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="FULL" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="EMPTY" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="DATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="Q" pad="false" right="0" type="std_logic" used="true"/></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="COREJTAGDEBUG_C0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="TRSTB" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TCK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TMS" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TDI" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TDO" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TGT_TCK_0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TGT_TMS_0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TGT_TDI_0" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TGT_TDO_0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TGT_TRSTN_0" pad="false" type="std_logic" used="true"/><group_port direction="IN" isUserNamed="false" name="JTAG_HEADER" used="true"><ports><portRef name="TRSTB"/><portRef name="TCK"/><portRef name="TMS"/><portRef name="TDI"/><portRef name="TDO"/></ports></group_port><group_port direction="OUT" isUserNamed="false" name="DEBUG_TARGET_0" used="true"><ports><portRef name="TGT_TCK_0"/><portRef name="TGT_TMS_0"/><portRef name="TGT_TDI_0"/><portRef name="TGT_TDO_0"/><portRef name="TGT_TRSTN_0"/></ports></group_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="CORESPI_0::work" type="11"><configuration/><scalar_port description="APB System Clock; Reference clock for all internal logic " direction="IN" export="false" isUserNamed="false" name="PCLK" pad="false" type="std_logic" used="true"/><scalar_port description="APB active low asynchronous reset " direction="IN" export="false" isUserNamed="false" name="PRESETN" pad="false" type="std_logic" used="true"/><scalar_port description="Interrupt Pending&#xA;This active high output signal is the interrupt output signal from CoreSPI. It can be programmed to become active on certain events, informing the CPU that such an event has occurred. The CPU can then take appropriate action." direction="OUT" export="false" isUserNamed="false" name="SPIINT" pad="false" type="std_logic" used="true"/><scalar_port description="Indicates receive data available to be read." direction="OUT" export="false" isUserNamed="false" name="SPIRXAVAIL" pad="false" type="std_logic" used="true"/><scalar_port description="Indicates transmit done - ready for more data." direction="OUT" export="false" isUserNamed="false" name="SPITXRFM" pad="false" type="std_logic" used="true"/><scalar_port description="Slave select in: Used to address CoreSPI in slave mode." direction="IN" export="false" isUserNamed="false" name="SPISSI" pad="false" type="std_logic" used="true"/><scalar_port description="Serial data in: Shift data input, master or slave mode." direction="IN" export="false" isUserNamed="false" name="SPISDI" pad="false" type="std_logic" used="true"/><scalar_port description="Serial clock in: Shift clock input, for slave mode operation." direction="IN" export="false" isUserNamed="false" name="SPICLKI" pad="false" type="std_logic" used="true"/><scalar_port description="Serial clock out: Generated by SPI in master mode." direction="OUT" export="false" isUserNamed="false" name="SPISCLKO" pad="false" type="std_logic" used="true"/><scalar_port description="Data output enable: When de-asserted output pad for SPISDO tri-stated). This is active when the SPI is writing output data and deactivated when there is not data to write. This signal is active high." direction="OUT" export="false" isUserNamed="false" name="SPIOEN" pad="false" type="std_logic" used="true"/><scalar_port description="Serial data out: Generated by SPI master." direction="OUT" export="false" isUserNamed="false" name="SPISDO" pad="false" type="std_logic" used="true"/><scalar_port description="CoreSPI mode indicator: When 1- master.  When 0 - slave." direction="OUT" export="false" isUserNamed="false" name="SPIMODE" pad="false" type="std_logic" used="true"/><scalar_port description="APB Slave Select; select signal for register for reads or writes " direction="IN" export="false" isUserNamed="false" name="PSEL" pad="false" type="std_logic" used="true"/><scalar_port description="APB Strobe. This signal indicates the second cycle of an APB transfer. " direction="IN" export="false" isUserNamed="false" name="PENABLE" pad="false" type="std_logic" used="true"/><scalar_port description="APB Write/Read. If high, a write occurs when an APB transfer takes place. If low, a read takes place. " direction="IN" export="false" isUserNamed="false" name="PWRITE" pad="false" type="std_logic" used="true"/><scalar_port description="APB ready&#xA;Used to insert wait states.  Not used in CoreSPI but part of APB3 Interface.  Tied high (always ready)." direction="OUT" export="false" isUserNamed="false" name="PREADY" pad="false" type="std_logic" used="true"/><scalar_port description="APB Error&#xA;Not used in CoreSPI but part of APB3 Interface.  Tied low." direction="OUT" export="false" isUserNamed="false" name="PSLVERR" pad="false" type="std_logic" used="true"/><bus_port description="Slave select: Generated by SPI in master mode." direction="OUT" export="false" isUserNamed="false" left="7" name="SPISS" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB address bus; address internal registers." direction="IN" export="false" isUserNamed="false" left="6" name="PADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB read data " direction="OUT" export="false" isUserNamed="false" left="31" name="PRDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB write data " direction="IN" export="false" isUserNamed="false" left="31" name="PWDATA" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APB_bif" role="slave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDR"/><signal definition_name="PSELx" port_name="PSEL"/><signal definition_name="PENABLE" port_name="PENABLE"/><signal definition_name="PWRITE" port_name="PWRITE"/><signal definition_name="PRDATA" port_name="PRDATA"/><signal definition_name="PWDATA" port_name="PWDATA"/><signal definition_name="PREADY" port_name="PREADY"/><signal definition_name="PSLVERR" port_name="PSLVERR"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="CORETSE_0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="MTXCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MTXRDY" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MTXACPT" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MTXSOF" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MTXEOF" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MTXHWM" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MRXCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MRXRDY" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MRXACPT" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MRXSOF" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MRXEOF" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TXCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="RXCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TBI_TX_CLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TBI_RX_CLK" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TBI_TX_VALID" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="SIGNAL_DETECT" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="SYNC" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="RCG_ERROR" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MDC" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="MDI" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MDO" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="MDOEN" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PRESETN" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PENABLE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PWRITE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSLVERR" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PSEL" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PREADY" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="MTXDAT" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="1" name="MTXBYTEVALID" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="MRXDAT" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="1" name="MRXBYTEVALID" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="9" name="TCG" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="9" name="RCG" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="9" name="ANX_STATE" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="TSM_CONTROL" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="3" name="TSM_TX_INTR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="3" name="TSM_RX_INTR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="PRDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="PWDATA" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APBS" role="slave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDR"/><signal definition_name="PSELx" port_name="PSEL"/><signal definition_name="PENABLE" port_name="PENABLE"/><signal definition_name="PWRITE" port_name="PWRITE"/><signal definition_name="PRDATA" port_name="PRDATA"/><signal definition_name="PWDATA" port_name="PWDATA"/><signal definition_name="PREADY" port_name="PREADY"/><signal definition_name="PSLVERR" port_name="PSLVERR"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="CoreUARTapb_0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="PCLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PRESETN" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TXRDY" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="RXRDY" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PARITY_ERR" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="OVERFLOW" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="RX" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TX" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="FRAMING_ERR" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PSEL" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PENABLE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PWRITE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PREADY" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PSLVERR" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="4" name="PADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="7" name="PRDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="7" name="PWDATA" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="APB" export="false" isUserNamed="false" library="AMBA2" name="APB_bif" role="slave" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="PADDR"/><signal definition_name="PSELx" port_name="PSEL"/><signal definition_name="PENABLE" port_name="PENABLE"/><signal definition_name="PWRITE" port_name="PWRITE"/><signal definition_name="PRDATA" port_name="PRDATA"/><signal definition_name="PWDATA" port_name="PWDATA"/><signal definition_name="PREADY" port_name="PREADY"/><signal definition_name="PSLVERR" port_name="PSLVERR"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="Core_reset_pf::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="CLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="EXT_RST_N" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="BANK_x_VDDI_STATUS" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="BANK_y_VDDI_STATUS" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PLL_LOCK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="SS_BUSY" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="FF_US_RESTORE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="FPGA_POR_N" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PLL_POWERDOWN_B" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="FABRIC_RESET_N" pad="false" type="std_logic" used="true"/></module><module class_type="Regular" file="hdl\fifo_to_tpsram_bridge.v" module_class="HdlModule" name="fifo_to_tpsram_bridge::work" type="3"><scalar_port direction="IN" export="false" isUserNamed="false" name="clk" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="reset_n" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="fifo_empty" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="fifo_rd_en" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="ram_w_en" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="transfer_enable" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="buffer_full" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="fifo_data_out" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="10" name="ram_w_addr" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="ram_w_data" pad="false" right="0" type="std_logic" used="true"/></module><module class_type="Regular" module_class="AdlibModule" name="INBUF_DIFF" type="9"><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADP" direction="IN" export="true" isUserNamed="false" name="PADP" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADN" direction="IN" export="true" isUserNamed="false" name="PADN" pad="true" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="Y" pad="false" type="std_logic" used="true"/></module><module class_type="CPU" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="MIV_RV32_C0::work" type="11"><configuration/><scalar_port description="System clock. All other I/Os are synchronous to this clock." direction="IN" export="false" isUserNamed="false" name="CLK" pad="false" type="std_logic" used="true"/><scalar_port description="Asynchronous reset signal. Active low." direction="IN" export="false" isUserNamed="false" name="RESETN" pad="false" type="std_logic" used="true"/><scalar_port description="External system reset, active low. Driven by RESETN and&#xA;Debugger system reset (debug mode)." direction="OUT" export="false" isUserNamed="false" name="EXT_RESETN" pad="false" type="std_logic" used="true"/><scalar_port description="APB Initiator Interface PENABLE output." direction="OUT" export="false" isUserNamed="false" name="APB_PENABLE" pad="false" type="std_logic" used="true"/><scalar_port description="APB Initiator Interface PWRITE output." direction="OUT" export="false" isUserNamed="false" name="APB_PWRITE" pad="false" type="std_logic" used="true"/><scalar_port description="APB Initiator Interface PREADY input." direction="IN" export="false" isUserNamed="false" name="APB_PREADY" pad="false" type="std_logic" used="true"/><scalar_port description="APB Initiator Interface PSLVERR input." direction="IN" export="false" isUserNamed="false" name="APB_PSLVERR" pad="false" type="std_logic" used="true"/><scalar_port description="APB Initiator Interface PSEL output." direction="OUT" export="false" isUserNamed="false" name="APB_PSEL" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="1" description="Test Reset (TRSTN Active low). This is an optional signal used to&#xA;reset the TAP controllers state machine." direction="IN" export="false" isUserNamed="false" name="JTAG_TRSTN" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="1" description="Test Clock (TCK). This signal is used by the JTAG device for&#xA;downloading and debugging programs." direction="IN" export="false" isUserNamed="false" name="JTAG_TCK" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" description="Test Data In (TDI). This signal is used by the JTAG device for&#xA;downloading and debugging programs. Sampled on the rising&#xA;edge of TCK." direction="IN" export="false" isUserNamed="false" name="JTAG_TDI" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" description="Test Mode Select (TMS). This signal is used by the JTAG device&#xA;when downloading and debugging programs. It is sampled on the&#xA;rising edge of TCK to determine the next state." direction="IN" export="false" isUserNamed="false" name="JTAG_TMS" pad="false" type="std_logic" used="true"/><scalar_port description="Test Data Out (TDO). This signal is the data which is shifted out of&#xA;the device during debugging. It is valid on FALLING/RISING edge&#xA;of TCK." direction="OUT" export="false" isUserNamed="false" name="JTAG_TDO" pad="false" type="std_logic" used="true"/><scalar_port description="Drive Test Data Out (DRV_TDO). This signal is used to drive a&#xA;tristate buffer." direction="OUT" export="false" isUserNamed="false" name="JTAG_TDO_DR" pad="false" type="std_logic" used="true"/><scalar_port defaultValue="0" description="External interrupt from peripheral source. An active high levelbased&#xA;interrupt signal. Tie this input low if unused." direction="IN" export="false" isUserNamed="false" name="EXT_IRQ" pad="false" type="std_logic" used="true"/><bus_port description="Internal system timer count." direction="OUT" export="false" isUserNamed="false" left="63" name="TIME_COUNT_OUT" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB Initiator Interface PADDR output." direction="OUT" export="false" isUserNamed="false" left="31" name="APB_PADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB Initiator Interface PRDATA input." direction="IN" export="false" isUserNamed="false" left="31" name="APB_PRDATA" pad="false" right="0" type="std_logic" used="true"/><bus_port description="APB Initiator Interface PWDATA output." direction="OUT" export="false" isUserNamed="false" left="31" name="APB_PWDATA" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="APB" description="APB Initiator." export="false" isUserNamed="false" library="AMBA2" name="APB_INITIATOR" role="master" used="true" vendor="AMBA" version="r0p0"><signal_map><signal definition_name="PADDR" port_name="APB_PADDR"/><signal definition_name="PSELx" port_name="APB_PSEL"/><signal definition_name="PENABLE" port_name="APB_PENABLE"/><signal definition_name="PWRITE" port_name="APB_PWRITE"/><signal definition_name="PRDATA" port_name="APB_PRDATA"/><signal definition_name="PWDATA" port_name="APB_PWDATA"/><signal definition_name="PREADY" port_name="APB_PREADY"/><signal definition_name="PSLVERR" port_name="APB_PSLVERR"/></signal_map><parameter_list/></bus_ifc_port><group_port direction="IN" isUserNamed="false" name="DEBUG" used="true"><ports><portRef name="JTAG_TRSTN"/><portRef name="JTAG_TCK"/><portRef name="JTAG_TDI"/><portRef name="JTAG_TMS"/><portRef name="JTAG_TDO"/><portRef name="JTAG_TDO_DR"/></ports></group_port><group_port direction="IN" isUserNamed="false" name="IRQ" used="true"><ports><portRef name="EXT_IRQ"/></ports></group_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="PF_CCC_0::work" type="11"><configuration/><scalar_port description="REF_CLK_0" direction="IN" export="false" isUserNamed="false" name="REF_CLK_0" pad="false" type="std_logic" used="true"/><scalar_port description="OUT0_FABCLK_0" direction="OUT" export="false" isUserNamed="false" name="OUT0_FABCLK_0" pad="false" type="std_logic" used="true"/><scalar_port description="PLL_LOCK_0" direction="OUT" export="false" isUserNamed="false" name="PLL_LOCK_0" pad="false" type="std_logic" used="true"/><scalar_port description="PLL_POWERDOWN_N_0" direction="IN" export="false" isUserNamed="false" name="PLL_POWERDOWN_N_0" pad="false" type="std_logic" used="true"/></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="pf_init_monitor_0::work" type="11"><configuration/><scalar_port description="FABRIC_POR_N" direction="OUT" export="false" isUserNamed="false" name="FABRIC_POR_N" pad="false" type="std_logic" used="true"/><scalar_port description="PCIE_INIT_DONE" direction="OUT" export="false" isUserNamed="false" name="PCIE_INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="USRAM_INIT_DONE" direction="OUT" export="false" isUserNamed="false" name="USRAM_INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="SRAM_INIT_DONE" direction="OUT" export="false" isUserNamed="false" name="SRAM_INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="DEVICE_INIT_DONE" direction="OUT" export="false" isUserNamed="false" name="DEVICE_INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="BANK_6_VDDI_STATUS" direction="OUT" export="false" isUserNamed="false" name="BANK_6_VDDI_STATUS" pad="false" type="std_logic" used="true"/><scalar_port description="XCVR_INIT_DONE" direction="OUT" export="false" isUserNamed="false" name="XCVR_INIT_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="USRAM_INIT_FROM_SNVM_DONE" direction="OUT" export="false" isUserNamed="false" name="USRAM_INIT_FROM_SNVM_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="USRAM_INIT_FROM_UPROM_DONE" direction="OUT" export="false" isUserNamed="false" name="USRAM_INIT_FROM_UPROM_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="USRAM_INIT_FROM_SPI_DONE" direction="OUT" export="false" isUserNamed="false" name="USRAM_INIT_FROM_SPI_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="SRAM_INIT_FROM_SNVM_DONE" direction="OUT" export="false" isUserNamed="false" name="SRAM_INIT_FROM_SNVM_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="SRAM_INIT_FROM_UPROM_DONE" direction="OUT" export="false" isUserNamed="false" name="SRAM_INIT_FROM_UPROM_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="SRAM_INIT_FROM_SPI_DONE" direction="OUT" export="false" isUserNamed="false" name="SRAM_INIT_FROM_SPI_DONE" pad="false" type="std_logic" used="true"/><scalar_port description="AUTOCALIB_DONE" direction="OUT" export="false" isUserNamed="false" name="AUTOCALIB_DONE" pad="false" type="std_logic" used="true"/></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="PF_IOD_CDR_C0::work" type="17"><configuration/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADP" direction="IN" export="true" isUserNamed="false" name="RX_P" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="INBUF_DIFF" PROPERTY_PADMACROPIN="PADN" direction="IN" export="true" isUserNamed="false" name="RX_N" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="OUTBUF_DIFF" PROPERTY_PADMACROPIN="PADP" direction="OUT" export="true" isUserNamed="false" name="TX_P" pad="true" type="std_logic" used="true"/><scalar_port PROPERTY_PADMACRO="OUTBUF_DIFF" PROPERTY_PADMACROPIN="PADN" direction="OUT" export="true" isUserNamed="false" name="TX_N" pad="true" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="TX_CLK_G" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="HS_IO_CLK_0" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="HS_IO_CLK_90" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="HS_IO_CLK_180" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="HS_IO_CLK_270" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="HS_IO_CLK_PAUSE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="PLL_LOCK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="DLL_LOCK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="DLL_VALID_CODE" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="CDR_START" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="STREAM_START" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="RX_CLK_R" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="RX_VAL" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="RST_N" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="6" name="DLL_DELAY_CODE" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="9" name="TX_DATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="9" name="RX_DATA" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="PF_CDR_CLK" export="false" isUserNamed="false" library="busdef.clock" name="CDR_CLOCKS" role="slave" used="true" vendor="Actel" version="1.0"><signal_map><signal definition_name="HS_IO_CLK_0" port_name="HS_IO_CLK_0"/><signal definition_name="HS_IO_CLK_90" port_name="HS_IO_CLK_90"/><signal definition_name="HS_IO_CLK_180" port_name="HS_IO_CLK_180"/><signal definition_name="HS_IO_CLK_270" port_name="HS_IO_CLK_270"/><signal definition_name="HS_IO_CLK_PAUSE" port_name="HS_IO_CLK_PAUSE"/><signal definition_name="DLL_LOCK" port_name="DLL_LOCK"/><signal definition_name="PLL_LOCK" port_name="PLL_LOCK"/><signal definition_name="TX_CLK_G" port_name="TX_CLK_G"/><signal definition_name="CDR_START" port_name="CDR_START"/><signal definition_name="DLL_DELAY_CODE" port_name="DLL_DELAY_CODE"/><signal definition_name="DLL_VALID_CODE" port_name="DLL_VALID_CODE"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="PF_IOD_CDR_CCC_C0::work" type="17"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="REF_CLK" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="ARST_N" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TX_CLK_G_TO_CDR" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="HS_IO_CLK_270" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="HS_IO_CLK_0" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="HS_IO_CLK_90" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="HS_IO_CLK_180" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="HS_IO_CLK_PAUSE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="PLL_LOCK" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="DLL_LOCK" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="DLL_VALID_CODE" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="CDR_START" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="TX_CLK_G" pad="false" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="6" name="DLL_DELAY_CODE" pad="false" right="0" type="std_logic" used="true"/><bus_ifc_port definition="PF_CDR_CLK" export="false" isUserNamed="false" library="busdef.clock" name="CDR_CLOCKS" role="master" used="true" vendor="Actel" version="1.0"><signal_map><signal definition_name="HS_IO_CLK_0" port_name="HS_IO_CLK_0"/><signal definition_name="HS_IO_CLK_90" port_name="HS_IO_CLK_90"/><signal definition_name="HS_IO_CLK_180" port_name="HS_IO_CLK_180"/><signal definition_name="HS_IO_CLK_270" port_name="HS_IO_CLK_270"/><signal definition_name="HS_IO_CLK_PAUSE" port_name="HS_IO_CLK_PAUSE"/><signal definition_name="DLL_LOCK" port_name="DLL_LOCK"/><signal definition_name="PLL_LOCK" port_name="PLL_LOCK"/><signal definition_name="TX_CLK_G" port_name="TX_CLK_G_TO_CDR"/><signal definition_name="CDR_START" port_name="CDR_START"/><signal definition_name="DLL_DELAY_CODE" port_name="DLL_DELAY_CODE"/><signal definition_name="DLL_VALID_CODE" port_name="DLL_VALID_CODE"/></signal_map><parameter_list/></bus_ifc_port></module><module class_type="Regular" id_library="" id_name="" id_vendor="" id_version="" module_class="ComponentModule" name="PF_TPSRAM_C0::work" type="11"><configuration/><scalar_port direction="IN" export="false" isUserNamed="false" name="W_EN" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="CLK" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="31" name="W_DATA" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="10" name="W_ADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="10" name="R_ADDR" pad="false" right="0" type="std_logic" used="true"/><bus_port direction="OUT" export="false" isUserNamed="false" left="31" name="R_DATA" pad="false" right="0" type="std_logic" used="true"/></module><module class_type="Regular" file="hdl\SSDetect.v" module_class="HdlModule" name="SSDetect::work" type="3"><scalar_port direction="IN" export="false" isUserNamed="false" name="rst_b" pad="false" type="std_logic" used="true"/><scalar_port direction="IN" export="false" isUserNamed="false" name="rck" pad="false" type="std_logic" used="true"/><scalar_port direction="OUT" export="false" isUserNamed="false" name="stream_start" pad="false" type="std_logic" used="true"/><bus_port direction="IN" export="false" isUserNamed="false" left="9" name="rx_data" pad="false" right="0" type="std_logic" used="true"/></module></module_list><instance_list><topinstance/><instance module="AND2::ADLIB" name="AND2_2"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="A" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="B" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Y" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="BIBUF::ADLIB" name="BIBUF_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="D" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="E" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Y" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PAD" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="Core_reset_pf::work" name="Core_reset_pf_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="EXT_RST_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="BANK_x_VDDI_STATUS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="BANK_y_VDDI_STATUS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PLL_LOCK" open="false"/><pin attribute="2" conduit="false" constant="0" exposed="false" inverted="false" name="SS_BUSY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="INIT_DONE" open="false"/><pin attribute="2" conduit="false" constant="0" exposed="false" inverted="false" name="FF_US_RESTORE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="FPGA_POR_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PLL_POWERDOWN_B" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="FABRIC_RESET_N" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="CoreAPB3_0::work" name="CoreAPB3_0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSEL" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PENABLE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWRITE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSELS0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PENABLES" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWRITES" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADYS0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERRS0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSELS1" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADYS1" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERRS1" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSELS2" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADYS2" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERRS2" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADDRS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATAS0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWDATAS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATAS1" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATAS2" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB3mmaster" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APBmslave0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APBmslave1" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APBmslave2" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="COREFIFO_C0::work" name="COREFIFO_C0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RESET_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="WE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RE" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="FULL" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="EMPTY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Q" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="COREJTAGDEBUG_C0::work" name="COREJTAGDEBUG_C0_0"><group_pin direction="IN" name="JTAG_HEADER" user_created="false"><pins><pinRef name="TRSTB"/><pinRef name="TCK"/><pinRef name="TMS"/><pinRef name="TDI"/><pinRef name="TDO"/></pins></group_pin><group_pin direction="OUT" name="DEBUG_TARGET_0" user_created="false"><pins><pinRef name="TGT_TCK_0"/><pinRef name="TGT_TMS_0"/><pinRef name="TGT_TDI_0"/><pinRef name="TGT_TDO_0"/><pinRef name="TGT_TRSTN_0"/></pins></group_pin><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TRSTB" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TMS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TDI" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TDO" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TGT_TCK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TGT_TMS_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TGT_TDI_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TGT_TDO_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TGT_TRSTN_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_HEADER" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DEBUG_TARGET_0" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="CORESPI_0::work" name="CORESPI_0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRESETN" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SPIINT" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SPIRXAVAIL" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SPITXRFM" open="true"/><pin attribute="1" conduit="false" constant="1" exposed="false" inverted="false" name="SPISSI" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="SPISDI" open="false"/><pin attribute="2" conduit="false" constant="0" exposed="false" inverted="false" name="SPICLKI" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="SPISCLKO" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SPIOEN" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="SPISDO" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SPIMODE" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSEL" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PENABLE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWRITE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="SPISS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_bif" open="false"/><slice_pin attribute="0" constant="" inverted="false" left="0" name="SPISS" open="false" right="0"/><slice_pin attribute="5" constant="" inverted="false" left="1" name="SPISS" open="true" right="1"/><slice_pin attribute="5" constant="" inverted="false" left="2" name="SPISS" open="true" right="2"/><slice_pin attribute="5" constant="" inverted="false" left="3" name="SPISS" open="true" right="3"/><slice_pin attribute="5" constant="" inverted="false" left="4" name="SPISS" open="true" right="4"/><slice_pin attribute="5" constant="" inverted="false" left="5" name="SPISS" open="true" right="5"/><slice_pin attribute="5" constant="" inverted="false" left="6" name="SPISS" open="true" right="6"/><slice_pin attribute="5" constant="" inverted="false" left="7" name="SPISS" open="true" right="7"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="CORETSE_0::work" name="CORETSE_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MTXCLK" open="false"/><pin attribute="2" conduit="false" constant="0" exposed="false" inverted="false" name="MTXRDY" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="MTXACPT" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MTXSOF" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MTXEOF" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="MTXHWM" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXRDY" open="false"/><pin attribute="1" conduit="false" constant="1" exposed="false" inverted="false" name="MRXACPT" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXSOF" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXEOF" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TXCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RXCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TBI_TX_CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TBI_RX_CLK" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TBI_TX_VALID" open="true"/><pin attribute="1" conduit="false" constant="1" exposed="false" inverted="false" name="SIGNAL_DETECT" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SYNC" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RCG_ERROR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MDC" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MDI" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MDO" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MDOEN" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRESETN" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PENABLE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWRITE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSEL" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADY" open="false"/><pin attribute="2" conduit="false" constant="00000000000000000000000000000000" exposed="false" inverted="false" name="MTXDAT" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MTXBYTEVALID" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXDAT" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="MRXBYTEVALID" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TCG" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RCG" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="ANX_STATE" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TSM_CONTROL" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TSM_TX_INTR" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TSM_RX_INTR" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APBS" open="false"/><slice_pin attribute="5" constant="" inverted="false" left="0" name="ANX_STATE" open="true" right="0"/><slice_pin attribute="5" constant="" inverted="false" left="1" name="ANX_STATE" open="true" right="1"/><slice_pin attribute="5" constant="" inverted="false" left="2" name="ANX_STATE" open="true" right="2"/><slice_pin attribute="5" constant="" inverted="false" left="3" name="ANX_STATE" open="true" right="3"/><slice_pin attribute="5" constant="" inverted="false" left="4" name="ANX_STATE" open="true" right="4"/><slice_pin attribute="5" constant="" inverted="false" left="5" name="ANX_STATE" open="true" right="5"/><slice_pin attribute="5" constant="" inverted="false" left="6" name="ANX_STATE" open="true" right="6"/><slice_pin attribute="5" constant="" inverted="false" left="7" name="ANX_STATE" open="true" right="7"/><slice_pin attribute="0" constant="" inverted="false" left="8" name="ANX_STATE" open="false" right="8"/><slice_pin attribute="5" constant="" inverted="false" left="9" name="ANX_STATE" open="true" right="9"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="CoreUARTapb_0::work" name="CoreUARTapb_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PCLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRESETN" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TXRDY" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="RXRDY" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="PARITY_ERR" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="OVERFLOW" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RX" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="FRAMING_ERR" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSEL" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PENABLE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWRITE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PREADY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PSLVERR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PRDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PWDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_bif" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="fifo_to_tpsram_bridge::work" name="fifo_to_tpsram_bridge_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="clk" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="reset_n" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="fifo_data_out" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="fifo_empty" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="fifo_rd_en" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="ram_w_addr" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="ram_w_data" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="ram_w_en" open="false"/><pin attribute="1" conduit="false" constant="1" exposed="false" inverted="false" name="transfer_enable" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="buffer_full" open="true"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="GND::work" name="GND"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Y" open="false"/></instance><instance module="INBUF_DIFF::ADLIB" name="INBUF_DIFF_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADP" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PADN" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Y" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="MIV_RV32_C0::work" name="MIV_RV32_C0_0"><group_pin direction="IN" name="DEBUG" user_created="false"><pins><pinRef name="JTAG_TRSTN"/><pinRef name="JTAG_TCK"/><pinRef name="JTAG_TDI"/><pinRef name="JTAG_TMS"/><pinRef name="JTAG_TDO"/><pinRef name="JTAG_TDO_DR"/></pins></group_pin><group_pin direction="IN" name="IRQ" user_created="false"><pins><pinRef name="EXT_IRQ"/></pins></group_pin><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RESETN" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="EXT_RESETN" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PENABLE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PWRITE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PREADY" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PSLVERR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PSEL" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TRSTN" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TDI" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TMS" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TDO" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="JTAG_TDO_DR" open="true"/><pin attribute="2" conduit="false" constant="0" exposed="false" inverted="false" name="EXT_IRQ" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="TIME_COUNT_OUT" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PRDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_PWDATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="APB_INITIATOR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DEBUG" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="IRQ" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="PF_CCC_0::work" name="PF_CCC_0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="REF_CLK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="OUT0_FABCLK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PLL_LOCK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PLL_POWERDOWN_N_0" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="pf_init_monitor_0::work" name="pf_init_monitor_0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="FABRIC_POR_N" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="PCIE_INIT_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="USRAM_INIT_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SRAM_INIT_DONE" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DEVICE_INIT_DONE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="BANK_6_VDDI_STATUS" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="XCVR_INIT_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="USRAM_INIT_FROM_SNVM_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="USRAM_INIT_FROM_UPROM_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="USRAM_INIT_FROM_SPI_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SRAM_INIT_FROM_SNVM_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SRAM_INIT_FROM_UPROM_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="SRAM_INIT_FROM_SPI_DONE" open="true"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="AUTOCALIB_DONE" open="true"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="PF_IOD_CDR_C0::work" name="PF_IOD_CDR_C0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RX_P" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RX_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_P" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_CLK_G" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_90" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_180" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_270" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_PAUSE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="PLL_LOCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_LOCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_VALID_CODE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CDR_START" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="STREAM_START" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RX_CLK_R" open="false"/><pin attribute="5" conduit="false" constant="" exposed="false" inverted="false" name="RX_VAL" open="true"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RST_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_DELAY_CODE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_DATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="RX_DATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CDR_CLOCKS" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="PF_IOD_CDR_CCC_C0::work" name="PF_IOD_CDR_CCC_C0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="REF_CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="ARST_N" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_CLK_G_TO_CDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_270" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_0" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_90" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_180" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="HS_IO_CLK_PAUSE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="true" inverted="false" name="PLL_LOCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_LOCK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_VALID_CODE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CDR_START" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="TX_CLK_G" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="DLL_DELAY_CODE" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CDR_CLOCKS" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="PF_TPSRAM_C0::work" name="PF_TPSRAM_C0_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="W_EN" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="CLK" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="W_DATA" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="W_ADDR" open="false"/><pin attribute="2" conduit="false" constant="00000000000" exposed="false" inverted="false" name="R_ADDR" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="R_DATA" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="SSDetect::work" name="SSDetect_0"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="rst_b" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="rck" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="stream_start" open="false"/><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="rx_data" open="false"/><controls><control name="ENABLE">1</control><control name="DELETEABLE">1</control><control name="MOVEABLE">1</control><control name="EDITABLE">1</control><control name="REPLACEABLE">1</control><control name="READONLY">0</control><control name="COPYABLE">1</control><control name="CANDISABLE">0</control><control name="CANREENABLE">1</control><control name="CONFIGURABLE">1</control></controls><configuration/></instance><instance module="VCC::work" name="VCC"><pin attribute="0" conduit="false" constant="" exposed="false" inverted="false" name="Y" open="false"/></instance></instance_list><fw_instance_list/><net_list><scalar_net isUserNamed="false" name="AND2_2_Y"><pin instance="PF_IOD_CDR_C0_0" port="RST_N" position="-1"/><pin instance="SSDetect_0" port="rst_b" position="-1"/><pin instance="COREFIFO_C0_0" port="RESET_N" position="-1"/><pin instance="AND2_2" port="Y" position="-1"/><pin instance="CORETSE_0" port="PRESETN" position="-1"/><pin instance="fifo_to_tpsram_bridge_0" port="reset_n" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="BIBUF_0_Y"><pin instance="BIBUF_0" port="Y" position="-1"/><pin instance="CORETSE_0" port="MDI" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="Core_reset_pf_0_PLL_POWERDOWN_B"><pin instance="PF_CCC_0_0" port="PLL_POWERDOWN_N_0" position="-1"/><pin instance="Core_reset_pf_0" port="PLL_POWERDOWN_B" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="COREFIFO_C0_0_EMPTY"><pin instance="COREFIFO_C0_0" port="EMPTY" position="-1"/><pin instance="fifo_to_tpsram_bridge_0" port="fifo_empty" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="COREJTAGDEBUG_C0_0_TGT_TCK_0"><pin instance="COREJTAGDEBUG_C0_0" port="TGT_TCK_0" position="-1"/><pin instance="MIV_RV32_C0_0" port="JTAG_TCK" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="COREJTAGDEBUG_C0_0_TGT_TDI_0"><pin instance="COREJTAGDEBUG_C0_0" port="TGT_TDI_0" position="-1"/><pin instance="MIV_RV32_C0_0" port="JTAG_TDI" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="COREJTAGDEBUG_C0_0_TGT_TMS_0"><pin instance="COREJTAGDEBUG_C0_0" port="TGT_TMS_0" position="-1"/><pin instance="MIV_RV32_C0_0" port="JTAG_TMS" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="COREJTAGDEBUG_C0_0_TGT_TRSTN_0"><pin instance="COREJTAGDEBUG_C0_0" port="TGT_TRSTN_0" position="-1"/><pin instance="MIV_RV32_C0_0" port="JTAG_TRSTN" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="CORETSE_0_MDO"><pin instance="BIBUF_0" port="D" position="-1"/><pin instance="CORETSE_0" port="MDO" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="CORETSE_0_MDOEN"><pin instance="BIBUF_0" port="E" position="-1"/><pin instance="CORETSE_0" port="MDOEN" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="CORETSE_0_MRXEOF"><pin instance="CORETSE_0" port="MTXEOF" position="-1"/><pin instance="CORETSE_0" port="MRXEOF" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="CORETSE_0_MRXRDY"><pin instance="COREFIFO_C0_0" port="WE" position="-1"/><pin instance="CORETSE_0" port="MRXRDY" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="CORETSE_0_MRXSOF"><pin instance="CORETSE_0" port="MTXSOF" position="-1"/><pin instance="CORETSE_0" port="MRXSOF" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="fifo_to_tpsram_bridge_0_fifo_rd_en"><pin instance="COREFIFO_C0_0" port="RE" position="-1"/><pin instance="fifo_to_tpsram_bridge_0" port="fifo_rd_en" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="fifo_to_tpsram_bridge_0_ram_w_en"><pin instance="PF_TPSRAM_C0_0" port="W_EN" position="-1"/><pin instance="fifo_to_tpsram_bridge_0" port="ram_w_en" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="INBUF_DIFF_0_Y"><pin instance="PF_IOD_CDR_CCC_C0_0" port="REF_CLK" position="-1"/><pin instance="INBUF_DIFF_0" port="Y" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="LINK_OK"><pin instance="top" port="LINK_OK" position="-1"/><slice_pin bus_port="ANX_STATE" instance="CORETSE_0" left="8" right="8"/></scalar_net><scalar_net isUserNamed="false" name="MIV_RV32_C0_0_JTAG_TDO"><pin instance="COREJTAGDEBUG_C0_0" port="TGT_TDO_0" position="-1"/><pin instance="MIV_RV32_C0_0" port="JTAG_TDO" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PF_CCC_0_0_OUT0_FABCLK_0"><pin instance="PF_CCC_0_0" port="OUT0_FABCLK_0" position="-1"/><pin instance="PF_TPSRAM_C0_0" port="CLK" position="-1"/><pin instance="COREFIFO_C0_0" port="CLK" position="-1"/><pin instance="CORESPI_0_0" port="PCLK" position="-1"/><pin instance="Core_reset_pf_0" port="CLK" position="-1"/><pin instance="CORETSE_0" port="MRXCLK" position="-1"/><pin instance="CORETSE_0" port="MTXCLK" position="-1"/><pin instance="CORETSE_0" port="PCLK" position="-1"/><pin instance="CoreUARTapb_0" port="PCLK" position="-1"/><pin instance="MIV_RV32_C0_0" port="CLK" position="-1"/><pin instance="fifo_to_tpsram_bridge_0" port="clk" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PF_CCC_0_0_PLL_LOCK_0"><pin instance="PF_CCC_0_0" port="PLL_LOCK_0" position="-1"/><pin instance="Core_reset_pf_0" port="PLL_LOCK" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="pf_init_monitor_0_0_BANK_6_VDDI_STATUS"><pin instance="pf_init_monitor_0_0" port="BANK_6_VDDI_STATUS" position="-1"/><pin instance="Core_reset_pf_0" port="BANK_y_VDDI_STATUS" position="-1"/><pin instance="Core_reset_pf_0" port="BANK_x_VDDI_STATUS" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="pf_init_monitor_0_0_DEVICE_INIT_DONE"><pin instance="pf_init_monitor_0_0" port="DEVICE_INIT_DONE" position="-1"/><pin instance="Core_reset_pf_0" port="INIT_DONE" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="pf_init_monitor_0_0_FABRIC_POR_N"><pin instance="pf_init_monitor_0_0" port="FABRIC_POR_N" position="-1"/><pin instance="Core_reset_pf_0" port="FPGA_POR_N" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PF_IOD_CDR_C0_0_RX_CLK_R"><pin instance="PF_IOD_CDR_C0_0" port="RX_CLK_R" position="-1"/><pin instance="SSDetect_0" port="rck" position="-1"/><pin instance="CORETSE_0" port="TBI_RX_CLK" position="-1"/><pin instance="CORETSE_0" port="RXCLK" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PF_IOD_CDR_CCC_C0_0_PLL_LOCK"><pin instance="PF_IOD_CDR_CCC_C0_0" port="PLL_LOCK" position="-1"/><pin instance="AND2_2" port="B" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PF_IOD_CDR_CCC_C0_0_TX_CLK_G"><pin instance="PF_IOD_CDR_CCC_C0_0" port="TX_CLK_G" position="-1"/><pin instance="CORETSE_0" port="TXCLK" position="-1"/><pin instance="CORETSE_0" port="TBI_TX_CLK" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PHY_MDC"><pin instance="top" port="PHY_MDC" position="-1"/><pin instance="CORETSE_0" port="MDC" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PHY_MDIO"><pin instance="top" port="PHY_MDIO" position="-1"/><pin instance="BIBUF_0" port="PAD" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="PHY_RST"><pin instance="PF_IOD_CDR_CCC_C0_0" port="ARST_N" position="-1"/><pin instance="CORESPI_0_0" port="PRESETN" position="-1"/><pin instance="top" port="PHY_RST" position="-1"/><pin instance="AND2_2" port="A" position="-1"/><pin instance="Core_reset_pf_0" port="FABRIC_RESET_N" position="-1"/><pin instance="CoreUARTapb_0" port="PRESETN" position="-1"/><pin instance="MIV_RV32_C0_0" port="RESETN" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="RD_BC_ERROR"><pin instance="top" port="RD_BC_ERROR" position="-1"/><pin instance="CORETSE_0" port="RCG_ERROR" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="REF_CLK_0"><pin instance="PF_CCC_0_0" port="REF_CLK_0" position="-1"/><pin instance="top" port="REF_CLK_0" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="REFCLK_N"><pin instance="top" port="REFCLK_N" position="-1"/><pin instance="INBUF_DIFF_0" port="PADN" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="REFCLK_P"><pin instance="top" port="REFCLK_P" position="-1"/><pin instance="INBUF_DIFF_0" port="PADP" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="RESET_N"><pin instance="top" port="RESET_N" position="-1"/><pin instance="top" port="REF_CLK_SEL" position="-1"/><pin instance="top" port="coma_mode" position="-1"/><pin instance="Core_reset_pf_0" port="EXT_RST_N" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="RX"><pin instance="top" port="RX" position="-1"/><pin instance="CoreUARTapb_0" port="RX" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="RX_N"><pin instance="PF_IOD_CDR_C0_0" port="RX_N" position="-1"/><pin instance="top" port="RX_N" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="RX_P"><pin instance="PF_IOD_CDR_C0_0" port="RX_P" position="-1"/><pin instance="top" port="RX_P" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="SPISCLKO"><pin instance="CORESPI_0_0" port="SPISCLKO" position="-1"/><pin instance="top" port="SPISCLKO" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="SPISDI"><pin instance="CORESPI_0_0" port="SPISDI" position="-1"/><pin instance="top" port="SPISDI" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="SPISDO"><pin instance="CORESPI_0_0" port="SPISDO" position="-1"/><pin instance="top" port="SPISDO" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="SPISS"><slice_pin bus_port="SPISS" instance="CORESPI_0_0" left="0" right="0"/><pin instance="top" port="SPISS" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="SSDetect_0_stream_start"><pin instance="PF_IOD_CDR_C0_0" port="STREAM_START" position="-1"/><pin instance="SSDetect_0" port="stream_start" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TCK"><pin instance="COREJTAGDEBUG_C0_0" port="TCK" position="-1"/><pin instance="top" port="TCK" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TDI"><pin instance="COREJTAGDEBUG_C0_0" port="TDI" position="-1"/><pin instance="top" port="TDI" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TDO"><pin instance="COREJTAGDEBUG_C0_0" port="TDO" position="-1"/><pin instance="top" port="TDO" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TMS"><pin instance="COREJTAGDEBUG_C0_0" port="TMS" position="-1"/><pin instance="top" port="TMS" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TRSTB"><pin instance="COREJTAGDEBUG_C0_0" port="TRSTB" position="-1"/><pin instance="top" port="TRSTB" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TX"><pin instance="top" port="TX" position="-1"/><pin instance="CoreUARTapb_0" port="TX" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TX_N"><pin instance="PF_IOD_CDR_C0_0" port="TX_N" position="-1"/><pin instance="top" port="TX_N" position="-1"/></scalar_net><scalar_net isUserNamed="false" name="TX_P"><pin instance="PF_IOD_CDR_C0_0" port="TX_P" position="-1"/><pin instance="top" port="TX_P" position="-1"/></scalar_net><bus_net isUserNamed="false" left="31" name="COREFIFO_C0_0_Q" right="0"><bus_pin bus_port="Q" instance="COREFIFO_C0_0"/><bus_pin bus_port="fifo_data_out" instance="fifo_to_tpsram_bridge_0"/></bus_net><bus_net isUserNamed="false" left="1" name="CORETSE_0_MRXBYTEVALID" right="0"><bus_pin bus_port="MTXBYTEVALID" instance="CORETSE_0"/><bus_pin bus_port="MRXBYTEVALID" instance="CORETSE_0"/></bus_net><bus_net isUserNamed="false" left="31" name="CORETSE_0_MRXDAT" right="0"><bus_pin bus_port="DATA" instance="COREFIFO_C0_0"/><bus_pin bus_port="MRXDAT" instance="CORETSE_0"/></bus_net><bus_net isUserNamed="false" left="9" name="CORETSE_0_TCG" right="0"><bus_pin bus_port="TX_DATA" instance="PF_IOD_CDR_C0_0"/><bus_pin bus_port="TCG" instance="CORETSE_0"/></bus_net><bus_net isUserNamed="false" left="9" name="fifo_to_tpsram_bridge_0_ram_w_addr" right="0"/><bus_net isUserNamed="false" left="15" name="fifo_to_tpsram_bridge_0_ram_w_addr_0" right="0"/><bus_net isUserNamed="false" left="9" name="fifo_to_tpsram_bridge_0_ram_w_addr_1" right="0"/><bus_net isUserNamed="false" left="12" name="fifo_to_tpsram_bridge_0_ram_w_addr_2" right="0"/><bus_net isUserNamed="false" left="9" name="fifo_to_tpsram_bridge_0_ram_w_addr_3" right="0"/><bus_net isUserNamed="false" left="10" name="fifo_to_tpsram_bridge_0_ram_w_addr_4" right="0"><bus_pin bus_port="W_ADDR" instance="PF_TPSRAM_C0_0"/><bus_pin bus_port="ram_w_addr" instance="fifo_to_tpsram_bridge_0"/></bus_net><bus_net isUserNamed="false" left="31" name="fifo_to_tpsram_bridge_0_ram_w_data" right="0"><bus_pin bus_port="W_DATA" instance="PF_TPSRAM_C0_0"/><bus_pin bus_port="ram_w_data" instance="fifo_to_tpsram_bridge_0"/></bus_net><bus_net isUserNamed="false" left="9" name="PF_IOD_CDR_C0_0_RX_DATA" right="0"><bus_pin bus_port="RX_DATA" instance="PF_IOD_CDR_C0_0"/><bus_pin bus_port="rx_data" instance="SSDetect_0"/><bus_pin bus_port="RCG" instance="CORETSE_0"/></bus_net><bus_net isUserNamed="false" left="31" name="R_DATA" right="0"><bus_pin bus_port="R_DATA" instance="PF_TPSRAM_C0_0"/><bus_pin bus_port="R_DATA" instance="top"/></bus_net><busifc_net isUserNamed="false" name="CoreAPB3_0_0_APBmslave0"><busifc_pin instance="CoreAPB3_0_0" name="APBmslave0"/><busifc_pin instance="CORETSE_0" name="APBS"/></busifc_net><busifc_net isUserNamed="false" name="CoreAPB3_0_0_APBmslave1"><busifc_pin instance="CoreAPB3_0_0" name="APBmslave1"/><busifc_pin instance="CoreUARTapb_0" name="APB_bif"/></busifc_net><busifc_net isUserNamed="false" name="CoreAPB3_0_0_APBmslave2"><busifc_pin instance="CORESPI_0_0" name="APB_bif"/><busifc_pin instance="CoreAPB3_0_0" name="APBmslave2"/></busifc_net><busifc_net isUserNamed="false" name="MIV_RV32_C0_0_APB_INITIATOR"><busifc_pin instance="MIV_RV32_C0_0" name="APB_INITIATOR"/><busifc_pin instance="CoreAPB3_0_0" name="APB3mmaster"/></busifc_net><busifc_net isUserNamed="false" name="PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS"><busifc_pin instance="PF_IOD_CDR_C0_0" name="CDR_CLOCKS"/><busifc_pin instance="PF_IOD_CDR_CCC_C0_0" name="CDR_CLOCKS"/></busifc_net></net_list></SdModel>