Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis # Written on Wed Apr 15 22:48:07 2026 ##### DESIGN INFO ####################################################### Top View: "top" Constraint File(s): "E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc" ##### SUMMARY ############################################################ Found 15 issues in 15 out of 47 constraints ##### DETAILS ############################################################ Clock Relationships ******************* Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | No paths | 10.000 | No paths REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 | 8.000 | 3.200 | 4.800 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | No paths | No paths PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | No paths | No paths | No paths PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp | No paths | No paths | No paths PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp | No paths | No paths | No paths PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp | No paths | Diff grp | No paths PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp | No paths | Diff grp | No paths PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | No paths PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 | No paths | No paths | No paths COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 | No paths | No paths | No paths COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp | No paths | No paths | Diff grp COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 | 10.000 | 5.000 | 5.000 ========================================================================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Unconstrained Start/End Points ****************************** p:LINK_OK p:PHY_RST p:RD_BC_ERROR p:REFCLK_N p:REF_CLK_SEL p:RX p:RX_N p:RX_P p:R_DATA[0] p:R_DATA[1] p:R_DATA[2] p:R_DATA[3] p:R_DATA[4] p:R_DATA[5] p:R_DATA[6] p:R_DATA[7] p:R_DATA[8] p:R_DATA[9] p:R_DATA[10] p:R_DATA[11] p:R_DATA[12] p:R_DATA[13] p:R_DATA[14] p:R_DATA[15] p:R_DATA[16] p:R_DATA[17] p:R_DATA[18] p:R_DATA[19] p:R_DATA[20] p:R_DATA[21] p:R_DATA[22] p:R_DATA[23] p:R_DATA[24] p:R_DATA[25] p:R_DATA[26] p:R_DATA[27] p:R_DATA[28] p:R_DATA[29] p:R_DATA[30] p:R_DATA[31] p:SPISCLKO p:SPISDI p:SPISDO p:SPISS p:TDI p:TDO p:TMS p:TRSTB p:TX p:TX_N p:TX_P p:coma_mode Inapplicable constraints ************************ (none) Applicable constraints with issues ********************************** set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design set_false_path -to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }] @W::"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design Constraints with matching wildcard expressions ********************************************** set_false_path -from [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":46:0:46:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* }]" applies to objects: PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane6_0_i4 PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane_4 set_false_path -from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] -through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|expression "[get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }]" applies to objects: PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[0] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[4] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[5] PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":28:0:28:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] }]" applies to objects: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[0] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[1] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[2] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[3] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[4] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[5] PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code[6] set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":30:0:30:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] }]" applies to objects: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1] set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":31:0:31:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] }]" applies to objects: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1] set_false_path -to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":29:0:29:0|expression "[get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] }]" applies to objects: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1] set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":44:0:44:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] }]" applies to objects: PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1] set_false_path -to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }] @N:MF891:"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":43:0:43:0|expression "[get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] }]" applies to objects: PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1] Library Report ************** # End of Constraint Checker Report