#--  Synopsys, Inc.
#--  Version V-2023.09M-5
#--  Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs

#project files
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/syn_comps.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_graytobinconv.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_fwft.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_bufd.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_uj_jtag.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_ujtag_wrapper.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_chanctrl.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_fifo.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_rf.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v"
add_file -verilog -lib CORESPI_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORESPI_0/CORESPI_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CORETSE_0/CORETSE_0.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreAPB3_0/CoreAPB3_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Clock_gen.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Rx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Tx_async.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/fifo_256x8_g5.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUART.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUARTapb.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/CoreUARTapb_0/CoreUARTapb_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf_0/core/corereset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/Core_reset_pf/Core_reset_pf.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_hart_cfg_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/hart_merged/miv_rv32_hart_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_subsys_pkg.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/subsys_merged/miv_rv32_subsys_merged.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp_ecc.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0_0/rtl/miv_rv32.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/MIV_RV32_C0/MIV_RV32_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_CCC_0/PF_CCC_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/rtl/vlog/core/CoreDelayCode_TIP.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CCC_0/PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_CLK_DIV_0/PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_IOD_CDR_CCC_C0/PF_IOD_CDR_CCC_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/PF_TPSRAM_C0/PF_TPSRAM_C0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/SSDetect.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/hdl/fifo_to_tpsram_bridge.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0_0/pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/pf_init_monitor_0/pf_init_monitor_0.v"
add_file -verilog "E:/AbhishekV/rising/ethernet_tpsram_test/component/work/top/top.v"
add_file -fpga_constraint "E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -infer_seqShift 1
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -async_clkint_removal 1

# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -report_preserve_cdc 1
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0
set_option -pack_uram_addr_reg 1
set_option -act_wide_mul_size 35

# NFilter
set_option -no_sequential_opt 0

# common_options
set_option -add_dut_hierarchy 0
set_option -prepare_readback 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis/top.vm"
impl -active "synthesis"