#Build: Synplify Pro (R) V-2023.09M-5, Build 540R, Apr 29 2025 #install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro #OS: Windows 10 or later #Hostname: SOFTWARE-PC # Fri Apr 17 08:27:19 2026 #Implementation: synthesis Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys HDL Compiler, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys Verilog Compiler, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v" (library work) @I::"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" (library work) @W:CG100 : syn_comps.v(21) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(61) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(88) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(118) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(168) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(213) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(232) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(281) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(335) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(657) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(761) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(795) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1059) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1369) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1396) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1441) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1474) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1492) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1518) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1559) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1581) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1599) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1616) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1635) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1652) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1681) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1712) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(1802) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2026) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2187) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2203) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2219) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2235) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2267) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(2648) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3661) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3732) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3861) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3879) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3896) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3911) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3926) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(3953) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4067) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4098) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4144) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4255) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4439) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4480) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4506) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4523) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(4600) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(5364) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(6174) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(6283) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(6321) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(6394) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(7283) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(8340) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(9299) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10035) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10750) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10784) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10820) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10867) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(10901) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(11767) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(12810) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(12822) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(12831) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(12843) | User defined pragma syn_black_box detected @W:CG100 : syn_comps.v(12856) | User defined pragma syn_black_box detected @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" (library work) @N:CG334 : COREFIFO.v(437) | Read directive translate_off. @N:CG333 : COREFIFO.v(449) | Read directive translate_on. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v" (library COREJTAGDEBUG_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v" (library COREJTAGDEBUG_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v" (library COREJTAGDEBUG_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v" (library COREJTAGDEBUG_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" (library CORESPI_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" (library CORESPI_LIB) @W:CG1337 : spi_chanctrl.v(805) | Net resetn_rx_s is not declared. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" (library CORESPI_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" (library CORESPI_LIB) @N:CG347 : spi_rf.v(160) | Read a parallel_case directive. @N:CG347 : spi_rf.v(223) | Read a parallel_case directive. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" (library CORESPI_LIB) @N:CG347 : spi_control.v(69) | Read a parallel_case directive. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" (library CORESPI_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" (library CORESPI_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v" (library work) @I:"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v" (library work) @W:CG1337 : CoreTSE.v(430844) | Net ooOI1 is not declared. @W:CG1337 : CoreTSE.v(430859) | Net ioOI1 is not declared. @W:CG1337 : CoreTSE.v(476678) | Net oI0i0 is not declared. @W:CG1337 : CoreTSE.v(476693) | Net Ol0i0 is not declared. @W:CG1337 : CoreTSE.v(548082) | Net l0iIo is not declared. @W:CG1337 : CoreTSE.v(548102) | Net o0iIo is not declared. @W:CG1337 : CoreTSE.v(548122) | Net i0iIo is not declared. @W:CG1337 : CoreTSE.v(548142) | Net O1iIo is not declared. @W:CG1337 : CoreTSE.v(548162) | Net I1iIo is not declared. @W:CG1337 : CoreTSE.v(548182) | Net l1iIo is not declared. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v" (library work) @N:CG334 : miv_rv32_pkg.v(796) | Read directive translate_off. @N:CG333 : miv_rv32_pkg.v(798) | Read directive translate_on. @N:CG334 : miv_rv32_pkg.v(1536) | Read directive translate_off. @N:CG333 : miv_rv32_pkg.v(1550) | Read directive translate_on. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v" (library work) @N:CG334 : miv_rv32_hart_merged.v(21267) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(21316) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(21861) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(21877) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(22391) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(22459) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(25452) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(25460) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(25769) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(25777) | Read directive translate_on. @W:CS138 : miv_rv32_hart_merged.v(26989) | Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine. @W:CS138 : miv_rv32_hart_merged.v(26990) | Macro definition for RAM_BIST_VIEW not found. Cannot undefine. @N:CG334 : miv_rv32_hart_merged.v(27214) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(27217) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(27227) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(27237) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(27242) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(27300) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(28378) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(28381) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(28391) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(28401) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(28406) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(28464) | Read directive translate_on. @W:CS141 : miv_rv32_hart_merged.v(29121) | Unrecognized synthesis directive dc_script_begin. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(29124) | Unrecognized synthesis directive dc_script_end. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(33910) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(34706) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(35086) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(35316) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(35536) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(35932) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(36264) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(36476) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(36692) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(37011) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(37227) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(37457) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(37837) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(38116) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(38316) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(38581) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CG104 : miv_rv32_hart_merged.v(39241) | Unsized number in concatenation is 32 bits @W:CS141 : miv_rv32_hart_merged.v(39806) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @N:CG334 : miv_rv32_hart_merged.v(40250) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(40254) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(41809) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(41814) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(41866) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(41880) | Read directive translate_on. @N:CG334 : miv_rv32_hart_merged.v(42004) | Read directive translate_off. @N:CG333 : miv_rv32_hart_merged.v(42037) | Read directive translate_on. @W:CS141 : miv_rv32_hart_merged.v(42208) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @W:CS141 : miv_rv32_hart_merged.v(42549) | Unrecognized synthesis directive sync_set_reset. Verify the correct directive name. @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v" (library work) @I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" (library work) Verilog syntax check successful! File E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v changed - recompiling File E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v changed - recompiling File E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v changed - recompiling File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling File miv_rv32_buffer_6s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling File miv_rv32_buffer_6s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling File miv_rv32_buffer_11s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling File miv_rv32_buffer_11s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling File miv_rv32_buffer_7s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling File miv_rv32_buffer_7s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling @N:CG364 : miv_rv32_hart_cfg_pkg.v(70) | Synthesizing module miv_rv32_hart_cfg_pkg in library work. @N:CG364 : miv_rv32_pkg.v(73) | Synthesizing module miv_rv32_pkg in library work. @N:CG364 : miv_rv32_subsys_pkg.v(69) | Synthesizing module miv_rv32_subsys_pkg in library work. @N:CG364 : miv_rv32_hart_merged.v(314) | Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit in library work. @N:CG364 : miv_rv32_subsys_merged.v(77) | Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit in library work. Selecting top level module top @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG775 : corejtagdebug.v(22) | Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB @N:CG775 : corespi.v(27) | Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB @N:CG364 : acg5.v(121) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N:CG364 : acg5.v(333) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N:CG364 : corereset_pf.v(21) | Synthesizing module Core_reset_pf_Core_reset_pf_0_CORERESET_PF in library work. Running optimization stage 1 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... Finished optimization stage 1 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N:CG364 : Core_reset_pf.v(21) | Synthesizing module Core_reset_pf in library work. Running optimization stage 1 on Core_reset_pf ....... Finished optimization stage 1 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 1 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b1 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000010 SL2=16'b0000000000000100 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z1 ....... Finished optimization stage 1 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N:CG364 : CoreAPB3_0.v(57) | Synthesizing module CoreAPB3_0 in library work. Running optimization stage 1 on CoreAPB3_0 ....... Finished optimization stage 1 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N:CG364 : COREFIFO.v(19) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000000100000 WWIDTH=32'b00000000000000000000000000100000 RDEPTH=32'b00000000000000000000010000000000 WDEPTH=32'b00000000000000000000010000000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000010 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000000 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000001111111100 PIPE=32'b00000000000000000000000000000001 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 ECC=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 RAM_OPT=32'b00000000000000000000000000000000 DIE_SIZE=32'b00000000000000000000000000001111 WMSB_DEPTH=32'b00000000000000000000000000001010 RMSB_DEPTH=32'b00000000000000000000000000001010 WDEPTH_CAL=32'b00000000000000000000000000001001 RDEPTH_CAL=32'b00000000000000000000000000001001 RESET_POLARITY=32'b00000000000000000000000000000000 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 Generated name = COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 @N:CG364 : corefifo_sync_scntr.v(20) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000000100000 WRITE_DEPTH=32'b00000000000000000000000000001010 FULL_WRITE_DEPTH=32'b00000000000000000000010000000000 READ_WIDTH=32'b00000000000000000000000000100000 READ_DEPTH=32'b00000000000000000000000000001010 FULL_READ_DEPTH=32'b00000000000000000000010000000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000000 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000001111111100 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000001 REGISTER_RADDR=32'b00000000000000000000000000000001 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 WDEPTH_CAL=32'b00000000000000000000000000001001 RDEPTH_CAL=32'b00000000000000000000000000001001 Generated name = COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 @W:CG360 : corefifo_sync_scntr.v(173) | Removing wire neg_reset, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 ....... @W:CL169 : corefifo_sync_scntr.v(485) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(463) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(463) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(463) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(371) | Pruning unused register sc_w[10:0]. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_sync_scntr.v(331) | Pruning unused register we_f_i. Make sure that there are no unused intermediate registers. @W:CL207 : corefifo_sync_scntr.v(579) | All reachable assignments to genblk8.wack_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(579) | All reachable assignments to genblk8.overflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(485) | All reachable assignments to underflow_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(485) | All reachable assignments to dvld_r assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(275) | All reachable assignments to rdcnt[10:0] assign 0, register removed by optimization. @W:CL207 : corefifo_sync_scntr.v(248) | All reachable assignments to wrcnt[10:0] assign 0, register removed by optimization. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 238MB) @N:CG364 : corefifo_fwft.v(20) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft in library work. RDEPTH=32'b00000000000000000000000000001010 WWIDTH=32'b00000000000000000000000000100000 RWIDTH=32'b00000000000000000000000000100000 WCLK_HIGH=32'b00000000000000000000000000000001 RCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 SYNC=32'b00000000000000000000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 RDEPTH_CAL=32'b00000000000000000000000000001001 Generated name = COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 @N:CG179 : corefifo_fwft.v(254) | Removing redundant assignment. @W:CG133 : corefifo_fwft.v(119) | Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : corefifo_fwft.v(125) | Removing wire aresetn, as there is no assignment to it. @W:CG360 : corefifo_fwft.v(132) | Removing wire empty1, as there is no assignment to it. @W:CG360 : corefifo_fwft.v(140) | Removing wire reset_wclk, as there is no assignment to it. @W:CG360 : corefifo_fwft.v(141) | Removing wire reset_rclk, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 ....... @W:CL169 : corefifo_fwft.v(358) | Pruning unused register we_p_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_fwft.v(244) | Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_fwft.v(233) | Pruning unused register re_p_d. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_fwft.v(214) | Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers. @W:CL169 : corefifo_fwft.v(214) | Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : acg5.v(578) | Synthesizing module RAM1K20 in library work. Running optimization stage 1 on RAM1K20 ....... Finished optimization stage 1 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : acg5.v(500) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : acg5.v(504) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v(5) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top in library work. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top ....... Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(4) | Synthesizing module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000000100000 WWIDTH=32'b00000000000000000000000000100000 RDEPTH=32'b00000000000000000000000000001010 WDEPTH=32'b00000000000000000000000000001010 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000001 CTRL_TYPE=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 RAM_OPT=32'b00000000000000000000000000000000 Generated name = COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s ....... @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(46) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(47) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(48) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v(49) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @W:CG360 : COREFIFO.v(211) | Removing wire pf_MEMRADDR, as there is no assignment to it. @W:CG360 : COREFIFO.v(217) | Removing wire pf_Q, as there is no assignment to it. @W:CG184 : COREFIFO.v(236) | Removing wire DVLD_async, as it has the load but no drivers. @W:CG184 : COREFIFO.v(238) | Removing wire DVLD_sync, as it has the load but no drivers. @W:CG360 : COREFIFO.v(241) | Removing wire pf_dvld, as there is no assignment to it. @W:CG133 : COREFIFO.v(250) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : COREFIFO.v(264) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : COREFIFO.v(283) | Removing wire reset_rclk, as there is no assignment to it. @W:CG360 : COREFIFO.v(284) | Removing wire reset_wclk, as there is no assignment to it. @W:CG360 : COREFIFO.v(285) | Removing wire reset_sync_r, as there is no assignment to it. @W:CG360 : COREFIFO.v(286) | Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 ....... @W:CL169 : COREFIFO.v(1175) | Pruning unused register RDATA_ext_r1[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1165) | Pruning unused register RDATA_ext_r[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register REN_d2. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register RE_d2. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1100) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1088) | Pruning unused register RDATA_r2[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1078) | Pruning unused register RDATA_r1[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1068) | Pruning unused register RDATA_r_pre[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(1058) | Pruning unused register fwft_Q_r[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(503) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(503) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(503) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(490) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W:CL169 : COREFIFO.v(490) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : COREFIFO_C0.v(49) | Synthesizing module COREFIFO_C0 in library work. Running optimization stage 1 on COREFIFO_C0 ....... Finished optimization stage 1 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : corejtagdebug.v(22) | Synthesizing module COREJTAGDEBUG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 NUM_DEBUG_TGTS=32'b00000000000000000000000000000001 TGT_ACTIVE_HIGH_RESET_0=32'b00000000000000000000000000000000 IR_CODE_TGT_0=8'b01010101 TGT_ACTIVE_HIGH_RESET_1=32'b00000000000000000000000000000000 IR_CODE_TGT_1=8'b01010110 TGT_ACTIVE_HIGH_RESET_2=32'b00000000000000000000000000000000 IR_CODE_TGT_2=8'b01010111 TGT_ACTIVE_HIGH_RESET_3=32'b00000000000000000000000000000000 IR_CODE_TGT_3=8'b01011000 TGT_ACTIVE_HIGH_RESET_4=32'b00000000000000000000000000000000 IR_CODE_TGT_4=8'b01011001 TGT_ACTIVE_HIGH_RESET_5=32'b00000000000000000000000000000000 IR_CODE_TGT_5=8'b01011010 TGT_ACTIVE_HIGH_RESET_6=32'b00000000000000000000000000000000 IR_CODE_TGT_6=8'b01011011 TGT_ACTIVE_HIGH_RESET_7=32'b00000000000000000000000000000000 IR_CODE_TGT_7=8'b01011100 TGT_ACTIVE_HIGH_RESET_8=32'b00000000000000000000000000000000 IR_CODE_TGT_8=8'b01011101 TGT_ACTIVE_HIGH_RESET_9=32'b00000000000000000000000000000000 IR_CODE_TGT_9=8'b01011110 TGT_ACTIVE_HIGH_RESET_10=32'b00000000000000000000000000000000 IR_CODE_TGT_10=8'b01011111 TGT_ACTIVE_HIGH_RESET_11=32'b00000000000000000000000000000000 IR_CODE_TGT_11=8'b01100000 TGT_ACTIVE_HIGH_RESET_12=32'b00000000000000000000000000000000 IR_CODE_TGT_12=8'b01100001 TGT_ACTIVE_HIGH_RESET_13=32'b00000000000000000000000000000000 IR_CODE_TGT_13=8'b01100010 TGT_ACTIVE_HIGH_RESET_14=32'b00000000000000000000000000000000 IR_CODE_TGT_14=8'b01100011 TGT_ACTIVE_HIGH_RESET_15=32'b00000000000000000000000000000000 IR_CODE_TGT_15=8'b01100100 UJTAG_BYPASS=32'b00000000000000000000000000000000 UJTAG_SEC_EN=1'b0 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=128'b01100100011000110110001001100001011000000101111101011110010111010101110001011011010110100101100101011000010101110101011001010101 TGT_ACTIVE_HIGH_RESET=16'b0000000000000000 USE_NEW_UJTAG=32'b00000000000000000000000000000001 USE_UJTAG_WRAPPER=32'b00000000000000000000000000000000 USE_UJTAG_SEC=32'b00000000000000000000000000000000 Generated name = COREJTAGDEBUG_Z5 @N:CG364 : acg5.v(1442) | Synthesizing module UJTAG in library work. Running optimization stage 1 on UJTAG ....... Finished optimization stage 1 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : corejtagdebug_bufd.v(20) | Synthesizing module corejtagdebug_bufd in library COREJTAGDEBUG_LIB. DELAY_NUM=32'b00000000000000000000000000100010 Generated name = corejtagdebug_bufd_34s @N:CG364 : acg5.v(229) | Synthesizing module BUFD in library work. Running optimization stage 1 on BUFD ....... Finished optimization stage 1 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) Running optimization stage 1 on corejtagdebug_bufd_34s ....... Finished optimization stage 1 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N:CG364 : corejtagdebug_uj_jtag.v(47) | Synthesizing module COREJTAGDEBUG_UJ_JTAG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 SYNC_RESET=32'b00000000000000000000000000000000 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=8'b01010101 NUM_LEAD_PAD_BITS=8'b00000000 NUM_TRAIL_PAD_BITS=8'b00000000 Generated name = COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 Running optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @W:CG360 : corejtagdebug.v(31) | Removing wire UTRSTB, as there is no assignment to it. @W:CG360 : corejtagdebug.v(32) | Removing wire UTMS, as there is no assignment to it. @W:CG360 : corejtagdebug.v(169) | Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it. @W:CG360 : corejtagdebug.v(176) | Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it. @W:CG360 : corejtagdebug.v(183) | Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it. @W:CG360 : corejtagdebug.v(190) | Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it. @W:CG360 : corejtagdebug.v(241) | Removing wire iURSTB_inv, as there is no assignment to it. Running optimization stage 1 on COREJTAGDEBUG_Z5 ....... @W:CL318 : corejtagdebug.v(31) | *Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : corejtagdebug.v(32) | *Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N:CG364 : COREJTAGDEBUG_C0.v(56) | Synthesizing module COREJTAGDEBUG_C0 in library work. Running optimization stage 1 on COREJTAGDEBUG_C0 ....... Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N:CG364 : spi_rf.v(31) | Synthesizing module spi_rf in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 ZEROS=32'b00000000000000000000000000000000 Generated name = spi_rf_32s_16s_0 Running optimization stage 1 on spi_rf_32s_16s_0 ....... @W:CL208 : spi_rf.v(134) | All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization. Finished optimization stage 1 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N:CG364 : spi_control.v(24) | Synthesizing module spi_control in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 Generated name = spi_control_16s Running optimization stage 1 on spi_control_16s ....... Finished optimization stage 1 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N:CG364 : spi_fifo.v(25) | Synthesizing module spi_fifo in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 PTR_WIDTH=32'b00000000000000000000000000000101 Generated name = spi_fifo_16s_32s_5 Running optimization stage 1 on spi_fifo_16s_32s_5 ....... Finished optimization stage 1 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 240MB peak: 241MB) @N:CG364 : spi_clockmux.v(24) | Synthesizing module spi_clockmux in library CORESPI_LIB. Running optimization stage 1 on spi_clockmux ....... Finished optimization stage 1 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 240MB peak: 241MB) @N:CG364 : spi_chanctrl.v(29) | Synthesizing module spi_chanctrl in library CORESPI_LIB. SPH=1'b0 SPO=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 CFG_CLKRATE=32'b00000000000000000000000000010000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000000100 MTX_IDLE1=4'b0000 MTX_IDLE2=4'b0001 MTX_MOTSTART=4'b0010 MTX_TISTART1=4'b0011 MTX_TISTART2=4'b0100 MTX_NSCSTART1=4'b0101 MTX_NSCSTART2=4'b0110 MTX_SHIFT1=4'b0111 MTX_SHIFT2=4'b1000 MTX_END=4'b1001 STXS_IDLE=1'b0 STXS_SHIFT=1'b1 MOTMODE=1'b1 TIMODE=1'b0 NSCMODE=1'b0 MOTNOSSEL=1'b1 NSCNOSSEL=1'b0 cfg_framesizeM1=32'b00000000000000000000000000001111 Generated name = spi_chanctrl_Z6 @W:CG1340 : spi_chanctrl.v(416) | Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible. @W:CG133 : spi_chanctrl.v(195) | Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : spi_chanctrl.v(196) | Removing wire resetn_rx_p, as there is no assignment to it. @W:CG360 : spi_chanctrl.v(200) | Removing wire resetn_rx_r, as there is no assignment to it. @W:CG133 : spi_chanctrl.v(222) | Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on spi_chanctrl_Z6 ....... @W:CL169 : spi_chanctrl.v(1130) | Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(823) | Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(719) | Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers. @W:CL177 : spi_chanctrl.v(343) | Sharing sequential element cfg_enable_P1 and merging msrx_async_reset_ok. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N:CG364 : spi.v(29) | Synthesizing module spi in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 SPO=1'b0 SPH=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 Generated name = spi_32s_16s_32s_16s_0_0_1_0s Running optimization stage 1 on spi_32s_16s_32s_16s_0_0_1_0s ....... Finished optimization stage 1 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N:CG364 : corespi.v(27) | Synthesizing module CORESPI in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 CFG_MODE=32'b00000000000000000000000000000000 CFG_MOT_MODE=32'b00000000000000000000000000000000 CFG_MOT_SSEL=32'b00000000000000000000000000000001 CFG_TI_NSC_CUSTOM=32'b00000000000000000000000000000000 CFG_TI_NSC_FRC=32'b00000000000000000000000000000000 CFG_TI_JMB_FRAMES=32'b00000000000000000000000000000000 CFG_NSC_OPERATION=32'b00000000000000000000000000000000 SPS=1'b1 SPO=1'b0 SPH=1'b0 Generated name = CORESPI_Z7 Running optimization stage 1 on CORESPI_Z7 ....... Finished optimization stage 1 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N:CG364 : CORESPI_0.v(32) | Synthesizing module CORESPI_0 in library work. Running optimization stage 1 on CORESPI_0 ....... Finished optimization stage 1 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_DECODER ....... Finished optimization stage 1 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s ....... Finished optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s ....... Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 243MB) Running optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 244MB) Running optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB) Running optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... Finished optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB) Running optimization stage 1 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... Finished optimization stage 1 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXFIF_HST_Z8 ....... Finished optimization stage 1 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXFIF_CLKRST_26s_1s ....... Finished optimization stage 1 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_SIB_SYNC_2FLP_1s_26s_1s ....... Finished optimization stage 1 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on OiOI1_26s_11s_12s_32s_2s_0s ....... Finished optimization stage 1 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_PETMC_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB) Running optimization stage 1 on CTSE_PECRC_1s_26s ....... Finished optimization stage 1 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB) Running optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s ....... Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 249MB peak: 256MB) Running optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s ....... Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 262MB) Running optimization stage 1 on CTSE_PERMC_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s ....... Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMGT_1s_26s ....... Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEHST_1s_26s ....... Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PECAR_26s_1s ....... Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s ....... Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s ....... Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_STORE_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s ....... Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_MMCXWOL_1s_26s ....... Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_SI_SAL_26s ....... Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_TSMAC_TOP_Z9 ....... Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_CLKRST_26s_1s ....... Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_ECC_0s_26s_16s ....... Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell. Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s ....... Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB) Running optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s ....... Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB) Running optimization stage 1 on CTSE_MSGMII_CNVTXI_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB) Running optimization stage 1 on CTSE_MSGMII_CNVTXO_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB) Running optimization stage 1 on CTSE_T8B10B ....... Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB) Running optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s ....... Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB) Running optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB) Running optimization stage 1 on CTSE_R10B8B ....... Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB) Running optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s ....... Finished optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_PEANX_SYNC_1s_26s ....... Finished optimization stage 1 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_MSGMII_PEANX_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_PETBM_26s_0s_1s ....... Finished optimization stage 1 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_PETCR_26s_1s ....... Finished optimization stage 1 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s ....... Finished optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_CNVRXI_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) Running optimization stage 1 on CTSE_MSGMII_CNVRXO_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) Running optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s ....... Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) Running optimization stage 1 on CTSE_CORETSE_TOP_Z10 ....... Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) Running optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 ....... Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) Running optimization stage 1 on CORETSE_Z11 ....... Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) @N:CG364 : CORETSE_0.v(31) | Synthesizing module CORETSE_0 in library work. @W:CG781 : CORETSE_0.v(270) | Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on CORETSE_0 ....... Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB) @N:CG364 : Clock_gen.v(38) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) @N:CG364 : Tx_async.v(31) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000000 tx_idle=32'b00000000000000000000000000000000 tx_load=32'b00000000000000000000000000000001 start_bit=32'b00000000000000000000000000000010 tx_data_bits=32'b00000000000000000000000000000011 parity_bit=32'b00000000000000000000000000000100 tx_stop_bit=32'b00000000000000000000000000000101 delay_state=32'b00000000000000000000000000000110 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s @W:CG1340 : Tx_async.v(268) | Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @W:CG1340 : Tx_async.v(268) | Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @N:CG179 : Tx_async.v(356) | Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @W:CL169 : Tx_async.v(119) | Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) @N:CG364 : Rx_async.v(30) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 receive_states_rx_idle=32'b00000000000000000000000000000000 receive_states_rx_data_bits=32'b00000000000000000000000000000001 receive_states_rx_stop_bit=32'b00000000000000000000000000000010 receive_states_rx_wait_state=32'b00000000000000000000000000000011 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s @N:CG179 : Rx_async.v(254) | Removing redundant assignment. @N:CG179 : Rx_async.v(280) | Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @W:CL177 : Rx_async.v(501) | Sharing sequential element clear_framing_error_en and merging clear_parity_en. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) @N:CG364 : CoreUART.v(31) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s @N:CG179 : CoreUART.v(390) | Removing redundant assignment. @W:CG133 : CoreUART.v(136) | Object data_ready is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... @W:CL169 : CoreUART.v(376) | Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(341) | Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(341) | Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(326) | Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(293) | Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(278) | Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(278) | Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(263) | Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(263) | Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(159) | Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Only the first 100 messages of id 'CG364' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CG364' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG364} -count unlimited' in the Tcl shell. FAMILY=32'b00000000000000000000000000011010 TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 BAUD_VALUE=32'b00000000000000000000000000000001 FIXEDMODE=32'b00000000000000000000000000000000 PRG_BIT8=32'b00000000000000000000000000000000 PRG_PARITY=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 @N:CG179 : CoreUARTapb.v(254) | Removing redundant assignment. @N:CG179 : CoreUARTapb.v(275) | Removing redundant assignment. @W:CG133 : CoreUARTapb.v(158) | Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 ....... Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on CoreUARTapb_0 ....... Finished optimization stage 1 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on fifo_to_tpsram_bridge ....... Finished optimization stage 1 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_BUFF_DEPTH=32'b00000000000000000000000000000010 MI_I_MEM=32'b00000000000000000000000000000000 Generated name = miv_rv32_ifu_iab_32s_2s_3s_2s_0s Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory . @W:CG532 : miv_rv32_hart_merged.v(18721) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory . @W:CG532 : miv_rv32_hart_merged.v(18721) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory . @W:CG532 : miv_rv32_hart_merged.v(18721) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s ....... Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_reset_vector=32'b10000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 IAB_BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_IAB_BUFF_DEPTH=32'b00000000000000000000000000000010 MAX_IFU_EMI_OS=32'b00000000000000000000000000000011 LOG2_MAX_IFU_EMI_OS=32'b00000000000000000000000000000010 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 IFU_MEM_ERROR_BIT=32'b00000000000000000000000000000000 IFU_PARITY_ERROR_BIT=32'b00000000000000000000000000000001 Generated name = miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 Running optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 ....... Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB) D_ADDR_WIDTH=32'b00000000000000000000000000100000 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 OS_COUNT_WIDTH=32'b00000000000000000000000000000010 MAX_OS=32'b00000000000000000000000000000010 Generated name = miv_rv32_lsu_32s_2s_1s_2s_2s @W:CG133 : miv_rv32_hart_merged.v(19009) | Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19017) | Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19020) | Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19021) | Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19022) | Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19023) | Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19024) | Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19025) | Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19026) | Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(19027) | Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... Finished optimization stage 1 on miv_rv32_lsu_32s_2s_1s_2s_2s (CPU Time 0h:00m:00s, Memory Used current: 270MB peak: 271MB) GEN_DECODE_RV32I=1'b1 GEN_DECODE_RV32M=32'b00000000000000000000000000000001 GEN_DECODE_RV32C=32'b00000000000000000000000000000001 GEN_DECODE_RV32F=32'b00000000000000000000000000000000 Generated name = miv_rv32_idecode_1_1s_1s_0s Running optimization stage 1 on miv_rv32_idecode_1_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 281MB peak: 282MB) CHECK_ILLEGAL=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_decode_1s_1s_0s Running optimization stage 1 on miv_rv32_csr_decode_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 281MB peak: 282MB) USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 cfg_div_en=32'b00000000000000000000000000000001 cfg_fast_mul=32'b00000000000000000000000000000000 cfg_slow_mul=32'b00000000000000000000000000000001 Generated name = miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 @W:CG1340 : miv_rv32_hart_merged.v(10740) | Index into variable mul_mp could be out of range ; a simulation mismatch is possible. @W:CG1340 : miv_rv32_hart_merged.v(10740) | Index into variable mul_mp could be out of range ; a simulation mismatch is possible. @W:CG133 : miv_rv32_hart_merged.v(10766) | Object fpu_frm_i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_hart_merged.v(10767) | Object op_i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_pkg.v(843) | Object status_o.NV is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_pkg.v(844) | Object status_o.DZ is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_pkg.v(845) | Object status_o.OF is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_pkg.v(846) | Object status_o.UF is declared but not assigned. Either assign a value or remove the declaration. Only the first 100 messages of id 'CG133' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CG133' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG133} -count unlimited' in the Tcl shell. Running optimization stage 1 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 ....... Finished optimization stage 1 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) Running optimization stage 1 on miv_rv32_bcu ....... Finished optimization stage 1 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) IRQ_STICKY_CAPTURE=32'b00000000000000000000000000000000 Generated name = miv_rv32_irq_reg_0s Running optimization stage 1 on miv_rv32_irq_reg_0s ....... Finished optimization stage 1 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 Generated name = miv_rv32_priv_irq_2s_0_0 Running optimization stage 1 on miv_rv32_priv_irq_2s_0_0 ....... Finished optimization stage 1 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) CHECK_ILLEGAL=32'b00000000000000000000000000000000 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_decode_0s_1s_0s Running optimization stage 1 on miv_rv32_csr_decode_0s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) WIDTH=32'b00000000000000000000000000000101 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_5s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000011 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_3s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000011111 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_31s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000101 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=5'b00000 Generated name = miv_rv32_csr_gpr_state_reg_5s_1s_0 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 Generated name = miv_rv32_csr_privarch_Z15 WIDTH=32'b00000000000000000000000000011110 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=30'b100000000000000000000000000001 Generated name = miv_rv32_csr_gpr_state_reg_30s_1s_536870913 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_0 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b10000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) Running optimization stage 1 on miv_rv32_csr_privarch_Z15 ....... @W:CL168 : miv_rv32_hart_merged.v(4310) | Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Finished optimization stage 1 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 l_core_cfg_gpr_fwd_hzd=1'b0 Generated name = miv_rv32_expipe_Z16 ECC_ENABLE=32'b00000000000000000000000000000000 l_core_cfg_gpr_fwd_hzd=1'b0 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 GPR_DEPTH=32'b00000000000000000000000000100000 Generated name = miv_rv32_gpr_ram_0s_0_0s_32s @N:CG179 : miv_rv32_hart_merged.v(6111) | Removing redundant assignment. @N:CG179 : miv_rv32_hart_merged.v(6112) | Removing redundant assignment. @N:CG179 : miv_rv32_hart_merged.v(6113) | Removing redundant assignment. d_width=32'b00000000000000000000000000100000 addr_width_gpr=32'b00000000000000000000000000000110 mem_depth=32'b00000000000000000000000000100000 Generated name = miv_rv32_gpr_ram_array_32s_6s_32s Running optimization stage 1 on miv_rv32_gpr_ram_array_32s_6s_32s ....... @N:CL134 : miv_rv32_hart_merged.v(6370) | Found RAM mem_xf, depth=32, width=32 @N:CL134 : miv_rv32_hart_merged.v(6370) | Found RAM mem_xf, depth=32, width=32 @N:CL134 : miv_rv32_hart_merged.v(6370) | Found RAM mem_xf, depth=32, width=32 Finished optimization stage 1 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) Running optimization stage 1 on miv_rv32_gpr_ram_0s_0_0s_32s ....... Finished optimization stage 1 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 313MB peak: 330MB) Running optimization stage 1 on miv_rv32_expipe_Z16 ....... @W:CL169 : miv_rv32_hart_merged.v(10390) | Pruning unused register sreset. Make sure that there are no unused intermediate registers. @N:CL189 : miv_rv32_hart_merged.v(9191) | Register bit gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5] is always 0. @W:CL260 : miv_rv32_hart_merged.v(9191) | Pruning register bit 5 of gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 Generated name = miv_rv32_hart_Z17 Running optimization stage 1 on miv_rv32_hart_Z17 ....... Finished optimization stage 1 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000000110 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_6s_2s_1s_1s Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000001011 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_11s_2s_1s_1s Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000011000000010000000011001000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_50397384 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000000111 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_7s_2s_1s_1s Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory . @W:CG532 : miv_rv32_subsys_merged.v(10042) | Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) REGS_ADDR_WIDTH=32'b00000000000000000000000000001100 ECC_ENABLE=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_gpr_ded_reset_en=1'b1 ICACHE_EN=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 REQ_BUFF_WIDTH=32'b00000000000000000000000000000111 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s Running optimization stage 1 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s ....... Finished optimization stage 1 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 ECC_ENABLE=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 MAX_OS_I_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_I_TRX=32'b00000000000000000000000000000001 MAX_OS_D_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_D_TRX=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_interconnect_Z18 Running optimization stage 1 on miv_rv32_subsys_interconnect_Z18 ....... Finished optimization stage 1 on miv_rv32_subsys_interconnect_Z18 (CPU Time 0h:00m:00s, Memory Used current: 290MB peak: 330MB) FAMILY=32'b00000000000000000000000000011010 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_REGISTER_IO=32'b00000000000000000000000000000001 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 SUBSYS_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_TAS_ADDR_WIDTH=32'b00000000000000000000000000100000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_apb_start_addr=32'b01100000000000000000000000000000 l_apb_end_addr=32'b01101111111111111111111111111111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_subsys_cfg_start_addr=32'b00000000000000000110000000000000 l_subsys_cfg_end_addr=32'b00000000000000000110111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_tas_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_tas_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_tcm_tas_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_tas_tcm0_end_addr=32'b00001111111111111111111111100101 l_tcm_tas_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_tas_tcm1_end_addr=32'b00001111111111111111111111101101 l_subsys_cfg_tcm_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_apb_present=32'b00000000000000000000000000000001 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 l_hart_cfg_hw_debug=32'b00000000000000000000000000000001 l_hart_cfg_num_triggers=32'b00000000000000000000000000000010 l_hart_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_hart_cfg_hw_compressed=32'b00000000000000000000000000000001 l_hart_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_hart_reset_vector=32'b10000000000000000000000000000000 l_hart_static_mtvec_base=32'b10000000000000000000000000000100 l_hart_cfg_static_mtvec_base=1'b0 l_hart_cfg_static_mtvec_mode=1'b1 l_hart_static_mtvec_mode=2'b00 l_hart_num_sys_ext_irqs=32'b00000000000000000000000000000000 l_hart_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_hart_cfg_time_count_width=32'b00000000000000000000000001000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 l_hart_cfg_lsu_fwd=1'b0 l_hart_cfg_csr_fwd=1'b0 l_hart_cfg_exu_fwd=1'b0 l_hart_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 I_REGS=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 ICACHE_DEPTH=32'b00000000000000000000000100000000 TCM0_DEPTH=32'b00000000000000001001000000000000 TCM0_WIDTH=32'b00000000000000000000000000010000 TCM1_DEPTH=32'b00000000000000000000000010000001 l_hart_total_sys_ext_irqs=32'b00000000000000000000000000000010 Generated name = miv_rv32_ipcore_Z19 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_dtm_jtag_1s @N:CG179 : miv_rv32_subsys_merged.v(16165) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16173) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16193) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16194) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16195) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16196) | Removing redundant assignment. @N:CG179 : miv_rv32_subsys_merged.v(16380) | Removing redundant assignment. Running optimization stage 1 on miv_rv32_debug_dtm_jtag_1s ....... Finished optimization stage 1 on miv_rv32_debug_dtm_jtag_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) WIDTH=32'b00000000000000000000000000101001 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_fifo_41s_1s_1s Running optimization stage 1 on miv_rv32_debug_fifo_41s_1s_1s ....... @W:CL169 : miv_rv32_subsys_merged.v(15811) | Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers. @N:CL134 : miv_rv32_subsys_merged.v(15839) | Found RAM fifo_memory, depth=2, width=41 @W:CL260 : miv_rv32_subsys_merged.v(15791) | Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_subsys_merged.v(15785) | Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_debug_fifo_41s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) WIDTH=32'b00000000000000000000000000100010 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_fifo_34s_1s_1s Running optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s ....... @W:CL169 : miv_rv32_subsys_merged.v(15811) | Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers. @N:CL134 : miv_rv32_subsys_merged.v(15839) | Found RAM fifo_memory, depth=2, width=34 @W:CL260 : miv_rv32_subsys_merged.v(15791) | Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_subsys_merged.v(15785) | Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) Running optimization stage 1 on miv_rv32_debug_sba ....... Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) Running optimization stage 1 on miv_rv32_debug_du ....... @W:CL265 : miv_rv32_subsys_merged.v(14337) | Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : miv_rv32_subsys_merged.v(14337) | Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : miv_rv32_subsys_merged.v(14337) | Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_debug_1s Running optimization stage 1 on miv_rv32_subsys_debug_1s ....... Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) NUM_REQS=32'b00000000000000000000000000000010 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_2s_1s_1s NUM_REQS=32'b00000000000000000000000000000010 Generated name = miv_rv32_fixed_arb_2s Running optimization stage 1 on miv_rv32_fixed_arb_2s ....... Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) Running optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) APB_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_REGISTER_IO=32'b00000000000000000000000000000001 l_subsys_cfg_apb_byte_shim=1'b1 IDLE_ST=3'b000 SETUP_ST=3'b001 ACCESS_ST=3'b010 BH_READ_0_ST=3'b011 BH_READ_1_ST=3'b100 BH_WRITE_ST=3'b101 Generated name = miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 @N:CG179 : miv_rv32_subsys_merged.v(6281) | Removing redundant assignment. Running optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 ....... Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) NUM_REQS=32'b00000000000000000000000000000011 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_3s_1s_1s NUM_REQS=32'b00000000000000000000000000000011 Generated name = miv_rv32_fixed_arb_3s Running optimization stage 1 on miv_rv32_fixed_arb_3s ....... Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) Running optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s ....... Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB) FAMILY=32'b00000000000000000000000000011010 UDMA_PRESENT=32'b00000000000000000000000000000000 TCM_TAS_PRESENT=32'b00000000000000000000000000000000 DEBUG_PRESENT=32'b00000000000000000000000000000001 CPU_I_PRESENT=32'b00000000000000000000000000000001 CPU_D_PRESENT=32'b00000000000000000000000000000001 USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 RAM_DEPTH=32'b00000000000000000010010000000000 TCM_ADDR_WIDTH=32'b00000000000000000000000000010000 ECC_ENABLE=32'b00000000000000000000000000000000 ROM=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b00000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b00000000000000000000000000000000 BOOTROM_DEST_ADDR=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 l_subsys_cfg_tcm_byte_shim=32'b00000000000000000000000000000001 RAM_DATA_WIDTH=32'b00000000000000000000000000100000 CPU_D_DEBUG_PRESENT=32'b00000000000000000000000000000001 NUM_REQUESTERS=32'b00000000000000000000000000000010 RAM_WEN_WIDTH=32'b00000000000000000000000000000001 UDMA_TAS_PRESENT=32'b00000000000000000000000000000000 BH_INIT=2'b00 BH_READ=2'b01 BH_WRITE=2'b10 Generated name = miv_rv32_subsys_tcm_Z20 Running optimization stage 1 on OR4 ....... Finished optimization stage 1 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on CFG2 ....... Finished optimization stage 1 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on CFG3 ....... Finished optimization stage 1 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on OR2 ....... Finished optimization stage 1 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on INV ....... Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 320MB peak: 330MB) RAM_DEPTH=32'b00000000000000000010010000000000 ADDR_WIDTH=32'b00000000000000000000000000001110 RAMINDEX_0=488'b00000000000000000101000001000110010111110101010001010000010100110101001001000001010011010101111101001101010000010101100001011111001100000010010100111001001100100011000100110110001011010011100100110010001100010011011000100101001100110011001000101101001100110011001000100101010100000100111101010111010001010101001000100101001100000010010100110000001001010101010001010111010011110010110101010000010011110101001001010100001001010100010101000011010000110101111101000101010011100010110100110000 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RAMINDEX_126=504'b000000000000000001010000010001100101111101010100010100000101001101010010010000010100110101011111010011010100000101011000010111110011000000100101001110010011001000110001001101100010110100111001001100100011000100110110001001010011001100110010001011010011001100110010001001010101000001001111010101110100010101010010001001010011000100110010001101100010010100110000001001010101010001010111010011110010110101010000010011110101001001010100001001010100010101000011010000110101111101000101010011100010110100110000 RAMINDEX_127=504'b000000000000000001010000010001100101111101010100010100000101001101010010010000010100110101011111010011010100000101011000010111110011000000100101001110010011001000110001001101100010110100111001001100100011000100110110001001010011001100110010001011010011001100110010001001010101000001001111010101110100010101010010001001010011000100110010001101110010010100110000001001010101010001010111010011110010110101010000010011110101001001010100001001010100010101000011010000110101111101000101010011100010110100110000 Generated name = miv_rv32_ram_singleport_lp_Z21 Running optimization stage 1 on miv_rv32_ram_singleport_lp_Z21 ....... @W:CL168 : miv_rv32_ram_singleport_lp.v(25538) | Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25498) | Removing instance miv_rv32_ram_singleport_lp_R20C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25465) | Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25376) | Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25295) | Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25265) | Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25182) | Removing instance miv_rv32_ram_singleport_lp_R24C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25159) | Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25104) | Removing instance \CFG2_BLKY2[6] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(25049) | Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24993) | Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24990) | Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24953) | Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24901) | Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24863) | Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24853) | Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24804) | Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24764) | Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24686) | Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24667) | Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24622) | Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24548) | Removing instance miv_rv32_ram_singleport_lp_R31C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24502) | Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24492) | Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24490) | Removing instance CFG3_22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24451) | Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24412) | Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24308) | Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24268) | Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24254) | Removing instance CFG3_11 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24231) | Removing instance CFG3_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24202) | Removing instance CFG3_21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24148) | Removing instance miv_rv32_ram_singleport_lp_R25C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24142) | Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24105) | Removing instance miv_rv32_ram_singleport_lp_R28C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24033) | Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(24029) | Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23903) | Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23864) | Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23805) | Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23799) | Removing instance \CFG2_BLKY2[7] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23753) | Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23685) | Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23662) | Removing instance \CFG2_BLKY2[5] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23601) | Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23540) | Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23490) | Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23440) | Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23401) | Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23338) | Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23292) | Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23222) | Removing instance miv_rv32_ram_singleport_lp_R26C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23130) | Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23092) | Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23071) | Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(23012) | Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22972) | Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22882) | Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22821) | Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22779) | Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22733) | Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22687) | Removing instance miv_rv32_ram_singleport_lp_R27C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22671) | Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22665) | Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22600) | Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22556) | Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22510) | Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22433) | Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22330) | Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22260) | Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22193) | Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22147) | Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(22094) | Removing instance miv_rv32_ram_singleport_lp_R29C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21997) | Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21988) | Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21943) | Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21894) | Removing instance miv_rv32_ram_singleport_lp_R30C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21848) | Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21845) | Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21838) | Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21814) | Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21791) | Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21713) | Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21667) | Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21589) | Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21586) | Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21578) | Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21562) | Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21440) | Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21385) | Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21341) | Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21304) | Removing instance miv_rv32_ram_singleport_lp_R18C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21236) | Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21193) | Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(21098) | Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Only the first 100 messages of id 'CL168' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL168' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL168} -count unlimited' in the Tcl shell. Finished optimization stage 1 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 332MB peak: 333MB) Running optimization stage 1 on miv_rv32_subsys_tcm_Z20 ....... @W:CL169 : miv_rv32_subsys_merged.v(10961) | Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_subsys_merged.v(10961) | Pruning unused register tcm_tas_access_disable_reg. Make sure that there are no unused intermediate registers. @W:CL265 : miv_rv32_subsys_merged.v(11237) | Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : miv_rv32_subsys_merged.v(11056) | Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 1 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 334MB) @W:CS263 : miv_rv32_subsys_merged.v(1481) | Port-width mismatch for port cpu_i_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CS263 : miv_rv32_subsys_merged.v(1494) | Port-width mismatch for port cpu_d_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CS263 : miv_rv32_subsys_merged.v(1509) | Port-width mismatch for port udma_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W:CS263 : miv_rv32_subsys_merged.v(1526) | Port-width mismatch for port tcm_tas_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 SYNC_RESET=32'b00000000000000000000000000000001 l_mtime_addr_u=32'b00000010000000001011111111111100 l_mtimecmp_addr_u=32'b00000010000000000100000000000100 Generated name = miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 Running optimization stage 1 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 ....... Finished optimization stage 1 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on miv_rv32_ipcore_Z19 ....... Finished optimization stage 1 on miv_rv32_ipcore_Z19 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) FAMILY=32'b00000000000000000000000000011010 RESET_VECTOR_ADDR_1=16'b1000000000000000 RESET_VECTOR_ADDR_0=16'b0000000000000000 DEBUGGER=32'b00000000000000000000000000000001 I_TRACE=32'b00000000000000000000000000000000 AXI_INITIATOR_TYPE=32'b00000000000000000000000000000000 AXI_TARGET_MIRROR=32'b00000000000000000000000000000000 AXI_START_ADDR_1=16'b0110000000000000 AXI_START_ADDR_0=16'b0000000000000000 AXI_END_ADDR_1=16'b0110111111111111 AXI_END_ADDR_0=16'b1111111111111111 AHB_INITIATOR_TYPE=32'b00000000000000000000000000000000 AHB_TARGET_MIRROR=32'b00000000000000000000000000000000 AHB_START_ADDR_1=16'b1000000000000000 AHB_START_ADDR_0=16'b0000000000000000 AHB_END_ADDR_1=16'b1000111111111111 AHB_END_ADDR_0=16'b1111111111111111 APB_INITIATOR_TYPE=32'b00000000000000000000000000000001 APB_TARGET_MIRROR=32'b00000000000000000000000000000000 APB_START_ADDR_1=16'b0110000000000000 APB_START_ADDR_0=16'b0000000000000000 APB_END_ADDR_1=16'b0110111111111111 APB_END_ADDR_0=16'b1111111111111111 TCM_PRESENT=32'b00000000000000000000000000000001 TCM_START_ADDR_1=16'b1000000000000000 TCM_START_ADDR_0=16'b0000000000000000 TCM_END_ADDR_1=16'b1000000000000000 TCM_END_ADDR_0=16'b1000111111111111 TCM_TAS_PRESENT=32'b00000000000000000000000000000000 TAS_START_ADDR_1=16'b0100000000000000 TAS_START_ADDR_0=16'b0000000000000000 TAS_END_ADDR_1=16'b0100000000000000 TAS_END_ADDR_0=16'b0011111111111111 C_EXT=32'b00000000000000000000000000000001 F_EXT=32'b00000000000000000000000000000000 M_EXT=32'b00000000000000000000000000000001 GEN_MUL_TYPE=32'b00000000000000000000000000000000 VECTORED_INTERRUPTS=32'b00000000000000000000000000000000 NUM_EXT_IRQS=32'b00000000000000000000000000000000 FWD_REGS=32'b00000000000000000000000000000000 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 GPR_REGS=32'b00000000000000000000000000000000 BOOTROM_PRESENT=32'b00000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_START_ADDR_LOWER=16'b0000000000000000 BOOTROM_SRC_END_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_END_ADDR_LOWER=16'b0011111111111111 BOOTROM_DEST_ADDR_UPPER=16'b0100000000000000 BOOTROM_DEST_ADDR_LOWER=16'b0000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 I_REGS=32'b00000000000000000000000000000000 MIV_HART_ID=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 APB_REGISTER_IO=32'b00000000000000000000000000000001 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 SUBSYS_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_TAS_ADDR_WIDTH=32'b00000000000000000000000000100000 MAX_EXT_IRQS=32'b00000000000000000000000000001000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_apb_present=32'b00000000000000000000000000000001 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 l_hart_cfg_hw_debug=32'b00000000000000000000000000000001 l_hart_cfg_num_triggers=32'b00000000000000000000000000000010 l_subsys_cfg_tcm_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_tas_present=32'b00000000000000000000000000000000 l_apb_start_addr=32'b01100000000000000000000000000000 l_apb_end_addr=32'b01101111111111111111111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_tcm_tas_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_tas_tcm0_end_addr=32'b00001111111111111111111111100101 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_tas_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_tas_tcm1_end_addr=32'b00001111111111111111111111101101 l_tcm_tas_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_tas_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_subsys_cfg_start_addr=32'b00000000000000000110000000000000 l_subsys_cfg_end_addr=32'b00000000000000000110111111111111 l_hart_cfg_time_count_width=32'b00000000000000000000000001000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 l_hart_reset_vector=32'b10000000000000000000000000000000 l_hart_mtvec_offset=28'b0000000000000000000000000100 l_hart_static_mtvec_base=32'b10000000000000000000000000000100 l_hart_cfg_static_mtvec_base=1'b0 l_hart_cfg_static_mtvec_mode=1'b1 l_hart_static_mtvec_mode=2'b00 l_hart_cfg_hw_compressed=32'b00000000000000000000000000000001 l_hart_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_hart_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_hart_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_hart_num_sys_ext_irqs=32'b00000000000000000000000000000000 l_hart_cfg_lsu_fwd=1'b0 l_hart_cfg_csr_fwd=1'b0 l_hart_cfg_exu_fwd=1'b0 l_hart_cfg_gpr_type=1'b0 l_icache_en=32'b00000000000000000000000000000000 l_mi_i_mem=32'b00000000000000000000000000000000 Generated name = MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 @W:CG360 : miv_rv32.v(343) | Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it. Running optimization stage 1 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 ....... Finished optimization stage 1 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CS263 : MIV_RV32_C0.v(305) | Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on MIV_RV32_C0 ....... Finished optimization stage 1 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PLL ....... Finished optimization stage 1 on PLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Finished optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_CCC_0 ....... Finished optimization stage 1 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on INIT ....... Finished optimization stage 1 on INIT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on BANKEN ....... Finished optimization stage 1 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Finished optimization stage 1 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on pf_init_monitor_0 ....... Finished optimization stage 1 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ST_RSWT=2'b00 ST_RWAT=2'b01 ST_LSWT=2'b10 ST_LWAT=2'b11 STEP=32'b00000000000000000000000000000011 COMP0_STEP=32'b00000000000000000000000000000000 COMP1_STEP=32'b00000000000000000000000000000100 COMP2_STEP=32'b00000000000000000000000000000001 COMP3_STEP=32'b00000000000000000000000000000001 EYEWIDTH=3'b001 Generated name = CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 Running optimization stage 1 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... Finished optimization stage 1 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on OUTBUF_DIFF ....... Finished optimization stage 1 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on IOD ....... Finished optimization stage 1 on IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v(64) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v(67) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54) | Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54) | Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(59) | Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on LANECTRL ....... Finished optimization stage 1 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 @W:CG360 : PF_LANECTRL_PAUSE_SYNC.v(21) | Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on RCLKINT ....... Finished optimization stage 1 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_C0 ....... Finished optimization stage 1 on PF_IOD_CDR_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on HS_IO_CLK ....... Finished optimization stage 1 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W:CG168 : PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v(47) | Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on DLL ....... Finished optimization stage 1 on DLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on ICB_CLKDIV ....... Finished optimization stage 1 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on COREDELAYCODE_TIP ....... Finished optimization stage 1 on COREDELAYCODE_TIP (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 @W:CG360 : PF_LANECTRL_PAUSE_SYNC.v(21) | Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0 ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM ....... Finished optimization stage 1 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_TPSRAM_C0 ....... Finished optimization stage 1 on PF_TPSRAM_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on SSDetect ....... Finished optimization stage 1 on SSDetect (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on SSDetect ....... @W:CL246 : SSDetect.v(24) | Input port bits 9 to 7 of rx_data[9:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on SSDetect (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_TPSRAM_C0 ....... Finished optimization stage 2 on PF_TPSRAM_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM ....... Finished optimization stage 2 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0 ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input CLK is unused. @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input RESET is unused. Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on COREDELAYCODE_TIP ....... @N:CL201 : CoreDelayCode_TIP.v(59) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on COREDELAYCODE_TIP (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on ICB_CLKDIV ....... Finished optimization stage 2 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on DLL ....... Finished optimization stage 2 on DLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on HS_IO_CLK ....... Finished optimization stage 2 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0 ....... @N:CL159 : PF_IOD_CDR_C0.v(70) | Input DLL_LOCK is unused. @N:CL159 : PF_IOD_CDR_C0.v(77) | Input PLL_LOCK is unused. Finished optimization stage 2 on PF_IOD_CDR_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on RCLKINT ....... Finished optimization stage 2 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input CLK is unused. @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input RESET is unused. Finished optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on LANECTRL ....... Finished optimization stage 2 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... @N:CL159 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(31) | Input FAB_CLK is unused. Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on IOD ....... Finished optimization stage 2 on IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on OUTBUF_DIFF ....... Finished optimization stage 2 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... @N:CL201 : corecdr4_cntl_tip.v(117) | Trying to extract state machine for register tune_st. Extracted state machine for register tune_st State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on pf_init_monitor_0 ....... Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on BANKEN ....... Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on INIT ....... Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on PF_CCC_0 ....... Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on PLL ....... Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on MIV_RV32_C0 ....... Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 ....... Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 ....... @N:CL159 : miv_rv32_subsys_merged.v(13005) | Input mtime_count_in is unused. Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 ....... Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on INV ....... Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on OR2 ....... Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on CFG3 ....... Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on CFG2 ....... Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on OR4 ....... Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_subsys_tcm_Z20 ....... @N:CL201 : miv_rv32_subsys_merged.v(11056) | Trying to extract state machine for register cpu_d_wr_rd_state. Extracted state machine for register cpu_d_wr_rd_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL279 : miv_rv32_subsys_merged.v(11056) | Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL246 : miv_rv32_subsys_merged.v(10831) | Input port bits 1 to 0 of cpu_i_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(10844) | Input port bits 1 to 0 of cpu_d_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : miv_rv32_subsys_merged.v(10889) | *Unassigned bits of tcm_ram_sb_out[3:0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : miv_rv32_subsys_merged.v(10821) | Input subsys_parity_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10830) | Input cpu_i_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10832) | Input cpu_i_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10834) | Input cpu_i_resp_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(10840) | Input cpu_d_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10842) | Input cpu_d_req_read is unused. @N:CL159 : miv_rv32_subsys_merged.v(10843) | Input cpu_d_req_write is unused. @N:CL159 : miv_rv32_subsys_merged.v(10845) | Input cpu_d_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10847) | Input cpu_d_req_wr_data_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10849) | Input cpu_d_resp_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(10855) | Input udma_req_valid is unused. @N:CL159 : miv_rv32_subsys_merged.v(10857) | Input udma_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10858) | Input udma_req_wr_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10859) | Input udma_req_read is unused. @N:CL159 : miv_rv32_subsys_merged.v(10860) | Input udma_req_write is unused. @N:CL159 : miv_rv32_subsys_merged.v(10861) | Input udma_req_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(10862) | Input udma_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10863) | Input udma_req_len is unused. @N:CL159 : miv_rv32_subsys_merged.v(10864) | Input udma_req_wr_data is unused. @N:CL159 : miv_rv32_subsys_merged.v(10865) | Input udma_req_wr_data_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10867) | Input udma_resp_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(10874) | Input tcm_dma_access_disable is unused. @N:CL159 : miv_rv32_subsys_merged.v(10875) | Input tcm_tas_access_disable is unused. @N:CL159 : miv_rv32_subsys_merged.v(10876) | Input tcm_tas_req_valid is unused. @N:CL159 : miv_rv32_subsys_merged.v(10878) | Input tcm_tas_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10879) | Input tcm_tas_req_wr_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(10880) | Input tcm_tas_req_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(10881) | Input tcm_tas_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10882) | Input tcm_tas_req_wr_data is unused. @N:CL159 : miv_rv32_subsys_merged.v(10883) | Input tcm_tas_req_wr_data_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(10885) | Input tcm_tas_resp_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(10890) | Input tcm_ram_sb_in is unused. @N:CL159 : miv_rv32_subsys_merged.v(10891) | Input tcm_ecc_error_injection is unused. Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_fixed_arb_3s ....... Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s ....... @N:CL201 : miv_rv32_subsys_merged.v(10391) | Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 7 reachable states with original encodings of: 001 010 011 100 101 110 111 Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 ....... @N:CL201 : miv_rv32_subsys_merged.v(6231) | Trying to extract state machine for register gen_apb_byte_shim.apb_st. Extracted state machine for register gen_apb_byte_shim.apb_st State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 @N:CL159 : miv_rv32_subsys_merged.v(6063) | Input subsys_parity_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(6070) | Input cpu_i_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(6072) | Input cpu_i_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(6074) | Input cpu_i_resp_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(6080) | Input cpu_d_req_rd_byte_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(6083) | Input cpu_d_req_addr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(6087) | Input cpu_d_resp_ready is unused. Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_fixed_arb_2s ....... Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s ....... @N:CL201 : miv_rv32_subsys_merged.v(10391) | Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 3 reachable states with original encodings of: 01 10 11 Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_subsys_debug_1s ....... Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB) Running optimization stage 2 on miv_rv32_debug_du ....... @N:CL201 : miv_rv32_subsys_merged.v(14736) | Trying to extract state machine for register debug_state. Extracted state machine for register debug_state State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @N:CL201 : miv_rv32_subsys_merged.v(14337) | Trying to extract state machine for register command_reg_state. @N:CL159 : miv_rv32_subsys_merged.v(13800) | Input dmi_resp_ready is unused. Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:01s, Memory Used current: 335MB peak: 354MB) Running optimization stage 2 on miv_rv32_debug_sba ....... @N:CL201 : miv_rv32_subsys_merged.v(15192) | Trying to extract state machine for register sba_state. Extracted state machine for register sba_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:02s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s ....... Finished optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s ....... Finished optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_dtm_jtag_1s ....... @N:CL201 : miv_rv32_subsys_merged.v(16135) | Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat. Extracted state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : miv_rv32_subsys_merged.v(16013) | Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState. Extracted state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N:CL159 : miv_rv32_subsys_merged.v(15942) | Input dtm_req_ready is unused. Finished optimization stage 2 on miv_rv32_debug_dtm_jtag_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_ipcore_Z19 ....... @A:CL153 : miv_rv32_subsys_merged.v(545) | *Unassigned bits of ahb_i_resp_last_net are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : miv_rv32_subsys_merged.v(191) | Input m_timer_irq is unused. @N:CL159 : miv_rv32_subsys_merged.v(227) | Input tcm1_cpu_access_disable is unused. @N:CL159 : miv_rv32_subsys_merged.v(228) | Input tcm1_dma_access_disable is unused. @N:CL159 : miv_rv32_subsys_merged.v(229) | Input tcm1_tas_access_disable is unused. @N:CL159 : miv_rv32_subsys_merged.v(230) | Input tcm_tas_paddr is unused. @N:CL159 : miv_rv32_subsys_merged.v(231) | Input tcm_tas_paddr_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(232) | Input tcm_tas_pprot is unused. @N:CL159 : miv_rv32_subsys_merged.v(233) | Input tcm_tas_psel is unused. @N:CL159 : miv_rv32_subsys_merged.v(234) | Input tcm_tas_penable is unused. @N:CL159 : miv_rv32_subsys_merged.v(235) | Input tcm_tas_pwrite is unused. @N:CL159 : miv_rv32_subsys_merged.v(236) | Input tcm_tas_pwdata is unused. @N:CL159 : miv_rv32_subsys_merged.v(237) | Input tcm_tas_pwdata_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(248) | Input tcm1_ram_sb_in is unused. @N:CL159 : miv_rv32_subsys_merged.v(252) | Input axi_aclk_en is unused. @N:CL159 : miv_rv32_subsys_merged.v(261) | Input axi_arready is unused. @N:CL159 : miv_rv32_subsys_merged.v(264) | Input axi_rresp is unused. @N:CL159 : miv_rv32_subsys_merged.v(265) | Input axi_rdata is unused. @N:CL159 : miv_rv32_subsys_merged.v(266) | Input axi_rlast is unused. @N:CL159 : miv_rv32_subsys_merged.v(267) | Input axi_rid is unused. @N:CL159 : miv_rv32_subsys_merged.v(269) | Input axi_rvalid is unused. @N:CL159 : miv_rv32_subsys_merged.v(270) | Input axi_r_data_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(280) | Input axi_awready is unused. @N:CL159 : miv_rv32_subsys_merged.v(286) | Input axi_wready is unused. @N:CL159 : miv_rv32_subsys_merged.v(289) | Input axi_bresp is unused. @N:CL159 : miv_rv32_subsys_merged.v(290) | Input axi_bid is unused. @N:CL159 : miv_rv32_subsys_merged.v(292) | Input axi_bvalid is unused. @N:CL159 : miv_rv32_subsys_merged.v(305) | Input ahb_hrdata is unused. @N:CL159 : miv_rv32_subsys_merged.v(306) | Input ahb_hrdata_p is unused. @N:CL159 : miv_rv32_subsys_merged.v(307) | Input ahb_hready is unused. @N:CL159 : miv_rv32_subsys_merged.v(308) | Input ahb_hresp is unused. Finished optimization stage 2 on miv_rv32_ipcore_Z19 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_subsys_interconnect_Z18 ....... @W:CL246 : miv_rv32_subsys_merged.v(2494) | Input port bits 11 to 0 of cfg_apb_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(2495) | Input port bits 11 to 0 of cfg_apb_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(2500) | Input port bits 11 to 0 of cfg_subsys_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(2501) | Input port bits 11 to 0 of cfg_subsys_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(2502) | Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(2503) | Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : miv_rv32_subsys_merged.v(2492) | Input cfg_axi_start_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2493) | Input cfg_axi_end_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2496) | Input cfg_ahb_start_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2497) | Input cfg_ahb_end_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2498) | Input cfg_udma_ctrl_start_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2499) | Input cfg_udma_ctrl_end_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2504) | Input cfg_tcm1_start_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2505) | Input cfg_tcm1_end_addr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2575) | Input apb_trx_os_d_rd is unused. @N:CL159 : miv_rv32_subsys_merged.v(2576) | Input apb_trx_os_d_wr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2604) | Input tcm0_trx_os_d_rd is unused. @N:CL159 : miv_rv32_subsys_merged.v(2605) | Input tcm0_trx_os_d_wr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2611) | Input tcm1_i_req_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(2621) | Input tcm1_d_req_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(2635) | Input tcm1_trx_os_d_rd is unused. @N:CL159 : miv_rv32_subsys_merged.v(2636) | Input tcm1_trx_os_d_wr is unused. @N:CL159 : miv_rv32_subsys_merged.v(2642) | Input axi_i_req_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(2647) | Input axi_i_resp_last is unused. @N:CL159 : miv_rv32_subsys_merged.v(2653) | Input axi_d_req_ready is unused. @N:CL159 : miv_rv32_subsys_merged.v(2668) | Input axi_trx_os_d_rd is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Finished optimization stage 2 on miv_rv32_subsys_interconnect_Z18 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s ....... @W:CL246 : miv_rv32_subsys_merged.v(4490) | Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_subsys_merged.v(4495) | Input port bits 31 to 3 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_7s_2s_1s_1s ....... @N:CL134 : miv_rv32_subsys_merged.v(10047) | Found RAM gen_buff_loop[0].buff_data, depth=2, width=7 Finished optimization stage 2 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_11s_2s_1s_1s ....... @N:CL134 : miv_rv32_subsys_merged.v(10047) | Found RAM gen_buff_loop[0].buff_data, depth=2, width=11 Finished optimization stage 2 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_6s_2s_1s_1s ....... @N:CL134 : miv_rv32_subsys_merged.v(10047) | Found RAM gen_buff_loop[0].buff_data, depth=2, width=6 Finished optimization stage 2 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_hart_Z17 ....... Finished optimization stage 2 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s ....... @W:CL247 : miv_rv32_hart_merged.v(6360) | Input port bit 5 of waddr0[5:0] is unused Finished optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s ....... Finished optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_expipe_Z16 ....... Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:02s, Memory Used current: 345MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_privarch_Z15 ....... @W:CL247 : miv_rv32_hart_merged.v(1854) | Input port bit 1 of excpt_trigger[1:0] is unused Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 ....... @W:CL246 : miv_rv32_hart_merged.v(6887) | Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_hart_merged.v(6887) | Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_hart_merged.v(6887) | Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_hart_merged.v(6887) | Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_hart_merged.v(6887) | Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_hart_merged.v(6896) | Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_irq_reg_0s ....... Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_bcu ....... Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB) Running optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 ....... @W:CL279 : miv_rv32_hart_merged.v(11446) | Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:03s, Memory Used current: 376MB peak: 397MB) Running optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 397MB) Running optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 376MB peak: 397MB) Running optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... @W:CL260 : miv_rv32_hart_merged.v(19324) | Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_hart_merged.v(19324) | Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_hart_merged.v(19324) | Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_hart_merged.v(19324) | Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 ....... Finished optimization stage 2 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s ....... @N:CL134 : miv_rv32_hart_merged.v(18735) | Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16 @N:CL134 : miv_rv32_hart_merged.v(18735) | Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32 @N:CL134 : miv_rv32_hart_merged.v(18735) | Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 @N:CL134 : miv_rv32_hart_merged.v(18735) | Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 Finished optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on fifo_to_tpsram_bridge ....... @N:CL201 : fifo_to_tpsram_bridge.v(65) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 Finished optimization stage 2 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0 ....... Finished optimization stage 2 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 ....... @W:CL246 : CoreUARTapb.v(104) | Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : CoreUARTapb.v(158) | *Unassigned bits of controlReg3[2:0] are referenced and tied to 0 -- simulation mismatch possible. Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @N:CL201 : Rx_async.v(286) | Trying to extract state machine for register rx_state. Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @N:CL201 : Tx_async.v(119) | Trying to extract state machine for register xmit_state. Extracted state machine for register xmit_state State machine has 6 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CORETSE_0 ....... Finished optimization stage 2 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 ....... Finished optimization stage 2 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CORETSE_Z11 ....... Finished optimization stage 2 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CORE_26s_0s_18s_0s ....... Finished optimization stage 2 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVRXO_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVRXI_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_TBI_26s_0s_0s_1s ....... Finished optimization stage 2 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETCR_26s_1s ....... Finished optimization stage 2 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETBM_26s_0s_1s ....... Finished optimization stage 2 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEANX_SYNC_1s_26s ....... Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s ....... Extracted state machine for register lI101 State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_R10B8B ....... Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s ....... Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_T8B10B ....... Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVTXO_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVTXI_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s ....... Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s ....... Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_CORETSE_TOP_Z10 ....... Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_ECC_0s_26s_16s ....... Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_CLKRST_26s_1s ....... Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_SI_SAL_26s ....... Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MMCXWOL_1s_26s ....... Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s ....... Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_STORE_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s ....... Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_TSMAC_TOP_Z9 ....... Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s ....... Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PECAR_26s_1s ....... Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEHST_1s_26s ....... Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PEMGT_1s_26s ....... Extracted state machine for register l0i11 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s ....... Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PERMC_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s ....... Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s ....... Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:01s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_PECRC_1s_26s ....... Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_PETMC_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s ....... Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s ....... Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s ....... Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXFIF_HST_Z8 ....... Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... Extracted state machine for register genblk1.O0Il1 State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s ....... Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s ....... Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CTSE_DECODER ....... Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CORESPI_0 ....... Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CORESPI_Z7 ....... Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s ....... @W:CL246 : spi.v(70) | Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_chanctrl_Z6 ....... @W:CL260 : spi_chanctrl.v(823) | Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : spi_chanctrl.v(416) | Trying to extract state machine for register mtx_state. Extracted state machine for register mtx_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0111 1000 1001 Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_clockmux ....... Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_fifo_16s_32s_5 ....... @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=1 @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=16 Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_control_16s ....... Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on spi_rf_32s_16s_0 ....... @W:CL246 : spi_rf.v(42) | Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREJTAGDEBUG_C0 ....... Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on BUFD ....... Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on corejtagdebug_bufd_34s ....... Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on UJTAG ....... Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREJTAGDEBUG_Z5 ....... Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0 ....... Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on RAM1K20 ....... Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CoreAPB3_0 ....... Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on CoreAPB3_Z1 ....... @W:CL246 : coreapb3.v(75) | Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on Core_reset_pf ....... Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... @N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1. Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB) For a summary of runtime per design unit, please see file: ========================================================== Linked File: layer0.duruntime At c_ver Exit (Real Time elapsed 0h:04m:12s; CPU Time elapsed 0h:04m:12s; Memory used current: 380MB peak: 397MB) Process took 0h:04m:12s realtime, 0h:04m:12s cputime Process completed successfully. # Fri Apr 17 08:31:33 2026 ###########################################################] ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @ @N: : | Running in 64-bit mode File E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 82MB peak: 133MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Fri Apr 17 08:31:37 2026 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:04m:17s; CPU Time elapsed 0h:04m:16s; Memory used current: 15MB peak: 24MB) Process took 0h:04m:17s realtime, 0h:04m:16s cputime Process completed successfully. # Fri Apr 17 08:31:37 2026 ###########################################################] ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @ @N: : | Running in 64-bit mode File E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 157MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime Process completed successfully. # Fri Apr 17 08:31:42 2026 ###########################################################] Premap Report # Fri Apr 17 08:31:43 2026 Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys Microchip Technology Pre-mapping, Version map202309act, Build 395R, Built Apr 29 2025 06:36:49, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB) Reading constraint file: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 261MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB) Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 265MB peak: 265MB) Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 266MB peak: 267MB) Vector Gate Optimization Enabled: Optimizing Partial Hanging Logic. NConnInternalConnection caching is on @W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @W:FX1172 : miv_rv32_hart_merged.v(18726) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_hart_merged.v(18726) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_hart_merged.v(18726) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture. @N:FX1171 : miv_rv32_hart_merged.v(11493) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(11473) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : miv_rv32_subsys_merged.v(14495) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_subsys_merged.v(14495) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture. @N:FX1171 : miv_rv32_hart_merged.v(5705) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture. @W:FX1172 : miv_rv32_subsys_merged.v(10047) | User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture. Starting HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 338MB) Finished HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB) @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(48) | Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(46) | Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(49) | Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(47) | Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(169) | Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(176) | Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(183) | Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(190) | Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(32) | Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(31) | Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND. Started DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 339MB) Finished DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 340MB) @N:BN115 : miv_rv32_hart_merged.v(7090) | Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_hart_merged.v(7090) | Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_hart_merged.v(7016) | Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_hart_merged.v(2565) | Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_subsys_merged.v(4653) | Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_subsys_merged.v(4904) | Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances. @N:BN115 : miv_rv32_subsys_merged.v(4923) | Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances. @N:BN115 : pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v(107) | Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances. @N:BN115 : pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v(93) | Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_async.v(501) | Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN362 : rx_async.v(501) | Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(5705) | Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances. @N:BN115 : miv_rv32_hart_merged.v(2594) | Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10461) | Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corefifo_sync_scntr.v(579) | Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(6376) | Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(5705) | Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(6361) | Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(6097) | Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(6370) | Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(6097) | Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : corefifo_sync_scntr.v(438) | Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(16308) | Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(9775) | Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(630) | Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(416) | Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(9245) | Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=952 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 348MB peak: 348MB) Some data will not be shown as it is part of encrypted module Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load -------------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1 1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 4979 2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0 0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT0_GRP 3 2 .. PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 8.000 generated (from REFCLK_P) Y_DIV_GRP 1410 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT1_GRP 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT2_GRP 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT3_GRP 1 0 - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 8.000 declared SGMII_CDR_0_0_CLK_OUT_GRP 1323 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - TCK 10.0 MHz 100.000 declared JTAG_Async_2 0 0 - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0_3 184 0 - PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz 10.000 inferred Inferred_clkgroup_0_1 2 ==================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 4979 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG) PHY_MDC_CLOCK 0 - - - - REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 3 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0(PLL) PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3.A(HS_IO_CLK) PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 1410 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV(ICB_CLKDIV) PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1:0].C - - PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7.A(HS_IO_CLK) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.REF_CLK(DLL) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15.A(HS_IO_CLK) PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 1323 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R(LANECTRL) SSDetect_0.rx_start[1:0].C - PF_IOD_CDR_C0_0.RCLKINT_0.A(RCLKINT) System 0 - - - - TCK 0 TCK(port) - - - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 184 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst.UDRCK(UJTAG) MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.genblk1\.rst_synch_reg[1:0].C - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.un1_jtag_tck.I[0](inv) PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK(LANECTRL) PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.CDR_CLK - - =========================================================================================================================================================================================================================================================================================================================================================================================================================== @W:MT530 : pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v(48) | Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : corejtagdebug_uj_jtag.v(215) | Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 334MB peak: 349MB) Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 Encoding state machine genblk1\.O0Il1[4:0] (in view: work.CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 Encoding state machine l0i11[31:0] (in view: work.CTSE_PEMGT_1s_26s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 Encoding state machine lI101_1[3:0] (in view: work.CTSE_PEREX_PCS_0s_26s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine xmit_state[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 Encoding state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. Encoding state machine state[2:0] (in view: work.fifo_to_tpsram_bridge(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_subsys_merged.v(16135) | There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required. Encoding state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_subsys_merged.v(15192) | There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required. Encoding state machine debug_state[5:0] (in view: work.miv_rv32_debug_du(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog)) original code -> new code 01 -> 00 10 -> 01 11 -> 10 Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) original code -> new code 001 -> 0000001 010 -> 0000010 011 -> 0000100 100 -> 0001000 101 -> 0010000 110 -> 0100000 111 -> 1000000 Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_subsys_tcm_Z20(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : corecdr4_cntl_tip.v(117) | There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required. Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coredelaycode_tip.v(59) | There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 342MB peak: 349MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 351MB peak: 366MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 249MB peak: 366MB) Process took 0h:00m:15s realtime, 0h:00m:15s cputime # Fri Apr 17 08:31:59 2026 ###########################################################] Map & Optimize Report # Fri Apr 17 08:32:00 2026 Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: V-2023.09M-5 Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro OS: Windows 10 or later Hostname: SOFTWARE-PC Implementation : synthesis Synopsys Microchip Technology Mapper, Version map202309act, Build 395R, Built Apr 29 2025 06:36:49, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 199MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 199MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 199MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 199MB) Vector Gate Optimization Enabled: Optimizing Partial Hanging Logic. Starting Optimization and Mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 296MB peak: 296MB) @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(49) | Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(48) | Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(47) | Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:MO111 : corefifo_c0_corefifo_c0_0_ram_wrapper.v(46) | Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND. @N:BN362 : corefifo_fwft.v(347) | Removing sequential instance genblk17\.u_corefifo_fwft.reg_valid_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : corefifo_fwft.v(347) | Removing sequential instance genblk17\.u_corefifo_fwft.empty_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BZ173 : spi_chanctrl.v(645) | ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) mapped in logic. @N:MO106 : spi_chanctrl.v(645) | Found ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) with 10 words by 2 bits. @N:BZ173 : miv_rv32_hart_merged.v(19089) | ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic. @N:MO106 : miv_rv32_hart_merged.v(19089) | Found ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 3 bits. @N:BZ173 : coreapb3.v(267) | ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic. @N:BZ173 : coreapb3.v(267) | ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic. @N:MO106 : coreapb3.v(267) | Found ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) with 3 words by 3 bits. @N:BN362 : miv_rv32_subsys_merged.v(6231) | Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 312MB peak: 322MB) @N:MO231 : corefifo_sync_scntr.v(636) | Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memraddr_r[9:0] @N:MO231 : corefifo_sync_scntr.v(620) | Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memwaddr_r[9:0] @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 @N:MO231 : spi_chanctrl.v(823) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance stxs_bitcnt[4:0] @N:MO231 : spi_chanctrl.v(286) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance spi_clk_count[7:0] Encoding state machine genblk1\.O0Il1[4:0] (in view: work.CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : | Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog)) Encoding state machine l0i11[31:0] (in view: work.CTSE_PEMGT_1s_26s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 Encoding state machine lI101_1[3:0] (in view: work.CTSE_PEREX_PCS_0s_26s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO231 : clock_gen.v(283) | Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0] Encoding state machine xmit_state[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 Encoding state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. @W:BN132 : rx_async.v(261) | Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine state[2:0] (in view: work.fifo_to_tpsram_bridge(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MO231 : fifo_to_tpsram_bridge.v(49) | Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[10:0] @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[25] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:FX107 : miv_rv32_subsys_merged.v(10047) | RAM u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX702 : miv_rv32_subsys_merged.v(10047) | Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)). @N:FX702 : miv_rv32_subsys_merged.v(10047) | Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] @N:MF135 : miv_rv32_subsys_merged.v(10047) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2]. @N:MF135 : miv_rv32_subsys_merged.v(10047) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[6:0] is 2 words by 7 bits. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[3]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[4]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[5]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[6]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[3]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[4]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[5]. @N:FX493 : | Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[6]. @N:MF135 : miv_rv32_subsys_merged.v(15839) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] is 2 words by 34 bits. @N:MF135 : miv_rv32_subsys_merged.v(15839) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] is 2 words by 41 bits. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10047) | Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(5705) | Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[0] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(5705) | Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[16] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances. @W:BN132 : miv_rv32_subsys_merged.v(15839) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_subsys_merged.v(15839) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MF135 : miv_rv32_hart_merged.v(18735) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] is 4 words by 1 bits. @N:MF135 : miv_rv32_hart_merged.v(18735) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[0] is 4 words by 1 bits. @N:MF135 : miv_rv32_hart_merged.v(18735) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] is 4 words by 32 bits. @N:MF135 : miv_rv32_hart_merged.v(18735) | RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] is 4 words by 16 bits. @N:BN362 : miv_rv32_hart_merged.v(18735) | Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_hart_merged.v(18735) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : miv_rv32_hart_merged.v(9798) | Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W:BN132 : miv_rv32_hart_merged.v(9414) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO231 : miv_rv32_hart_merged.v(11446) | Found counter in view:work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog) instance mul_div_cnt[5:0] @N:MF179 : miv_rv32_hart_merged.v(11165) | Found 32 by 32 bit equality operator ('==') un152_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog)) @N:FX403 : miv_rv32_hart_merged.v(6370) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] with specified coding style. Inferring block RAM. @W:FX107 : miv_rv32_hart_merged.v(6370) | RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : miv_rv32_hart_merged.v(6370) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] with specified coding style. Inferring block RAM. @W:FX107 : miv_rv32_hart_merged.v(6370) | RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MF179 : miv_rv32_hart_merged.v(4547) | Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog)) @N:MF179 : miv_rv32_hart_merged.v(4547) | Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog)) Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_subsys_merged.v(16135) | There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required. Encoding state machine debug_state[5:0] (in view: work.miv_rv32_debug_du(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_subsys_merged.v(15192) | There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required. @N:MO231 : miv_rv32_subsys_merged.v(15548) | Found counter in view:work.miv_rv32_debug_sba(verilog) instance counter[7:0] Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog)) original code -> new code 01 -> 00 10 -> 01 11 -> 10 Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_subsys_tcm_Z20(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) original code -> new code 001 -> 0000001 010 -> 0000010 011 -> 0000100 100 -> 0001000 101 -> 0010000 110 -> 0100000 111 -> 1000000 @N:MO231 : miv_rv32_subsys_merged.v(13076) | Found counter in view:work.miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820(verilog) instance mtime_count_out[63:0] Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : corecdr4_cntl_tip.v(117) | There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required. Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coredelaycode_tip.v(59) | There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required. @N:MO231 : coredelaycode_tip.v(59) | Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0] Starting factoring (Real Time elapsed 0h:00m:46s; CPU Time elapsed 0h:00m:43s; Memory used current: 344MB peak: 344MB) @N:BN362 : miv_rv32_hart_merged.v(8721) | Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances. @N:BN362 : corefifo_sync_scntr.v(463) | Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:01m:10s; CPU Time elapsed 0h:01m:06s; Memory used current: 445MB peak: 447MB) Available hyper_sources - for debug and ip models None Found NConnInternalConnection caching is on @N:BN362 : miv_rv32_hart_merged.v(9395) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_hart_merged.v(9775) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10391) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_subsys_merged.v(10391) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:01m:22s; CPU Time elapsed 0h:01m:19s; Memory used current: 412MB peak: 474MB) @W:BN132 : miv_rv32_hart_merged.v(5705) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting Early Timing Optimization (Real Time elapsed 0h:01m:28s; CPU Time elapsed 0h:01m:24s; Memory used current: 420MB peak: 474MB) Finished Early Timing Optimization (Real Time elapsed 0h:02m:47s; CPU Time elapsed 0h:02m:44s; Memory used current: 489MB peak: 489MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:02m:49s; CPU Time elapsed 0h:02m:46s; Memory used current: 489MB peak: 490MB) @N:BN362 : miv_rv32_subsys_merged.v(16013) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(286) | Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:02m:59s; CPU Time elapsed 0h:02m:56s; Memory used current: 491MB peak: 491MB) Finished technology mapping (Real Time elapsed 0h:03m:12s; CPU Time elapsed 0h:03m:09s; Memory used current: 515MB peak: 564MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:03m:11s -32.17ns 16216 / 7209 2 0h:03m:12s -32.17ns 15924 / 7209 3 0h:03m:13s -32.17ns 15924 / 7209 4 0h:03m:15s -32.17ns 15924 / 7209 5 0h:03m:21s -32.17ns 15928 / 7209 6 0h:03m:23s -32.17ns 15931 / 7209 7 0h:03m:23s -32.17ns 15931 / 7209 8 0h:03m:24s -32.17ns 15934 / 7209 9 0h:03m:25s -32.17ns 15936 / 7209 10 0h:03m:27s -32.17ns 15947 / 7209 11 0h:03m:28s -32.17ns 15948 / 7209 12 0h:03m:29s -32.17ns 15948 / 7209 13 0h:03m:32s -32.17ns 15948 / 7209 14 0h:03m:34s -32.17ns 15951 / 7209 @N:FP130 : | Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4374 @N:FP130 : | Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4375 @N:FP130 : | Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4376 @N:FP130 : | Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4377 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:03m:43s; CPU Time elapsed 0h:03m:39s; Memory used current: 522MB peak: 564MB) Finished restoring hierarchy (Real Time elapsed 0h:03m:44s; CPU Time elapsed 0h:03m:41s; Memory used current: 527MB peak: 564MB) Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:03m:46s; CPU Time elapsed 0h:03m:43s; Memory used current: 530MB peak: 564MB) Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:03m:46s; CPU Time elapsed 0h:03m:43s; Memory used current: 530MB peak: 564MB) Start Writing Netlists (Real Time elapsed 0h:03m:47s; CPU Time elapsed 0h:03m:44s; Memory used current: 364MB peak: 564MB) Writing Analyst data base E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:03m:51s; CPU Time elapsed 0h:03m:48s; Memory used current: 461MB peak: 564MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : synthesis.fdc(47) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(48) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(49) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(50) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(51) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(52) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(53) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(54) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW150 : | Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:03m:58s; CPU Time elapsed 0h:03m:55s; Memory used current: 450MB peak: 564MB) Finished Writing Netlists (Real Time elapsed 0h:03m:58s; CPU Time elapsed 0h:03m:55s; Memory used current: 450MB peak: 564MB) Start final timing analysis (Real Time elapsed 0h:04m:00s; CPU Time elapsed 0h:03m:56s; Memory used current: 436MB peak: 564MB) @W:MT246 : pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v(40) | Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock REF_CLK_0 with period 20.00ns @N:MT615 : | Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns @N:MT615 : | Found clock REFCLK_P with period 8.00ns @N:MT615 : | Found clock TCK with period 100.00ns @N:MT615 : | Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns @N:MT615 : | Found clock PHY_MDC_CLOCK with period 350.00ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns @W:MT420 : | Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK. @W:MT420 : | Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK_0. ##### START OF TIMING REPORT #####[ # Timing report written on Fri Apr 17 08:36:01 2026 # Top view: top Requested Frequency: 2.9 MHz Wire load mode: top Paths requested: 5 Constraint File(s): E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. Performance Summary ******************* Worst slack in design: -32.246 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 13.4 MHz 10.000 74.491 -32.246 inferred Inferred_clkgroup_0_3 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 55.1 MHz 12.500 18.138 -5.638 generated (from REF_CLK_0) (multiple) PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 116.7 MHz 8.000 8.569 -0.228 declared SGMII_CDR_0_0_CLK_OUT_GRP PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0_1 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT0_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT1_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT2_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT3_GRP PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 225.1 MHz 8.000 4.443 3.557 generated (from REFCLK_P) Y_DIV_GRP PHY_MDC_CLOCK 2.9 MHz NA 350.000 NA NA generated (from REF_CLK_0) default_clkgroup REFCLK_P 125.0 MHz NA 8.000 NA NA declared default_clkgroup REF_CLK_0 50.0 MHz NA 20.000 NA NA declared default_clkgroup TCK 10.0 MHz NA 100.000 NA NA declared JTAG_Async_2 System 100.0 MHz 26.5 MHz 10.000 37.793 -27.793 system system_clkgroup ======================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 11.225 | No paths - | No paths - | No paths - System COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 -27.793 | No paths - | 10.000 -26.963 | No paths - REF_CLK_0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 1.643 | 8.000 3.249 | 3.200 -0.228 | 4.800 3.427 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 -5.638 | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | Diff grp - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 3.557 | No paths - | No paths - | No paths - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock System | 10.000 8.633 | No paths - | No paths - | No paths - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | Diff grp - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock | 10.000 5.295 | 10.000 6.546 | 5.000 1.962 | 5.000 -32.246 ==================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------- PHY_MDIO PHY_MDC_CLOCK (rising) 20.000 NA NA NA RESET_N REF_CLK_0 (rising) 20.000 NA NA NA ===================================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- PHY_MDIO PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 (rising) 10.000(PHY_MDC_CLOCK rising) 4.556 NA NA =============================================================================================================================== ==================================== Detailed Report for Clock: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q tmsenb 0.218 -32.246 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.endofshift COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q endofshift 0.218 -32.148 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[2] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[2] 0.218 1.628 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[1] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[1] 0.218 1.669 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[0] 0.201 1.897 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[3] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[3] 0.218 1.938 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[0] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[0] 0.218 1.962 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[4] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q irReg[4] 0.201 1.995 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[3] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[3] 0.218 2.032 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[1] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE Q state[1] 0.218 2.048 ============================================================================================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_5 5.000 -32.246 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_3 5.000 -32.246 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0 5.000 -32.201 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_0 5.000 -32.201 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_2 5.000 -32.201 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_4 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[7] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[7] 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[9] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[9] 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_7 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[14] COREJTAGDEBUG_Z5|iUDRCK_inferred_clock SLE D currTapState_ns[14] 5.000 -32.181 ==================================================================================================================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.246 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -32.246 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] / D The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 Y Out 0.212 37.128 f - gen_N_3_mux_0_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] SLE D In - 37.246 f - ========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.246 is 4.070(10.9%) logic and 33.176(89.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.246 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -32.246 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] / D The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 Y Out 0.212 37.128 f - gen_N_3_mux_0_3 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] SLE D In - 37.246 f - =========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.246 is 4.070(10.9%) logic and 33.176(89.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.201 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.201 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.168 37.083 r - gen_N_3_mux_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.201 r - ========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.201 is 4.026(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.201 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.201 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] / D The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 Y Out 0.168 37.083 r - gen_N_3_mux_0_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] SLE D In - 37.201 r - ========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.201 is 4.026(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.201 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.201 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] / D The start point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 Y Out 0.168 37.083 r - gen_N_3_mux_0_2 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] SLE D In - 37.201 r - =========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.201 is 4.026(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q trace_priv_i 0.218 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[0] 2.241 -5.413 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[1] 2.241 -5.394 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R11C0_B_DOUT[0] 2.241 -5.382 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R14C0_B_DOUT[0] 2.241 -5.382 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R11C0_B_DOUT[1] 2.241 -5.362 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R14C0_B_DOUT[1] 2.241 -5.362 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R10C0_B_DOUT[0] 2.241 -5.351 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R10C0_B_DOUT[1] 2.241 -5.331 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_lsu_0.buff_rd_ptr[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE Q buff_rd_ptr[0] 0.218 -5.313 ================================================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[1] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[4] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[5] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[6] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[7] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[8] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[9] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_2_1_RNISIFQHS3 12.373 -5.638 ================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.500 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.373 - Propagation time: 18.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -5.638 Number of logic level(s): 22 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] / EN The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r - trace_priv_i Net - - 1.255 - 242 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f - per_trigger_debug[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f - trigger_debug_enter_taken Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 C In - 2.866 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 Y Out 0.145 3.012 f - debug_enter_retr Net - - 0.965 - 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 C In - 3.977 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 Y Out 0.145 4.122 f - interrupt_pending_2 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 D In - 4.246 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 Y Out 0.192 4.438 f - interrupt_taken_sw Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 C In - 5.017 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 Y Out 0.145 5.163 f - machine_implicit_wr_mtval_tval_wr_en Net - - 1.020 - 89 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 C In - 6.183 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 Y Out 0.145 6.329 f - exu_alu_operand0_valid Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 D In - 6.892 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 Y Out 0.192 7.084 f - start_slow_mul Net - - 0.888 - 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 A In - 7.971 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 Y Out 0.048 8.019 f - un1_alu_op_sel_int Net - - 0.883 - 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 C In - 8.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 Y Out 0.130 9.033 r - exu_alu_result192_1 Net - - 0.650 - 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 C In - 9.682 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 Y Out 0.132 9.814 f - un5_m1_e_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 B In - 9.932 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 Y Out 0.077 10.010 f - un5_N_4_0_i Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 D In - 10.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 Y Out 0.232 11.133 r - apb_i_req_addr_net[16] Net - - 0.623 - 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 D In - 11.757 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 Y Out 0.212 11.969 f - cpu_i_req_is_tcm0_4_2 Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 C In - 12.532 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 Y Out 0.145 12.677 f - cpu_m8_0_a3_0_3 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 C In - 13.385 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 Y Out 0.130 13.515 r - lsu_op_complete_ex_out Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 D In - 14.152 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 Y Out 0.212 14.364 f - lsu_op_complete_ex_s_0_RNI1TBI281 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 D In - 14.911 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 Y Out 0.232 15.143 r - instr_m3_e_N_5L8_1_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 C In - 15.261 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 Y Out 0.132 15.393 f - gpr_rd_rs3_complete_ex_0_RNICHBA5T Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 D In - 15.511 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 Y Out 0.232 15.743 r - instr_accepted_ex Net - - 1.125 - 150 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 A In - 16.868 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 Y Out 0.051 16.918 r - instr_accepted_ex_2_1_RNIEDMV8U3 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 A In - 17.042 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 Y Out 0.051 17.093 r - instr_accepted_ex_2_1_RNISIFQHS3 Net - - 0.918 - 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] SLE EN In - 18.012 r - ========================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 18.138 is 3.536(19.5%) logic and 14.602(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 12.500 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.373 - Propagation time: 18.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -5.638 Number of logic level(s): 22 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_mem_error_ex / EN The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r - trace_priv_i Net - - 1.255 - 242 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f - per_trigger_debug[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f - trigger_debug_enter_taken Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 C In - 2.866 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 Y Out 0.145 3.012 f - debug_enter_retr Net - - 0.965 - 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 C In - 3.977 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 Y Out 0.145 4.122 f - interrupt_pending_2 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 D In - 4.246 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 Y Out 0.192 4.438 f - interrupt_taken_sw Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 C In - 5.017 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 Y Out 0.145 5.163 f - machine_implicit_wr_mtval_tval_wr_en Net - - 1.020 - 89 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 C In - 6.183 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 Y Out 0.145 6.329 f - exu_alu_operand0_valid Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 D In - 6.892 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 Y Out 0.192 7.084 f - start_slow_mul Net - - 0.888 - 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 A In - 7.971 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 Y Out 0.048 8.019 f - un1_alu_op_sel_int Net - - 0.883 - 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 C In - 8.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 Y Out 0.130 9.033 r - exu_alu_result192_1 Net - - 0.650 - 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 C In - 9.682 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 Y Out 0.132 9.814 f - un5_m1_e_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 B In - 9.932 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 Y Out 0.077 10.010 f - un5_N_4_0_i Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 D In - 10.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 Y Out 0.232 11.133 r - apb_i_req_addr_net[16] Net - - 0.623 - 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 D In - 11.757 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 Y Out 0.212 11.969 f - cpu_i_req_is_tcm0_4_2 Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 C In - 12.532 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 Y Out 0.145 12.677 f - cpu_m8_0_a3_0_3 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 C In - 13.385 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 Y Out 0.130 13.515 r - lsu_op_complete_ex_out Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 D In - 14.152 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 Y Out 0.212 14.364 f - lsu_op_complete_ex_s_0_RNI1TBI281 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 D In - 14.911 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 Y Out 0.232 15.143 r - instr_m3_e_N_5L8_1_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 C In - 15.261 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 Y Out 0.132 15.393 f - gpr_rd_rs3_complete_ex_0_RNICHBA5T Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 D In - 15.511 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 Y Out 0.232 15.743 r - instr_accepted_ex Net - - 1.125 - 150 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 A In - 16.868 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 Y Out 0.051 16.918 r - instr_accepted_ex_2_1_RNIEDMV8U3 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 A In - 17.042 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 Y Out 0.051 17.093 r - instr_accepted_ex_2_1_RNISIFQHS3 Net - - 0.918 - 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_mem_error_ex SLE EN In - 18.012 r - ========================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 18.138 is 3.536(19.5%) logic and 14.602(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 12.500 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.373 - Propagation time: 18.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -5.638 Number of logic level(s): 22 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_misalign_error_ex / EN The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r - trace_priv_i Net - - 1.255 - 242 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f - per_trigger_debug[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f - trigger_debug_enter_taken Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 C In - 2.866 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 Y Out 0.145 3.012 f - debug_enter_retr Net - - 0.965 - 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 C In - 3.977 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 Y Out 0.145 4.122 f - interrupt_pending_2 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 D In - 4.246 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 Y Out 0.192 4.438 f - interrupt_taken_sw Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 C In - 5.017 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 Y Out 0.145 5.163 f - machine_implicit_wr_mtval_tval_wr_en Net - - 1.020 - 89 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 C In - 6.183 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 Y Out 0.145 6.329 f - exu_alu_operand0_valid Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 D In - 6.892 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 Y Out 0.192 7.084 f - start_slow_mul Net - - 0.888 - 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 A In - 7.971 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 Y Out 0.048 8.019 f - un1_alu_op_sel_int Net - - 0.883 - 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 C In - 8.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 Y Out 0.130 9.033 r - exu_alu_result192_1 Net - - 0.650 - 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 C In - 9.682 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 Y Out 0.132 9.814 f - un5_m1_e_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 B In - 9.932 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 Y Out 0.077 10.010 f - un5_N_4_0_i Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 D In - 10.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 Y Out 0.232 11.133 r - apb_i_req_addr_net[16] Net - - 0.623 - 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 D In - 11.757 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 Y Out 0.212 11.969 f - cpu_i_req_is_tcm0_4_2 Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 C In - 12.532 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 Y Out 0.145 12.677 f - cpu_m8_0_a3_0_3 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 C In - 13.385 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 Y Out 0.130 13.515 r - lsu_op_complete_ex_out Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 D In - 14.152 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 Y Out 0.212 14.364 f - lsu_op_complete_ex_s_0_RNI1TBI281 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 D In - 14.911 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 Y Out 0.232 15.143 r - instr_m3_e_N_5L8_1_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 C In - 15.261 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 Y Out 0.132 15.393 f - gpr_rd_rs3_complete_ex_0_RNICHBA5T Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 D In - 15.511 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 Y Out 0.232 15.743 r - instr_accepted_ex Net - - 1.125 - 150 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 A In - 16.868 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 Y Out 0.051 16.918 r - instr_accepted_ex_2_1_RNIEDMV8U3 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 A In - 17.042 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 Y Out 0.051 17.093 r - instr_accepted_ex_2_1_RNISIFQHS3 Net - - 0.918 - 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_i_access_misalign_error_ex SLE EN In - 18.012 r - ========================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 18.138 is 3.536(19.5%) logic and 14.602(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 12.500 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.373 - Propagation time: 18.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -5.638 Number of logic level(s): 22 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] / EN The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r - trace_priv_i Net - - 1.255 - 242 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f - per_trigger_debug[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f - trigger_debug_enter_taken Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 C In - 2.866 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 Y Out 0.145 3.012 f - debug_enter_retr Net - - 0.965 - 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 C In - 3.977 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 Y Out 0.145 4.122 f - interrupt_pending_2 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 D In - 4.246 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 Y Out 0.192 4.438 f - interrupt_taken_sw Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 C In - 5.017 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 Y Out 0.145 5.163 f - machine_implicit_wr_mtval_tval_wr_en Net - - 1.020 - 89 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 C In - 6.183 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 Y Out 0.145 6.329 f - exu_alu_operand0_valid Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 D In - 6.892 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 Y Out 0.192 7.084 f - start_slow_mul Net - - 0.888 - 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 A In - 7.971 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 Y Out 0.048 8.019 f - un1_alu_op_sel_int Net - - 0.883 - 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 C In - 8.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 Y Out 0.130 9.033 r - exu_alu_result192_1 Net - - 0.650 - 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 C In - 9.682 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 Y Out 0.132 9.814 f - un5_m1_e_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 B In - 9.932 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 Y Out 0.077 10.010 f - un5_N_4_0_i Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 D In - 10.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 Y Out 0.232 11.133 r - apb_i_req_addr_net[16] Net - - 0.623 - 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 D In - 11.757 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 Y Out 0.212 11.969 f - cpu_i_req_is_tcm0_4_2 Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 C In - 12.532 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 Y Out 0.145 12.677 f - cpu_m8_0_a3_0_3 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 C In - 13.385 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 Y Out 0.130 13.515 r - lsu_op_complete_ex_out Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 D In - 14.152 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 Y Out 0.212 14.364 f - lsu_op_complete_ex_s_0_RNI1TBI281 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 D In - 14.911 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 Y Out 0.232 15.143 r - instr_m3_e_N_5L8_1_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 C In - 15.261 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 Y Out 0.132 15.393 f - gpr_rd_rs3_complete_ex_0_RNICHBA5T Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 D In - 15.511 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 Y Out 0.232 15.743 r - instr_accepted_ex Net - - 1.125 - 150 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 A In - 16.868 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 Y Out 0.051 16.918 r - instr_accepted_ex_2_1_RNIEDMV8U3 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 A In - 17.042 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 Y Out 0.051 17.093 r - instr_accepted_ex_2_1_RNISIFQHS3 Net - - 0.918 - 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] SLE EN In - 18.012 r - ========================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 18.138 is 3.536(19.5%) logic and 14.602(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 12.500 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.373 - Propagation time: 18.012 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -5.638 Number of logic level(s): 22 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] / EN The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.debug_mode SLE Q Out 0.218 0.218 r - trace_priv_i Net - - 1.255 - 242 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 C In - 1.473 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2\.per_trigger_debug[0] CFG3 Y Out 0.132 1.605 f - per_trigger_debug[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 B In - 2.152 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.trigger_debug_enter_taken CFG3 Y Out 0.077 2.230 f - trigger_debug_enter_taken Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 C In - 2.866 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.debug_mode_enter CFG4 Y Out 0.145 3.012 f - debug_enter_retr Net - - 0.965 - 64 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 C In - 3.977 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_pending_2 CFG4 Y Out 0.145 4.122 f - interrupt_pending_2 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 D In - 4.246 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_miv_rv32_priv_irq_0.u_miv_rv32_irq_reg_sw.interrupt_taken_0 CFG4 Y Out 0.192 4.438 f - interrupt_taken_sw Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 C In - 5.017 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug\.u_csr_gpr_state_reg_dcsr_step.machine_implicit_wr_mtval_tval_wr_en CFG4 Y Out 0.145 5.163 f - machine_implicit_wr_mtval_tval_wr_en Net - - 1.020 - 89 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 C In - 6.183 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u CFG4 Y Out 0.145 6.329 f - exu_alu_operand0_valid Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 D In - 6.892 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_operand0_valid_u_RNIA72AVC CFG4 Y Out 0.192 7.084 f - start_slow_mul Net - - 0.888 - 41 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 A In - 7.971 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.mul_div_cnt_RNIBKIM4D[5] CFG2 Y Out 0.048 8.019 f - un1_alu_op_sel_int Net - - 0.883 - 40 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 C In - 8.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_alu_result192_1 CFG3 Y Out 0.130 9.033 r - exu_alu_result192_1 Net - - 0.650 - 10 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 C In - 9.682 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_m1_e_1 CFG4 Y Out 0.132 9.814 f - un5_m1_e_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 B In - 9.932 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 CFG4 Y Out 0.077 10.010 f - un5_N_4_0_i Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 D In - 10.902 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 CFG4 Y Out 0.232 11.133 r - apb_i_req_addr_net[16] Net - - 0.623 - 8 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 D In - 11.757 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_4_2 CFG4 Y Out 0.212 11.969 f - cpu_i_req_is_tcm0_4_2 Net - - 0.563 - 4 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 C In - 12.532 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.cpu_i_req_is_tcm0_0 CFG3 Y Out 0.145 12.677 f - cpu_m8_0_a3_0_3 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 C In - 13.385 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0 CFG4 Y Out 0.130 13.515 r - lsu_op_complete_ex_out Net - - 0.637 - 9 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 D In - 14.152 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI1TBI281 CFG4 Y Out 0.212 14.364 f - lsu_op_complete_ex_s_0_RNI1TBI281 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 D In - 14.911 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.lsu_op_complete_ex_s_0_RNI63HIUN CFG4 Y Out 0.232 15.143 r - instr_m3_e_N_5L8_1_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 C In - 15.261 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNICHBA5T CFG4 Y Out 0.132 15.393 f - gpr_rd_rs3_complete_ex_0_RNICHBA5T Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 D In - 15.511 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 CFG4 Y Out 0.232 15.743 r - instr_accepted_ex Net - - 1.125 - 150 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 A In - 16.868 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNIEDMV8U3 CFG2 Y Out 0.051 16.918 r - instr_accepted_ex_2_1_RNIEDMV8U3 Net - - 0.124 - 2 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 A In - 17.042 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_idecode_0.instr_accepted_ex_2_1_RNISIFQHS3 CFG2 Y Out 0.051 17.093 r - instr_accepted_ex_2_1_RNISIFQHS3 Net - - 0.918 - 34 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] SLE EN In - 18.012 r - ========================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 18.138 is 3.536(19.5%) logic and 14.602(80.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q rst_n[0] 0.218 -0.228 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q IOOi1 0.218 1.643 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.SELA_LANE[10] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q SELA_LANE_net_0[10] 0.218 1.907 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[0] 0.201 1.966 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[2] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[2] 0.201 2.007 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[10] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[10] 0.201 2.007 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[12] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[12] 0.201 2.010 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[11] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[11] 0.201 2.129 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[3] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[3] 0.218 2.216 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.Oiio1[14] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q Oiio1[14] 0.218 2.254 ================================================================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn CLR_FLAGS_N_arst_i 3.200 -0.228 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE ALn CLR_FLAGS_N_arst_i 3.200 -0.228 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[4] 8.000 1.643 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[5] 8.000 1.643 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D lliO1_0_iv_i[7] 8.000 1.643 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.O00o1[11] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D Il0o1[5] 8.000 1.690 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.O00o1[9] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D O00o1_N_3_mux_i_0 8.000 1.751 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.O00o1[10] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D Il0o1[4] 8.000 1.758 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[20] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D Ol0o1[4] 8.000 1.777 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[21] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D Ol0o1[5] 8.000 1.777 ================================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.200 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.200 - Propagation time: 3.428 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.228 Number of logic level(s): 2 Starting point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] / Q Ending point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] / ALn The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [falling] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] SLE Q Out 0.218 0.218 r - rst_n[0] Net - - 1.100 - 54 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 B In - 1.318 r - PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 Y Out 0.088 1.406 f - CLR_FLAGS_N Net - - 0.974 - 3 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 A In - 2.380 f - PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 Y Out 0.047 2.427 r - CLR_FLAGS_N_arst_i Net - - 1.001 - 4 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[0] SLE ALn In - 3.428 r - ================================================================================================================== Total path delay (propagation time + setup) of 3.428 is 0.353(10.3%) logic and 3.075(89.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 3.200 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.200 - Propagation time: 3.428 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.228 Number of logic level(s): 2 Starting point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] / Q Ending point: PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] / ALn The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [falling] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------ PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.rst_n[0] SLE Q Out 0.218 0.218 r - rst_n[0] Net - - 1.100 - 54 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 B In - 1.318 r - PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N CFG2 Y Out 0.088 1.406 f - CLR_FLAGS_N Net - - 0.974 - 3 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 A In - 2.380 f - PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.CLR_FLAGS_N_RNIOF22 CFG1 Y Out 0.047 2.427 r - CLR_FLAGS_N_arst_i Net - - 1.001 - 4 PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[0] SLE ALn In - 3.428 r - ================================================================================================================== Total path delay (propagation time + setup) of 3.428 is 0.353(10.3%) logic and 3.075(89.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 8.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.000 - Propagation time: 6.357 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.643 Number of logic level(s): 11 Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] / D The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r - IOOi1 Net - - 0.943 - 56 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 B In - 1.161 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 Y Out 0.088 1.248 f - OlI11[0] Net - - 0.878 - 39 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 C In - 2.127 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 Y Out 0.145 2.272 f - m2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 D In - 2.390 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 Y Out 0.232 2.622 r - i5_mux_0_0 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 A In - 2.740 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 Y Out 0.046 2.786 f - OO0Io Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 C In - 2.904 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 Y Out 0.145 3.050 f - lI0o1_1[1] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 D In - 3.168 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 Y Out 0.192 3.360 f - lI0o1[1] Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 C In - 3.969 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 Y Out 0.148 4.116 f - un12_lolIo Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 D In - 4.234 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.232 4.466 r - lolIo_2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 C In - 4.584 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.148 4.732 r - lolIo Net - - 0.674 - 12 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.406 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.046 5.452 f - un1_N_3_mux_1_i Net - - 0.594 - 6 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI4KONQ4 CFG4 D In - 6.047 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI4KONQ4 CFG4 Y Out 0.192 6.239 f - lliO1_0_iv_i[4] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[28] SLE D In - 6.357 f - ========================================================================================================================================================================================================== Total path delay (propagation time + setup) of 6.357 is 1.832(28.8%) logic and 4.525(71.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 8.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.000 - Propagation time: 6.357 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.643 Number of logic level(s): 11 Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] / D The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r - IOOi1 Net - - 0.943 - 56 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 B In - 1.161 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 Y Out 0.088 1.248 f - OlI11[0] Net - - 0.878 - 39 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 C In - 2.127 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 Y Out 0.145 2.272 f - m2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 D In - 2.390 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 Y Out 0.232 2.622 r - i5_mux_0_0 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 A In - 2.740 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 Y Out 0.046 2.786 f - OO0Io Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 C In - 2.904 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 Y Out 0.145 3.050 f - lI0o1_1[1] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 D In - 3.168 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 Y Out 0.192 3.360 f - lI0o1[1] Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 C In - 3.969 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 Y Out 0.148 4.116 f - un12_lolIo Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 D In - 4.234 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.232 4.466 r - lolIo_2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 C In - 4.584 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.148 4.732 r - lolIo Net - - 0.674 - 12 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.406 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.046 5.452 f - un1_N_3_mux_1_i Net - - 0.594 - 6 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU_0 CFG4 D In - 6.047 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU_0 CFG4 Y Out 0.192 6.239 f - lliO1_0_iv_i[7] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[31] SLE D In - 6.357 f - ========================================================================================================================================================================================================== Total path delay (propagation time + setup) of 6.357 is 1.832(28.8%) logic and 4.525(71.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 8.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.000 - Propagation time: 6.357 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.643 Number of logic level(s): 11 Starting point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] / D The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.IOOi1 SLE Q Out 0.218 0.218 r - IOOi1 Net - - 0.943 - 56 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 B In - 1.161 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PMA_1.OlI11[0] CFG3 Y Out 0.088 1.248 f - OlI11[0] Net - - 0.878 - 39 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 C In - 2.127 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m2 CFG3 Y Out 0.145 2.272 f - m2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 D In - 2.390 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.m9 CFG4 Y Out 0.232 2.622 r - i5_mux_0_0 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 A In - 2.740 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io_2_0_0_.i4_mux_i CFG3 Y Out 0.046 2.786 f - OO0Io Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 C In - 2.904 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1_1[1] CFG4 Y Out 0.145 3.050 f - lI0o1_1[1] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 D In - 3.168 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.lI0o1[1] CFG4 Y Out 0.192 3.360 f - lI0o1[1] Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 C In - 3.969 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.un12_lolIo CFG4 Y Out 0.148 4.116 f - un12_lolIo Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 D In - 4.234 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_2 CFG4 Y Out 0.232 4.466 r - lolIo_2 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 C In - 4.584 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo CFG4 Y Out 0.148 4.732 r - lolIo Net - - 0.674 - 12 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 A In - 5.406 r - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNISGOVC CFG3 Y Out 0.046 5.452 f - un1_N_3_mux_1_i Net - - 0.594 - 6 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU CFG4 D In - 6.047 f - CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.lolIo_RNI8EFAU CFG4 Y Out 0.192 6.239 f - lliO1_0_iv_i[5] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.il0o1[29] SLE D In - 6.357 f - ========================================================================================================================================================================================================== Total path delay (propagation time + setup) of 6.357 is 1.832(28.8%) logic and 4.525(71.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[0] 0.218 3.557 CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXTFIF_SYS_1.I1ol1[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q I1ol1[0] 0.218 3.970 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[1] 0.218 3.988 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[2] 0.218 3.996 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[3] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[3] 0.218 4.004 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[4] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[4] 0.218 4.012 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[5] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[5] 0.218 4.020 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[6] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[6] 0.218 4.028 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.o11Io\.il1Io_1[7] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Ol1Io10_a_4 0.218 4.029 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[7] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q Il1Io[7] 0.218 4.036 ========================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[3] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[4] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[5] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[6] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[7] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[8] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[9] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE EN Il1Ioe 7.873 3.557 ======================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: 7.873 - Propagation time: 4.316 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 3.557 Number of logic level(s): 27 Starting point: CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] / EN The start point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] SLE Q Out 0.218 0.218 r - Il1Io[0] Net - - 0.547 - 3 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_0 ARI1 B In - 0.765 r - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_0 ARI1 FCO Out 0.328 1.093 f - Ol1Io10_a_4_cry_0 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_1 ARI1 FCI In - 1.093 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_1 ARI1 FCO Out 0.008 1.101 f - Ol1Io10_a_4_cry_1 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_2 ARI1 FCI In - 1.101 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_2 ARI1 FCO Out 0.008 1.109 f - Ol1Io10_a_4_cry_2 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_3 ARI1 FCI In - 1.109 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_3 ARI1 FCO Out 0.008 1.117 f - Ol1Io10_a_4_cry_3 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_4 ARI1 FCI In - 1.117 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_4 ARI1 FCO Out 0.008 1.125 f - Ol1Io10_a_4_cry_4 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_5 ARI1 FCI In - 1.125 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_5 ARI1 FCO Out 0.008 1.133 f - Ol1Io10_a_4_cry_5 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_6 ARI1 FCI In - 1.133 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_6 ARI1 FCO Out 0.008 1.141 f - Ol1Io10_a_4_cry_6 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_7 ARI1 FCI In - 1.141 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_7 ARI1 FCO Out 0.008 1.149 f - Ol1Io10_a_4_cry_7 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_8 ARI1 FCI In - 1.149 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_8 ARI1 FCO Out 0.008 1.157 f - Ol1Io10_a_4_cry_8 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_9 ARI1 FCI In - 1.157 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_9 ARI1 FCO Out 0.008 1.165 f - Ol1Io10_a_4_cry_9 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10 ARI1 FCI In - 1.165 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10 ARI1 FCO Out 0.008 1.173 f - Ol1Io10_a_4_cry_10 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_11 ARI1 FCI In - 1.173 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_11 ARI1 FCO Out 0.008 1.181 f - Ol1Io10_a_4_cry_11 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_12 ARI1 FCI In - 1.181 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_12 ARI1 FCO Out 0.008 1.189 f - Ol1Io10_a_4_cry_12 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_13 ARI1 FCI In - 1.189 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_13 ARI1 FCO Out 0.008 1.197 f - Ol1Io10_a_4_cry_13 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_14 ARI1 FCI In - 1.197 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_14 ARI1 FCO Out 0.008 1.205 f - Ol1Io10_a_4_cry_14 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_15 ARI1 FCI In - 1.205 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_15 ARI1 FCO Out 0.008 1.213 f - Ol1Io10_a_4_cry_15 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_16 ARI1 FCI In - 1.213 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_16 ARI1 FCO Out 0.008 1.221 f - Ol1Io10_a_4_cry_16 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_17 ARI1 FCI In - 1.221 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_17 ARI1 FCO Out 0.008 1.229 f - Ol1Io10_a_4_cry_17 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_18 ARI1 FCI In - 1.229 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_18 ARI1 FCO Out 0.008 1.237 f - Ol1Io10_a_4_cry_18 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19 ARI1 FCI In - 1.237 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19 ARI1 FCO Out 0.008 1.245 f - Ol1Io10_a_4_cry_19 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_20 ARI1 FCI In - 1.245 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_20 ARI1 FCO Out 0.008 1.253 f - Ol1Io10_a_4_cry_20 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_21 ARI1 FCI In - 1.253 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_21 ARI1 FCO Out 0.008 1.261 f - Ol1Io10_a_4_cry_21 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_22 ARI1 FCI In - 1.261 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_22 ARI1 S Out 0.300 1.561 r - Ol1Io10_22 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19_RNIR5LRM CFG4 D In - 1.679 r - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_19_RNIR5LRM CFG4 Y Out 0.168 1.847 r - Ol1Io10_NE_19 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10_RNI818323 CFG4 D In - 1.965 r - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_10_RNI818323 CFG4 Y Out 0.168 2.132 r - Ol1Io10_NE_25 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_23_RNI7FA6M5 CFG4 D In - 2.250 r - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io10_a_4_cry_23_RNI7FA6M5 CFG4 Y Out 0.212 2.462 f - Ol1Io10_NE Net - - 0.817 - 42 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io6_10_RNIEPCN26 CFG4 D In - 3.279 f - CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Ol1Io6_10_RNIEPCN26 CFG4 Y Out 0.232 3.511 r - Il1Ioe Net - - 0.805 - 27 CORETSE_0_inst_0.CORETSE_0_0.i\.OI.genblk1\.Il1Io[0] SLE EN In - 4.316 r - ======================================================================================================================================= Total path delay (propagation time + setup) of 4.443 is 1.920(43.2%) logic and 2.523(56.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UTDI UTDIInt 0.000 -27.793 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG URSTB iURSTB 0.000 -26.963 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[0] UIREGInt[0] 0.000 5.570 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[2] UIREGInt[2] 0.000 5.617 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[3] UIREGInt[3] 0.000 5.628 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[1] UIREGInt[1] 0.000 5.670 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[4] UIREGInt[4] 0.000 5.685 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[6] UIREGInt[6] 0.000 5.715 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[7] UIREGInt[7] 0.000 5.938 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UIREG[5] UIREGInt[5] 0.000 5.979 ======================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] System SLE D gen_N_3_mux_0_5 10.000 -27.793 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] System SLE D gen_N_3_mux_0_3 10.000 -27.793 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] System SLE D gen_N_3_mux_0 10.000 -27.748 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] System SLE D gen_N_3_mux_0_0 10.000 -27.748 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] System SLE D gen_N_3_mux_0_2 10.000 -27.748 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] System SLE D gen_N_3_mux_0_4 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[7] System SLE D currTapState_ns[7] 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[9] System SLE D currTapState_ns[9] 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] System SLE D gen_N_3_mux_0_7 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[14] System SLE D currTapState_ns[14] 10.000 -27.728 ======================================================================================================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.792 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.792 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 6 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[6] CFG4 Y Out 0.212 37.675 f - gen_N_3_mux_0_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] SLE D In - 37.792 f - =========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.792 is 3.787(10.0%) logic and 34.006(90.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.792 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.792 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 6 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[13] CFG4 Y Out 0.212 37.675 f - gen_N_3_mux_0_3 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] SLE D In - 37.792 f - ============================================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 37.792 is 3.787(10.0%) logic and 34.006(90.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.748 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.748 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 6 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.168 37.630 r - gen_N_3_mux_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.748 r - =========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.748 is 3.742(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.748 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.748 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 6 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[8] CFG4 Y Out 0.168 37.630 r - gen_N_3_mux_0_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] SLE D In - 37.748 r - =========================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.748 is 3.742(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.748 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.748 Number of logic level(s): 36 Starting point: COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z5|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 6 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - COREJTAGDEBUG_C0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[15] CFG4 Y Out 0.168 37.630 r - gen_N_3_mux_0_2 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15] SLE D In - 37.748 r - ============================================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 37.748 is 3.742(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(25) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(26) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(27) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(32) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(33) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(34) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(35) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(36) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(37) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(38) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(39) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(40) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(41) | Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(42) | Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(45) | Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:04m:01s; CPU Time elapsed 0h:03m:57s; Memory used current: 444MB peak: 564MB) Finished timing report (Real Time elapsed 0h:04m:01s; CPU Time elapsed 0h:03m:58s; Memory used current: 444MB peak: 564MB) --------------------------------------- Resource Usage Report for top Mapping to part: mpf300tfcg1152-1 Cell usage: AND2 1 use BANKEN 1 use BUFD 102 uses CLKINT 6 uses DLL 1 use HS_IO_CLK 4 uses ICB_CLKDIV 1 use INIT 1 use INV 4 uses IOD 5 uses LANECTRL 2 uses OR2 32 uses OR4 1344 uses PLL 2 uses RCLKINT 1 use UJTAG 1 use CFG1 109 uses CFG2 1853 uses CFG3 3347 uses CFG4 8280 uses Carry cells: ARI1 2037 uses - used for arithmetic functions ARI1 226 uses - used for Wide-Mux implementation Total ARI1 2263 uses Sequential Cells: SLE 7208 uses DSP Blocks: 0 of 924 (0%) I/O ports: 58 I/O primitives: 50 BIBUF 1 use INBUF 4 uses INBUF_DIFF 2 uses OUTBUF 42 uses OUTBUF_DIFF 1 use Global Clock Buffers: 7 RAM/ROM usage summary Total Block RAMs (RAM1K20) : 36 of 952 (3%) Total Block RAMs (RAM64x12) : 11 of 2772 (0%) Total LUTs: 15852 Extra resources required for RAM and MACC_PA interface logic during P&R: RAM64X12 Interface Logic : SLEs = 132; LUTs = 132; RAM1K20 Interface Logic : SLEs = 1296; LUTs = 1296; MACC_PA Interface Logic : SLEs = 0; LUTs = 0; MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 7208 + 132 + 1296 + 0 = 8636; Total number of LUTs after P&R: 15852 + 132 + 1296 + 0 = 17280; Mapper successful! At Mapper Exit (Real Time elapsed 0h:04m:01s; CPU Time elapsed 0h:03m:58s; Memory used current: 209MB peak: 564MB) Process took 0h:04m:02s realtime, 0h:03m:59s cputime # Fri Apr 17 08:36:02 2026 ###########################################################]