##### START OF RAM REPORT #####
##### LSRAM REPORT #####
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH(A/B) LOW-POWER_MODE ECC A_DOUT_PIPE_REG(EN/ARST/SRST) B_DOUT_PIPE_REG(EN/ARST/SRST) WRITE_MODE(A/B) COMMENTS
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io[35:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_0 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_1 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_2 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_3 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_4 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_5 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_6 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 1(1/1/1) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io[39:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_0 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_1 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_2 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_3 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 NA NA COREFIFO_C0_0.COREFIFO_C0_0.genblk22\.UI_ram_wrapper_1.L3_syncnonpipe.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
=====================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### URAM REPORT #####
INSTANTIATED RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE MAPPED_INSTANCE DEPTH_X_WIDTH LOW-POWER_MODE ECC R_ADDR_REG(EN/ARST/SRST) R_DATA_PIPE_REG(EN/ARST/SRST) COMMENTS
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NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_mem_xf_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_0 64X12 0 0 0(0/0/0) 1(0/0/1) RAM instance meets the required threshold for mapping using URAM.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_1 64X12 0 0 0(0/0/0) 1(0/0/1)
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_xf_1_mem_xf_1_0_2 64X12 0 0 0(0/0/0) 1(0/0/1)
NO CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
NO CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[15:0] RAM DEFAULT CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[16] RAM CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_1 64X12 0 0 0(0/0/0) 0(0/0/0)
NO MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[6:0] RAM DEFAULT MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data_gen_buff_loop\[0\]\.buff_data_0_0 64X12 0 0 0(0/0/0) 0(0/0/0) RAM instance meets the required threshold for mapping using URAM.
===================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### REG/LOGIC REPORT #####
RTL_INSTANCE PRIMITIVE_TYPE USER_ATTRIBUTE COMMENTS
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Core_reset_pf_0.Core_reset_pf_0.dff NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_FAB_1.lI1I1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lo0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.lI0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Ii0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.o10l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.Il0l1 NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.amcxfif_U0.CTSE_AMCXRFIF_SYS_1.oO0l1[7:0] NA NA Instance meets the required threshold for mapping using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.iOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.olIIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.O0IO1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.ilIO1_1 NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.OOOIo NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.IiiOo[7:0] NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.lo1Oo[3:0] NA NA Mapping instance using registers.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.tsmac_top_U0.pe_mcxmac_U0.CTSE_PE_MCXMAC_CORE_1.CTSE_PETFN_TOP_1.Ol1Oo NA NA Mapping instance using registers.
CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_out_2 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i1oIo[5:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.IooIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.I0I11.OolOo.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.lO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.IO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.Ooio1.i0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OO0Io ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.oolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.iolIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.OolIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I1lIo[2:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.i1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l1lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.I0lIo[4:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.o0lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.O1lIo[1:0] ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.SGMII_INSTANCE\.msgmii_core_u0.CTSE_MSGMII_TBI_1.CTSE_PEREX_PCS_1.loio1.l0lIo ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
Could not find a packable register for mapping ROM using LSRAM. Inferring using URAM.
Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[5:0] RAM DEFAULT RAM instance meets the required threshold for mapping using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[10:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[1:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] RAM syn_ramstyle=registers Found property syn_ramstyle="registers". Inferring instance using registers.
MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_lsu_0.lsu_emi_req_fence_1 ROM NA Mapping ROM instance using logic since value for switch "rom_map_logic" is set to 1.
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##### END OF RAM REPORT #####