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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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BIN
synthesis/synwork/.cckTransfer
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Binary file not shown.

18
synthesis/synwork/.layer0.srs_dep
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@@ -1,9 +1,9 @@
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block

891
synthesis/synwork/incr_compile.rpt
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File diff suppressed because it is too large Load Diff

19
synthesis/synwork/layer0.duruntime
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@@ -2,13 +2,16 @@ Runtime Summary:
================
* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
Hardware Generation Phase : 0h:00m:02s
Hardware Generation Phase : 0h:00m:03s
* Library: work, DesignUnit: miv_rv32_rr_pri_arb_3s_1s_1s
Hardware Generation Phase : 0h:00m:01s
* Library: work, DesignUnit: miv_rv32_debug_sba
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: miv_rv32_ipcore_Z19
Hardware Generation Phase : 0h:00m:08s
Hardware Generation Phase : 0h:00m:14s
* Library: work, DesignUnit: miv_rv32_expipe_Z16
Hardware Generation Phase : 0h:00m:01s
@@ -24,19 +27,19 @@ Runtime Summary:
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: CTSE_CORETSE_TOP_Z10
Hardware Generation Phase : 0h:00m:08s
Hardware Generation Phase : 0h:00m:12s
* Library: work, DesignUnit: CTSE_PEMSTAT_EIM_26s_1s_0s
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: CTSE_TSMAC_TOP_Z9
Hardware Generation Phase : 0h:00m:06s
Hardware Generation Phase : 0h:00m:10s
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_Z5
Hardware Generation Phase : 0h:00m:01s
Hardware Generation Phase : 0h:00m:02s
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2
Hardware Generation Phase : 0h:00m:02s
Hardware Generation Phase : 0h:00m:03s
The following design units have negligible CPU times:
=====================================================
@@ -94,8 +97,6 @@ Runtime Summary:
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_fixed_arb_3s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_rr_pri_arb_3s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_fixed_arb_2s
@@ -386,6 +387,8 @@ Runtime Summary:
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_rr_pri_arb_3s_1s_1s
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_ipcore_Z19
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_expipe_Z16

28
synthesis/synwork/layer0.fdep
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@@ -4,7 +4,7 @@
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\hypermods.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_objects.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_pipes.svh":1745942006
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776273292
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776394635
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_graytobinconv.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_nstagessync.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_async.v":1776257512
@@ -70,22 +70,22 @@
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_IOD_CDR_CCC_C0.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776273031
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776394591
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776273264
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776394606
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
#numinternalfiles:4
#defaultlanguage:verilog
0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog

23
synthesis/synwork/layer0.rt.csv
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@@ -1,13 +1,14 @@
Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
work, miv_rv32_subsys_tcm_Z20,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 353 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 23 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 364 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 364 MB, 2 MB, 1 MB, 0 MB, 1 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 61 MB, 0 MB, 30 MB, 32 MB
work, miv_rv32_subsys_tcm_Z20,0h:00m:03s,0h:00m:03s,0h:00m:00s,0h:00m:00s, 354 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_rr_pri_arb_3s_1s_1s,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 354 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:02s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 22 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:14s,0h:00m:14s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:03s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 365 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 365 MB, 2 MB, 1 MB, 0 MB, 0 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 60 MB, 0 MB, 29 MB, 30 MB
work, miv_rv32_idecode_1_1s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 11 MB, 10 MB, 1 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 398 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:06s,0h:00m:06s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 398 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:13s,0h:00m:12s,0h:00m:00s,0h:00m:00s, 397 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:02s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:10s,0h:00m:10s,0h:00m:00s,0h:00m:00s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 397 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:03s,0h:00m:03s,0h:00m:00s,0h:00m:00s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
1 Library Design Unit Compile time Hardware Gen Optimization Stg1 Optimization Stg2 Peak Mem Usage Incr Mem Usage Hardware Gen Optimization Stg1 Optimization Stg2
2 work miv_rv32_subsys_tcm_Z20 0h:00m:02s 0h:00m:03s 0h:00m:02s 0h:00m:03s 0h:00m:00s 0h:00m:00s 353 MB 354 MB 35 MB 34 MB 1 MB 0 MB
3 work miv_rv32_debug_sba miv_rv32_rr_pri_arb_3s_1s_1s 0h:00m:01s 0h:00m:00s 0h:00m:01s 0h:00m:00s 0h:00m:01s 0h:00m:00s 355 MB 354 MB 23 MB 0 MB 0 MB 6 MB 0 MB 16 MB 0 MB
4 work miv_rv32_ipcore_Z19 miv_rv32_debug_sba 0h:00m:08s 0h:00m:02s 0h:00m:08s 0h:00m:00s 0h:00m:00s 0h:00m:00s 0h:00m:01s 355 MB 43 MB 22 MB 43 MB 0 MB 0 MB 6 MB 0 MB 16 MB
5 work miv_rv32_expipe_Z16 miv_rv32_ipcore_Z19 0h:00m:02s 0h:00m:14s 0h:00m:01s 0h:00m:14s 0h:00m:00s 0h:00m:01s 0h:00m:00s 364 MB 355 MB 2 MB 43 MB 0 MB 43 MB 2 MB 0 MB 0 MB
6 work miv_rv32_csr_privarch_Z15 miv_rv32_expipe_Z16 0h:00m:02s 0h:00m:03s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 364 MB 365 MB 2 MB 1 MB 0 MB 0 MB 2 MB 1 MB 0 MB
7 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 miv_rv32_csr_privarch_Z15 0h:00m:03s 0h:00m:02s 0h:00m:00s 0h:00m:01s 0h:00m:00s 0h:00m:02s 0h:00m:00s 397 MB 365 MB 61 MB 2 MB 0 MB 1 MB 30 MB 0 MB 32 MB 0 MB
8 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 0h:00m:03s 0h:00m:00s 0h:00m:00s 0h:00m:02s 397 MB 60 MB 0 MB 29 MB 30 MB
9 work miv_rv32_idecode_1_1s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 397 MB 11 MB 10 MB 1 MB 0 MB
10 work CTSE_CORETSE_TOP_Z10 0h:00m:08s 0h:00m:13s 0h:00m:08s 0h:00m:12s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 13 MB 13 MB 0 MB 0 MB
11 work CTSE_PEMSTAT_EIM_26s_1s_0s 0h:00m:01s 0h:00m:02s 0h:00m:00s 0h:00m:00s 0h:00m:01s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB
12 work CTSE_TSMAC_TOP_Z9 0h:00m:06s 0h:00m:10s 0h:00m:06s 0h:00m:10s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB
13 COREJTAGDEBUG_LIB COREJTAGDEBUG_Z5 0h:00m:01s 0h:00m:02s 0h:00m:01s 0h:00m:02s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 1 MB 1 MB 0 MB 0 MB
14 work COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 0h:00m:02s 0h:00m:03s 0h:00m:02s 0h:00m:03s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB

5
synthesis/synwork/layer0.so Normal file
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@@ -0,0 +1,5 @@
<?xml version="1.0" encoding="UTF-8" ?>
<SynplifyOutput>
<result>Failure</result>
<details>View log file for error messages</details>
</SynplifyOutput>

BIN
synthesis/synwork/layer0.srs
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Binary file not shown.

397
synthesis/synwork/layer0.tlg
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@@ -353,10 +353,10 @@ Finished optimization stage 1 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Me
NUM_TRAIL_PAD_BITS=8'b00000000
Generated name = COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0
Running optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 .......
Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|Removing wire UTRSTB, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|Removing wire UTMS, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":169:8:169:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.
@@ -367,10 +367,10 @@ Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used curren
Running optimization stage 1 on COREJTAGDEBUG_Z5 .......
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v":56:7:56:22|Synthesizing module COREJTAGDEBUG_C0 in library work.
Running optimization stage 1 on COREJTAGDEBUG_C0 .......
Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":31:7:31:12|Synthesizing module spi_rf in library CORESPI_LIB.
APB_DWIDTH=32'b00000000000000000000000000100000
@@ -478,9 +478,9 @@ Finished optimization stage 1 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used
Running optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s .......
Finished optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB)
Running optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s .......
Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB)
Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 243MB)
Running optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s .......
Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 242MB peak: 243MB)
Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 244MB)
Running optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s .......
Finished optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB)
Running optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s .......
@@ -502,73 +502,73 @@ Finished optimization stage 1 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Mem
Running optimization stage 1 on CTSE_PECRC_1s_26s .......
Finished optimization stage 1 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB)
Running optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s .......
Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 248MB peak: 256MB)
Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 249MB peak: 256MB)
Running optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s .......
Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 261MB)
Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 262MB)
Running optimization stage 1 on CTSE_PERMC_TOP_1s_26s .......
Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB)
Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s .......
Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB)
Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMGT_1s_26s .......
Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEHST_1s_26s .......
Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PECAR_26s_1s .......
Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s .......
Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s .......
Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_STORE_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s .......
Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_MMCXWOL_1s_26s .......
Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_SI_SAL_26s .......
Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_TSMAC_TOP_Z9 .......
Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_CLKRST_26s_1s .......
Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_ECC_0s_26s_16s .......
Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell.
Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s .......
Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s .......
Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_MSGMII_CNVTXI_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_MSGMII_CNVTXO_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_T8B10B .......
Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB)
Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB)
Running optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s .......
Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB)
Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB)
Running optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 .......
Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB)
Running optimization stage 1 on CTSE_R10B8B .......
Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB)
Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB)
Running optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s .......
Finished optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB)
Running optimization stage 1 on CTSE_PEANX_SYNC_1s_26s .......
@@ -582,28 +582,28 @@ Finished optimization stage 1 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory
Running optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s .......
Finished optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Running optimization stage 1 on CTSE_MSGMII_CNVRXI_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_MSGMII_CNVRXO_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s .......
Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_CORETSE_TOP_Z10 .......
Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 .......
Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CORETSE_Z11 .......
Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":31:7:31:15|Synthesizing module CORETSE_0 in library work.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":270:0:270:10|Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
Running optimization stage 1 on CORETSE_0 .......
Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work.
BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s .......
Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work.
SYNC_RESET=32'b00000000000000000000000000000000
@@ -692,14 +692,14 @@ Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used cu
LOG2_BUFF_DEPTH=32'b00000000000000000000000000000010
MI_I_MEM=32'b00000000000000000000000000000000
Generated name = miv_rv32_ifu_iab_32s_2s_3s_2s_0s
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s .......
Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB)
Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB)
I_ADDR_WIDTH=32'b00000000000000000000000000100000
l_core_reset_vector=32'b10000000000000000000000000000000
@@ -713,7 +713,7 @@ Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:0
IFU_PARITY_ERROR_BIT=32'b00000000000000000000000000000001
Generated name = miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14
Running optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 .......
Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB)
Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB)
D_ADDR_WIDTH=32'b00000000000000000000000000100000
REQ_BUFF_DEPTH=32'b00000000000000000000000000000010
@@ -1000,24 +1000,24 @@ Finished optimization stage 1 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_6s_2s_1s_1s
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
BUFF_WIDTH=32'b00000000000000000000000000001011
BUFF_SIZE=32'b00000000000000000000000000000010
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_11s_2s_1s_1s
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
WIDTH=32'b00000000000000000000000000100000
FIELD_RESET_EN=32'b00000000000000000000000000000001
@@ -1031,9 +1031,9 @@ Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_7s_2s_1s_1s
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
@@ -1197,17 +1197,17 @@ Running optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB)
Running optimization stage 1 on miv_rv32_debug_sba .......
Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_debug_du .......
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001
Generated name = miv_rv32_subsys_debug_1s
Running optimization stage 1 on miv_rv32_subsys_debug_1s .......
Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
NUM_REQS=32'b00000000000000000000000000000010
USE_FORMAL=32'b00000000000000000000000000000001
@@ -1217,9 +1217,9 @@ Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s,
NUM_REQS=32'b00000000000000000000000000000010
Generated name = miv_rv32_fixed_arb_2s
Running optimization stage 1 on miv_rv32_fixed_arb_2s .......
Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
APB_ADDR_WIDTH=32'b00000000000000000000000000100000
APB_REGISTER_IO=32'b00000000000000000000000000000001
@@ -1233,7 +1233,7 @@ Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:0
Generated name = miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6281:36:6281:48|Removing redundant assignment.
Running optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 .......
Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
NUM_REQS=32'b00000000000000000000000000000011
USE_FORMAL=32'b00000000000000000000000000000001
@@ -1243,9 +1243,9 @@ Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_
NUM_REQS=32'b00000000000000000000000000000011
Generated name = miv_rv32_fixed_arb_3s
Running optimization stage 1 on miv_rv32_fixed_arb_3s .......
Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s .......
Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
FAMILY=32'b00000000000000000000000000011010
UDMA_PRESENT=32'b00000000000000000000000000000000
@@ -1284,7 +1284,7 @@ Finished optimization stage 1 on CFG3 (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on OR2 .......
Finished optimization stage 1 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB)
Running optimization stage 1 on INV .......
Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 319MB peak: 330MB)
Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 320MB peak: 330MB)
RAM_DEPTH=32'b00000000000000000010010000000000
ADDR_WIDTH=32'b00000000000000000000000000001110
@@ -1857,40 +1857,40 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on pf_init_monitor_0 .......
Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR .......
Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on BANKEN .......
Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on INIT .......
Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PF_CCC_0 .......
Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC .......
Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PLL .......
Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on MIV_RV32_C0 .......
Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 .......
Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 .......
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13005:27:13005:40|Input mtime_count_in is unused.
Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 .......
Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on INV .......
Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on OR2 .......
Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on CFG3 .......
Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on CFG2 .......
Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on OR4 .......
Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_tcm_Z20 .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Trying to extract state machine for register cpu_d_wr_rd_state.
Extracted state machine for register cpu_d_wr_rd_state
@@ -1935,9 +1935,9 @@ State machine has 3 reachable states with original encodings of:
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10885:49:10885:66|Input tcm_tas_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10890:49:10890:61|Input tcm_ram_sb_in is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10891:49:10891:71|Input tcm_ecc_error_injection is unused.
Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_fixed_arb_3s .......
Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
Extracted state machine for register hipri_req_ptr
@@ -1949,7 +1949,7 @@ State machine has 7 reachable states with original encodings of:
101
110
111
Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Trying to extract state machine for register gen_apb_byte_shim.apb_st.
Extracted state machine for register gen_apb_byte_shim.apb_st
@@ -1967,9 +1967,9 @@ State machine has 6 reachable states with original encodings of:
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6080:49:6080:68|Input cpu_d_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6083:49:6083:64|Input cpu_d_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6087:49:6087:64|Input cpu_d_resp_ready is unused.
Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_fixed_arb_2s .......
Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
Extracted state machine for register hipri_req_ptr
@@ -1977,9 +1977,9 @@ State machine has 3 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_debug_1s .......
Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_debug_du .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14736:0:14736:8|Trying to extract state machine for register debug_state.
Extracted state machine for register debug_state
@@ -1992,7 +1992,7 @@ State machine has 6 reachable states with original encodings of:
100000
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Trying to extract state machine for register command_reg_state.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13800:39:13800:52|Input dmi_resp_ready is unused.
Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:01s, Memory Used current: 335MB peak: 354MB)
Running optimization stage 2 on miv_rv32_debug_sba .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|Trying to extract state machine for register sba_state.
Extracted state machine for register sba_state
@@ -2001,7 +2001,7 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:01s, Memory Used current: 350MB peak: 355MB)
Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:02s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s .......
Finished optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s .......
@@ -2122,33 +2122,33 @@ Finished optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:
Running optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s .......
Finished optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_expipe_Z16 .......
Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:01s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:02s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_privarch_Z15 .......
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":1854:60:1854:72|Input port bit 1 of excpt_trigger[1:0] is unused
Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@@ -2156,18 +2156,18 @@ Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6896:43:6896:57|Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_irq_reg_0s .......
Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_bcu .......
Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 .......
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:02s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:03s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@@ -2185,11 +2185,12 @@ Finished optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:0
Running optimization stage 2 on INBUF_DIFF .......
Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on fifo_to_tpsram_bridge .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":65:4:65:9|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
State machine has 3 reachable states with original encodings of:
00
01
10
Finished optimization stage 2 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CoreUARTapb_0 .......
Finished optimization stage 2 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
@@ -2240,9 +2241,9 @@ Finished optimization stage 2 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory
Running optimization stage 2 on CTSE_PETBM_26s_0s_1s .......
Finished optimization stage 2 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB)
Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEANX_SYNC_1s_26s .......
Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB)
Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s .......
Extracted state machine for register lI101
State machine has 4 reachable states with original encodings of:
@@ -2250,65 +2251,65 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_R10B8B .......
Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 .......
Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s .......
Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_T8B10B .......
Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_CNVTXO_26s .......
Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_CNVTXI_26s .......
Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s .......
Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s .......
Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_CORETSE_TOP_Z10 .......
Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_ECC_0s_26s_16s .......
Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_CLKRST_26s_1s .......
Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_SI_SAL_26s .......
Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MMCXWOL_1s_26s .......
Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s .......
Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_STORE_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s .......
Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_TSMAC_TOP_Z9 .......
Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s .......
Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PECAR_26s_1s .......
Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEHST_1s_26s .......
Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMGT_1s_26s .......
Extracted state machine for register l0i11
State machine has 32 reachable states with original encodings of:
@@ -2344,31 +2345,31 @@ State machine has 32 reachable states with original encodings of:
11101
11110
11111
Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s .......
Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PERMC_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s .......
Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s .......
Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:01s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_PECRC_1s_26s .......
Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_PETMC_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s .......
Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s .......
Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s .......
Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXFIF_HST_Z8 .......
Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 .......
Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s .......
Extracted state machine for register genblk1.O0Il1
State machine has 5 reachable states with original encodings of:
@@ -2377,24 +2378,24 @@ State machine has 5 reachable states with original encodings of:
1100
1110
1111
Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s .......
Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s .......
Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_DECODER .......
Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CORESPI_0 .......
Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CORESPI_Z7 .......
Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_chanctrl_Z6 .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state.
@@ -2406,66 +2407,66 @@ State machine has 6 reachable states with original encodings of:
0111
1000
1001
Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_clockmux .......
Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_fifo_16s_32s_5 .......
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=1
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=16
Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_control_16s .......
Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_rf_32s_16s_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_C0 .......
Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CLKINT .......
Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 .......
Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on BUFD .......
Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on corejtagdebug_bufd_34s .......
Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on UJTAG .......
Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_Z5 .......
Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0 .......
Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on VCC .......
Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on GND .......
Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on RAM1K20 .......
Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CoreAPB3_0 .......
Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CoreAPB3_Z1 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREAPB3_MUXPTOB3 .......
Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on Core_reset_pf .......
Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF .......
@N: CL135 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on BIBUF .......
Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on AND2 .......
Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
For a summary of runtime per design unit, please see file:
==========================================================

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synthesis/synwork/layer0.tlg.db
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synthesis/synwork/modulechange.db
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synthesis/synwork/top_comp.fdep
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@@ -4,7 +4,7 @@
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\hypermods.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_objects.v":1745942006
#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_pipes.svh":1745942006
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776273292
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776394635
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_graytobinconv.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_nstagessync.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_async.v":1776257512
@@ -70,22 +70,22 @@
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_IOD_CDR_CCC_C0.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776384266
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776273031
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776394591
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776273264
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776394606
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog
1 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" verilog
2 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" verilog

23
synthesis/synwork/top_comp.rt.csv
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@@ -1,13 +1,14 @@
Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
work, miv_rv32_subsys_tcm_Z20,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 353 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 23 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 364 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 364 MB, 2 MB, 1 MB, 0 MB, 1 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 61 MB, 0 MB, 30 MB, 32 MB
work, miv_rv32_subsys_tcm_Z20,0h:00m:03s,0h:00m:03s,0h:00m:00s,0h:00m:00s, 354 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_rr_pri_arb_3s_1s_1s,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 354 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:02s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 22 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:14s,0h:00m:14s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:03s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 365 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 365 MB, 2 MB, 1 MB, 0 MB, 0 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 60 MB, 0 MB, 29 MB, 30 MB
work, miv_rv32_idecode_1_1s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 11 MB, 10 MB, 1 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 398 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:06s,0h:00m:06s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 398 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:13s,0h:00m:12s,0h:00m:00s,0h:00m:00s, 397 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:02s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:10s,0h:00m:10s,0h:00m:00s,0h:00m:00s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 397 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:03s,0h:00m:03s,0h:00m:00s,0h:00m:00s, 397 MB, 0 MB, 0 MB, 0 MB, 0 MB
1 Library Design Unit Compile time Hardware Gen Optimization Stg1 Optimization Stg2 Peak Mem Usage Incr Mem Usage Hardware Gen Optimization Stg1 Optimization Stg2
2 work miv_rv32_subsys_tcm_Z20 0h:00m:02s 0h:00m:03s 0h:00m:02s 0h:00m:03s 0h:00m:00s 0h:00m:00s 353 MB 354 MB 35 MB 34 MB 1 MB 0 MB
3 work miv_rv32_debug_sba miv_rv32_rr_pri_arb_3s_1s_1s 0h:00m:01s 0h:00m:00s 0h:00m:01s 0h:00m:00s 0h:00m:01s 0h:00m:00s 355 MB 354 MB 23 MB 0 MB 0 MB 6 MB 0 MB 16 MB 0 MB
4 work miv_rv32_ipcore_Z19 miv_rv32_debug_sba 0h:00m:08s 0h:00m:02s 0h:00m:08s 0h:00m:00s 0h:00m:00s 0h:00m:00s 0h:00m:01s 355 MB 43 MB 22 MB 43 MB 0 MB 0 MB 6 MB 0 MB 16 MB
5 work miv_rv32_expipe_Z16 miv_rv32_ipcore_Z19 0h:00m:02s 0h:00m:14s 0h:00m:01s 0h:00m:14s 0h:00m:00s 0h:00m:01s 0h:00m:00s 364 MB 355 MB 2 MB 43 MB 0 MB 43 MB 2 MB 0 MB 0 MB
6 work miv_rv32_csr_privarch_Z15 miv_rv32_expipe_Z16 0h:00m:02s 0h:00m:03s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 364 MB 365 MB 2 MB 1 MB 0 MB 0 MB 2 MB 1 MB 0 MB
7 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 miv_rv32_csr_privarch_Z15 0h:00m:03s 0h:00m:02s 0h:00m:00s 0h:00m:01s 0h:00m:00s 0h:00m:02s 0h:00m:00s 397 MB 365 MB 61 MB 2 MB 0 MB 1 MB 30 MB 0 MB 32 MB 0 MB
8 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 0h:00m:03s 0h:00m:00s 0h:00m:00s 0h:00m:02s 397 MB 60 MB 0 MB 29 MB 30 MB
9 work miv_rv32_idecode_1_1s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 397 MB 11 MB 10 MB 1 MB 0 MB
10 work CTSE_CORETSE_TOP_Z10 0h:00m:08s 0h:00m:13s 0h:00m:08s 0h:00m:12s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 13 MB 13 MB 0 MB 0 MB
11 work CTSE_PEMSTAT_EIM_26s_1s_0s 0h:00m:01s 0h:00m:02s 0h:00m:00s 0h:00m:00s 0h:00m:01s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB
12 work CTSE_TSMAC_TOP_Z9 0h:00m:06s 0h:00m:10s 0h:00m:06s 0h:00m:10s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB
13 COREJTAGDEBUG_LIB COREJTAGDEBUG_Z5 0h:00m:01s 0h:00m:02s 0h:00m:01s 0h:00m:02s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 1 MB 1 MB 0 MB 0 MB
14 work COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 0h:00m:02s 0h:00m:03s 0h:00m:02s 0h:00m:03s 0h:00m:00s 0h:00m:00s 398 MB 397 MB 0 MB 0 MB 0 MB 0 MB

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synthesis/synwork/top_prem.fse
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@@ -137,13 +137,15 @@ fsm_state_encoding {37286028612} 11 {11}
fsm_registers {37286028612} {rx_state[1]} {rx_state[0]}
fsm_encoding {734544511} sequential
fsm_encoding {736546511} sequential
fsm_state_encoding {734544511} IDLE {0}
fsm_state_encoding {736546511} IDLE {00}
fsm_state_encoding {734544511} WRITE {1}
fsm_state_encoding {736546511} IGNORE {01}
fsm_registers {734544511} {state[0]}
fsm_state_encoding {736546511} WRITE {10}
fsm_registers {736546511} {state[1]} {state[0]}
fsm_encoding {4916013121601310} onehot

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